Commit graph

13503 commits

Author SHA1 Message Date
Kangheui Won
39ef890336 mb/google/guybrush: disable KBRSTEN
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.

BUG=b:183340503
TEST=build

Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-24 19:37:09 +00:00
Wayne3 Wang
6d837df908 mb/google/volteer/variants/drobit: Modify touchpad power sequence
Modify power sequence of touchpad to meet the definition in the spec.

BUG=b:178353432
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.

Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 17:43:36 +00:00
Benjamin Doron
8c5994f92d mb/emulation/qemu-q35: Fix format specifier for a size_t
Fix compilation on GCC 10.2.1

Change-Id: I47d29ef065f57f171f429bb6a368bc86e31acee9
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-24 07:54:05 +00:00
Tim Crawford
427487b173 mb/system76/gaze15: Add System76 Gazelle 15
Tested with TianoCore payload (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10

Not working:

- Discrete/Hybrid graphics

This requires a new driver to work correctly, which will be added and
enabled later.

Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-24 07:53:40 +00:00
Usha P
f02fa4a1a8 mb/intel/adlrvp: Enable CnviBtAudioOffload
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.

BUG=None
TEST=Verified BT offload working on ADL RVP

Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-03-24 07:52:48 +00:00
Yu-Ping Wu
71c5ca764f soc/mediatek: Use MRC cache API for asurada
Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.

This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.

Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.

With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.

BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none

Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-24 05:43:50 +00:00
Derek Basehore
cbe266142e mb/google/octopus: Wake up AP on AC plug and unplug
This patch makes all Octopus variants resume from S0ix/S3 on AC plug
and unplug.

Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa
Signed-off-by: Derek Basehore <dbasehore@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-23 22:50:04 +00:00
Angel Pons
36714d9fe6 haswell boards: Use zero length for disabled USB ports
For disabled USB ports, the length setting does not matter. In future
commits, disabled USB ports will end up with length field set to zero.

Change-Id: I7613e1b0c89c0b58eca790ca14fcd1633c8a93af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2021-03-23 10:59:40 +00:00
Angel Pons
c4ee714881 nb/intel/haswell: Use unshifted SPD addresses in mainboards
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 10:59:26 +00:00
Sunway
8d529421d3 mb/google/kukui: Add a new config 'Makomo'
A new board introduced to Kukui family.

BUG=None
TEST=make # select Makomo
BRANCH=kukui

Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I42b84e2c0926e755ba210fc8baac19f8ed2c4e57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51565
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-23 01:45:41 +00:00
Ravi Sarawadi
c6bc3a56d6 mb/google/volteer/variants/delbin: Disable PmcUsb2PhySusPgEnable
eDP panel flicker during system idle state is observed.
Disabling USB2 SUS well power gating can remove flicker symptom.
Please refer to doc#634894 for more details.

BUG=b:182323059
BRANCH=None
TEST=Boot and confirm no display flicker.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2021-03-23 00:03:15 +00:00
Nick Vaccaro
7ef6aeec14 mb/google/volteer/variants/eldrid: Include SPD for H4AAG165WB-BCWE
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE.

Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H4AAG165WB-BCWE DDR4 memory parts.

BUG=b:181732562
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.

Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 21:18:27 +00:00
Ian Feng
7be232a21c mb/google/dedede: Create cret variant
Create the cret variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:181325655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CRET

Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-22 17:31:24 +00:00
hao_chou
9fd2ad1d52 mb/google/volteer/variants/copano: Configure specific DPTF parameters
Configure board specific DPTF parameters for copano

BUG=b:176961219
BRANCH=firmware-volteer-13672.B
TEST=build and verify by thermal team

Change-Id: Ibce67f81503b84b58798bc198947e61907276ad3
Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51561
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 16:32:17 +00:00
Michael Niewöhner
480c2de549 purism/librem_14: add on-board LAN device
On-board devices should be present in the devicetree, so that
`.on_mainboard` field of `struct device` is `1`.

Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3678514482724377bcdfcbdc7f2c5b312a48b2c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-03-22 11:32:09 +00:00
Keith Hui
023fdaffd1 mb/asus/p2b: Refactor southbridge ACPI stuff
Move (remaining) southbridge ACPI stuff into one file under
sb/intel/i82371eb, that is simply included from the board's \_SB scope.

Change-Id: Ibed49a800dec19534761e5ab22a6cbb1e6bd4a5d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-22 11:30:55 +00:00
Angel Pons
88f94a9635 lynxpoint/broadwell: Rename LP GPIO config global
Do not use the same name as the non-LP GPIO config. This allows checking
at build-time that a mainboard uses the correct GPIO config format.

Without this commit, there are no build-time errors when using the wrong
format of GPIO config, but there would be undefined behavior at runtime.

Tested by trying to build asrock/b85m_pro4 and hp/folio_9480m after
toggling the `INTEL_LYNXPOINT_LP` Kconfig option (and trimming down the
USB config arrays for asrock/b85m_pro4). In both cases, building failed
because the necessary GPIO config global is not defined, as expected.

Change-Id: Ib06507ef8179da22bdb27593daf972e788051f3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51661
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:26:22 +00:00
Frank Wu
d12d24b039 mb/google/zork: Enable SSFC as upper 32 bit of fw_config
To append SSFC to top 32 bits of fw_config.

BUG=b:177971830
BRANCH=firmware-zork-13434.B
TEST=Build coreboot and get the value of SSFC.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Iab1596f1cc8fbbf45e6a9269351bf422a43f3583
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51655
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:25:48 +00:00
Sugnan Prabhu S
31f383686a mb/google/brya: Enable S0ix
This change enables S0ix for brya platform.

BUG=b:181843816
TEST=Built image and booted to kernel.

Change-Id: Idc6f7fce9779ef4458375becebf5dc65b228abeb
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51526
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 11:25:26 +00:00
Zanxi Chen
d92966b610 mb/google/dedede/var/storo: Add USB Port Configuration
Add USB Port configuration into devicetree for storo

BUG=b:177389444
BRANCH=dedede
TEST=built firmware and verified USB3.0 function is OK

Change-Id: I1527c7178ffac9b2322eb65aab6e2086d949e47c
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-22 11:22:06 +00:00
Eric Lai
7f4c30c1d5 mb/google/zork: Move max98357a out of baseboard
Not all of dalboz variants support the this amp. Thus, move out of baseboard.

BUG=b:182815488
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If708574f5fb18dd3b4f2ef978529a16a40d5dc0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-22 03:51:23 +00:00
Karthikeyan Ramasubramanian
8f7fca5370 mb/google/guybrush: Enable AP <-> H1 communication
Configure H1 I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for H1 device and enable the required
config items.

BUG=b:180528902
TEST=Build Guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I040a5e6101bab0c7425d7b6cc6fbed3b479a5a44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22 03:50:08 +00:00
Karthikeyan Ramasubramanian
699a709bdc mb/google/guybrush: Add initial I2C configuration
Add I2C peripheral reset configuration required during early init.
Enabled I2C generic and HID drivers. I2C GPIOs are configured as
required in CB:50091.

BUG=b:180531661
TEST=Build guybrush mainboard.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I67690fbd25639879a730260aaca4cddb5e47bbc7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-22 03:49:18 +00:00
Zheng Bao
16e1fd5ae9 mb/amd/majolica: Set IOMUX to enable I2C2 & I2C3
Change-Id: I142c06c150214d58acc04b8c6b3b027fff0256db
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
2021-03-22 03:40:53 +00:00
Karthikeyan Ramasubramanian
4f87ae1d4a soc/amd/common/block/i2c: Move SoC agnostic parts into common
The logic behind I2C bus initialization, I2C MMIO base address getter
and setter, I2C bus ACPI name resolution are identical for all the AMD
SoCs. Hence moving all the SoC agnotic parts of the driver into the
common driver and just configure the SoC specific parts into individual
I2C drivers.

BUG=None
TEST=Build Dalboz and Grunt. Boot to OS in Dalboz. Ensure that the I2C
peripherals are detected as earlier in Dalboz. Verify some I2C
peripheral functionality like trackpad and touchscreen.

Change-Id: Ic9c99ec769d7d8ad7e1e566fdf42a5206657183d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Suggested-by: Kyosti Malkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51509
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-22 03:40:42 +00:00
Marc Jones
f332e47f56 mainboard/: Register chipset_lockdown on xeon_sp mainboards
Set chipset_lockdown in devicetree for recommended security settings.

Change-Id: Ie27450dd32463243b1456932a1d39d40afa81da1
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51388
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 16:00:54 +00:00
Matt DeVillier
4c3851afbf mb/purism/librem_cnl: Add new board/variant Librem 14
Add support for the CometLake-U based Librem 14 laptop.

Change-Id: I24a2a92091cc272638ecaf8ea23a896cab8a7153
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51549
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-20 12:22:21 +00:00
Kevin Chiu
4490689d88 google/trogdor: Add new variant Marzipan
This patch adds a new variant called Marzipan that is identical to Lazor
for now.

BUG=b:182181519,b:182018606
BRANCH=master
TEST=make

Change-Id: I92b667c63b0a06255d1e9511d7486293d8b4426a
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:31:06 +00:00
xuxinxiong
8f11d24038 mb/google/trogdor: Add support for SPI_FLASH_GIGADEVICE
Add support SPI_FLASH_GIGADEVICE for some project.

BUG=b:182246432
BRANCH=trogdor
TEST=emerge-strongbad and test with power on.

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: I6ab948909f4e17b4b992be6d699646f7a62bef7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-03-20 01:11:51 +00:00
Kevin Keijzer
51b1b2a0c4 mb/lenovo/x200: Fix boot-time docking state
The X200 would undock itself when waking up from S3, requiring a
physical reconnection before the dock would work again.

Similar to 4611ad8, this reintroduces h8_mb_init() for the X200. A hook
function h8_mb_init() will be called at the end of h8_enable(), in place
of the ancient h8_mainboard_init_dock().

This should fix the regression the X201 and T410 also suffered from for
the X200.

Change-Id: Icb6dd145e56b90e0e04133810c5e9ac7b641ad68
Signed-off-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51123
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 17:18:37 +00:00
Julien Viard de Galbert
b3e504c310 mb/scaleway/tagada: Don't change FIAMUX when Security Override is set
This will not enable M.2 SATA drive if the ME config was lost
(For instance after flashing a full flash factory image)

This is required so that the system can boot without FIA MUX error
during flash update procedure.

Change-Id: I55a8bcdc30bc67af2d3e9ccb8844eac599727108
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:36:27 +00:00
Wisley Chen
0afecd8d08 mb/google/volteer/var/elemi: Config GPP_B7/GPP_B8 as NC
elemi does not use the GPP_B7/GPP_B8, so config to NC.
Currently, there is no functional impact.

BUG=b:182981460
TEST=emerge-volteer coreboot, boot into OS, and suspend/resume
successfully.

Change-Id: I7b491fd595b0e77e6dcce08e3172dbe592f63c37
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-03-19 11:22:17 +00:00
Matt DeVillier
9e82bf36c8 mb/purism/librem_cnl: drop MAX_CPUS from Kconfig
No need to restrict this further than the platform default,
and will be problematic with the addition of the upcoming
6C/12T Librem 14 board.

Change-Id: I1913992ec12578e1ad3bf6bf679d1a35a46d7370
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-19 11:21:23 +00:00
Angel Pons
747a2fc90e mb/{clevo/cml-u,system76/lemp9}: Clarify gen2_dec use
This I/O range is for a PM channel on the EC, not the PCH PMC.

Change-Id: I64422e537c1edcd0673cf87f16139fb117b10e75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51604
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:21:12 +00:00
Angel Pons
90ae08922d nb/intel/haswell: Consolidate memory-down SPD handling
Mainboards do not need to know about `pei_data` to tell northbridge code
where to find the SPD data. Adjust `mb_get_spd_map` to take a pointer to
a struct instead of an array, and update all the mainboards accordingly.

Currently, the only board with memory-down in the tree is google/slippy.
Mainboard code now obtains the SPD index in `mb_get_spd_map` and adjusts
the channel population accordingly. Then, northbridge code reads the SPD
file and uses the index that was read in `mb_get_spd_map`, and copies it
to channel 0 slot 0 unconditionally. MRC only uses the first position of
the `spd_data` array, and ignores the other positions. In coreboot code,
`setup_sdram_meminfo` uses the data of each SPD index, so `copy_spd` has
to account for this.

Tested on Asrock B85M Pro4, still boots and still resumes from S3.

Change-Id: Ibaed5c6de9853db6abd08f53bbfda8800d207c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51448
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-19 11:20:06 +00:00
Angel Pons
afc6c0ae12 mb/google/slippy: Correct memory-down SPD handling
MRC only uses the SPD data for the first index, and ignores the rest.
Moreover, index 1 corresponds to the second DIMM on the first channel,
which does not exist on ULT (only one DIMM per channel is supported).

Copy the SPD to the first DIMM on channel 1 instead. Adjust northbridge
code to retrieve the serial number from the correct SPD data block.

Tested on Google Wolf, both channels are still correctly detected.

Change-Id: Ic60ff75043e6b96a59baa9e5ebffb712a100a934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-19 11:19:51 +00:00
Tim Wawrzynczak
914ea8e530 mb/google/brya: Implement SLP_S0_GATE signal
The SLP_S0_GATE# signal is used in conjunction with the PCH's SLP_S0# to
provide an indication to the rest of the platform when the system is
entering its software-initiated low-power state (i.e. S0ix). This lets
the platform distinguish between opportunistic S0ix entry and the runtime
suspend mechanism.

BUG=b:180401723
TEST=abuild

Change-Id: I7fe2e3707465778baf56283617a8485a94f2dbca
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50881
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 22:31:36 +00:00
Raul E Rangel
d211ede937 mb/amd/majolica: Generate OIPG Package
This fixes the unknown reference errors for OIPG. Since Majolica
doesn't actually have any of the GPIOs ChromeOS uses, we leave
the arrays empty.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifeae84e0ccab187a4e7131cd6ea9e1336d79df67
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51536
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 18:10:11 +00:00
Mathew King
447a681d3f mb/google/guybrush: Add eSPI GPIO back to init table
GPIOs should be configured in ramstage even if they are configured in an
earlier stage.

BUG=b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I9896db41dbe2812856357510bc4420482e73ab3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51547
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 17:55:45 +00:00
Mathew King
cec52453b7 mb/google/guybrush: Configure UART0 gpio in early stage
BUG=b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8aa54acf1fa9295b27c33a0066432665e6e3755c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-18 17:55:23 +00:00
Johnny Lin
a699240612 mb/ocp/deltalake: Initialize VPD 'coreboot_uart_io' with default value 1
In case the VPD variable cannot be read.

Change-Id: I79fae6f4b4aad91a4040387ca6ddee8dfcc34d90
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 13:17:10 +00:00
Eric Lai
73b9fa6930 mb/google/mancomb: Configure eSPI GPIOs in early stage
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifa51705b3b5aab16f9cd2c11084220aafacd2774
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18 08:17:20 +00:00
Eric Lai
d807c806b3 mb/google/mancomb: Configure early GPIOs in earliest stage
Configure early GPIOs in verstage if it is run in PSP otherwise
configure them in bootblock.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic1faeea59462319c1652c69034b4dde01669e13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18 08:17:11 +00:00
Eric Lai
a906918ae0 mb/google/mancomb: Enable internal graphics device
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f5026b77513118a6c21eca78c9788c0bdc7ec6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18 08:16:36 +00:00
Eric Lai
1120519e73 mb/google/mancomb: Enable verstage
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic07a3ac556637919742fcbe899ee3fdfac38bb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-18 08:15:57 +00:00
Kane Chen
2988942b38 mb/google/zork/var/shuboz: adjust telemetry settings
According to stardust test tracking report to adjust
telemetry setting.

VDD Slope : 30518 -> 30595
VDD Offset: 435   -> 77
SOC Slope : 22965 -> 24063
SOC Offset: 165   -> 105

BUG=b:182399760
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie7e6af77bdaad6cc964ac206a69ccb854aae869f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-18 08:15:42 +00:00
Angel Pons
a12e16233b mb/prodrive/hermes: Disable HDA codec Port E by default on R04+
If the board settings aren't valid, Port E uses the settings for earlier
board revisions, which is undesired. Disable Port E by default on R04+.

Change-Id: I03bd50b915a2120283b77179debaa735bb7ef027
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51529
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 08:15:01 +00:00
Arthur Heymans
e69d2dfdb7 mb/emulation/qemu-q35: Add support for SMM_TSEG with parallel MP init
Tested with and without -enable-kvm, with -smp 1 2 and 32.

Change-Id: I612cebcd2ddef809434eb9bfae9d8681cda112ef
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48262
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-18 08:10:11 +00:00
Julius Werner
a9b44f4c79 spd_bin: Replace get_spd_cbfs_rdev() with spd_cbfs_map()
In pursuit of the goal of eliminating the proliferation of raw region
devices to represent CBFS files outside of the CBFS core code, this
patch removes the get_spd_cbfs_rdev() API and instead replaces it with
spd_cbfs_map() which will find and map the SPD file in one go and return
a pointer to the relevant section. (This makes it impossible to unmap
the mapping again, which all but one of the users didn't bother to do
anyway since the API is only used on platforms with memory-mapped
flash. Presumably this will stay that way in the future so this is not
something worth worrying about.)

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Iec7571bec809f2f0712e7a97b4c853b8b40702d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17 08:10:35 +00:00
Julius Werner
77639e4537 cbfs: Replace more instances of cbfs_boot_locate() with newer APIs
In pursuit of the eventual goal of removing cbfs_boot_locate() (and
direct rdev access) from CBFS APIs, this patch replaces all remaining
"simple" uses of the function call that can easily be replaced by the
newer APIs (like cbfs_load() or cbfs_map()). Some cases of
cbfs_boot_locate() remain that will be more complicated to solve.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Icd0f21e2fa49c7cc834523578b7b45b5482cb1a8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-17 08:10:20 +00:00
Lucas Chen
4cc42752fe mb/google/kukui: Add new config 'cozmo'
New board 'cozmo'.

BUG=b:181144502
TEST=None
BRANCH=kukui

Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Change-Id: Ia0ec1d89444d2634bfcfb3475a422f4e4ae92b7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-17 08:03:24 +00:00
wuweimin
709a1948b4 mb/google/dedede/var/sasukette: Enable ALC1015 AMP (Auto Mode) driver
Enable gpio mode driver for ALC1015 AMP Auto Mode.

BUG=b:176956779
BRANCH=dedede
TEST=ALC1015Q-VB drive speaker OK

Change-Id: Iaa5650e120362e81fa36530f6a207c9c07e1139a
Signed-off-by: wuweimin <wuweimin@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17 08:02:47 +00:00
Tony Huang
4248d8e7bb mb/google/dedede/var/lantis: Update DPTF parameters
DPTF paramerters from thermal team.

1. PL2 =15W
2. Add TSR sensor charger, 5V regulator

BUG=b:177249297
BRANCH=dedede
TEST=build image and verified by thermal team.

Change-Id: Ia5f6cc2a4564bb5558cbaca8daf31ee70145019f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-17 07:59:19 +00:00
Sugnan Prabhu S
efe873e633 mb/intel/shadowmountain: Update HDMI audio mode to 8T
This patch sets the HDMI audio mode to 8T as required by the latest FSP
version v2081_02

TEST: HDMI audio codecs detection is failing without this change.

Change-Id: Ie5a825da7d199c9ee61e64d8f4ee7dec28fdaacd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
2021-03-17 07:58:38 +00:00
Sugnan Prabhu S
565359fee0 mb/intel/shadowmountain: Disable xDCI
This patch disables the xDCI which is causing PC8 to PC10 state
transitions during sleep.

TEST: Confirmed that the transition is happening with this change.

Change-Id: I9bbf7b52c36954600d7e66f9b03fad39b8881a5f
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
2021-03-17 07:58:28 +00:00
Furquan Shaikh
7fe5d3d382 sar: Fix semantics of get_wifi_sar_cbfs_filename()
Currently, if `get_wifi_sar_cbfs_filename()` returns NULL, then
`get_wifi_sar_limits()` assumes that the default filename is used for
CBFS SAR file. This prevents a board from supporting different models
using the same firmware -- some which require SAR support and some
which don't.

This change updates the logic in `get_wifi_sar_limits()` to return
early if filename is not provided by the mainboard. In order to
maintain the same logic as before, current mainboards are updated to
return WIFI_SAR_CBFS_DEFAULT_FILENAME instead of NULL in default
case.

Change-Id: I68b5bdd213767a3cd81fe41ace66540acd68e26a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51485
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-17 07:56:13 +00:00
Furquan Shaikh
31f6320afe drivers/wifi, mb/google: Drop config WIFI_SAR_CBFS
Now that SAR support in VPD is deprecated in coreboot, there is no
need for a separate Kconfig `WIFI_SAR_CBFS` as the SAR table is only
supported as a CBFS file. This change drops the config `WIFI_SAR_CBFS`
from drivers/wifi/generic/Kconfig and its selection in
mb/google/.../Kconfig.

wifi_sar_defaults.hex is added to CBFS only if
CONFIG_WIFI_SAR_CBFS_FILEPATH is not empty because current mainboards
do not provide a default SAR file in
coreboot. Thus, CONFIG_WIFI_SAR_CBFS_FILEPATH is updated to have a
default value of "".

BUG=b:173465272

Cq-Depend: chromium:2757781
Change-Id: I0bb8f6e2511596e4503fe4d8c34439228ceaa3c7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-17 07:55:40 +00:00
Kyösti Mälkki
0dd6ee783f AGESA,binaryPI boards: Drop invalid MP table files
If we spot any error in the file, treat it as untested and
broken copy-paste.

Change-Id: Idd13b8b006fce7383f3f73c3c0a5d51a71c0155b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38313
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16 21:32:06 +00:00
Kyösti Mälkki
27f340e777 AGESA,binaryPI boards: Move IRQ table programming
IRQ programming should be done outside (obsolete) MP table
generation.

Change-Id: Ibce2af4de91549c4c9743cd997f625164672a713
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38564
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16 21:26:06 +00:00
Zanxi Chen
63813f9d79 mb/google/dedede/var/storo: Add USB Port Configuration
Add USB Port into devicetree for storo

BUG=b:177389444
BRANCH=dedede
TEST=built firmware and verified USB3.0 function is OK

Change-Id: I4d5160ff23d2bd386cb33164b580e6d6f3bf30fd
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16 13:17:36 +00:00
Zanxi Chen
b2641792a3 mb/google/dedede/var/blipper: Add camera support
Add camera support in devicetree and associated GPIO configuration.

BUG=b:181729304
BRANCH=dedede
TEST=built blipper firmware and verified camera function is OK

Change-Id: I806ec207a454d4383aca093159553b7e618e16b2
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16 11:17:59 +00:00
Zanxi Chen
aa2b614cb6 mb/google/dedede/var/blipper: Add codec and speaker amplifier support
Add audio codec and speaker amplifier support into devicetree

BUG=b:181732574
BRANCH=dedede
TEST=built blipper firmware and verified audio function is OK

Change-Id: Id4633649b5e0595ed99a40ae35eb54b005154604
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16 11:17:51 +00:00
Zanxi Chen
75f3d7ddbc mb/google/dedede/var/blipper: Enable touchscreen for blipper
Add G2 and ELAN touchscreen into devicetree for blipper.

BUG=b:181098785
BRANCH=dedede
TEST=built blipper firmware and verified touchscreen function is ok

Change-Id: Ie0bfc2972fc1a33a6f02495d3976b816209e956b
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-16 11:17:40 +00:00
Seunghwan Kim
bcc090d5e0 mb/google/dedede/var/sasuke: Configure GPP_B7 as GPO_HIGH
Configuring GPP_B7 as GPO_HIGH.
Sasuke doesn't have SAR sensor, GPP_B7 is routed to the LTE module
and is kept high so that the LTE module uses the default emission power.

BUG=b:180492044
BRANCH=firmware-dedede-13606.B
TEST="FW_NAME=sasuke emerge-dedede coreboot"

Change-Id: Ib38c649830db2291b3a2a771f5c884acf37dcbeb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51049
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-16 04:59:39 +00:00
Hung-Te Lin
46d05bcc4e mb/google/asurada: fix boot failure when reading SKU ID
The SKU IDs also need mapping table when reading voltages.

BUG=None
BRANCH=asurada
TEST=emerge-asurada coreboot

Change-Id: Ice91961d6c33cfa27254221663edca1547c9ddcc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-16 03:48:27 +00:00
Mathew King
00b490dd59 mb/google/guybrush: Add initial fch irq routing
BUG=b:181972598
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I1abb070324254e21b03bfe00d6eee3b70120564c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-16 02:33:38 +00:00
Mathew King
447cb44696 mb/google/guybrush: Enable eSPI VW SCI events
Guybrush does not have a dedicated SCI pin so it uses VW.

BUG=b:181134664
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I12fb7c23718ad2350478b89b321e9f0aa099e53b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51238
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 16:20:45 +00:00
Karthikeyan Ramasubramanian
913824c910 mb/google/dedede/var/magolor: Fix DPTF passive and critical policies
Some of the temperature sensors defined in baseboard do not exist in
magolor. With the format the DPTF policies are defined in magolor, all
the entries from the baseboard are included and then the overrides
applied. This causes the non-existent DPTF devices to be exported in
the ACPI table and in turn OS reading invalid temperatures. Fix the
format for DPTF passive and critical policies.

BUG=None
BRANCH=dedede
TEST=Build and boot to OS in magolor. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I43f0b188e49e24657db055ce898ce159d499a22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 16:08:43 +00:00
Karthikeyan Ramasubramanian
ab8961e7be mb/google/dedede/var/madoo: Fix DPTF passive and critical policies
Some of the temperature sensors defined in baseboard do not exist in
madoo. With the format the DPTF policies are defined in madoo, all the
entries from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI
table and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.

BUG=b:182513022
BRANCH=dedede
TEST=Build and boot to OS in madoo. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Idc5d0b357d61b9346b4d20ec8322b124c9655b4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 16:08:22 +00:00
Alexander Couzens
1295fa218f mb/supermicro/x11-lga1151-series: add support of X11SSH-LN4F to X11SSH-F
The X11SSH-LN4F and X11SSH-F are very similiar. They both use the same
PCB and use the same Supermicro BIOS ID. The X11SSH-LN4F has 4 NICs in
difference to the X11SSH-F which only has 2 NICs. The two additional
NICs aren't populated on the X11SSH-F. Enable the PCIe root ports
connected to the two additional Intel NICs.

Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Change-Id: Id4e66be47ceef75905ba760b8d5a14284e130f63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-15 09:45:23 +00:00
Patrick Rudolph
1d242799c2 mb/prodrive/hermes: Drop AZALIA_PLUGIN_SUPPORT
Already selected by SoC.

Change-Id: I1d941881f50350b6b581416a2e722ea2e7485a1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-15 06:32:00 +00:00
Tao Xia
b01a4c5757 mb/google/dedede/var/sasukette: Add USB2 PHY parameters
This change adds fine-tuned USB2 PHY parameters for sasukette.

BUG=180753635
TEST=Built and verified USB2 eye diagram test result

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5612e7dcca15b340763dee1475e979ee551a2146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:30:59 +00:00
Kevin Chang
80273918d5 mb/google/volteer/variant/lindar: Disable SA GV for Samsung memory with wrong date code MB
Disable SA GV, because factory used Samsung memory with wrong date code.
So we need to use board version to identify build MB phase to disable SA GV.
Disable SA GV when board version equal one.

BUG=b:179747696
BRANCH=firmware-volteer-13672.B
TEST=Built and booted into OS.

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I51f4adcf0dd8dbf1cf39d8aec6e4303565551e5f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:30:35 +00:00
Bora Guvendik
9d4d2d014c mb/intel/tglrvp: Enable RTD3 for WWAN
Enable the PCIe RTD3 driver for WWAN device attached to PCIe Root
Port 4 and provide the reset GPIO / src clk pin.

BUG=none
TEST=Boot to OS, verify the link is in L2 state during S0ix.

Change-Id: I669e02bd02e3af878648a6f3cf4fbb4d06c9857f
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2021-03-15 06:29:56 +00:00
chenzanxi
011e1b3fbc mb/google/dedede/var/storo: Support LTE module
Add LTE module support into devicetree and associated GPIO configuartion.

BUG=b:177955524
BRANCH=dedede
TEST=LTE function is OK

Change-Id: I9aff9608e08eae00ab5ac8547f63bc83b62fea78
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:28:59 +00:00
chenzanxi
46ee366216 mb/google/dedede/var/storo:Add P-sensor for storo
Add P-sensor into devicetree for storo according to
configuration information provided by the vendor.

BUG=b:177392203
BRANCH=dedede
TEST=built storo firmware and verified P-sensor function

Change-Id: Iced4ab7d94b38ef8b1807955cbb887454accb1e8
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-15 06:28:46 +00:00
chenzanxi
f8aa8dc248 mb/google/dedede/var/storo: Add codec and speaker amplifier support
Add audio codec and speaker amplifier support into devicetree

BUG=b:179057895
BRANCH=dedede
TEST=audio function is OK

Change-Id: Ia864ac47223adb80463966209f6ff3640b715378
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51003
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:28:32 +00:00
chenzanxi
c4691ab754 mb/google/dedede/var/storo: Add camera support
To support mipi camera.
1. enable DRIVERS_INTEL_MIPI_CAMERA/SOC_INTEL_COMMON_BLOCK_IPU
2. add IPU/VCM/NVM/CAM1 into devicetree
To support usb camera.
add camera support in devicetree and associated GPIO configuration.

BUG=b:177393430, b:177388006
TEST=Build and boot to OS. Camera function is OK.

Change-Id: I98d5708d1955406c2e46db972903057bb3d12dcc
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50995
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:28:18 +00:00
Da Lao
e325a4d0dc mb/lenovo/t440p: update VBT to version 2179
Update T440p's VBT from version 1215 to version 2179. Extracted
using VBiosFinder (https://github.com/coderobe/VBiosFinder)
from the latest bios update file:
https://download.lenovo.com/pccbbs/mobiles/gluj42us.iso

The new version solves the problem that DP output was broken
under Windows.

Test: boot t440p with both SeaBIOS and Tianocore payloads,
verify dp output and backlight control all works under both
Linux and Windows.

Signed-off-by: Da Lao <dalao@tutanota.com>
Change-Id: If8669b8de6fa0801e261138651b8b2cf50432a70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jamal Wright <Crabstorage@getbackinthe.kitchen>
2021-03-15 06:28:12 +00:00
Cliff Huang
3663fb36ec mb/intel/tglrvp/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: I8de5615235f24e6169bf67dbbadb92e69437bc4e
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50899
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:26:37 +00:00
Cliff Huang
2eee6c3a7d mb/google/volteer/variants: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add BT flag. There is no PCI host interface
in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS to make sure BT is
enumerated.

Change-Id: Ic700021d7a09be63ffc2715f31992257e2e893af
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50898
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:26:25 +00:00
Kenneth Chan
285f20a7f0 mb/google/hatch: Update DPTF parameters for genesis
update the DPTF parameters received from the thermal team.

BUG=b:181627614
TEST=emerge-ambassador coreboot

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ied6b71d9285662a70446af2e781b630e184c3b19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joe Tessler <jrt@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-03-15 06:25:29 +00:00
Cliff Huang
9b725cf311 mb/google/brya: Remove BT PCI interface and add BT flag
Remove the CNVi BT PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I7e8ca1bb6a57721a72478137612d7a9c391ca0b2
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:25:14 +00:00
Cliff Huang
b1a128fc88 mb/intel/adlrvp: Disable non-existing BT PCI interface and add BT flag
Remove the CNVi Bt PCI config and add Bt flag.
There is no PCI host interface in this version of CNVi.
TEST: BT is checked using 'lsusb -d 8087:0026' from OS.

Change-Id: I17c3e2761f91fb397d140d1954b6d4b451c4c603
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:24:56 +00:00
Bryant Ou
f6efeae66c mb/ocp/deltalake: Override uart base address via VPD variable
Use VPD of "coreboot_uart_io" to select uart io if
OVERRIDE_UART_FOR_CONSOLE is selected.

Tested=On OCP Delta Lake, console messages correctly output to uart
port which is defined in VPD.

Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Change-Id: I55a85d6f137ef1aba95466e7b094740b685bf9bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15 06:18:39 +00:00
FrankChu
f8b2d32ad9 mb/google/volteer: Create collis variant
Create the collis variant of the volteer reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:182227204
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COLLIS

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ibcf8b59b38d02517cea0a3ee474ff82fc0a2a958
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2021-03-15 06:18:27 +00:00
Meera Ravindranath
8dffc38f6e mb/intel/adlrvp_p: Support VBT for LP4, LP5 and DDR5 SKUs
Add support to pick the right vbt from cbfs according to
SKU-ID.

Change-Id: I8795cc67d87429eddb31328f1e2a90c346b53533
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:16:50 +00:00
Tim Chu
e82aa2238d mb/ocp/deltalake: Override SMBIOS type 2 feature flags
Override SMBIOS type 2 board feature flags. For Delta Lake, board is
replaceable and is a hosting board.

Tested=Execute "dmidecode -t 2" to check info is correct.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4469360ec51369dbf8179b3cbac0519ead7f0382
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
2021-03-15 06:12:40 +00:00
Eric Lai
4f4e86ec5e mb/google/mancomb: Configure non-native function GPIOs
Follow 20210308 schematic.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib259f3defc606c373f5ccac5f022d93e9a5c1469
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:11:54 +00:00
Eric Lai
0b18296ca0 mb/google/mancomb: First pass GPIO configuration
Follow 20210308 schematic.

BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1720ea8fec004d3ed3b3faaffa3b37dfcd710241
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:11:41 +00:00
Zhuohao Lee
e6f12d0d50 rammus: get cbfs sar table name based on the sku id
This patch overrides the get_wifi_sar_cbfs_filename()
to return different sar table according to the sku id.

BUG=b:173465272
TEST=checked bios log and the correct sar table was loaded.

Change-Id: Ia30d760b1a029197d470818c73bfd2c00514652d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-15 06:10:44 +00:00
hao_chou
a776ebb801 mb/google/volteer/variants/copano: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event.
Also setting gpio wake pin for wake events.

BUG=b:175519097
BRANCH=firmware-volteer-13672.B
TEST=build and verify on a Copano

Change-Id: Id0a132aa398abde4983af123d00e355ac61839a8
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51249
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:09:51 +00:00
Aamir Bohra
7f61e5703b mb/intel/shadowmountain: Add ACPI entry for BT reset GPIO
Change-Id: Ia9e57f34eceaf1925dc5e3ffa6370ba0241447a4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-03-15 06:09:27 +00:00
Kevin Chang
d2c4797891 mb/google/volteer: Add WiFi SAR table support for Lindar/Lillipup
Lindar/Lillipup uses the WIFI_SAR_ID field in FW_CONFIG to pick which
SAR table to load.

BUG=b:178302811
BRANCH=volteer
TEST=build and test no lindar/lillipup

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ibe829062033ba8246b9d9550cdcdc360f5f67dd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
2021-03-15 06:08:33 +00:00
Kevin Chang
1c02f6f088 mb/google/volteer/var/lindar: Add FW_CONFIG WIFI_SAR_ID fields in devicetree
Add FW_CONFIG WIFI_SAR_ID fields in devicetree.

BUG=b:178302811
BRANCH=volteer
TEST=build and test on lindar/lillipup

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I7ec37b80ffca6924f1f0952dcfbc43c378a70923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51386
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:08:19 +00:00
Eric Lai
1d6a13c7ee mb/google/octopus/var/fleex: Add RTL5682 support
Fleex will use SSFC to support RTL5682.

BUG=b:178653122
TEST=abuild

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icb06eabe297c5562bd2171b52cc9671c342e6dfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
2021-03-15 06:06:21 +00:00
Seunghwan Kim
e990f345c4 mb/google/dedede/var/sasuke: Update LTE GPIO configuration
Update GPP_A10 and GPP_H17 configuration to meet LTE power sequence
specification.
- FCPO (GPP_A10) should not turned off during warm reset.

BUG=b:177177967
BRANCH=dedede
TEST=Verified LTE power signal waveforms during powering on and off

Change-Id: I469f9c94ebd6bf2b68a0edc74f229158d82d0ef8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-15 06:05:18 +00:00
Felix Held
ec2cbecf93 mb/google/kahlee: remove get_gpe_table
Since no board overrides the weak get_gpe_table function,
gpe_configure_sci wasn't called for any variant, so drop the function.

TEST=none

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de204cc808449b625e1fa1e79fe653608e4b88a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-15 06:04:31 +00:00
Tim Wawrzynczak
8996b277ab mb/intel/adlrvp: Select ADL_ENABLE_USB4_PCIE_RESOURCES
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the adlrvp mainboard.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic56ebab02e50a466662a07d122d8f40eaf16b54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51461
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:03:55 +00:00
Tim Wawrzynczak
7b97289d56 mb/google/brya: Select ADL_ENABLE_USB4_PCIE_RESOURCES for brya0
This change select the Kconfig to pre-allocate the Intel-recommended bus
and memory resources per-PCIe TBT root port for the brya0 mainboard.

TEST=snippet from dmesg logs shows the correct resources being allocated:
   PCI: 00:07.0 resource base 27fc00000 size 1c000000 align 20 gran 20 limit 29bbfffff flags 60181202 index 24
   PCI: 00:07.0 resource base 83000000 size c200000 align 20 gran 20 limit 8f1fffff flags 60080202 index 20
   PCI: 00:07.1 resource base 29bc00000 size 1c000000 align 20 gran 20 limit 2b7bfffff flags 60181202 index 24
   PCI: 00:07.1 resource base a0000000 size c200000 align 20 gran 20 limit ac1fffff flags 60080202 index 20
   PCI: 00:07.2 resource base 2b7c00000 size 1c000000 align 20 gran 20 limit 2d3bfffff flags 60181202 index 24
   PCI: 00:07.2 resource base ac200000 size c200000 align 20 gran 20 limit b83fffff flags 60080202 index 20

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6b520ae50f19a730263de7918594718f3b4b1c1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51455
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:03:45 +00:00
Zanxi Chen
535d6d8cf1 mb/google/dedede/var/blipper: Enable touchpad support
Add touchpad into devicetree for blipper.

BUG=b:172787208
BRANCH=dedede
TEST=built blipper firmware and verified touchpad function
the kernel log: found RMI device, manufacturer: Synaptics

Change-Id: I2c9b61ba9d282f994e2f756bafe4af1091d4d617
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51188
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-15 06:01:49 +00:00
Kevin Chiu
ae5ab1826a Revert "mb/google/zork: restore stamp_boost parameter to 2500 for dirinboz"
This reverts commit 87a1bd696d.

Reason for revert: skin temperature is overheating due to boost time is too long

BUG=b:175364713
TEST=1. emerge-zork coreboot
     2. run balance performance and skin temperature test => pass

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I31db06f4bcb986398e7bd2ac2858ffbedb257e2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-15 05:20:48 +00:00
Hung-Te Lin
a79d6e76b8 mb/google/asurada: get SKU ID from AP strapping pins
The SKU ID for Asurada should come from AP ADC channel 5 and 6.

BUG=None
TEST=make; boots on asurada

Change-Id: I6a00c555f20aca4cd7f8bcee46ee81c17ef6ca3c
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-15 02:28:10 +00:00
Yidi Lin
2fcbebbbcd mb/google/asurada: revise PMIC and RTC initialization
Move the initialization from bootblock to romstage for following reasons:
- Follow MT8183 initialization sequence.
- PMIC and RTC functions are only called after verstage.
- Reduce bootblock size.
- PMIC initialization setting is complex and may need to be changed by
  an RW firmware update.

TEST=boot to kernel successfully

Change-Id: I3e4c3f918639590ffc73076450235771d06aae91
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xi Chen <xixi.chen@mediatek.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2021-03-15 02:27:57 +00:00
Mathew King
095bdecab3 mb/google/guybrush: Enable PCIe devices in devicetree
BUG=b:181690884
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8ceeb8db24be34588b370c13d865753f095e4be6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-14 19:11:42 +00:00
Martin Roth
de89e950a9 mb/google/guybrush: Add SPDs into build
This enables the standard library method of adding SPDs to CBFS.

BUG=b:178715165
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I2ec94fd866409e1dfa5cb65f6960ea07cbe22f2a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51022
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14 00:39:57 +00:00
Mathew King
60954722fa mb/google/guybrush: Enable EM100 support on guybrush
Add the option to build guybrush firmware with support for EM100.
This will assist in bringup of the new board.

BUG=b:180723776
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I2246d2952f341cd8fff8fd486cf989cdb7929411
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51071
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-14 00:39:45 +00:00
Raul E Rangel
88dbfa96e6 mb/amd/majolica,google/guybrush,google/mancomb: select HAVE_ACPI_RESUME
Since not all mainboards based on the Cezanne SoC have to support ACPI
resume, select this option in the mainboard's Kconfig and not in the
SoC's Kconfig.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I988276ccb5b61837d7f3f015d1d1aba783324b02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13 23:15:26 +00:00
Martin Roth
99f967b7a5 mb/google/guybrush: Add guybrush APCBs into build
This adds the Guybrush APCBs into the AMD firmware binary.

BUG=b:182510885
TEST=Build

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iba40cab1d68e9f8d7291e7d715be185a3b6249f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-13 02:48:16 +00:00
Mathew King
1ab35a7f50 mb/google/guybrush: Add ACPI support for Chrome EC
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Icb8aba87390475cad7a2a9911c3832a59c987b65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13 02:37:30 +00:00
Mathew King
d5baf6d89c mb/google/guybrush: Configure eSPI GPIOs in early stage
BUG=b:181961514, b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I0d22de977f09cbf46b28243d9f0c1e9a36e1398f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51295
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-13 01:31:47 +00:00
Mathew King
d490afbe04 mb/google/guybrush: Configure early GPIOs in earliest stage
Configure early GPIOs in verstage if it is run in PSP otherwise
configure them in bootblock.

BUG=b:181961514, b:180721208
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ib9410089592776ffe198901f2de914fd04bdbade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13 01:31:12 +00:00
Mathew King
7a8108deb9 mb/google/guybrush: Enable verstage
BUG=b:181961514
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I289a2ad1adc5dcc33c5863d6138f66b9b6dc6590
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-13 01:30:43 +00:00
Stanley Wu
105d91e114 mb/google/dedede/var/boten: Increase Goodix touchscreen reset delay to 180 ms
1. Follow GT7375P Programming Guide_Rev.0.6 to increase
   reset delay to 180ms.
2. Add TOUCH_RPT_EN pin(GPP_A11) control to fix TOUCH_RPT_EN pin
   keep high after system suspend.

BUG=b:181711141
TEST=Build and boot boten to OS.
     Confirm TOUCH_RPT_EN pin keep low after system suspend.

Change-Id: I98efbe68dab538906802647582eba0e068d9c11f
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51254
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 17:31:06 +00:00
Stanley Wu
5c4056dd02 mb/google/dedede/var/boten: Configure I2C5 p-sensor high and low time
Configure I2C bus 5 high and low time for p-sensor device.

BUG=b:181727056
TEST=Measured the I2C bus frequency reduce to 387 KHz.

Change-Id: I4b6d78d84b8ea145093f52bbb13684e2c6aa979c
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-12 17:30:26 +00:00
Angel Pons
18edd0008c soc/intel/braswell: Factor out common acpi_fill_madt
Function is identical for all mainboards, so factor it out.

Change-Id: Ibe08fa7ae19bfc238d09158309f0a9fdb31ad21c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50028
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 15:41:35 +00:00
Michael Niewöhner
2b5892256c mb/intel/adlrvp: do UART pad config at board-level
UART pad configuration should not be done in common code, because that
may cause short circuits, when the user sets a wrong UART index. Thus,
add the corresponding pads to the early UART gpio table for the board as
a first step. Common UART pad config code then gets dropped in CB:48829.

Also switch to `bootblock_mainboard_early_init` to configure the pads in
early bootblock before console initialization, to make the console work
as early as possible. The board does not do any other gpio configuration
in bootblock, so this should not influence behaviour in a negative way
(e.g. breaking overrides).

Change-Id: I55815a824ea3a77e6e603ba4beb17457f37c48f5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-12 08:47:53 +00:00
V Sowmya
8cb7af8e7c mb/intel/shadowmountain: Enable Type-C subsystem
This patch adds the changes to enable the TCSS.

BUG=b:175808146
TEST= Boot shadowmountain board, Test the functionality of the Type-C
ports on both the mainboard and daughterboard by plugging in the Type-C
devices and verified the devices are detected via EC console and in the
OS.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ieaf1170ca718a14d24b773a4a85516e0bbfbb569
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51026
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 04:26:39 +00:00
Stanley Wu
5a702653cd mb/google/dedede/var/boten: Adjust p-sensor detect distance to 20mm
P-sensor vendor fine-tune detect distance as 20mm for WWAN SAR table switch.

BUG=b:179000150
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
     un-approach:
       => register address: 0x01 value: 0x00
     approach:
       => register address: 0x01 value: 0x02
     Confirm WWAN SAR table work as expected.

Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I659721e60aa0766ed4c277dae43ded222e18ad1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51343
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-12 00:33:28 +00:00
Angel Pons
a70d17dba2 mb/system76/lemp9: Drop unneeded memcfg values and comments
This mainboard uses a Comet Lake SoC and mixed-topology DDR4 memory.
Drop LPDDR-specific DQ and DQS mappings and comment about Cannon Lake.

Change-Id: Icb986d1c074e64b3cfad3897b69d35d108f64bff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-03-11 17:12:25 +00:00
Eric Lai
4626a6684c mb/google/mancomb: Add eSPI configuration
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie3a3bb7526d734ae1936b8c4db43543b1174829d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:39 +00:00
Eric Lai
e6b3168ff1 mb/google/mancomb: Enable mancomb variant
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I554e7193494a4bbf005aaf2fb4efd6ded383fe07
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:29 +00:00
Eric Lai
b9204fc012 mb/google/mancomb: Enable console UART
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia03169c524dd12b8e7803ea8039c0e98a2b069e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:09:06 +00:00
Eric Lai
c23fa81e94 mb/google/mancomb: Enable ACPI tables
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I623fd052404a08cf0adb471bb654622960f1aa62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:08:51 +00:00
Eric Lai
6f06883856 mb/google/mancomb: Enable CONFIG_CHROMEOS
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45dcaa8b430721f864d4e5d78ae60883175085c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:41 +00:00
Eric Lai
6bb5b9a058 mb/google/mancomb: Add stubs to configure GPIOs
BUG=b:182211161
TEST=builds

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I7de5e4a4d2273d0ea5a84210ea0ce28d312eaa95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
2021-03-11 15:07:06 +00:00
Mathew King
238242bda4 mb/google/guybrush: Enable USB ports in devicetree
BUG=b:180529005
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I94d97a38d992f46b32c2c6aca4c8da688d3b76fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51257
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-11 01:17:40 +00:00
Mathew King
72cdbfa2f3 mb/amd/majolica: Enable USB ACPI in devicetree
BUG=b:180529005
TEST=boot majolica, all USB ports work

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I6d3506bb4d54c7f8ea1e53576ef68d2aface6c89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:17:09 +00:00
Mathew King
641690b7ae mb/google/guybrush: Enable Chrome EC SKUID and BOARDID
BUG=b:181910592
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7851d3b11ea3b026b999019d02df1144f8393753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-11 01:16:20 +00:00
Mathew King
454426d9d0 mb/google/guybrush: Log mainboard events to elog
BUG=b:180653357
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ifd43d9cc1832d8ed8d90c68ba88b5667e3c04f89
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-11 01:14:32 +00:00
Mathew King
78f0301ba4 mb/google/guybrush: Add chomeec device to lpc bridge
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I7b8b2ab73d66e0aaa0e9b7570661c885f7f777ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51296
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:49:11 +00:00
Kane Chen
807ce6258a mb/google/zork/var/shuboz: support regular/numpad touchpad
Define the 26th bit of the fw_config for the regular touchpad
and numpad touchpad selection.

REGULAR_TOUCHPAD: 1
NUMPAD_TOUCHPAD: 0

BUG=b:174964012
BRANCH=zork
TEST=build pass

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ie2055d6bb45a64bc0e59209cecc0f8a31c0f3718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:44:49 +00:00
Angel Pons
06b20ceb2f mb/{amd/padmelon,google/zork}: Do not select VGA_BIOS
The VGA BIOS for AMD Padmelon and Google Zork are stored in `amd_blobs`.
Do not force inclusion of VGA BIOS when `USE_AMD_BLOBS` is not enabled.

Change-Id: I206e8fadc14ec0d9b162dc4d72813fdd3d43958b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:42:53 +00:00
Angel Pons
83f9f8983b mainboard: Drop unnecessary VGA_BIOS default
This option defaults to n already.

Change-Id: I9f6407152f7cf2e2ac6fd1fff874e400f89a27ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-10 23:35:00 +00:00
Matt Papageorge
a37ec522e1 mb/amd/majolica: Update to use proper APCBs built for Majolica
Some of the previous binaries were incorrect and should not be used
for Majolica because they are templates instead of APCBs specifically
built for the board. This APCB update also places the UMA region under
4G and size 32 MB which is essential for video output.

TEST=Boot with UEFI BIOS and verify we can get to OS. Also verify memory
region size, base and alignment.

Change-Id: Id797e2ad5bd67815c09752aedc19dad7dcf8ad12
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:28:19 +00:00
Kane Chen
d3a767f47e mb/google/zork/var/shuboz: adjust I2C2 data hold time for TP
Add ".data_hold_time_ns" to follow I2C specification.
The adjusted result aobut 0.315us(more than 0.3us)

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Id92fadcb54b9722709e32ced1f0be001b8c97975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-10 23:10:30 +00:00
Mathew King
612e403d53 mb/google/zork: Use SOC defines instead of magic numbers
BUG=b:182269526
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I351fb4fc493bb92b31e2c8bc946dfb048045335c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-03-10 23:05:41 +00:00
John Su
2f67b34e12 mb/google/zork/var/vilboz: Add Mainboard Type for VCORE IC
To define Mainboard Type config, use the fw_config bit[26].
Check MB Type to modify SDLE settings for different VCORE IC.

BUG=b:177193131
BRANCH=zork

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: If153c0a3e641ae32ef89737925bd9f62dfb71f3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-10 23:04:32 +00:00
Chris Wang
216d69d459 mb/google/zork: add UPDM updating function before runing FSP-M
Add the UPD updating hook in early stage for customization.

BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.

Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 23:03:59 +00:00
Gwendal Grignou
689c25b9d6 drivers/i2c: sx9310: Replace register map with descriptive names
The current driver is using chip registers map to configure the SAR
sensor, which is opaque, especially when the datasheet is not published
widely.

Use more descriptive names, as defined in Linux kernel documentation at
https://www.kernel.org/doc/Documentation/devicetree/bindings/iio/proximity/semtech%2Csx9310.yaml

BUG=b:173341604
BRANCH=volteer
TEST=Dump all tables, check semtech property:
for i in $(find  /sys/firmware/acpi/tables/ -type f) ; do
 f=$(basename $i);  cat $i > /tmp/$f.dat ; iasl -d /tmp/$f.dat
done
In SSDT.dsl, we have:
Package (0x06)
 {
     Package (0x02)
     {
         "semtech,cs0-ground",
         Zero
     },
     Package (0x02)
     {
         "semtech,startup-sensor",
         Zero
     },
     Package (0x02)
     {
         "semtech,proxraw-strength",
         Zero
     },
     Package (0x02)
     {
         "semtech,avg-pos-strength",
         0x0200
     },
     Package (0x02)
     {
         "semtech,combined-sensors",
         Package (0x03)
         {
             Zero,
             One,
             0x02
         }
     },
     Package (0x02)
     {
         "semtech,resolution",
         "finest"
     }
 }

Change-Id: I8d1c81b56eaeef1dbb0f73c1d74c3a20e8b2fd7b
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-10 19:33:01 +00:00
Mathew King
ee10ce6268 mb/google/guybrush: Add smihandler
BUG=b:180507707
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I25ce0ca869ca854ff33242d2c416319e9688cc6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51264
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:38:23 +00:00
Mathew King
ad83023425 mb/google/guybrush: Enable Chrome EC
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I3cdd6422b1bc53ea934346327359cbc6d86baeeb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51043
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-10 00:35:06 +00:00
Tim Wawrzynczak
885e84eb4d mb/google/brya: Define ChromeOS GPIO support in ACPI tbales
Define the ChromeOS GPIOs (physical write-protect and virtual recovery
mode) in ACPI tables so the OS knows which physical pad is used for them.

BUG=b:181887865
TEST=flashrom_tester is able to "see" the WP GPIO

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I3feed366afd6507894a1d31304891cc785a4d314
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09 18:45:13 +00:00
Tim Wawrzynczak
659a591aa7 mb/google/brya: Reorganize flashmap
Intel ADL-P supports an additional memory-mapped 16MiB window into the
platform SPI flash. Support for this window already exists at the SoC
level, so all that is needed is to properly organize the flash map to
take advantage of this. FW_SECTION_A moves down to the bottom of the
available space in the lower 16MiB half, and FW_SECTION_B moves to the
bottom of the top 16MiB half. RW_LEGACY is squashed down to 2M.

BUG=b:182088676
TEST=build and boot to OS from FW_MAIN_A

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I60483b7e638c0a7e41f1f7e2b5503ae02e9906bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-09 18:45:00 +00:00
Yu-Ping Wu
3322d33e08 mb/google/asurada: Enlarge CONSOLE_CBMEM_BUFFER_SIZE
Enlarge CONSOLE_CBMEM_BUFFER_SIZE from 128K (default) to 512K, so that
more DRAM calibration logs can be stored in CBMEM console.

BUG=b:181933863
TEST=emerge-asurada coreboot
TEST="cbmem -c" shows the whole full calibration log
BRANCH=none

Change-Id: If82cbee5d2d5e97d98cbdaecda739d91a7cca0f8
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51275
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-09 08:14:26 +00:00
Eric Lai
c03ab47dc4 mb/google/octopus/var/fleex: Only check LTE sku on fleex
Fleex has other project share the same FW. Only fleex has LTE sku.
So we need to make sure it is fleex then check if LTE sku.

BUG=b:181946744
BRANCH=octopus
TEST=Check no SAR table can be loaded with sku id 4 and 5.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9f3d5fed4315fc716acad1a07735221d154c377e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
2021-03-09 03:38:47 +00:00
Raul E Rangel
8e6059db28 soc/amd,mb/google/,mb/amd: Move sleepstates.asl
This file is common for all the AMD platforms.

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08 23:30:38 +00:00
Julius Werner
9b1f3cc6fb cbfs: Pull handling of the CBFS_CACHE mem_pool into CBFS core
This patch pulls control of the memory pool serving allocations from the
CBFS_CACHE memlayout area into cbfs.c and makes it a core part of the
CBFS API. Previously, platforms would independently instantiate this as
part of boot_device_ro() (mostly through cbfs_spi.c). The new cbfs_cache
pool is exported as a global so these platforms can still use it to
directly back rdev_mmap() on their boot device, but the cbfs_cache can
now also use it to directly make allocations itself. This is used to
allow transparent decompression support in cbfs_map().

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0d52b6a8f582a81a19fd0fd663bb89eab55a49d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2021-03-08 22:31:29 +00:00
Mathew King
abc69712c2 mb/google/guybrush: Enable internal graphics
BUG=b:181809122
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I64475a475e9b72a6edd04ce0728591e0649d9f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-08 21:17:09 +00:00
Tim Wawrzynczak
96771fac9d mb/google/brya: Add Board and SKU ID support from Chrome EC
BUG=b:180456030
TEST=`mosys` is able to detect the platform correctly

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ifbaa4a380bdb546bb54d579b46fe5760b2f4b754
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-08 18:25:18 +00:00
Tim Wawrzynczak
c4e9c4e554 mb/google/brya: Finish support for ChromeOS GPIOs
BUG=b:181887865
TEST=`crossystem` shows correct state of WP signal when toggled

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If49ca1d70cc36ab74d70e858336679c0a9a3258e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-08 18:25:11 +00:00
Xi Chen
05764cd6c9 mb/google/asurada: Add generic DRAM groups
To reduce qualification effort, we want to pre-populate DRAM by their
size, package type and geometry so when a new DRAM is introduced we
don't need to spin off a new firmware release.

Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I42ee170c159e551e840ab4e748f18f5149506b4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-08 03:16:02 +00:00
Jessy Jiang
69da754112 mb/google/kukui: Add Micron 4GB discrete LPDDR4X DDR support
Support 4G+128G MT29VZZZAD9GQFSM-046 W.9S9 discrete DDR bootup.

BUG=b:162292216
BRANCH=kukui
TEST=Boots correctly on Kukui.

Signed-off-by: Jessy Jiang <jiangchao5@huaqin.corp-partner.google.com>
Change-Id: I5657a007154bc52c6f0f27e1de6e3294a5e74ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-03-08 01:49:33 +00:00
Furquan Shaikh
ab53c3964c mb/google/brya: Move GPE configuration to baseboard/devicetree.cb
This change moves GPE configuration from brya0/overridetree.cb to
baseboard/devicetree.cb since all variants will end up using the same
configuration.

TEST=Verified using "abuild -p none -t google/brya -b brya0
--timeless" that coreboot.rom generated with and without this change
is the same.

Change-Id: Ie31bf2bf8a91da82fca77c78fb0a735a2645de55
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-06 21:14:07 +00:00
Furquan Shaikh
a742681628 mb/google/brya: Fix MAINBOARD_PART_NUMBER
This change updates MAINBOARD_PART_NUMBER string to use uppercase for
first character. This matches what all others boards do.

BUG=b:180456030

Change-Id: I10eaeef5ec662a5718b787a3f0e3705cf70d751d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51297
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-06 21:13:55 +00:00
Tim Wawrzynczak
0c057c21e5 soc/intel/adl, mb/google/brya: Add IPU to devicetree
BUG=b:181843816

Change-Id: I25309a8f0900070a8307fbce90ccb6d47f9c3dfc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51261
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05 20:09:41 +00:00
Tim Wawrzynczak
e94a578039 mb/google/brya: Add IPU ASL to DSDT
BUG=b:181843816

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I74246cd0d2f866022604ec3e8a8d523c273cdef4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 20:09:30 +00:00
Tim Wawrzynczak
ba2e51bd49 mb/google/brya: brya0: Add ACPI support for Type-C ports
BUG=b:181160586, b:181843816

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic201ad047fd0d593749d2b993f843f7e188a5c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-05 20:09:15 +00:00
Brandon Breitenstein
7b42492bed mb/google/volteer: Configure tcss port information for early tcss init
Implement the mainboard_tcss_get_port_info weak function so that the TCSS
muxes can be properly configured to ensure mapping is correct in mux. This
ensures that any devices that are connected during boot are not improperly
configured by the Kernel.

BUG=b:180426950
BRANCH=firmare-volteer-13672.B
TEST= Verified that the SOC code that initialized TCSS muxes to disconnect
mode is executing properly for all TCSS ports and verified that USB3 devices
are no longer downgrading to USB2 speed if connected during boot.

Change-Id: I59e5c5a7d2ab5ef5293abe6c59c3a585b25f7b75
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-05 17:02:31 +00:00
Arthur Heymans
54c04d5536 sb/ti/pcixx12: Remove NOOP chip driver
Change-Id: I46bc854239e723a1685279f634e635b72e7b3af9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-03-05 10:58:33 +00:00
Zanxi Chen
7cdcf64f71 mb/google/dedede/var/blipper: Generate SPD ID for supported memory parts
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE

BUG=None
TEST=Build the blipper board.

Change-Id: Ia7e4c1d5c06013c1902816d6dcafb5a8a0386bb3
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-03-05 10:56:42 +00:00
John Su
99059d170a mb/google/zork/var/vilboz: Update telemetry settings
Update telemetry settings for vilboz.

VDD Slope : 26939 -> 27225
VDD Offset: 125   -> 187
SOC Slope : 20001 -> 26559
SOC Offset: 168   -> 89

BUG=b:177162553
BRANCH=zork
TEST=emerge-zork coreboot

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Iaf7c5083c4c5affec5ae0b5583efb5237e10d0ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: chris wang <Chris.Wang@amd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2021-03-05 04:47:36 +00:00
Nick Vaccaro
2f78ce0995 mb/google/volteer: Fix FPMCU pwr/rst gpio handling
1. No gpio control in bootblock
2. Power on and then deassert reset at the end of ramstage gpio
3. Disable power and assert reset when entering S5

On "reboot", the amount of time the power is disabled for is
equivalent to the amount of time between triggering  and wrapping
around to .

This change affects the following volteer variants that include an FPMCU:
  1. Drobit
  2. Eldrid
  3. Elemi
  4. Halvor
  5. Malefor
  6. Terrador
  7. Trondo
  8. Voema
  9. Volteer2
 10. Voxel

BUG=b:178094376
TEST=none

Change-Id: Ib51815349cea299907c10d6c56c27bd239e499e7
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-03-05 04:28:36 +00:00
hao_chou
b967c60dc7 mb/google/volteer/variants/copano: Describe USB ports in devicetree
Modify USB port to match schematics.
And assigned USB2 port to type-c use.

BUG=b:177481079
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Change-Id: I25412d16df8ad809c05635022c11bd8882d002c5
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49980
Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-04 08:47:40 +00:00
Frank Wu
edd748fdb3 mb/google/zork/var/vilboz: Update WiFi SAR for Vilboz
Loading wifi_sar-vilboz-1.hex for vilboz360 LTE sku for the present.

BUG=b:177684735, b:176168400
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage, then verify that tables are
in CBFS and loaded by iwlwifi driver.

Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I477b55d64fd9d33d753b10b2de443041a12d13e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-03-03 18:59:55 +00:00
Zheng Bao
2494aa952c mb/amd/majolica: Add eSPI support
Change-Id: I3e82a51173f561df560c36528a9b7ec26cf489b5
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-03-03 18:39:27 +00:00
Amanda Huang
b2f3151ed9 mb/google/brya: Add support for 2 new DRAM parts
1) Micron MT53E1G32D2NP-046
2) Micron MT53E2G32D4NQ-046

BUG=b:181378727
TEST=none

Change-Id: I413e35cdb7c34388c3e159f8f9584fae2d21a355
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 15:50:54 +00:00
Aamir Bohra
1d14ef25f3 mb/google/brya: fix BT enumeration issue
Current implementation exposes GPP_F4 cnvi reset pin as reset
gpio instead of GPP_D4(BT_DISABLE_L). GPP_F4 is native and driven
by SoC. It should not be driven by driver.

BUG=b:180875586

Change-Id: I589fc2b55ee2947cc638fe17540bbd24f5bfb8f4
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51178
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 15:22:14 +00:00
Paul Menzel
bd78c5a649 AGESA boards: Captilize ASL names
ASL+ Optimizing Compiler/Disassembler version 20200925 remarks:

        IASL       build/dsdt.aml

    Intel ACPI Component Architecture
    ASL+ Optimizing Compiler/Disassembler version 20200925
    Copyright (c) 2000 - 2020 Intel Corporation

    dsdt.asl    222:  Name(PSa, Package(){
    Remark   2182 -         ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (PSA_)

    dsdt.asl    228:  Name(APSa, Package(){
    Remark   2182 -          ^ At least one lower case letter found in NameSeg, ASL is case insensitive - converting to upper case (APSA)

Execute the command below to fix all occurences:

    git grep -l PSa | xargs sed -i 's/PSa/PSA/g'

Change-Id: Ia458c98a4774fb5745825aecf996a476e66eaa3f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:03:02 +00:00
Angel Pons
98521c51f4 soc/intel: Retype CnviBtAudioOffload devicetree option
The `FORCE_ENABLE` and `FORCE_DISABLE` names do not match what FSP UPDs
say, and can be confused with the `PchHdaTestPowerClockGating` UPD.

Replace the enum with a bool, and drop the confusing names. Note that
the enum for Ice Lake was incorrect, but no mainboards used the option.

Change-Id: I2c9b4c6a2f210ffca946ca196299fa672a06ccc7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51154
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:02:03 +00:00
Angel Pons
68b447c2f8 mb/purism/librem_mini: Implement die_notify
Make the SATA LED blink when coreboot dies. GPIO functions aren't
compiled in for postcar, so add a check to prevent linker failures.

TEST: Try to boot Librem Mini WHL without RAM, observe blinking (and
      also blinding LED). Re-install RAM (and re-seat RAM a few times),
      boot to OS, and observe SATA LED operating normally, as expected.

Change-Id: I0ffac0ab02e52e9fbba7990f401d87e50a1b5154
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50013
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-03 09:01:32 +00:00
Arthur Heymans
bab7f18a43 mb/*/*: Don't select PCIEXP_HOTPLUG
PCIEXP_HOTPLUG has a prompt and as such is not supposed to be forced.
Just change the default value to 'y'.

Change-Id: Ie4248700f5ab5168bff551b740d347713273763c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:01:04 +00:00
Arthur Heymans
8eb3a342d1 mb/{intel/d510mo,foxconn/d41s}/devicetree.cb: Remove PEG device
Pineview does not support PEG.

Change-Id: Ib0006dbd54e6f2031b97ed11ce61407ffcfa6244
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 09:00:08 +00:00
Arthur Heymans
0ba27fbc44 mb/intel/d510mo/devicetree.cb: Indent with tabs
This is a cosmetic change.
Make the formatting consistent with the rest of the tree.

Change-Id: Ic90e5584938592f1c2ab41edfcc773702822070d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-03-03 08:59:53 +00:00
Angel Pons
ebd4dfa53e mb/gigabyte: Add GA-D510UD
Booted fine on the first try. Most things work properly, but I haven't
tested them thoroughly. Native raminit chokes with a DIMM in the second
slot, but the first slot works properly.

Change-Id: I2126c7d31e0d8a8f80df69fdcdcd202b87f219a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-03 08:59:36 +00:00
Karthikeyan Ramasubramanian
e8e5107b49 mb/google/dedede/var/drawcia: Re-tune override GPIO table
There is going to be an upcoming board version for Drawlat/man and
Drawcia. Hence apply the override GPIO table without pad termination for
board versions 6 or 8 alone.

BUG=None
BRANCH=dedede
TEST=Build and boot to OS in Drawcia.

Change-Id: I320de9a0c37ac033f3efda74eeb8f36e34667fd4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Evan Green <evgreen@chromium.org>
2021-03-03 05:27:57 +00:00
Martin Roth
7221830894 mb/google/guybrush: Add SPDs to build for Guybrush variant
These files were automatically generated by the lpddr4 version of
gen_part_id.go.

BUG=b:178715165
TEST=Build

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3797ba6d52248961418000614a4f7885182521a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 03:47:47 +00:00
Martin Roth
dd25dffa1d mb/google/guybrush: Add generated LPDDR4x SPDs
These SPDs were generated by the lpddr4 version of gen_spd.go from the
global_lp4x_mem_parts.json.txt file.

BUG=b:178715165
TEST=None

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I7b9bd04534d6e45dbfe10a0028052978ef3d7c17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-03-03 03:47:36 +00:00
Julius Werner
d5c8a15d74 google/trogdor: Fix trogdor-rev1 eDP power GPIO
Looks like I forgot about trogdor-rev1 in CB:51004. Unlike rev0 (other
special case) or rev2 (works like CoachZ/Homestar), rev1 used the same
pin as Lazor and Pompom for EN_PP3300_DX_EDP. Apparently there are still
some people using these, so add in another special case for that.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7093aa63778d69fde240af3b0c62b97ac99c28dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51196
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02 23:14:06 +00:00
Mathew King
c8c83ce027 mb/amd/majolica: Enable required devices in devicetree
Most devices are now disabled by default in the chipset. Enable the
iGPU and two XHCI controllers that are required to boot the board.

BUG=b:180528708
TEST=To be tested

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I54a4547217fb8e9f67fc0c8e1e36e96dfaae331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51095
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02 17:28:37 +00:00
Mathew King
22b5ef961c mb/google/guybrush: Set up FW_CONFIG fields
BUG=b:180523962
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic8f30f6d7c4781d4e8451546b39395a74393608f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2021-03-02 17:11:13 +00:00
Mathew King
c44cc19079 mb/google/guybrush: Add eSPI configuration
BUG=b:180507937
TEST=builds

Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Ic607d6bca5c70255332a6fbee2b63e6daba7d1e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02 17:04:59 +00:00
Tim Wawrzynczak
37c332782a mb/google/brya: Fix a few mistakes in brya0 overridetree
1) Both SAR sensors had a UID of `2`, making them indistinguishable
2) No `device` underneath max98357a `chip`

Change-Id: Icf586229532819a7779652cbee73755b036dfbdc
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51145
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-02 16:59:44 +00:00
Nico Huber
3173f857b6 mb/lenovo/x200: Fix docking events
Even though `device` entries are children of `chip` entries in the
devicetree source format, the chips in the translated C structures
are only hooked up to device nodes. Hence, to configure a chip in
a device- or overridetree, it always needs a `device` below it.

This should fix docking events for the X200 ThinkPad.

Change-Id: I561e7ae81f2e096a091868ce51daa1c8f66af067
Signed-off-by: Nico Huber <nico.h@gmx.de>
Found-by: Kevin Keijzer <kevin@quietlife.nl>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kevin Keijzer
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-03-02 12:17:14 +00:00
Mathew King
1037e34123 mb/google/guybrush: Add option to toggle GPIO for sign of life
Enabling the GPIO_SIGN_OF_LIFE option will allow for early boot testing.

BUG=b:180721202
TEST=builds

Change-Id: I069623ae76a4e4d1e43a47dd95fdfcece398ebfb
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-03-02 06:31:03 +00:00
Angel Pons
6bd99f9ada soc/intel/skylake: Clean up SD GPIO handling
This is to align with newer platforms.

Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 19:37:36 +00:00
Kane Chen
13818f5c5c mb/google/zork/var/shuboz: Decrease I2C3 CLK below 400 kHz
Modify I2C3 setting to follow I2C specification (lower than 400kHz).
Original setting:
.rise_time_ns = 184
.fall_time_ns = 42

Change to:
.rise_time_ns = 110
.fall_time_ns = 34

BUG=b:181091107
BRANCH=zork
TEST=emerge-zork coreboot chromeos-bootimage

Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ibdbb9a7dde524bdbde4789ee7ea005646080d97a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01 08:32:06 +00:00
Kyösti Mälkki
95be98ac2a mb/: Drop print of MAINBOARD_PART_NUMBER
Change-Id: Ie3870bc666acaea316f00b205de512cf790e720c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2021-03-01 08:22:37 +00:00
Angel Pons
6e82ebff73 mb/ocp/deltalake: Fill ECC type in romstage
Fill the ECC type in `struct memory_info` in romstage, and in SoC code.
The SMBIOS override is unnecessary, and this is not mainboard-specific.

Change-Id: I8370b3ee7d75914b895946b53923598adf87b522
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50179
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 08:22:28 +00:00
Tao Xia
bda338a1be mb/google/dedede/var/sasukette: Configure I2C times for touchpad/codec/AMP
Configure I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).

Measured I2C frequency just as below after tuning:
touchpad:372 kHz
audio codec RT5682:386.8 kHz
speaker AMP L:387.5 kHz
speaker AMP R:388.9 kHz

BUG=b:181342340
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz

Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I05d78c088190e349281a34b2aeed39ae8d867dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 08:21:10 +00:00
chenzanxi
a03b18012d mb/google/dedede/var/storo: Enable ELAN touchscreen
Add ELAN touchscreen into devicetree for storo.

BUG=b:177389448
BRANCH=dedede
TEST=built storo firmware and verified touchscreen function

Change-Id: I0d9e5005928c6fda3d1f0ce8bd9ae135e4a04867
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50981
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-03-01 08:20:49 +00:00
Tony Huang
5f5ea02b3d mb/google/dedede/var/kracko: Add elan touchscreen support
BUG=b:177834652
BRANCH=dedede
TEST=build kracko firmware

Change-Id: I360920f80f4ce5dcbcde25c433e23803fa72569b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-27 09:41:22 +00:00
V Sowmya
cfb1bf2275 mb/intel/shadowmountain: Add the ASL code
This reverts commit d510b60f5b.

This patch includes the DSDT ASL code for shadowmountain board.

BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I5aa60730fc9b93fa97b2bafbb8b2714b6b37becc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27 09:40:57 +00:00
V Sowmya
ae930d85c2 mb/intel/shadowmountain: Add the ramstage code
This patch includes the ramstage changes for the
shadowmountain board.

BUG=b:175808146
TEST= Build and boot shadowmountain board.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I419eecefddf9ee6e4249ada041ebeb1b78e85eb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49732
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27 09:40:47 +00:00
Eric Lai
dcb14c63af mb/google/brya: add HAS_RECOVERY_MRC_CACHE flag
Brya’s chromeos.fmd contains a region for RECOVERY_MRC_CACHE,
but does not select HAS_RECOVERY_MRC_CACHE, so it’s unused.

BUG=b:174266035
TEST=Check MRC cache can allocate in recovery mode.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I6b83eec3dcf27bafde610a701e55f1371a5d4571
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51081
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-27 09:38:32 +00:00
Joel Kitching
a904fd6173 vboot: update GBB flags to use altfw terminology
As per CL:2641346, update GBB flag names:
  GBB_FLAG_FORCE_DEV_BOOT_LEGACY -> GBB_FLAG_FORCE_DEV_BOOT_ALTFW
  GBB_FLAG_DEFAULT_DEV_BOOT_LEGACY -> GBB_FLAG_DEFAULT_DEV_BOOT_ALTFW

BUG=b:179458327
TEST=make clean && make test-abuild
BRANCH=none

Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I0ac5c9fde5a175f8844e9006bb18f792923f4f6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-02-27 09:37:49 +00:00
Wisley Chen
332da01c89 mb/google/volteer/var/elemi: Configure IRQ as level triggered for elan_ts
Follow elan's suggestion to configure IRQ as level trigger to prevent touchscreen lost

BUG=b:180778934
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot

Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I3aca0ad20791c989dec9e70d69d637b28c9cc043
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50417
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26 21:24:45 +00:00
Nick Vaccaro
3865a33231 mb/google/volteer: add variant_ramstage_init()
Add a weak variant routine to allow variants to perform any needed
initialization in ramstage.

BUG=b:178094376
TEST=none

Change-Id: I65dc1cdf15b68d9f2239e02fcb4b2c902d749378
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50827
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26 07:30:42 +00:00
Stanley Wu
e8118acfbe mb/google/dedede/var/boten: route GPP_E11 via APIC
GPP_E11 should be configured to be routed via APIC to avoid
p-sensor communication error in OS.

BUG=b:178465379
BRANCH=dedede
TEST=run "i2cdump -y -f 15 0x28" to confirm registers as expected.
       un-approach:
         => register address: 0x01 value: 0x00
       approach:
         => register address: 0x01 value: 0x02
     verify sx932x IRQ in "/proc/interrupts" loading as expected.

Change-Id: I7d639ec1f9b31b240475dc1c8025bf59ae1e8e0b
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50876
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-02-26 07:29:51 +00:00
chenzanxi
f7407eaf02 mb/google/dedede: Create blipper variant
Create the blipper variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:179648964
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BLIPPER

Signed-off-by: chenzanxi <chenzanxi@huaqin.corp-partner.google.com>
Change-Id: I8e67521bd9ab05c257cb3d5d5d4cf506f258bfa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-02-26 07:07:57 +00:00