Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug, so there is no need to specify a MMIO address for the early EHCI
BAR configuration.
Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug.
Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add code to collect all required information and generate ACPI CRAT
table entries. Publish tables generated from cb, rather than use the
tables created by FSP binary.
BUG=b:155307433
TEST=Boot trembyle and compare coreboot generated tables with tables
that FSP published previously.
BRANCH=Zork
Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This struct isn't used anywhere else, so there's no need to name it.
Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are no longer really useful. We can also enable Power Resource
ACPI debug in the kernel if we want these messages.
BUG=none
BRANCH=zork
TEST=emerge-zork and verify debug messages are no longer posted
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I936e816266825f1c59377c2e079ffe1a5188838c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This will result in less code duplication when the common AMD SoC UART
support gets used for more AMD SoCs.
Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 6f8f9c969b
by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since
the number and base addresses of UARTs turned out to be rather SoC-
specific. The help text for the AMD_SOC_CONSOLE_UART option also
contained those base addresses, so remove that as well.
Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.
In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.
The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.
TEST=SoC UART console still works on Mandolin.
Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is causing boot errors on zork:
coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.
Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.
BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly
generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.
BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The set_resources field in the root_complex_operations struct shouldn't
be NULL, but a pointer to noop_set_resources instead. This fixes the
error "PCI: 00:00.0 missing set_resources".
Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move CPUID definitions out of msr.h into new cpuid.h header.
BUG=b:155307433
BRANCH=Zork
Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
GEVENT_MASK should cover all GEVENT pins, but was missing
SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8.
Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.
The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.
Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.
Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new helper function to support reading a register from the data
fabric.
BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork
Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP integration code needs this function to be present. It's not
supposed to be called, but if it is, it'll print an error and call the
SoC's cold reset function.
Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
all-y will also add a compilation unit to the verstage on PSP build that
runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't
have verstage on PSP support yet, but since it'll eventually land it
doesn't hurt to already add the comment now.
Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since aoac gets also linked into verstage on PSP, all-y can be used
here.
Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if
PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in
this case.
Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.
Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.
According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR
BUG=b:159823235
BRANCH=zork
TEST=build zork
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.
Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.
Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace sb prefix with fch prefix, since those are all FCHs and no south
bridges any more. Verstage on PSP uses the I/O access mechanism instead
of the MMIO one, so keep a separate function for that, but also move it
to the common mmio_util file to have them all in one place.
Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO
code block that actually gets used. Also fix the indentation of the
ACPIMMIO register decode defines in the common code.
Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now pci_domain_ops in chip.c can also be marked as static.
Change-Id: Ia92b778a5882d991b391dc29aeee0a5615677913
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48315
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since config.c also gets linked into verstage on PSP and not only into
the stages running on the x86 cores, use all-y instead of adding
config.c to all classes separately.
Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.
Also replace the base GPIO address with the corresponding define.
Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At least a part or the remaining definitions in the soc-specific smi.h
files are also common, but those have to be verified more closely.
Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The patch also rewrites the bit definition using shifts to make them
easier to read.
The older non-SoC chips can probably also use the new header file, but
for this patch the scope is limited to soc/amd, since the older non-SoC
chips don't use the SMBUS controller code in soc/amd/common.
TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change.
Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The register locations and bit definitions are the same for Stoneyridge
and Picasso. Since not all devices are present on all SoCs, keep those
numbers in the SoC-specific code.
Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that the initial version of the Picasso FSP binaries have finally
landed, we can set the default paths to point to them now.
Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42472
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The numbers in the array are unsigned, so use an unsigned type there.
Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit,
so the comment should be that it powers off the devices.
Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in
the corresponding SoC code, so remove it from the SoC's Kconfig and
reanme it in the mainboard's Kconfig to MANDOLIN_LPC.
Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding functionality in the SoC's Makefile.inc was removed in
commit ef3395d990
Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There's no need to have the bootblock in its own sub-directory, so move
it to each SoC's main directory to avoid clutter. This makes soc/amd
more consistent with the coreboot code base in src/northbridge,
src/southbridge and src/soc with the exception of src/soc/intel.
Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There will be more files added to the common non-CAR Makefile.inc, so
use an ifeq statement there.
Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Different models within family 17h have different PCI IDs for their PCIe
GPP port and internal bus devices.
Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Different models within family 17h have different PCI IDs for their data
fabric PCI devices.
Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In the file uintptr_t that is defined in stdint.h and struct device that
is defined in device/device.h are used, so include them directly to
avoid having to rely on them being included in the file that includes
this header file.
Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This also reduces the difference to the equivalent file from
stoneyridge.
Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47581
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.
Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This prototype will be used outside of soc/amd.
Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.
Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls. By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increasing the vboot hash buffer size greatly speeds up the SHA
calculations. Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.
Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize timestamp table with data from psp_verstage on bootblock.
PSP keeps its own timestamp and pass it in transfer_buffer. However PSP
timestamp and TSC may be out of sync so we can't just merge two tables
without modification.
info->timestamp contains PSP's clock value (in us) when x86 processor
released and base_timestamp contains TSC value when bootblock is
started. The time between x86 release and bootblock entry should be very
short so we can think those two happened at the same time and use them
for sync.
In some cases there will be underflow in timestamp entries but cbmem
utility can handle wrap-over in entries. Few timestamp values including
1st timestamp can be very large but we can still get the time spent on
boot without any problem.
BUG=b:159220781, b:167148121, b:171422583
BRANCH=zork
TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are
included in the result.
Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Zork(picasso) platform we run verstage on the PSP. It has its own
timer, but the frequency is not matched with TSC.
To ease the work to merge timestamps from the PSP and TSC, add a layer
around tsc to have microsecond granularity for timestamp table. PSP
already records timestamp in microseconds.
BUG=b:159220781
BRANCH=zork
TEST=build, flash and boot, check timestamps are correct
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46058
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.
BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.
BUG=None
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented. The trigger address must be an SMI trigger
register. Assign one of the reserved triggers to the PSP.
The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.
This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP. The call only exists so the PSP will
honor a mailbox command during S3 suspend.
BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to
correctly enable backlight in OS for zork.
BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I702f807a5907d85d083295cf339ba9d31b246627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove all typedefs and cleanup references to all structs and enums.
BUG=b:159061802
TEST=Boot morphius to shell.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Picasso build describes the DRAM region where the PSP places
our bootblock. Rather than relying on Kconfig values, make the build
more robust by using the actual size and target base address
from the boot block's ELF file.
Sample output of "readelf -l bootblock.elf" is:
------------------
Elf file type is EXEC (Executable file)
Entry point 0x203fff0
There is 1 program header, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .data .bss .reset
------------------
We can extract the information from here.
BUG=b:154957411
TEST=Build & boot on mandolin
Change-Id: I5a26047726f897c57325387cb304fddbc73f6504
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP does not accept the SmmInfo command during a resume so
remove the call.
BUG=b:163017485
TEST=Run SST on trembyle, verify error message goes away
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the base address. This should have no noticeable effect,
as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The
argument writes were not getting to any target.
BUG=b:171037051
TEST=Run SST on morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp.
Instead of using hardware acceleration for whole RSA process,
acclerating only calculation part(modexp) increases transparency
without affecting boot time.
BUG=b:169157796
BRANCH=zork
TEST=build and flash, check time spent on RSA is not changed
Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead.
The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1.
Now variant can use the usb3_port_force_gen1 to customize which port
it needs to limit.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The PSP will now pass us data on the PSP boot mode and the production
silicon level. Print these values out to save in the log.
These definitions are in a vendorcode include directory that was
previously only included in verstage. Add the include directory
to all stages.
BUG=b:170237834
TEST=Build & Boot - See values printed.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The transfer buffer check had gotten large enough to deserve a function
of its own, so break it out.
BUG=None
TEST=Build
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:169199392
TEST=Corrupt vboot signature to force an error, see that the system
halts instead of rebooting forever.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
psp_verstage uses separate printk implementation, which does not include
code to add console output to cbmem.
Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem.
BUG=b:159220781
TEST=build
BRANCH=zork
Change-Id: I63ba5814903565c372dbeb50004565a371dad730
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
BRANCH=zork
TEST=build verstage for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The PSP will be adding information into these fields after verstage
runs. This allows data to be passed directly to coreboot very early
in the boot process.
BUG=b:168895748
TEST=None
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows passing in the presets to FSP.
I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.
BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork
Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.
BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
add dptc support for different power parameter on tablet/clamshell mode
The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing the BIOS to request power state changes independently of specific
events.
BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The register number is always non-negative, so it should be an unsigned
type.
Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.
Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.
Use method from dram/ddr4.c instead.
BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
and dmidecode -t17
BRANCH=Zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This I/O region is already covered by the range declared right above the
deleted one.
TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork
Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.
This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.
Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.
BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The AOAC device number is never negative, so make it unsigned.
BRANCH=zork
Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
