This commit creates an ampton variant for Octopus. The initial settings
are copied from Bip, but the following changes are made to support
hardware differences:
* GPIO_66 is not connected (LTE).
* GPIO_67 is not connected (LTE).
* Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet.
* GPIO_143 is not connected.
* GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected.
* EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146.
* GPIO_213 is not connected.
* GPIO_214 is not connected.
BUG=b:111498206
TEST=None
Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for
the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL.
BUG=none
TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake
boards and also check the margin data is proper in FSP.
Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28568
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch,
depthcharge will fail to tell if the EC firmware is RW.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC_IN_RW GPIO.
Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28670
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved
to DMIC0.
BUG=b:113744731,b:111106010
TEST=none
Change-Id: I8ef42627e542182707c81389af9da33a114bc184
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28689
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt variants need a way to customize the mainboard vendor based on the
platform. For future boards, this can probably be done via CBI, but
grunt doesn't support that method.
BUG=b:79874904
TEST=Build, boot, see updated mainboard vendor
Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/28651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@google.com>
Update Power Limit1 and Power Limit2 values along with stepsize.
Correct the charger effect for Temperature sensor2.
BUG=b:112448519
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28530
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT.
BUG=b:115965629
TEST=verified it in meep proto board which rework ram id.
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363
Reviewed-on: https://review.coreboot.org/28658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
AMD has tested careena, and for the time being is recommending a scalar
of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM
configuration code, set the desired values.
BUG=b:111561217
TEST=none, code was tested with grunt.
Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
While the pin was set to a pull-down, with the external pull-up, this
wasn't enough to keep the pin low. Set to output low to drive to 0V.
TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V.
BUG=b:115661061
Change-Id: Ife014b8a879274df5d892c1de386976808de1df0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Default STAPM percentage causes a lot of thermal throttling on grunt.
AMD experimented with 80%, it works for grunt. This is initial code to
provide easy change path for other grunt based platforms.
BUG=b:111608748
TEST=build and boot grunt.
Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron,
with the following changes:
- add buddy-specific variant code
- add handling to auron for buddy's lan init, which no other variants have
- add handling to auron's mainboard ACPI due buddy having different PCIe
port assigments than all other variants
Ported from Chromium branch firmware-buddy-6301.202.B, commit
ebb82ce [Buddy: Lock management engine + SPI descriptor]
Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads
Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use an empty weak function for variant_romstage_entry(), rather than
having separate empty functions for boards which don't utilize it.
Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Set up EMMC gpios for payloads.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and
CIO2 devices to avoid the system failed to enter S0ix.
BUG=b:114502527
BRANCH=master
TEST=On DUT, echo freeze > /sys/power/state
1. check the S0ix status on EC console
2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec
Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side,
pad R23) that is supposed to be high in S0, and low in S3 (and X/don't
care in S5).
This should be set as early as possible in bootblock.
BUG=b:113367227
TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high.
BRANCH=None
Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
This patch sets the MRC UPD CmdTriStateDis for the atlas boards.
Atlas is a LPDDR3 design without RTT for CMD/CTRL.
The original change for
nocturne is I0f593761dcbd121e7e758421af178931b9d78295
mb/google/poppy: Set UPD CmdTriStateDis for Nocturne
BUG=b:111812662
Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The board version is part of EC's EEPROM, but is not being populated
from EEPROM. Instead a default Kconfig parameter is returned as board
version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable
requesting the EC for board version.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This modification for DVT build and use CBI method
enable all memory particles.
BUG=b:112870780
TEST=verify it under the EVT unit and pre-test EVT
unit(rework RAM ID follow the proposal) respectively.
Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Only for those that are x86 and also have a RW_LEGACY region.
The assumption is that all devices touched have 64k block sizes when
choosing size and alignment of the region.
Change-Id: I12addb137604f003d1296f34f555dae219330b18
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On rammus, headset uses DA7219 so that we need to enable it.
BUG=b:112945714
BRANCH=master
TEST=emerge-rammus coreboot chromeos-bootimage
Flash FW and check in kernel to see if DA7219 is up.
Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45
Signed-off-by: marxwang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28537
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the MRC UPD CmdTriStateDis for the
nocturne boards.Nocturne is LPDDR3 design without RTT
for CMD/CTRL.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: I0f593761dcbd121e7e758421af178931b9d78295
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28379
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md
Copy ChromeOS VPD driver to add support for VPD without CROMEOS.
Possible use case:
* Storing calibration data
* Storing MAC address
* Storing serial
* Storing boot options
+ Now it's possible to define the VPD space by choosing
one of the following enums: VPD_ANY, VPD_RW, VPD_RO.
+ CHROMEOS selects now VPD as part of it.
+ VPD is implemented as driver.
Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25046
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD chips don't hold off a reset to the end of I2C transitions, so
devices on the i2c bus can be left in a bad state. To avoid this,
make sure the trackpad and touchscreen chips get disabled
during boot.
BUG=b:114411165
TEST=build, reboot watch trackpad enable go low
Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28538
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and
clock#4.
BUG=b:113369699
TEST=booted on atlas
Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change configures GPIO_63 (which is used for H1 interrupts) as Rx
Level. This ensures that the signal gets passed on to the next logic
state as is and the APIC entry can be configured to trigger interrupt
on level or edge as per the kernel driver expectation.
TEST=Verified that no H1 interrupt timeouts are seen with 100
iterations of warm and 100 iterations of cold reboot.
Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On rammus, system halt was observed because of gspi clk value being set to 0.
Log info from serial coreboot:
FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes)
SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000
VBNV: Restore from flash failed
ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443
gspi.c
442
443 assert(gspi_clk_mhz != 0);
444 assert(ref_clk_mhz != 0);
445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK;
BUG=none
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure system boots up.
Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28405
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus-Wifi with m3 AP got a halt issue during CTS test.
Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was
validated only with Celeron. Since Celeron deos not support turbo
boost mode, its steady power demend and lower CPU frequency may not
reflect the potential noise hidden inside the board.
Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the
potential noise coupling to VCC_GT/SA, and we verified this change
makes this issue go away on Nautilus-Wifi board.
Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have
better grounding and less noise/ripple than 8L PCB.
BUG=b:111417632
BRANCH=poppy
TEST=Verified CTS test pass without an issue.
Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the mainboard.c in order to support the sku id in smbios
table where the sku id is queried from the eeprom via EC.
BUG=b:113714761
BRANCH=master
TEST=check the result of 'dmidecode'
Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node.
Without DRIVERS_SPI_ACPI, the kernel will popped out the below error:
cr50-update[592]: Starting cr50 update
cr50_get_name[595]: updater is /usr/sbin/gsctool -s
cr50-update[609]: exit status: 3
cr50-update[613]: output: Could not open TPM: No such file or directory
cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod'
cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod
cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state
cr50-update[682]: not running
cr50-result[782]: Not running normal image. Skip setting Board ID
trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory
BUG=none
BRANCH=master
TEST=/dev/tpm0 is created
Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/28400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable Synaptics touchpad device for liara
BUG=b:113309346
BRANCH=master
TEST=Verify touchpad on liara works with this change
Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch overhauls the Cheza FMAP, removing some sections we don't
seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of
RW_DDR_TRAINING), and adding new sections we're going to need soon or
should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY).
Make more use of implicit offsets and sizes, because we can and because
it should make future adjustments easier.
Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: T Michael Turney <mturney@codeaurora.org>
Also removed internal pull ups for CX_PREQ_L and
CX_PREQ_L signals as they have external pull ups.
BUG=b:110654510
TEST=On Yorp Proto 2, flashed image and verified that it boots to OS.
Checked Wake-on-Wifi works with both cnvi and pcie modules.
Also executed a few suspend resume cycles.
Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/28328
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt takes a few seconds to update the EC, so display a notification
screen while that's happening.
BUG=b:113286040
TEST=Boot Grunt with old EC firmware, see update screen
Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to
make the infrasturture to handle both LPDDR4 and DDR4 cases in the
future. Consider the case of reading SPD from SMBus other than providing
SPD pointer directly.
BUG=N/A
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28248
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set EC SPI bus config and init SPI bus according to the config.
BUG=b:80501386
BRANCH=none
TEST=EC is not working yet. This makes depthcharge go forward a little.
Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28251
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set up EC interrupt GPIO to boot depthcharge. Without this patch,
depthcharge will fail to detect EC interrupt GPIO.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and see in logs, that depthcharge detects
EC interrupt GPIO.
Change-Id: I0ec2c70c189a059219954e0384aaf98995285728
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Bayhub eMMC controller default runs SD base 50MHz at the first power on.
After boot into OS, mmc kernel driver will config controller to HS200/208MHz
and send MMC CMD21 (tuning block).
But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear
after system warm reset.
So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge.
It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to
load kernel and trap in 0x5B error (No bootable kernel found on disk).
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:113101335
BRANCH=atlas
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU0: Package temperature above threshold'
Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619
Reviewed-on: https://review.coreboot.org/28325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reduce the CPU passive threshold sample rate from 5 seconds to 1
second so DPTF will react faster to rapid temperature increases.
Signed-off-by: Todd Broch <tbroch@chromium.org>
BUG=b:67459049
BRANCH=nocturne
TEST=manual performance/power testing on nocturne.
No longer see messages like below in syslog,
'CPU3: Package temperature above threshold'
Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458
Reviewed-on: https://review.coreboot.org/28324
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update TSR1 trip point from 48C to 50C.
Also, change power limit2 minimum value from 8W to 10W.
These are the values as per recent thermal tuning.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/28187
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit fixes the values and thus fixes the issue of
audio device not getting detected on random reboots.
Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.
Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Change PL1 from 4.5W to 7W, based on thermal test results.
BRANCH=eve
BUG=b:73133864
TEST=Verify the MSR PL1 limitation is set to 7W.
Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad
Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28078
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is meant to solve an issue where the proximity sensor may fluctuate
between CLOSE / FAR in rapid succession upon the user removing their hand
from the unit, before settling on the correct output.
Using the hardware debouncing filter solves this issue and removes the
spurious fluctuations.
BRANCH=None
BUG=None
TEST=manual on Nocturne, observing events come in
Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/28112
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix scope of ResourceSource, which should match the scope of the
device itself.
Change-Id: I9d0ff0ecc2721ec55b1ed12dddb495cd55966daf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The romstage main() entry point on arm64 boards is usually in mainboard
code, but there are a handful of lines that are always needed in there
and not really mainboard specific (or chipset specific). We keep arguing
every once in a while that this isn't ideal, so rather than arguing any
longer let's just fix it. This patch moves the main() function into arch
code with callbacks that the platform can hook into. (This approach can
probably be expanded onto other architectures, so when that happens this
file should move into src/lib.)
Tested on Cheza and Kevin. I think the approach is straight-forward
enough that we can take this without testing every board. (Note that in
a few cases, this delays some platform-specific calls until after
console_init() and exception_init()... since these functions don't
really take that long, especially if there is no serial console
configured, I don't expect this to cause any issues.)
Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/28199
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the following failure from FWTS:
FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line
131
Line | AML source
--------------------------------------------------------------------------------
00128| }
00129| }
00130| })
00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings
| ^
| Remark 2120: Control Method should be made Serialized (due to creation of named objects within)
00132| {
00133| Name (RBUF, ResourceTemplate ()
00134| {
================================================================================
ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is
created inside a non-serialized method - this method should be serialized. It is
possible that one thread enters the method and blocks and then a second thread
also executes the method, ending up in two attempts to create the object and
causing a failure.
BUG=b:112476331
TEST= Run FWTS.
Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28122
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nami doesn't support wakeup from hibernation by CR50. This causes the
device to remain turned off after CR50 update.
This patch disables turning off EC on cr50 update. CR50 resets the
whole system. So, EC reset is not required.
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
BUG=b:112604277
BRANCH=none
TEST=gsctool -a -u /media/removable/cr50.bin && reboot
Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update'
then reboots.
Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709
Reviewed-on: https://review.coreboot.org/28113
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files are being updated to match the prevailing style
of cmos.default files.
Change-Id: I47d31d6fec8c9eb856aed0c63824d9556b7705e4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Used default console log level is 7 in src/console/Kconfig.
So let cmos.default use the same level as default.
Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Side effect was observed that after override BayHub EMMC
driving strength to the max, EMMC CLK will be reduced to
51.x Mhz from 200 Mhz.
This will cause OS installation fail on Samsung EMMC sku.
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This file contains two instances of "dptf_enable" = "1". This change
removes the 2nd instance (it doesn't have an explicit comment like the
1st instance).
The dptf devices still seem to be present even with this change, as
expected.
Change-Id: I890006644be9176ebaf555cc121c816e12f2b596
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The spec of the sx9310 says the I2C interface can handle standard
(100kb/s) and fast mode (400kb/s). The current setting is using fast
plus (1000kb/s) so this change is reducing the speed to fast mode.
I've been using the sensors with this change for a few weeks now, though
I also don't recall seeing an issue prior to this change.
Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 1fdb76945a.
Camera power is now handled by ACPI rules - no need to force the GPIOs
on by default.
BUG=b:80106316,b:111141128
Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28072
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This defines new GPIO pin for controlling the display panel CABC
function. The default value is high (enabled).
BUG=b:112154569
Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28070
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This updates the DPTF sensor names to reflect the sensor locations on
the board.
BUG=b:75454415
TEST=verified new strings show up in
/sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description
Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28069
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates Power Limit (PL) for AML.
- PL1 as 5W TDP as POR
- PL2 as 18W TDP as POR
BUG=None
BRANCH=None
TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP.
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power
5000000 (5W TDP)
cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power
18000000 (18W TDP)
Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/27427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change updates GPIO configuration for bobba boards with id >= 1
This follows the same model as fleex:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
BUG=b:112354568
TEST=Built firmware for bobba
Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/28071
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in
soc, therefore just use the defaults in sb/intel/common/firmware.
Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28011
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no need set the default HAVE_IFD_BIN explicitly to n.
Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28008
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no need to redefine option present in
southbridge/intel/common/firmware/Kconfig.
Change-Id: I9999440031b07006e2df11e00dfb9f3dbe04f832
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=none
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: Ic61a69e19e97520da0702dfe6cb7496563fc34f4
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove icc_max overrides to allow SoC code to set proper
icc_max based on CPU SKU.
BUG=b:78122599
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash to
nocturne, boot to kernel and verify device doesn't hang after
a few minutes.
Change-Id: I37c44e2428b802d754f2b12b8a57601d257e6582
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27996
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-nocturne coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: Idfdc0c2434fdef56a7c25df05e640837a5096973
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27997
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite PL2 setting based on CPU
sku. From doc #594883, PL2 is 18W for AML-Y.
BUG=b:110890675
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage & test with AML-Y
and KBL-Y skus.
Change-Id: I468befcd2c4ad6c2bb9ae91b323a43f87ff65a26
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27765
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow thermal table (b:112274477 comment#1) for first tunning.
BUG=b:112274477
TEST=Match the result from DPTF UI.
Change-Id: I63b2e50a4f6fc5453e6564e277600498ac0e6244
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Enable the GEO SAR feature for Octopus. Program wifi_sar VPD key.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:112288077
TEST=Program VPD key, extract acpi table ssdt and valiate WGDS entry.
Change-Id: I40a6fd9e0ec8b440996bf3389322fd89bcca15a4
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PERST signal is asserted/deasserted by ACPI routines during
suspend/resume. Configuring IOStandby for WLAN_PE_RST can result in
failure to resume from suspend state with wake-over-WLAN. This change
removes the IOStandby configuration for WLAN_PE_RST.
BUG=b:112371978
Change-Id: Ic7c0b2aa144233f8bbb4e5169d96347a1290abe1
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CNVi is being used, external wake using GPIO_119 is not
required. This change configures GPIO_119 as PAD_NC if CNVi is taken
out of reset.
BUG=b:112371978
Change-Id: Ifee90f428ed43c4d7c612c170476aff43b4a33ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses drivers/intel/wifi chip for CNVi device to ensure
that:
1. Correct device name shows up in ACPI node
2. It is possible to pass any parameters from devicetree to wifi
driver for SSDT generation.
BUG=b:112371978
Change-Id: Ia49820dd4f9cf2e0a9ef14931fbddd8a723208c0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change checks to see if CNVi module is out of reset:
1. If yes, then PCIe device for WiFi is disabled.
2. If no, then CNVi device is disabled.
BUG=b:112371978
Change-Id: I6e6cf2e646c897df017913056db87ac0cffa1a8e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change updates GPIO configuration for fleex boards with id >= 1
This follows the same model as phaser:
a. Dynamically update touchscreen power enable GPIO in devicetree.
b. Provide default and bid0 tables for GPIO configuration in ramstage.
c. Configure WLAN enable GPIO differently in bootblock based on
boardid.
d. Disable unused I2C devices in devicetree.
BUG=b:112458032
TEST=No errors observed on boot-up on fleex.
Change-Id: Ib4c449168b08e2393e2395d6b49469be5599c2ce
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Allow for shared dram configuration by introducing a new table
that collapses the common settings after removing the part
numbers. When employing this scheme the part number comes
from CBI.
BUG=b:112203105
TEST=Placed part number in cbi. Faked out memory sku id. And enabled
DRAM part num always in cbi. Everything checked out.
Change-Id: I5229695ce3eb686421b89ac55d8df4b9fcec705c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Rotor is dead, long live [PROJECT NAME REDACTED]!
Change-Id: Ia9308944257255e077a44c1df262c7f49c69890c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27964
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add 3 new Kconfig options:
DRAM_PART_NUM_IN_CBI
DRAM_PART_NUM_ALWAYS_IN_CBI
DRAM_PART_IN_CBI_BOARD_ID_MIN
These control whether to 1. attempt to use CBI at all 2. always use cbi
and 3. conditionally use cbi based on board id. The intent is that the
MIN variant would be used for the tranisition period then cut over to
ALWAYS after full transition. Since multiple OEMs have different
schedules these options are there to bridge the gap. yorp. bip, and
octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case
someone does the MIN values are 255 to always take the old path.
BUG=b:112203105
TEST=Set correct part number on phaser during testing.
Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Careena EVT SanDisk EMMC sku has high fail rate of 0x5B reboot failure.
It'll need to increase 1.8V EMMC CLK/CMD, Data driving strength for
this issue.
CLK[6:4]
CMD,DATA[3:1]
original register value: 0x6B
enhanced: 0x7F
BUG=b:111964336
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I3db38ff12c566c258895c6643008a0472ca528bb
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27816
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Micron material that was broken has long since been fixed that
required this option. glkrvp had these stale entries and were
subsequently copied to octopus. Remove the need for this option.
BUG=b:35581751
Change-Id: Id73584367c2ad0e4958b5ea0f04a28e5fc82d085
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27959
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Skylake SoC code now sets the icc_max based on the CPU SKU, so we
should not hard-code it in the device tree.
BUG=b:110890675
BRANCH=None
TEST=boots on atlas
Change-Id: I7eb3499b7bea9ab2c49e1f299e2dbb688c8d1c33
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
This configures the ACPI FADT perferred power management profile to
PM_MOBILE instead of PM_DESKTOP.
I'm not sure what impact this actually has. I just noticed the other
boards have it set.
BUG=b:110971913
TEST=Made sure SYSTEM_TYPE_LAPTOP shows up in coreboot.config
Change-Id: Iea1b8359b80d167e69745358f543f025713294ba
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If GPP_E22(CABC_EN) remained floating GPI(SoC default) at V3.3_DX_EDP on,
it may cause damage on the GPIO pad.
To prevent, we would set this pad to GPO on romstage before EDP power on.
Since we need to cover all systems in market, I put it into romstage
instead of early_gpio_table.
BUG=b:111860510
BRANCH=poppy
TEST=Verified CABC_EN is set to GPO high 5ms before EDP power on
Change-Id: I34e2fe86329a88eb05e0ea3c6beac6a64754b41e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds variant callback to get GPIO configuration table in
romstage and configures these GPIOs before memory training is
performed.
BUG=b:111860510
BRANCH=poppy
Change-Id: I1eb51356fb3f4c0f4ff29b22dbcde6dbece303ad
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that an updated bootloader with important fixes is available at coreboot
repository, all stoneyridge boards should use it. Move the selection of
SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge.
BUG=b:111428800
TEST=Build and boot grunt.
Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27844
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update power limit1 value from 8W to 10W. There is an error
in the energy calculation for current VR solution on GLK.
Experiments show that when power limit1 set to 10W, gained
performance improvement with SoC TDP reaches max (6W) power.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Ic320d442e7401e4be2e8e16d691db4c803f0fdc1
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the default value for Iccmax which is specified in vr_config.c.
The AcLoadline and DcLoadline keep the poppy value. Besides, the
USB 2.0 ports located on the mainboard are set to USB2_PORT_SHORT
and the others on the daughterboard are set to USB2_PORT_LONG.
Those setting need to be fine tuned later.
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: Icabfac04c94b3d480872c243d811509e274ef122
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The gpio setting is based on the proto board schematics
BUG=b:111579386
BRANCH=Master
TEST=Build pass
Change-Id: I20fc081d372b8686f6128a7e85276f9c6798b199
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kahlee based boards don't use SATA, so disable SATA on all boards to save
power.
BUG=b:112139043
TEST=Build and boot grunt, checked the absence of SATA PCI.
Change-Id: I6a12c03a5a95b1c8b40609a3fe656df92548b80b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since only a handful of boards have descriptor blobs in the tree, it makes no
sense to have `HAVE_IFD_BIN` enabled by default then disabled on each mainboard.
This patch flips the default value of said variable, rendering all current
overrides unnecessary. The few boards which have an IFD in the blobs repo use
`select HAVE_IFD_BIN` to enable adding the IFD by default.
Since `HAVE_ME_BIN` depends on `HAVE_IFD_BIN`, the former has been removed
alongside the latter, and has been added to the boards with a ME blob as
`select HAVE_ME_BIN`.
Both `HAVE_IFD_BIN` and `HAVE_ME_BIN` have been removed from autoport as well.
Change-Id: I330c4886f8bea4b1a8ecad6505a0e5cc381654d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These boards require polling vs interrupts, so remove the IRQ definition to
prevent it being added to the SSDT device entry.
Test: Boot Linux on various auron and cyan variants, verify no error for
'TPM interrupt not working' present in kernel boot log.
Change-Id: Ia1139389f075934d41e823ce5190011c90c7cc88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes sure we deassert the USB hub reset pin so the hub will
work with the next board revision that drops the external pull-up.
(Actual USB support comes in a later patch.)
Change-Id: I1efdc3594cfa3229891d42d445a21c1739170b79
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27790
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the required callbacks to read all strapping IDs on
Cheza.
Change-Id: I6437bbd03bdd00dfeedcafebabeb00b13588d052
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tuning of fan speed for different temperature values. Earlier while
running few benchmarks, fan was always getting on and starting at
higher speed. With this change fan will start with lower speed and
slowly speed gets increased if temperature continue going high.
Thermal team provided these data after fine tuning of fan speed.
BUG=None.
TEST=Verified on Nami running with different benchmarks and observed
fan speed.
Change-Id: Ic3be9e44deef9570200c71807a2ee712d9f20876
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27683
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Nami is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:112081534
BRANCH=None
TEST=Build and boot Nami
Verify that suspend/resume and consecutive reboots are working
Change-Id: I6ec18a4c3fae6a66cf8a95685d91a8ba51e2697c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/27780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from chromium commit adcb858
[cyan: Configure WLAN_CLKREQ as GPIO and always assert low]
This is a workaround for issue b/35648315 as proposed by Intel to
ensure that WLAN_CLKREQ always stays low.
BUG=b:35648315
Original-Change-Id: I178b3e4fbf74cf08eadfa8bd31b80b018f330e77
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1055652
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Tested-by: Rajat Jain <rajatja@chromium.org>
Change-Id: Ie3458b3fbd1ecadf6b99b9804fb98440cf8d6938
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from chromium commit 3750e09
[Strago: mark GpioInt() resources as PullDefault]
coreboot considers GPIO resources first-class citizens and initializes
all pads according to their intended use, with necessary pull settings
applied. Therefore let's use PullDefault as pull qualifier in AML,
letting the kernel know that it should not attempt to alter pull settings
when using GPIOs.
TEST=Built and booted on celes, cyan, and egdar; built for other cyan devices.
Original-Change-Id: Iff58a324e73a7eeac9b38df05a095fcfe7acd31b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/898259
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I0c69e77c58b8ceca71bc0c99e16d10c3e539f783
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27760
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adapted from chromium commit 126d352
[Strago: switch Touchpad and Touchscreen interrupts to be level-triggered]
The Elan and other touch controllers found in this device work much
more reliably if used with level-triggered interrupts rather than
edge-triggered.
TEST=Boot several cyan boards, verify that touchpad and touchscreen
work.
Original-Change-Id: I59d05d9dfa9c41e5472d756ef51f0817a503c889
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894689
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4f8cf83351dae0d78995ce0b0ed902d1e4ac3e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from chromium commit ee7a150
[Strago: do not hardcode virtual interrupt numbers]
Instead of hardcoding virtual interrupt numbers that may change as
the kernel changes, use GpioInt() resources to describe keyboard,
touchpad, and touchscreen interrupt lines.
TEST=Build and boot several cyan variant boards, verify keyboard,
touchpad and touchscreen work with newer kernels (4.14+).
Original-Change-Id: I98d5726f5b8094d639fb40dfca128364f63bb30b
Original-Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/894687
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Iecfb45be433249d274532eb746588483fedb3f52
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since this works on Yorp and Bip, we should enable EC SW sync for all
known boards so that it doesn't get forgotten.
BUG=None
TEST=None
Change-Id: Ifee8e0b6620dc7554160a10a8e4663db25b6413d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27755
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With commits 9987534 [southbridge/intel: Remove leftover TPM ACPI code]
and 66ce18c [soc/intel: Remove legacy static TPM asl code] removing
TPM ASL code from the southbridge's LPCB device, the LPC TPM chip driver
(drivers/pc80/tpm) must be added to devicetree in order to ensure the
new acpigen code is used to replace it.
Test: boot various google/samsung boards, verify SSDT created with
LPBC.TPM device and TPM visible to and usable by SeaBIOS and Linux
Change-Id: Iedaa01f26fb357914549bb3dda24b0bd6ef67480
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27786
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a function to overwrite AC/DC loadlines for differnt
projects.
BUG=b:111761175
BRANCH=None
TEST=emerge-nami coreboot chromeos-bootimage and use DCI to dump
AC/DC loadline settings. Tested on Vayne and Akali.
Change-Id: Id0068c5334c257b9f4c32b6088becbfe8391a864
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/27644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This never got enabled for fleex; we should enable this to make it
easier to have updated EC firmware.
With this commit, here's the relevant console messages:
sync_one_ec: devidx=0 select_rw=4
update_ec: Updating RW(active)...
Trying to locate 'ecrw' in CBFS
update_ec: image len = 137580
EFS: EC is verifying updated image...
send_packet: CrosEC result code 1
EFS: EC doesn't support EFS_VERIFY command
vboot_hash_image: No valid hash (status=0 size=0). Compute one...
print_hash: RW(active) hash: 35ba735cf97dd990f6f7f0895264382aa20beb4e7ba57270b0a7b24686e26afd
Trying to locate 'ecrw.hash' in CBFS
sync_one_ec: jumping to EC-RW
send_packet: CrosEC result code 12
EC returned from reboot after 27753us
BUG=b:112038021
TEST=Successful boot after EC update via sync
Change-Id: I2dc97c8e2b07f3bdef0d723789cc12c23b32c135
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The careena board requires a different setting within VBIOS in order to
pass the eDP eye diagram test. Update all kahlee boards to use the new vBIOS.
CQ-DEPEND=CL:1153080
BUG=b:111673328
TEST=Verify, via SOME unspecified method, that the new vBIOS is built into
the Grunt/Careena ROM files.
Change-Id: I268cd3dbce6ba1f7bd781d768f470463846a4e10
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27643
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, AGESA environment needs eDP high vdiff enabled.
BUG=b:111673328
TEST=Add debug code to AGESA to display set eDP. Build AGESA. Build and
boot grunt. Add new code to grunt, build and boot, verify eDP changed.
Change-Id: I3e6b409699e8192eb39cc189628ff95b9f985e54
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change primarily moves the PowerResource up to a more common scope so
that the _PRx references are simpler. The ^ scope modifier isn't well
supported everywhere amongst OSes and drivers. Windows 10 will BSOD
early during boot with ACPI_BIOS_ERROR (code 0x6, which means it could
not find the object referenced by a _PRx) with the way things are currently
laid out).
I've also not seen a firmware outside of coreboot that tries to reference
count _ON and _OFF. Isn't it up to the OS to deference count, and whatever
it tells ACPI is what should happen (i.e., on means on and off means off)?
Some of the _UIDs are also duplicated. This change makes them unique.
A few cosmetic changes are made so that diffing cam0.asl against
cam1.asl has fewer extraneous differences.
Change-Id: I9c9f6c712b075450539d5b84ac5bb221b3cbb57e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/27605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Adapted from chromium commit 7633daa
[caroline: Change debounce time for jack insertion and ejection]
We are using max debounce time. During this time line, MICBIAS will be
zero because of jack chasis. At the moment we got 0 button (PLAY/PAUSE)
We need to reduce this time to below 100ms for caroline device.
BUG=b:79559096
TEST=see there is no more irq before jack insertion/ejection irq
complete
Original-Change-Id: Ib6abdb4ff041823ca89f74cf59e2bfa644bb0d6a
Original-Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/1143109
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wonjoon Lee <woojoo.lee@samsung.com>
Change-Id: I8f605989d6ffc8a75127ed6722e7a37db95029ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27659
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On kukui board, the eMMC is routed to EC for boot ROM emulation when
loading bootblock, and should be set back to real eMMC as early as
possible after bootblock is loaded.
BUG=b:80501386
TEST=make; boots and verified BOOTBLOCK_EN_L GPIO is enabled.
BRANCH=None
Change-Id: Ifefb2e26ed048c38595907cc0875757410129828
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable power to FPMCU by default on power-on and deassert
the PCH_FPMCU_RST_ODL reset line.
BUG=b:111880258
BRANCH=none
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, login and execute "powerd_dbus_suspend" at kernel
prompt, wait a few seconds, press power button to wake, then execute
"cat /var/log/cros_fp.log | grep 'Reset cause'" and assure search comes
up empty.
Change-Id: I7f8419dd58f79816f8061d0da4a0d3984c814289
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27658
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable nocturne to wake from lid attach/detach events.
BUG=b:111803637
BRANCH=none
TEST="emerge-nocturne coreboot chromeos-bootimage", verify EC has
commit a5abbbb4eb9b15a72624dddbfd727d0b324c3f36, and verify nocturne
wakes from suspend on a lid attach/detach event.
Change-Id: I22b957d741426ca8b49d1819cf39c940f55198eb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27649
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some fields were only required during early stages of IPU3.
Remove some fields that aren't used for the current version of IPU3.
BUG:None
TEST=Launch camera app and check if it works properly.
Change-Id: I72bcba13cc353a1b16fedeb7543fbbac432fbf5d
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For unused pins, configure them as GPIO input and use the default
termination. For the pins where board has an external termination,
remove SOC's internal termintation.
BUG=b:110654510
TEST=On Bip, flashed image and verified that it boots to OS. Also
executed a few suspend resume cycles.
Change-Id: I343fed54ebc04199acecab257d7b8253d0a3d83b
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, default GPP_D21(LTE3_BODY_SAR) output level is low, it means
LTE tx power is backoff mode as default.
We would set GPP_D21 to high to change LTE tx power to normal mode as
default.
BUG=None
BRANCH=poppy
TEST=Verified default LTE tx power mode is normal mode as default
Change-Id: I62e77196c2116924f437f61368f0ae7efd0e144c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27661
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the new setting for fan performance state.
BUG=b:111860513, b:11865138
TEST=Fan do not run below trip point
Change-Id: I894460b8b418217e2477608094c37018437cbb78
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
All of the other SPDs are padded with spaces to make them use the full
size of the serial number field. The hynix-H5AN8G6NCJR-VKC SPD was not,
and that seems to be causing problems with some tools.
BUG=b:111903749
TEST=Mosys correctly identifies memory on board using that SPD.
Change-Id: I0e831873acab2f6fc7d76e85647198d3b7af4b12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
A variant might talk to the EC to get board id in order to identify the
right GPIO configuration. Thus it is important to ensure that the LPC IO
windows are configured before this. This change moves the call to
perform EC init before configuring bootblock GPIOs.
BUG=b:111933657
TEST=Verified that reading board id does not fail on phaser.
Change-Id: Ic23c6fd7597a314e0b6421be39ccc0b1dfb46567
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27671
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets SPI flash related configs and inits SPI bus 1 to
support SPI NOR flash.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I1a18a456f41a7c7daec954e961c9fbee3650493d
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add audio codec definitions in devicetree, which were accidentally
dropped when upstreaming
Test: build/boot Caroline with GalliumOS 3.0a2, verify working audio.
Change-Id: I707b93c83f773cde2108b75ec550a15e5566d974
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27626
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove duplicate FMCN package for I2C2, since already generated by
the devicetree-linked generic i2c driver. This fixes an ACPI parsing
error which resulted in the touchpad and touchscreen being non-functional.
Test: build/boot Caroline with GalliumOS 3.0a2, verify touchpad and
touchscreen functioning properly, no ACPI errors in dmesg.
Change-Id: I68315daf087aef0fc51411605b054e6322d5d7f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change provides override GPIO table for variant phaser depending
upon the board id. Additionally, early_gpio_table is also provided for
phaser since EN_PP3300_WLAN needs to be handled differently based on
board id.
BUG=b:111743717
TEST=Verified that GPIO configuration for the override GPIOs is
different than before with this change.
Change-Id: I4d2e829e1b886299442c17cecc069854b742b43c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates mainboard_init to call
gpio_configure_pads_with_override instead of gpio_configure_pads to
allow variants to provide overrides for the GPIO config table provided
by the baseboard.
BUG=b:111743717
TEST=Verified on phaser that GPIO config with and without this change
is the same.
Change-Id: I494a950100e5ec82504d652ff6e8a75746456d1f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The next build for phaser swapped the gpio for the touchscreen
enable. In order to support previous builds the devicetree needs
to be updated at runtime based on board revision id.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I45ef05ea0b991d04d5bf410cd7a175913bf0bf5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27638
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The variants of the octopus family have their own schedule and needs
for modifying settings based on the phase of the build schedule while
also needing to maintain support for previous builds. Therefore, utilize
the SoC callback, mainboard_devtree_update(), but just callback into
the newly introduced variant_update_devtree(). The indirection allows
for the ability to move the call around earlier than the
mainboard_devtree_update() if needed while maintaining consistency in
the naming of the variant API.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: If1c2f60cabe65b5f1c6a04dd60e056e50c4993df
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The variant_board_id() API was never used on octopus because all
boards in the octopus family used the EC to get board id, i.e. they
all use EC_GOOGLE_CHROMEEC_BOARDID. Therefore, remove the code
and declarations so as not to cause confusion.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: I4f9a24b46dd4262120075d3d42daf22015a3dd50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
MT8183 only allows booting from eMMC, so we have to do eMMC emulation
from an external source, for example EC, which makes the size of
bootblock very important.
A fully functional bootblock (that can boot into verstage or romstage)
is about 38000 bytes. If self decompression (CONFIG_COMPRESS_BOOTBLOCK)
is enabled, only 25088 (66%) bytes are needed.
Inspired from crosreview.com/1070018.
BUG=b:80501386
TEST=manually flashed into kukui and boots into romstage.
Change-Id: I7a739866a4ea3bcafe2ff7b9e88d5ed00f3f3e40
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/27599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These values are Intel recommended.
IccMax = 28A
DC and AC LL = 4mOhms
Pl2 = 18w
BUG=b:79666828
BRANCH=none
TEST=Enabled p-states with patch
Change-Id:I82d1516998cc26b789faa5d4e897feb06dc06020 and then
"emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi
image onto nocturne, boot to kernel and verify device stays alive and
responsive for several minutes without locking up.
Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27175
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables p-states for nocturne which was disabled by commit
de31587a (mb/google/poppy/variants/nocturne: disable p-states). p-states
feature was disabled as a temporary work-around as system was getting
hung while booting up. Now with IMVP7 firmwware turning and hardware
rework the issue is not seen, so its safe to enable p-states.
BUG=b:79666828
BRANCH=none
TEST=cherry picked Change-Id: I4c67c6a095aecc158e529a6b393baf03ec358a3d
patch and then "emerge-nocturne depthcharge coreboot chromeos-bootimage"
, flash spi image onto nocturne, boot to kernel and verify device stays
alive and responsive for several minutes without locking up.
Change-Id: I82d1516998cc26b789faa5d4e897feb06dc06020
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27257
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For unused pins in octopus baseboard, configure them as GPIO input
and use the default termination. For the pins where board has an
external termination, remove SOC's internal termintation.
BUG=b:110654510
Change-Id: I67ec62913b0ef47105289838218f5d74c004223c
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/27183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per the ACPI specification, there are two types of power button
devices:
1. Fixed hardware power button
2. Generic hardware power button
Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
is not set in FADT by the BIOS. This device has its programming model
in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
power button device by default if the power button FADT flag is not
set.
On the other hand, generic hardware power button can be used by
platforms if fixed register space cannot be used for the power button
device. In order to support this, power button device object with HID
PNP0C0C is expected to be added to ACPI tables. Additionally,
POWER_BUTTON flag should be set to indicate the presence of control
method for power button.
Chrome EC mainboards implemented the generic hardware power button in
a broken manner i.e. power button object with HID PNP0C0C is added to
ACPI however none of the boards set POWER_BUTTON flag in FADT. This
results in Linux kernel adding both fixed hardware power button as
well as generic hardware power button to the list of devices present
on the system. Though this is mostly harmless, it is logically
incorrect and can confuse any userspace utilities scanning the ACPI
devices.
This change gets rid of the generic hardware power button from all
google mainboards and relies completely on the fixed hardware power
button.
BUG=b:110913245
TEST=Verified that fixed hardware power button still works correctly
on nautilus.
Change-Id: I733e69affc82ed77aa79c5eca6654aaa531476ca
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Logic: If vboot is not used and the tpm is not initialized in the
romstage makes use of the ramstage driver to initialize the TPM
globally without having setup calls in lower SoC level implementations.
* Add TPM driver in ramstage chip init which calls the tpm_setup
function.
* Purge all occurrences of TPM init code and headers.
* Only compile TIS drivers into ramstage except for vboot usage.
* Remove Google Urara/Rotor TPM support because of missing i2c driver
in ramstage.
Change-Id: I7536c9734732aeaa85ccc7916c12eecb9ca26b2e
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24905
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Coolstar's custom touchpad drivers for Windows require level triggering,
and the Linux drivers don't care/perform identically either way. Set
touchpad interrupt to level trigger, matching change made to other
Chromebooks.
Test: boot Windows 10 on google/chell, verify touchpad functional
Change-Id: Id5f145b8b24c04f9c6661710a0cda95f135293e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Explicitly enable VMX, as some OSes (eg, Windows) need VMX
feature enabled and locked in order to fully support virtualization
Test: boot Windows 10 on google/chell, verify OS reports virtualization
enabled
Change-Id: I53ff575755a9ca376dbf953db96191c17bf57f5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change adds variant rammus derived from baseboard poppy.
The setting is copied from the poppy and will be modified later
BUG=b:111579386
BRANCH=master
TEST=emerge-rammus coreboot
Change-Id: I169c225e28183a7a93f1142a3bf87a60b26ce9ca
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/27547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides implementation of smbios_mainboard_sku
that queries the EC for SKU ID using CBI. Currently,
get_board_sku() is implemented as a common function for all
variants since this is the only way used by all the octopus
variants to query SKU ID. If this changes in the future,
this function can be changed to a variant_* callback.
BUG=b:111671163
TEST=Verified following on phaser:
1. "mosys platform sku" returns the SKU ID programmed in CBI
2. "dmidecode -t 1" shows SKU information as "skuXYZ" where XYZ
is the SKU ID programmed in CBI.
Change-Id: Ic0d344b3c13632f2ca582adc36aa337b99959712
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This change increases COREBOOT region size by the amount of unused space
left in RO_SECTION. This extra space is useful when building images with
debug enabled.
BUG=b:111661025
Change-Id: Icbd88c3350f96707f37b69fe01f8ae9c7838ab82
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27555
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DW9807 NVM support by adding required ACPI code
BUG🅱️110815821
TEST=On Nautilus board, execute "cat /sys/bus/i2c/devices/i2c-INT3499:00/eeprom"
in the terminal and see if there is any data to be dumped.
Change-Id: Ib83fa1a522402a59566e3f55fa5c1af4490266e4
Signed-off-by: Alan Chiang <alanx.chiang@intel.com>
Reviewed-on: https://review.coreboot.org/27508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Nautilus-WiFi board doesn't have external pull-up on USB2_OC2# route,then
abnormal over-current is asserted on USB type-A port.
It causes USB type-A port to be blocked, so we need this internal pull-up.
BUG=b:111578984
BRANCH=poppy
TEST=Verified over-current not triggered abnormally on basic sku board
Change-Id: I159f686cef9c8d254f390d7f1dff8011f43fc066
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Convert lars to a variant of glados Skylake reference board:
- add lars-specific DPTF, EC config, GPIO config, Kconfig,
NHLT config, PEI data, VBT, SPD data, and devicetree
- add conditional generation of NHLT ACPI data for Maxim codec,
including override of OEM ID and OEM table ID
- remove existing lars board/directory
Test: build/boot google/lars, verify functionality unchanged
from pre-variant configuration
Change-Id: Iab37f1b92b0f3a5d99796f916a6fdcc14ce4eef4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27413
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert Skylake reference board glados to variant setup in
preparation for merge with existing Skylake boards chell and lars,
and upstreaming of new boards asuka, caroline, cave, and sentry.
The following changes have been made:
- move DPTF to variant subdir
- move non-common EC defs to variant subdir
- adjust Kconfig for variant setup
- move non-common NHLT config to variant Kconfig
- make non-common NHLT ACPI code conditional
- move devicetree to variant subdir
- move board GPIO defs to variant subdir
- move board PEI data to variant subdir
- move SPD index calculation to romstage so available for
dual-channel determination during PEI for boards which need it
- move SPD compilation to variant makefile
- add weak function for determination of dual-channel RAM
- add weak function for mainboard_gpio_smi_sleep() so SKL-Y variants
can override and power down rails as needed
Test: build google/glados
Change-Id: I41615979dc11b5a10e32d6b5f477a256735cde53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the GEO SAR feature for nocturne. OxM programs wifi_sar VPD key in factory.
coreboot reads the VPD and creates the ACPI table as per the WGDS spec.
BUG=b:65155728
BRANCH=none
TEST= Set the wifi_sar VPD with below command (values are junk for test purpose only,
actual values would be set be OxM)
sudo vpd -f <coreboot.rom> -s wifi_sar=30313233343536373839303132333435363738393030313
24142433435364445463031324142433400364445463031323343444546303132333435
Flash the <coreboot.rom> and boot to kernel. Get ACPI table and WGDS would get created
with VPD values passed in.
Change-Id: I32ad591f15fdb34704c8d98d98646dfa2d8882ff
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/27501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Refactor GPIO code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is based on the Grunt variant.
BUG=b:111607004
TEST=Build Liara
Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This is based on the Grunt variant.
BUG=b:111606874
TEST=Build Aleena
Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Observed thermal shutdown initiated by DPTF due to CPU temperature
reaching critical temperature trip value. During stress testing with
busty workloads like Octane, Aquarium on open yorp board with heat sink,
sometime CPU temperature spikes till 99 degree Celsius and DPTF
initiates system shutdown. With reference to previous APL/reef/coral
platforms, this updates 105 degree Celsius for the CPU critical
temperature trip value to avoid shutdown. This patch also updates power
limit1 value to avoid the abrupt thermal shutdown by DPTF.
BUG=b:79779737
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/27294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.
Note: This currently does not appear to have any effect on grunt.
BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff
With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1
Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We should use active-state power management where possible to reduce
power consumption during normal operation. Enable these options.
Linux does not seem to enable this for AMD, and the Intel code in coreboot
does enable these options.
PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it.
BUG=b:110041917
TEST=boot on grunt, see that WiFi and eMMC still run OK
Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27464
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This creates a meep variant for octopus.
The devicetree overrides are copied from yorp, otherwise everything
just defaults to baseboard settings.
BUG=b:111543000
TEST=None
Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
