Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: Ibb63f3ecd9cfbb6f564e0a9968c2776c25d84f79
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments.
Change-Id: I42458f16a323d3e37d0ee1bd8335e1f8d0e1fadc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move includes using library paths to the top and remove unnecessary
comments. Also, get rid of that unnecessary _SB scope. Use an absolute
path for the PCI0 device instead.
Change-Id: I730cd3eeffff60b3b569bfb748febbdc8ca85990
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change replaces the device tree walks with device pointers by
using alias for dptf_policy device.
Change-Id: I02ca63ac2cc1b8ed2f5a381b3824c9beff7f33ec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57870
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These statements fit on a single line. Reflow them to ease future works.
Change-Id: Ie18e9a00f67b999fdcedcab3c28b68e34bc93da4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This patch allows ADL-RVP mainboards to set AUX GPIO PADs based
on the board id value.
Various ADL-P and ADL-M RVPs SKUs demand different GPIO AUX programming
hence, this patch implements a helper function inside `adlrvp` mainboard
to override devicetree chip config.
Note: Different ADL-P/M SKUs (LP4/LP5/DDR4/DDR5) don't have dedicated
devicetree for overrides hence, board id is being used for unique SKU
identification.
Additionally, skip AUX GPIO PAD filling up for Windows SKUs.
TEST=Able to override AUX GPIO PADs based on ADL-P RVP board id.
Change-Id: I2f0a37c7a8bd69af715551df2a93e6eed89e954a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change uses the newly added `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
Kconfig to enable USB4 resources and drops the configuration
in mainboard.
Change-Id: I707c5d63ea8c58e72126fe0d319ba81a99221ba5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
FSP-S hides the PMC from the PCI bus when it runs, but there are still
initialization steps coreboot programs for the PMC. Therefore, change
all of the cannonlake mainboards to set the PMC as hidden in the
devicetree, which means the device will be skipped during enumeration,
but device callbacks are still issued as if the device were enabled.
TEST=Ran full patch train on google/dratini, disassembled SSDT and the
PEPD device matches what is in pep.asl. Also verified via dmesg that the
INT33A1 device is still initialized by the kernel.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib4a20ce9075ce7653388a5d3e281fe774bf89355
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These defines are copy-paste leftovers from Kunimitsu. However, neither
Saddle Brook nor KBLRVP use memory-down, so drop the unneeded defines.
Change-Id: I396aeaa634f619be7be0ee97c0cab1c682f53ff2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Disable devicetree devices disabled in the `SerialIoDevMode` array.
These devices get disabled by FSP-S, and coreboot doesn't see them.
Change-Id: I8dbb45c96eae5188e5999df9a458f06f6b196adf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
All KBLRVP variants select the `INTEL_LPSS_UART_FOR_CONSOLE` Kconfig
option and set `UART_FOR_CONSOLE` to `2`, so that UART #2 is used as
coreboot console. However, the LPSS console driver requires the LPSS
UART to be memory-mapped (and not I/O-mapped, like Super I/O UARTs).
KBLRVP variant RVP8 uses `PchSerialIoLegacyUart` for UART #2, which
makes FSP-S configure UART #2 in legacy, I/O-mapped mode. This most
likely results in the UART console not working after FSP-S has run.
This change updates RVP8 to use `PchSerialIoSkipInit` for UART #2, like
the other KBLRVP variants do.
Change-Id: Ic5c78f5895fe1dd5e7be6ef7aec3de6940dd2475
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This is most likely a copy-paste remnant, and will never be needed for
RVP8: the SDXC device does not exist on PCH-H (and RVP8 uses a PCH-H).
Change-Id: I69059a88dcdb032beaab5fb03981dccbae0db02e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The I2C #4 and I2C #5 devices do not exist on PCH-H. Disable the devices
using the PCH-H variants' overridetrees (the base devicetree enables I2C
#4), set the `SerialIoDevMode` entries to `PchSerialIoDisabled` and drop
inapplicable I2C #4 voltage settings.
Change-Id: I56f34fa2004993d2123ccd5c1008fd71682ec2bd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change adds a new Kconfig `SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES`
that can be selected by mainboard to reserve hotplug resources for
USB4 at the SoC level. `ADL_ENABLE_USB4_PCIE_RESOURCES` is dropped
from soc/intel/alderlake and instead the newly added Kconfig is now
used. This new Kconfig is added so that the same config can be used
across different platforms. In following changes, this Kconfig is
utilized by TGL as well.
Change-Id: Id7c359a0e255c43c2732f6cbe287bc7da14a46e3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The overrides set the options to the same value as drivers/intel/fsp2_0/
Kconfig does, so drop the overrides.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53922786382a2e7d29b3df560a1998f41e1d2ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Normally, selecting FSP_USE_REPO will select FSP_FULL_FD which then will
configure the proper paths for FSP_M_FILE and FSP_S_FILE. The override
in these two boards caused FSP_M_FILE and FSP_S_FILE being empty despite
ADD_FSP_BINARIES being selected by FSP_USE_REPO which is an invalid case
that needs to be avoided, so remove the board-level override of those
two options.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I20c8cebea8327d59f0f33d05b824a74bf2121f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The ADD_FSP_BINARIES override in the mainboard's Kconfig caused this
option to not be selected when FSP_USE_REPO is selected. Remove the
override to fix this problem. These two boards are the only ones in tree
that had an override for this option, so now the ADD_FSP_BINARIES option
is only defined in drivers/intel/fsp2_0/Kconfig.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23439f3134eef9460625addbff7efd64c5f65ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
CONFIG_DRIVERS_INTEL_MIPI_CAMERA and CONFIG_SOC_INTEL_COMMON_BLOCK_IPU
are getting selected for all ADLRVPs irrespective of ADL-P and ADL-M
(internal and external EC SKUs) hence, select those Kconfigs from
mainboard Kconfig rather Kconfig.name.
Also, select DRIVERS_INTEL_SOUNDWIRE as per alphabetical order.
TEST=No changes are seen while the .config file is getting auto
generated.
Change-Id: I62d5ec19c3364da79ebe7287b1b3d6eb2a0efca0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set the `UserBd` FSP-M UPD to `BOARD_TYPE_DESKTOP` by default on PCH-H.
Remove now-redundant mainboard code to set the `UserBd` UPD.
Change-Id: I349abe5d89f562c158ce9baadbca2b2f56695846
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57261
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DIMM_SPD_SIZE` Kconfig symbol once.
Change-Id: I619833dbce6d2dbe414ed9b37f43196b4b52730e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This fix will enable PCIe x1 slot for ADL-M LP4 and LP5 RVPs.
The BDF for this PCIe slot is pci is: 0000:00:1d.0
TEST = show device command:
$ lspci -s 00:19.0
expect this:
00:19.0 Serial bus controller [0c80]: Intel Corporation Device 51c5
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia988fa0b5d8fefe68503b39843aab06c4229b36f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57053
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change follows other Intel SoCs common way to support SKUs with
bsp lapic_id != 0 by removing hardcoded lapic 0 from devicetree.cb and
allowing its detection at boottime. It completes support for HCV/DNV
after base SoC patch: commit ba936ce5db
soc/intel/denverton_ns: Ensure CPU device has a valid link
Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/YLMK2FBWWL6RKDNKBVZB3NJDYMEYHED7/
"A different lapic number in devicetree.cb needed for CPU with the same SKU and steping (Intel Atom C3538)."
Change-Id: I88f60f64d2beb2768ec9833de582d7901f456b11
Signed-off-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: King Sumo <kingsumos@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since all mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, make it the
default by changing its enum value to 0 and remove its configuration
from all related devicetrees.
If `common_soc_config.chipset_lockdown` is not configured with
something else in the devicetree, then `CHIPSET_LOCKDOWN_COREBOOT`
is used.
Also, add a release note for the upcoming 4.15 release.
Change-Id: I369f01d3da2e901e2fb57f2c83bd07380f3946a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This will add ACPI information to enable WACOM touchscreen.
TEST=Boot DUT and issue command:
$ ls -al /sys/bus/i2c/devices
WACOM PWB-D893 device should be listed and touchscreen should be functional.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I37c0831485135fda3284dda6b61f4825b7fc51a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Make `mainboard_fill_spd_data` mandatory and adapt mainboards to define
this function accordingly.
Change-Id: Ic18c4c574e8c963bbb41c980f43bdbacc57735af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55806
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables eNEM flow for Alder Lake SoC hence drop INTEL_CAR_NEM
Kconfig from ADL-P RVP. ALDERLAKE_CAR_ENHANCED_NEM Kconfig will select all
relevant Kconfig required to enable eNEM for Alder Lake.
Additionally, select INTEL_CAR_NEM Kconfig for ADL-M RVPs from Kconfig.name.
BUG=b:168820083
TEST=Able to build and boot ADL-P RVP using eNEM mode.
Change-Id: I08561c8f50bbc4afe2bcdff4cc50e74d8fa2f68e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48345
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch decouples the selection of eNEM feature enablement from SoC
to ensure the ADLRVP does the validation first prior enabling this
feature on OEM/ODM reference designs.
BUG=b:168820083
TEST=No changing is being observed in .config with and without this CL.
Change-Id: I709185159d9869501b1d8e8d00f6d25ec77838bf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I20bf1a87c7a9b343a86053692617c127a1a3250d
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56955
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig options and enable TPM device in devicetree
BUG=None
TEST=Booted the image and checked the successful TPM
communication in verstage,romstage & ramstage from
coreboot logs.
Signed-off-by: Thejaswani Puta thejaswani.putta@intel.com <thejaswani.putta@intel.com>
Change-Id: Icaedf9f17e35e82c35cbabd6d2938c167e42e9e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
With current setting Display audio codec probe fails.
Hence HDMI/DP audio fails.
Earlier, with FSP 2037 was used the mode was incorrectly programmed to 4T
This setting was carried ahead with below change:
Commit : 50f8b4ebdd
The issue was fixed in later FSPs and with current
FSP v2237, we need to set the TMODE to 8T as per spec.
TEST=Verify HDMI/DP Playback on ADL P RVP
Fixes: 50f8b4ebdd
(soc/intel/alderlake: Add enum for HDA audio configuration)
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Change-Id: Ia39a33f5da2fea0dc2eaf4eae45999a711c61c33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56208
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For mainboard devicetree, it always have definition for enabling
cpu_cluster 0 which is required for all the variants.
Since it is SoC related settings, it's better to keep in chipset.cb
as a common setting for all the mainboards using the same SoC.
BUG=None
BRANCH=None
TEST=Change has no functional impact on the brya board.
Change-Id: I8f7c3184b62f8d84ca4605fb9f2a1cc569f1f964
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56853
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: Ibc60494b0032a3139c1e6c79251fb2da750c8de8
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This will enable to include multiple VBT binaries in a single image
and load corresponding file according to HW configuration.
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iace0e5e0783b2074393a537da8cc645102d2acda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55969
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.
As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.
BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.
Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Specify the type of the `VARIANT_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: Iea2f992a59e41e00fec3cdc9d6a13b5f3ab0a437
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56558
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `FMDFILE` Kconfig symbol once instead of doing
so on each and every mainboard.
Change-Id: I810bd3fe8d42102586db6c2c58b7037a60189257
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56557
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `OVERRIDE_DEVICETREE` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I4cbf4e318a30f0cf75aa8690e7454b9caa115c9d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56556
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `DEVICETREE` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If68f11a5ceaa67a3e8218f89e1138c247ebb9a25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56555
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_PART_NUMBER` Kconfig symbol once
instead of doing so on each and every mainboard.
Change-Id: I3692f9e82fe90af4d0da1d037018a20aa1b45793
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56554
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Specify the type of the `MAINBOARD_DIR` Kconfig symbol once instead of
doing so on each and every mainboard.
Change-Id: If1cc538b0c4938dac193699897b690e402b3c1e8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56553
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to specify the type of the `CBFS_SIZE` Kconfig symbol
more than once. This is done in `src/Kconfig`, along with its prompt.
Change-Id: I9e08e23e24e372e60c32ae8cd7387ddd4b618ddc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56552
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove redundant type, prompt and help text, and replace `depends on`
clause with conditional default to allow specifying a FMAP when vboot
is not selected.
Change-Id: I37ddab3a27e304e810ea55f13821d755bb70cb4b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56551
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, internal flashing is not possible due to FSP lockdown. Thus
let coreboot do chipset lockdown on all variants.
Change-Id: Ib25a0543bfee0889dce071f3b01725daabd0a0eb
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56407
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide an option to set xHCI LFPS period sampling off time
(SS_U3_LFPS_PRDC_SAMPLING_OFFTIME_CTRL in JSL EDS revision 2.0).
If the option is set in the devicetree, the bits[7:4] in
xHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated.
The host will sample LFPS for U3 wake-up detection when suspended, but
it doesn't sample LFPS at all time due to power management, the
default xHCI LFPS period sampling off time is 9ms. If the xHCI LFPS
period sampling off time is not 0ms, the host may miss the
device-initiated U3 wake-up and causes some kind of race condition for
U3 wake-up between the host and the device.
BUG=b:187801363, b:191426542
TEST=build coreboot with xhci_lfps_sampling_offtime_ms and flash
the image to the device. Run following command to check the bits[7:4]:
iotools mmio_read32 "XHCI MMIO BAR + 0x80A4"
Signed-off-by: Ben Kao <ben.kao@intel.com>
Change-Id: I0e13b7f51771dc185a105c5a84a8e377ee4d7d73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch sets the optimized FIVR configs for ehlcrb customized
based on the performance measurements to achieve the better power
savings in sleep states.
- Enable the external V1p05, Vnn, VnnSx rails in S0i3, S3, S4, S5
states.
- Update the supported voltage states.
- Update max supported current, voltage transition time and RFI
spread spectrum.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I1e30ff6d84bfe078fcce0f968fce6aaab7fd575b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55981
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates PMC Descriptor which is part of Descriptor Region if
system equipped with Alder lake A0 silicon. This change allows to use
unified Descriptor Region for Alder lake A0(CPU ID:0x906a0) and B0
(CPUD ID:0x906a1) silicons. The change has to be reverted before EOM is
enableda on the system.
BUG=B:187431859
TEST=Verified PMC Descriptor getting modified for Alder lake B0 silicon
if not updated.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2a1f60fda7575212bb694fc423bd229452515903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Clean up lockdown configuration and move it to the baseboard's
devicetree.
Since most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, use it
for the rvp8 variant for consistency as well.
Built intel/rvp11 with `BUILD_TIMELESS=1` and coreboot.rom remains
identical. intel/rvp8 changes, as expected.
Change-Id: I78e847c321c61c3a974b26f30bc2823ff84df651
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56212
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Power Limit2 (PL2) minimum value to the same as maximum value.
DTT does not throttle PL2, so this minimum value change here does not
impact any existing behavior on the system.
BUG=None
BRANCH=None
TEST=Build and test on tglrvp system
Change-Id: I6bbbfa8e43a241df721b91425294983c1d561f2c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I39f82dc9eb91496d80479ae3f59ca5e03402a599
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This change updates device tree to enable SSDT generation for
world facing camera and user facing camera for ADLRVP.
Also reverts DSDT changes related to both camera.
TEST=Build and Boot aldrvp check i2c enumeration and output of media-ctl
Compared SSDT with this patch against DSDT without this patch, they are same
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I08834bbcf80dc46737de07f69a2402ed6bf93d4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch sets the optimized FIVR configuration for adlrvp cutomized
based on the pnp measurements to achieve the better power savings in
sleep states.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 states.
* Update the supported voltage states.
* Set the ICC max to 500mA for v1p05 and vnn.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I83e6910502d5cf9d4c26fa581272f59ac483ae19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Enable PCH GBE with following changes:
1. Configure PCH GBE related FSP UPD flags
2. Use EHL own GBE ACPI instead of common code version due to
different B:D.F from the usual GBE
3. Add kconfig PMC_EPOC to use the PMC XTAL read function
Due to EHL GBE comes with time sensitive networking (TSN)
capability integrated, EHL FSP is using 'PchTsn' instead of the
usual 'PchLan' naming convention across the board.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I6b0108e892064e804693a34e360034ae7dbee68f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
google_chromeec_get_event returns 0 for no event. Return
EC_HOST_EVENT_NONE=0 to improve readability.
BUG=b:184074997
TEST=Build and boot guybrush without error
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic08ed9ccdd7c0023d0fe8b641fcf60dca495a242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This provide a more consistent mechanism to enable corresponding USB
TCSS port.
BUG=b:182960979
TEST=Boot device, Type C port should operate correctly.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Iadc0df2e6e19a5afacbb7db1ae0bc7546dbcdc1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55772
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates mainboard_memory_init_params() function argument from
FSPM_UPD to FSP_M_CONFIG. Ideally mainboard_memory_init_params()
function don't need to override anything other than FSP_M_CONFIG UPDs
hence passing config block alone rather passing entire FSP-M UPD
structure.
Change-Id: I238870478a1427918abf888d71ba9c9fa80d3427
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change the default rom size to 32MB and remove chromeos.fmd
because Chrome OS is not supported on EHL for now.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I49d9404eb901087037b5423a4a503c5271e14138
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55554
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to latest corresponding UPD filling implementation, this is not
required.
This patch fixed the brokenness caused by
Commit hash b10afbd2e2.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I49e434f7bbafcb148e82202697e87c3e4268d7b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1), this causes redundancy with legacy HPD interruption.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=None
TEST=Boot to kernel and verified no kernel HPD pins assertion message.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: I80ef40a1aca19cd6ad56219175d2fd40890a393d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sanrio Alvares <sanrio.alvares@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Use hostbridge.asl from Haswell instead of Broadwell. Both files are
equivalent. Then, drop the now-unused hostbridge.asl from Broadwell.
Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.
Change-Id: I87d51727b75a9c59e2f5f3ba8d48c575ce93c78c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable all display related UPDs if IGD is not enabled as FSP
don't need to perform display port initialization while IGD itself
is disabled else assign UPDs based on devicetree config.
TEST=Dump FSP-M display related UPDs with IGD enable and disable
to ensure patch integrity.
Change-Id: I0479904141dfc5e707679109aa18b7ef4264cf96
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The same functionality can be provided through a runtime-generated SSDT.
The remaining parts of device NVS are removed in a follow-up.
Since the SSDTs are only loaded after the DSDT (if loaded at all), using
SSDT-provided objects outside method bodies is not possible: the objects
are not yet in OSPM's ACPI namespace, which causes in ACPI errors. Owing
to this, the operation regions used by the _PS0 and _PS3 methods need to
be moved into the SSDT, as they depend on the SSDT-provided BAR1 values.
Tested on out-of-tree Compal LA-A992P, generated SSDT disassembles with
no errors and contains expected values. Linux does not complain either.
Change-Id: I89fb658fbb10a8769ebea2e6535c45cd7c212d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most of the Kconfig files for Intel SOC devices define the MAX_CPUS
value within src/soc/intel/*/Kconfig.
Move the definition there for Tiger Lake and remove from the mainboard
Kconfig files.
Signed-off-by: Andy Pont <andy.pont@sdcsystems.com>
Change-Id: If145b9eb5d99821f4ce513118e4417d05f821ef5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Power limits (PL1 and PL2) depend on the specific SKU of the CPU.
By expanding the SoC chip config power_limits_config member to
an array indexed by ADL_*_POWER_LIMITS_*_CORE macros, the
appropriate power limits are applied. Using this the correct
set of power limits are being selected from the array based on
system agent PCI ID. Based on this, chipset.cb file contains
the set of power limits being used by varieties of ADL boards.
These power limit values are as per document 619501.
BUG=None
BRANCH=None
TEST=Built and verified the following console output on below boards
On adlrvp (482):
CPU PL1 = 28 Watts
CPU PL2 = 64 Watts
On adlrvp (682):
CPU PL1 = 45 Watts
CPU PL2 = 115 Watts
On brya (282):
CPU PL1 = 15 Watts
CPU PL2 = 55 Watts
Change-Id: Ic1676e2b4d611cdc85e770f131d5b6d5ecd180be
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
IO MWAIT redirection is not enabled, and C-states are reported using the
_CST ACPI object, which overrides the P_LVLx values.
Change-Id: I737bd58bcda3e7c5f6591e4c2309530ff035e2c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
shadowmountain board variants.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: I2b769d653ad8ad8ff069a0787d00ff33ead5c912
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use the device aliases provided by alderlake chipset.cb instead of
the raw pci device+function. Take advantage of the default states
in chipset.cb and only list the devices that are enabled for all
different adlrvp boards.
TEST=Dump devicetree device enable list without and with this CL, no
difference observed.
Change-Id: Ib9e82d953416c076588974f3167d00ae96f01bb5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55205
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot to OS and verify acpi tables.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c78ac44afa3515acef9ea2d59f22f95e6b45e90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54490
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Upload the FSP-M UPD configs. This CL also updated the chip.h and
devicetree.cb with the relevant variables and configs.
This CL also updated the GPIO related settings (PMC & SD card) in
devicetree.cb.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: If6321064b37535b390cf3dd7c41a719c598a0cd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
These PCIe and DMA ports are not available for adlrvp_m.
BUG=none
TEST=Boot device
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ic568c692fbb82fb3fc70c0cafc2328f8fa2cd74d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Initial upload of the GPIO configs for EHL CRB.
This CL also includes the UART GPIO configs in early GPIO table.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Ied4cbb34149b0b837597c0fc17dc5956f3ca409e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This changes updates mainboard properties by adding DFP number and
power_gpio for each DFP.
BUG=b:186521258
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I29480bf77f7df9890bef64a5f9f02074a34dc131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Along with upstream kernel for Retimer firmware update, coreboot defines
power control for each DFP respectively under host router. This change
removes the power_gpio from the baseboard. Individual DFPx power_gpio
will be added once the dependent definition is complete.
BUG=b:186521258
TEST=Build image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I819d2900afabbfdb2713fa8eee35d3c90cb904fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Most boards use `device lapic 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I1d3b1ac107e33aae11189cdd5e719b8e48b10f08
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Most boards use `device domain 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I6e2f0a19d57cfe6fc4e4ac4d14310133ad6b01d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Most boards use `device cpu_cluster 0 on` with zero written in decimal.
For the sake of consistency, update the remaining boards to follow suit.
Change-Id: I083c8f8e9b38ddcc217dc8bf17ae3c9473ba77e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Since we have TPM disabled on ADLRVP, if we enable EC sync, it keeps
rebooting with hash error.
Change-Id: I62a4fceb83dc6b20f699b4662e8f421aadafdee5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work due to the dependency on
FSP-M PCIe configuration. Since we're removing this programming from
FSP, coreboot needs to take care of programming this GPIOs. Also we
need to enable virtual wire messaging for native gpios for CPU PCIE
root ports.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I27c898943471d834bd82e3c7e8b36cceb12de099
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52865
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ADL-M LP4 RVP has command mirror enabled and we need to fill correct
value of this UPD to pass the MRC.
Also, Value of TxDqDqsRetraining is set to 1 by default and we need to
disable it for only ADL-M LP5 RVP.
BUG=None
BRANCH=None
TEST=UPD values has been pass correctly and MRC passes on LP4/LP5 board
Change-Id: I3e16b9a3d3e6a92dacba9d38782df408596ed5e1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Remove a blank line and correct the indentation of another line.
Change-Id: Id66f0a847720713c1d3445ac70a9e075228dfe88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54017
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We need to configure CPU PCIE root port related gpios in early
boot block stage for CPU root ports to work. Since we're removing
this programming from FSP, coreboot needs to take care of programming
this GPIOs. Also we need to enable virtual wire messaging for native
gpios for CPU PCIE root ports.
Change-Id: Ieda6b6c31ce5bd5e84e4efe544bfc659283ce6f1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52270
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now the bootblock is not limited to 64K so integrating vboot into the
bootblock reduces the binary size.
Change-Id: Ic92ecf8068f327a893d20924685ce571752d379f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52787
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS on shadowmountain. Ensure that the
EC Software Sync is complete.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8648db685d9c63ed1f2b3e599ca951d6648b7baf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Balaji Manigandan <balaji.manigandan@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
While building adlrvp board with chromeos.fmd and adding all chromeos
related artifacts, RO region is running out of space. Also, we need
to increase RW region size to accommodate all binaries and artifacts.
Aligning chromeos.fmd with Brya will help in solving this issue, thus
aligning chromeos.fmd with Brya.
BUG=b:184997582
BRANCH=NONE
TEST=Code compiles fine and able to boot adlrvp platform
Change-Id: I644e2e5ba06d2b816d413a7cc9f5f248d8a6fee8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52732
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL configures TCSS, BT and WiFi related GPIOs based on schematics.
BUG=None
TEST= BT, WIFI and TCSS functionalities validated with this change.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: Ie0e665275c281fcbad0d02ceb723cea433637711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50516
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and specify the srcclk pin and reset GPIO.
TEST=Tested on shadowmountain platform to ensure the system can enter the
S0ix state and suspend/resume is stable
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable DPTF functionality for Alder Lake based adlrvp board
BRANCH=None
BUG=None
TEST=Built and tested on adlrvp board
Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry
since it is not used anymore.
BUG=none
TEST=Check lsusb to see if BT enumerated.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change adds an enum to configure the audio related UPDs used for
configuring the audio over HDMI/DP and rename a variable for better
readability.
TEST=On shadowmountain audio sound cards are detected and listed by the
Linux kernel. Audio playback and capture is working fine.
Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure
GPIO pads for audio. However, mainboard is expected to perform all
GPIO configration in coreboot and hence these UPDs must be set to
0. There is no need to expose these UPDs in chip.h and provide
mainboard an option to set these in devicetree.
This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from
chip.h and the corresponding devicetree in mainboards. Currently,
shadowmountain already set these UPDs to 0, whereas adlrvp set these
to 1. But all the ADL boards are correctly configuring the GPIO pads
for audio, so this change should not impact audio for any of these
boards.
BUG=b:183482000
TEST=adlrvp and shadowmountain build successfully.
Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the
devicetree option's value is not used anywhere, drop it.
Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
DPTF HIDs are different per-platform going forward, so refactor these
into SoC-specific structures which the DPTF driver can query at runtime
for platform-specific information.
Change-Id: I6307f9d28f4274b851323ad69180ff4ae35053da
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Port 80 (actually 0x80-0x8f) is a fixed I/O range and thus does not have
to be set up as generic range. Drop the entries from the devicetrees.
Change-Id: I8a54d3c35a321a2d57bd846662f7339eff53e5a8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The patch enables Bluetooth config in the devicetree and removes
non-existent Bluetooth PCI interface.
TEST=Verified by checking Garfield Peak controller's PID:VID(8087:0033) in
the lsusb ouput.
Output of lsusb:
Bus 004 Device 003: ID 0bda:8153 Realtek Semiconductor Corp. USB 10/100/1000 LAN
Bus 004 Device 002: ID 0bda:0411 Realtek Semiconductor Corp. 4-Port USB 3.0 Hub
Bus 004 Device 001: ID 1d6b:0003 Linux Foundation 3.0 root hub
Bus 003 Device 003: ID 0781:55a9 SanDisk Corp. Dual Drive
Bus 003 Device 004: ID 413c:2113 Dell Computer Corp. Dell KB216 Wired Keyboard
Bus 003 Device 002: ID 0bda:5411 Realtek Semiconductor Corp. 4-Port USB 2.0 Hub
Bus 003 Device 005: ID 8087:0033 Intel Corp.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I7a54d344ef1b0418bee56e7308977a61604b954a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52182
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The intel/soc/broadwell smihandler has no handler for this APM call.
Change-Id: I2bcec7cce00d433a197a9e2fb01434a2998e1452
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52167
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.
BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP
Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC
TEST=Build, Boot and Verify streaming in both Camera
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5
BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP
Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP
TEST=Able to build ADL-M
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST=Verified build for Shadowmountain
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST= Built and booted on ADL-P LP4 RVP
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to write the GDCRTRAININGRESULT registers after raminit.
Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch disables the unsued CPU PCIe RP for shadowmountain.
TEST= Boot shadowmountain and verify the device is disabled.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
