Commit graph

15087 commits

Author SHA1 Message Date
Angel Pons
0b697a2473 mb/prodrive/hermes: Clean up some cosmetics
Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-03 15:51:22 +00:00
Angel Pons
e81560c6cf mb/prodrive/hermes: Get rid of variant structure
There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.

Reorganize the mainboard code to get rid of the variant structure.

Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-03 15:51:02 +00:00
Angel Pons
c1d49b65b8 mb/prodrive/hermes: Add board URL
Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-12-03 15:50:43 +00:00
Karthikeyan Ramasubramanian
9450a40ffd mb/google/guybrush: Configure EN_SPKR GPIO in PSP verstage
EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID
straps and Developer Mode Beep signals. During boot up it is LOW and
selects RAM_ID straps. When the system enters OS, it is driven HIGH and
selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5
domain it does not reset until the system enters mechanical off (G3)
state. On scenarios where the power button is pressed when the system is
in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still
selecting DEV BEEP signal. This causes boot up failures. Fix this by
configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage.

BUG=b:204450368
TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle
followed by a S5 -> S0 boot cycle for 2 iterations successfully.

Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-03 15:50:21 +00:00
Alan Huang
a7ebca3969 mb/google/brya/var/brask: Enable LAN driver to program MAC
Turn on the LAN device in devicetree and add Kconfig item
RT8168_GET_MAC_FROM_VPD to support programming MAC address.

BUG=b:193750191
BRANCH=None
TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD.
     Use 'ifconfig' to check if the MAC written successfully.

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03 15:49:44 +00:00
Kane Chen
2a30359d5a mb/google/brya/var/brask: Set vGPIO reset type
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack

BUG=b:207625007
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal

Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03 15:38:00 +00:00
Teddy Shih
e0869c3e49 mb/google/dedede: Create beadrix variant
Create the beadrix variant of the waddledee reference board by
copying the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:204882915
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEADRIX

Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-03 15:35:56 +00:00
Malik_Hsu
ac812eda0b mb/google/brya/variants/primus: Swap TPM I2C with touchscreen I2C
In next build phase, primus will exchange i2c port for touchscreen and cr50.

BUG=b:207834727
TEST=build pass

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03 03:32:22 +00:00
Kevin Chang
df72b18db7 mb/google/brya/var/taeko: Set vGPIO reset type
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack

BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03 03:32:11 +00:00
Joey Peng
900758bd33 mb/google/brya: Create taniks variant
Create the taniks variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)

BUG=b:207402720
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TANIKS

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-03 03:15:21 +00:00
Alan Huang
b1da051f17 mb/google/brya/var/brask: Set PL and PsysPL
1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55
   and Intel's doc #626774.
2. Set PsysPL2 and PsysPmax according to the conclusion in issue
   b:193864533 comment#23 and comment#29.

BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
     from the command 'dump_intel_rapl_consumption'.

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02 21:00:16 +00:00
Alan Huang
b974dd96b6 mb/google/brya/var/baseboard/brask: Add power limits functions
Copy function variant_update_power_limits from brya to set power limits.

Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and configure the psys power limits.

BUG=b:193864533
BRANCH=none
TEST=Build pass

Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02 21:00:00 +00:00
Mark Hsieh
4457768300 mb/google/brya/var/gimble: Swap TPM I2C with touchscreen I2C
DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap
TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C,
need change I2C map, sch amd GPIO map. b/196293623

BUG=b:207613972
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02 20:51:48 +00:00
Eric Lai
cca657f898 mb/google/brya/var/felwinter: Swap TPM and touchscreen I2C bus
Follow the latest HW schematic change.

BUG=b:208556921
TEST=build pass

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-02 20:46:49 +00:00
Meera Ravindranath
1ce0f3aab7 mb/google/brya: Fix S0i3 regression
Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)

BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after
exiting S0ix suspend states.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-02 16:37:32 +00:00
Angel Pons
db925aaf38 soc/intel/alderlake: Add Kconfigs for all PCH types
The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.

Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.

Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-12-02 12:36:25 +00:00
Vadim Bendebury
74033df2bd guybrush: add RO_GSCVD area to FMAP
This area is used for storing AP RO verification information.

BRANCH=none
BUG=b:141191727
TEST=built a guybrush firmware image and verified that the RO_GSCVD
     area was indeed added:

 $ dump_fmap /build/guybrush/firmware/image-guybrush.bin  | \
     grep -B3 RO_GSCVD
 area:            25
 area_offset:     0x00808000
 area_size:       0x00002000 (8192)
 area_name:       RO_GSCVD
 $

  - verified that guybrush device boots fine with the new image.

Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01 23:34:54 +00:00
Tim Wawrzynczak
0167f5adbb mb/google/brya/redrix: Add _HID for privacy screen device
The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this.

Patch for 5.10 kernel can be found at:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984

BUG=b:206850071
TEST=dump SSDT, see _HID instead of _ADR

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-01 22:05:00 +00:00
Sandeep Maheswaram
ccff304751 herobrine: Assert gpio for USB_HUB_LDO_EN
Some herobrine variants have USB hub powered by discrete LDO that is
controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot.

BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-01 00:39:51 +00:00
Ravi Kumar Bokka
d11c814172 mb/google/herobrine: Initialize USB by calling SOC method
Initialize by calling `setup_usb_host0()` from SOC code

BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
2021-11-30 23:31:24 +00:00
David Wu
b63e1f114b mb/google/brya/var/kano: Enable USB2 port 9 for BlueTooth
BlueTooth disappeared after disabled USB2 port 9,
so we need to re-enable it.

BUG=none
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7971509d7428562c80e781339ead059a189cea13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-30 19:44:50 +00:00
wizard
50f428d48b mb/google/dedede/var/beetley: Enable GEO_SAR_ENABLE for beetley
BUG=b:207307897
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.

Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e
Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
2021-11-30 17:45:11 +00:00
YH Lin
6ba7bee1aa brya: add various ES variants
Fork multiple "4ES" variants off some brya devices to
properly support ES SoC.

BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts

Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-30 17:11:56 +00:00
Sandeep Maheswaram
6c2b860691 soc/qualcomm/common/usb: Add support for common USB driver
Add common USB driver for qualcomm soc sc7180 and sc7280.

This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.

BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board

Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-29 23:43:49 +00:00
Kyösti Mälkki
88da0b8622 mb/lippert/frontrunner-af: Use common cpu/ and nb/ ASL files
There are no quad-core CPU models with fam14, \_SB.C002 and .C003 get
removed from ASL.

Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-29 17:35:23 +00:00
Kyösti Mälkki
60df92fdce lippert/frontrunner-af: Use common cimx/sb800 ASL
Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-28 16:40:03 +00:00
Kyösti Mälkki
6670c68934 lippert/frontrunner-af: Fix PCI devices ASL
There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.

There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.

Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-28 16:38:25 +00:00
Kyösti Mälkki
0d30ddde55 sb/amd/cimx/sb800: Separate a section from fch.asl
The section is the same and at root scope.

Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-28 16:38:13 +00:00
Michał Żygowski
8ddbc7dcbe mb/dell/optiplex_9010/romstage.c: Add interrupt routing map
Dumped using inteltool from the Dell BIOS version A30.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-27 14:24:12 +00:00
Rex-BC Chen
fca89d3d05 mb/google/corsola: Add an option for SD card initialization
There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26 11:23:43 +00:00
Rex-BC Chen
81a69665dc mb/google/corsola: Get RAM code from ADC
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26 11:23:01 +00:00
Rex-BC Chen
47516553fb mb/google/corsola: Raise little CPU frequency
Raise little CPU to 2GHz at romstage.

TEST=check little core cpu frequency is 2GHz
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26 11:22:21 +00:00
Rex-BC Chen
c5e56f5948 mb/google/corsola: Add VPROC12/VSRAM_PROC12 to regulator interface
Add VPROC12/VSRAM_PROC12 to adjust power for raising little
CPU frequency.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I59b4627220022a51a116716036a8ba0048039508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26 11:22:03 +00:00
Rex-BC Chen
580150de46 mb/google/corsola: configure GPIOs
Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-26 11:20:14 +00:00
David Wu
02cef7a4a8 mb/google/brya/var/kano: swap TPM i2c with TS i2c for the next build phase
Kano EVT will exchange i2c port for touchscreen and cr50.

BUG=b:195853169
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-26 11:19:16 +00:00
Malik_Hsu
655fa5c39b mb/google/brya/variants/primus: update gpios for power consumption
In different sku, some unused GPIO pins are processed by NC for power
consumption.

BUG=b:196790249
TEST=emerge-brya coreboot chromeos-bootimage and check power

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 23:49:50 +00:00
Kane Chen
7fd65a9791 src/mb/brya: Enable crashlog on brya0
Enabling crashlog helps partners to debug hang issues efficiently.

BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in
depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble

Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 21:06:36 +00:00
Simon Glass
e0ab086028 emulation/qemu-i440fx: Use a 4MB ROM by default
At present the default ROM for for QEMU is too small for U-Boot to fit.
Add a condition to catch this and expand it to a 1MB ROM. This allows
booting U-Boot under emulation.

It also matches the size used by other emulation boards.

Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia1a8c1109e3ece5fec56255173a2d19d4a130bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-25 21:05:34 +00:00
Malik_Hsu
4298e13868 mb/google/brya/variants/primus: add fw config probe for speaker amp
Added fw config probe for MX98360A.

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I2452b752ce58a5d0f1008cf187fb79ace6c4285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 19:43:19 +00:00
John Su
2cb8ed1128 mb/google/brya/var/felwinter: Add DPTF parameters for Felwinter
The DPTF parameters were verified by the thermal team.

BUG=b:207463762
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 13:31:19 +00:00
Ariel_Fang
7fe266d59d mb/google/brya/var/primus: Update thermal table for primus
- Add 4 TEMP_SENSORs
- Configure granularity of power limits

BUG=b:200836803
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com>
Change-Id: Id4d8dbe678b7f0870aeffa0a0118e65de9d5c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25 10:43:08 +00:00
David Wu
3e8ca37b6c mb/google/brya/var/kano: Update thermal table
Update thermal setting from thermal team.

BUG=b:205648035
TEST=build and verified by thermal team.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If5082462b79c88ecf510f7a552381c792604366e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-25 10:42:56 +00:00
David Wu
9ed2490e5b mb/google/brya/var/kano: set power limits for thermal
Set power limits for kano based on CPU SKUs.

BUG=b:205648035
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-25 10:41:12 +00:00
Mark Hsieh
05c6d65308 mb/google/brya/var/gimble: Enable DRIVERS_GENESYSLOGIC_GL9750
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble.

BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-24 17:10:01 +00:00
Evgeny Zinoviev
72628fa813 mb/lenovo: Enable MEI on Sandy Bridge ThinkPads
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.

On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.

Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.

Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2021-11-23 16:57:14 +00:00
Angel Pons
b207f3f370 mb/prodrive/hermes: Number Ethernet devices
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:

 PHY 0 ---> enp6s0
 PHY 1 ---> enp4s0
 PHY 2 ---> enp3s0
 PHY 3 ---> enp1s0
 PHY 4 ---> enp2s0

These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.

To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:

 PHY 0 ---> eno0
 PHY 1 ---> eno1
 PHY 2 ---> eno2
 PHY 3 ---> eno3
 PHY 4 ---> eno4

No matter what PCIe devices are present, these names don't change.

Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-23 16:56:51 +00:00
Michał Żygowski
8ebea12763 mb/dell/optiplex_9010/devicetree.cb: Enable missing GPEs
Enable PCI_EXP_EN, PME_EN and PME_B0_EN GPEs used for PCI devices.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I4480921a294f35a0dfe1e5acd90d55f6fb4c85b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-11-23 16:55:38 +00:00
Michał Żygowski
aa133e42ba mb/dell/optiplex_9010/Kconfig: Select Super I/O UART availability
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie1b270d49660fd60b6a91194167467c4453e1b6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-11-23 16:54:55 +00:00
Tim Crawford
34b70fd163 mb/system76/*: Enable dGPU temp/fan reporting
Select the EC option on boards with dGPUs to report GPU temperature and
fan data.

Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.

    system76_acpi-acpi-0
    Adapter: ACPI interface
    CPU fan:     1985 RPM
    GPU fan:     2348 RPM
    CPU temp:     +68.0°C
    GPU temp:      +0.0°C

Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23 09:22:42 +00:00
Tim Crawford
12a98ffbfb mb/system76/*: Disable IME by CMOS option
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.

The HECI device must be enabled in devicetree for switching modes to
function correctly.

Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-23 09:22:10 +00:00
Wisley Chen
d88d2da813 mb/google/brya/var/redrix: Disable autonomous GPIO power management
With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.

BUG=b:202246591
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage.

Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-23 09:20:53 +00:00
Julian Stecklina
15235b2d89 emulation/qemu-i440fx,q35: avoid writing to ROM
libcbfs has a workaround to avoid writing to ROM areas:

        /* Hacky way to not load programs over read only media. The stages
         * that would hit this path initialize themselves. */
        if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) &&
            !CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {

This workaround is not triggered in QEMU, because
BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This
results in confusing (to the VMM developer) writes to read-only
memory.

As far as I can tell, this issue is weird but harmless, because the
code does memcpy to ROM with source == destination. The concensus in
the mailing list thread [1] was that it's worthwhile to be fixed
regardless.

[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI6YQCPXSQF4NDUAAC7TIXQKSZ6T4X7/

Change-Id: I5cefbc31f917021236105f7dc969118d612ac399
Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-23 09:20:28 +00:00
Sheng-Liang Pan
f1dbd67381 mb/google/trogdor: change pin define for quackingstick
change TP_EN pin to GPIO_67 for quackingstick

BUG=b:206862167
BRANCH=trogdor
TEST=make

Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7cc1083111f46cd3489cbbb9e579c34dc972b0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Bob Moragues <moragues@google.com>
2021-11-23 09:20:05 +00:00
Angel Pons
63c0fd2dbe mb/prodrive/hermes: Rename "internal audio" setting
The "internal audio connection" setting is actually about the front
panel audio. Rename functions and variables to reflect this.

Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-11-22 16:21:49 +00:00
Bernardo Perez Priego
c47beec2d3 mb/intel/adlrvp: Use dedicated VBT files for ADL-M
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.

VBT files added at chrome-internal:4138272

BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.

Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2021-11-22 15:11:36 +00:00
Adam Liu
37e261f374 mainboard/google/brya: Enable dev screen in bios-stage for Brask
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION.

TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage.
BUG=b:199490251, b:206014054

Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com>
Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:55:10 +00:00
David Wu
6de48981fa mb/google/brya: Move cr50 configuration to variant
Brya schematic will swap TPM I2C with touchscreen I2C,
so move into variant level.

BUG=b:195853169
TEST=build pass.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ie5276527da135ec15045a81985ae006722871b0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:54:44 +00:00
Malik_Hsu
797bc1b8e4 mb/google/brya/variants/primus: add fw_config_probe for ALC5682I-VS
Added fw_config_probe method to distinguish different audio codecs to
facilitate the use of different topology files by the OS.

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:53:53 +00:00
Eric Lai
6b81adf8bc mb/google/brya/var/felwinter: Add ALC5682I-VS codec support
ALC5682I-VS will use in next build.

BUG=b:194367025
TEST=none.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-22 14:53:39 +00:00
Sean Rhodes
17441a3ac5 mainboard/starlabs: Add StarBook Mk V
Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21

No known issues.

https://starlabs.systems/pages/starbook-specification

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I090971a9e8d2be5b08be886d00d304607304b645
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56088
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-22 14:53:04 +00:00
Seunghwan Kim
be0722ac91 mb/google/dedede/var/bugzzy: Configure Acoustic noise mitigation UPDs
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8
which is calibrated value for the board.

BUG=b:207046230
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-22 14:47:50 +00:00
Joey Peng
7cbf203d9b mb/google/brya: Move EC_HOST_EVENT_USB_MUX wake event to S0ix only
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.

BUG=b:206867635
TEST=emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19 22:51:56 +00:00
Sheng-Liang Pan
bef23d1f79 mb/google/volteer/var/chronicler: set DdrMemoryDown enable
as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1.

BUG=b:192478111
BRANCH=volteer
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19 15:35:25 +00:00
Varshit B Pandya
f0e721050a mb/google/brya/var/redrix: Configure _DSC for CAM devices to ACPI_DEVICE_SLEEP_D3_COLD
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial
probe during kernel boot and prevent privacy LED blink.

BUG=b:199823938
TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED
during boot.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-19 14:54:02 +00:00
Meera Ravindranath
98e827ea74 mb/intel/adlrvp: Enable CPU PCIe RP 2
Disabling CPU PCIe RP 2 (commit:3fd39467b Fix S0ix regression)
causes regression in NVMe boot on ADL-P RVP boards.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76a5537d8b80777cb7588ce6b22281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59392
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-19 06:21:21 +00:00
Rob Barnes
188be6b270 mb/google/guybrush: Add variant_tpm_gpio_table
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:33:15 +00:00
Eric Lai
eae7bf2327 mb/google/brya/var/felwinter: Correct USB3 TCSS setting
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per
port. And if uses USB3 directly you need to set TcssAuxOri accordingly.

BUG=b:206716691,b:205235144
TEST=USB function work as expected at USB3 only sku.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:32:43 +00:00
Mark Hsieh
88295c35cc mb/google/brya/var/gimble: Include 2 new SPDs
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B
and MT53E512M32D1NP-046 WT:B.

BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-18 23:32:22 +00:00
Wisley Chen
da815303a3 mb/google/brya/var/redrix: De-assert SSD PERST# in romstage
After CB:57539 applied, it can support romstage GPIO table override.
We can move SSD PERST# de-assertion to romstage.

The reason for this is to give enough time after PERST#
deassertion so that the SSD has enough time to initialize before
the FSP scans the RPs for downstream devices.

BUG=b:199714453
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:58 +00:00
Wisley Chen
cd04c6e07d mb/google/brya/var/redrix: Correct WWAN power sequence
Correct the WWAN power sequence to meet spec

BUG=b:206079177
TEST=build

Change-Id: Ibba1ecc04b563ae4eedd7596594f33812cbac150
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:40 +00:00
Wisley Chen
e589ee3879 mb/google/brya/var/redrix: Configure Acoustic noise mitigation
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8

BUG=b:204009588
TEST=build and verified by power team

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-18 23:31:21 +00:00
Zheng Bao
570645dc2a amdfwtool: Call the set_efs_table for Stoneyridge
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.

But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.

Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-18 23:29:48 +00:00
Eric Lai
3feddeb398 mb/google/brya/var/felwinter: Add MT53E1G32D2NP-046 WT:B SPD
Add MT53E1G32D2NP-046 WT:B SPD.

BUG=b:205669003
TEST=Boot up without issues.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If084a8af941b36a8f3f608271078e32b093d9108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 23:46:03 +00:00
Matt DeVillier
9afe02798a mb/google/cyan: use shared touchpad/touchscreen interrupts
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Cyan's touchpad/touchscreen interrupts as SharedAndWake
rather than ExclusiveAndWake.

Test: build/boot Windows 10 on Relm, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad/touchscreen in use.

Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 23:45:50 +00:00
Zanxi Chen
e1095496e1 mb/google/trogdor: Adjust mipi panel backlight gpio
According hareware design, mipi panel backlight relies on
AP_BKLTEN(GPIO_12) and TP_EN(GPIO_85). Meanwhile, TP_EN(GPIO_85)
needs pull up to enable PP3300_DISP_ON before AP_BKLTEN(GPIO_12) up.

BUG=b:197709288,b:199081803,b:205166230
BRANCH=trogdor
TEST=emerge-strongbad coreboot

Change-Id: Ie9920e5366f6b1ea9e0da228bd211317516b390a
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-17 18:50:37 +00:00
Joey Peng
0087de817a mb/google/brya/var/taeko: Correct touchpad GPE settings
Correct GPE settings so touchpad can wake up DUT.

BUG=b:206526991
TEST=emerge-brya coreboot and builds without error

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 18:44:16 +00:00
Joey Peng
fcb267a81d mb/google/brya/var/taeko: disabled autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 18:44:05 +00:00
Casper Chang
d16a085110 mb/google/brya/variants/primus: Correct SSD power sequence
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.

BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.

Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:48 +00:00
Boris Mittelberg
5c3d12eaee mb/google/brya: Enable early EC sync
Enable VBOOT_EARLY_EC_SYNC in corebot

BUG=b:201356952
BRANCH=None
TEST=Tested on Brya id 2

Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I6e480d64a5d90d5bb9cf59ed60b7b53af9edf46a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:31 +00:00
Matt DeVillier
f9df79e8d6 mb/google/hatch: Add VBTs for variants
Add VBTs for all hatch variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.

Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:32:10 +00:00
Matt DeVillier
f347166928 mb/google/hatch: Alphabetize variants in Kconfig.name
Change-Id: Ie29242e635bae1e2754bc1109754a64cb496af29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:31:40 +00:00
Eric Lai
6296ae0258 mb/google/brya: Move typeC AUX configuration to variant
TypeC AUX configuration is variant specific. So move into variant level.

BUG=b:205235144
TEST=No typeC port 0 AUX in felwinter.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:31:23 +00:00
Kevin Chiu
a592bef03f mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin
For Guybrush Board Version 2, Nipperking Board Version 1,
update SPKR GPIO to match H/W schematic:
SPKR: GPIO31

For Nipperkin Board Version 2, update SPKR GPIO to
match H/W schematic:
SPKR: GPIO70

BUG=b:202992077
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-17 14:30:34 +00:00
Matt DeVillier
1a4b132413 mb/google/octopus: Add missing VBTs for variants
Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.

Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:28:46 +00:00
Matt DeVillier
e08df8e138 mb/google/octopus: Alphabetize variants in Kconfig.name
Change-Id: I2e57c4f1baa8a42bde2642e7f76ddead7bfd6a58
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:27:47 +00:00
Matt DeVillier
a952b3f794 mb/google/slippy/peppy: use shared touchpad interrupts
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Peppy's interrupts as Shared rather than the default
of Exclusive.

Test: build/boot Windows 10 on Peppy, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad in use.

Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 14:27:32 +00:00
Werner Zeh
98c7d55eaa mb/siemens/mc_ehl1: Send POST codes to NC FPGA via PCI
This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.

Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-17 14:27:03 +00:00
Yuchen Huang
9a640c0f69 soc/mediatek/mt8186: Add RTC and clkbuf drivers
Add support for RTC and clkbuf.

TEST=boot to kernel and check log ok
BUG=b:202871018

Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: Ia02a74f685feb2466c113a77cbfa3a7d8fedb595
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:31:32 +00:00
Rex-BC Chen
ad5fda5fbf mb/google/corsola: Initialize SPM
Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.

TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:31:14 +00:00
Rex-BC Chen
15486f44a2 soc/mediatek: move MSDC drivers to soc folder
Setting of MSDC is defined by soc, so we move them to soc folder.

TEST=emerge-cherry coreboot; emerge-asurada coreboot

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-17 10:30:27 +00:00
Bora Guvendik
db85b096d4 mb/intel/adlrvp: Fix sagv point3 clipping to 4800Mhz
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.

TEST=Boot to OS, verify frequency locked.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:35:59 +00:00
Meera Ravindranath
3fd39467b5 mb/intel/adlrvp: Fix S0ix regression
The following changes are needed to fix S0ix regression on RVP
1) Disable Clk src 3
2) Disable Ext FIVR settings

TEST=Boot adlrvp to OS, confirm S0ix is working.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b8b76b5527d8b80776cb7588ce6b12281af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-11-17 00:35:18 +00:00
Malik_Hsu
df99e57289 mb/google/brya/variants/primus: enable ALC5682I-VS
In next phase build, the audio codec will change to ALC5682I-VS

BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-17 00:34:41 +00:00
Wisley Chen
88c0faddad mb/google/brya/var/redrix: Update dsm parameters for speeker/tweeter
For tuning, redrix needs differnet dsm paramters file for L/R
speeker/tweeter.

BUG=b:204841998
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I6f93603a6809f9a5aea9f2e554935de5d0457286
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-16 13:01:49 +00:00
Rex-BC Chen
4ab77addc5 soc/mediatek/mt8186: add early initialization for eMMC
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.

TEST=boot kernel from eMMC ok
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16 08:01:57 +00:00
Wenbin Mei
966b502d35 mb/google/corsola: Configure eMMC and SD Card
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.

TEST=boot kernel from eMMC and SDCard ok
BUG=b:202871018

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16 08:01:32 +00:00
Wenbin Mei
1cbcfc13eb soc/mediatek/mt8186: Configure eMMC and SD Card
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.

TEST=build pass
BUG=b:202871018

Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-16 08:01:27 +00:00
Kevin Chiu
2ec91a37bc mb/google/brya/var/vell: Generate LP5 RAM ID
Add the support LP5 RAM parts for vell:
DRAM Part Name                 ID to assign
MT62F512M32D2DR-031 WT:B       0 (0000)
MT62F1G32D4DR-031 WT:B         1 (0001)

BUG=b:204284866
TEST=emerge-brya coreboot

Change-Id: I49745948ebdb25fd98e285defd75714f80271968
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
2021-11-16 02:52:22 +00:00
Rob Barnes
da0c4f42f6 mb/google/guybrush: Make GPIO_69 default for SD_AUX_RESET_L
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant
is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default
and only overriding to GPIO_70 for guybrush bid==1.

BUG=b:202992077
BRANCH=None
TEST=Build and boot guybrush, SD card works

Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-16 00:36:02 +00:00
Wisley Chen
b8b833fc6a mb/google/brya/var/redrix: Hook up two missing sensors
Redrix has 4 thermal sensors, so add the missing sensors settings.

BUG=b:200134784
TEST=build and verified by thermal team.

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15 18:27:29 +00:00
Shelley Chen
d31effffc8 mb/google/herobrine: Use same I2C/SPI configs for piglin and hoglin
As Hoglin variant was recently added, need to make sure that it uses
the same configs as piglin.

BUG=b:197366666
BRANCH=None
TEST=create hoglin image and make sure that it boots on CRD 2.0

Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-15 17:04:07 +00:00
Hsuan-ting Chen
642508aa9c Reland "vboot_logic: Set VB2_CONTEXT_EC_TRUSTED in verstage_main"
This reverts commit adb393bdd6.
This relands commit 6260bf712a.

Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage

This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
			   poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.

For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
	     early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
	     it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.

For qemu-q35: Add support for get_ec_is_trusted() with always trusted.

We could attempt another land.

Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 12:00:12 +00:00
Mario Scheithauer
436eac827a mb/siemens/mc_ehl2: Adjust PCIe clock source settings in devicetree
With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.

Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-15 11:19:50 +00:00
Mario Scheithauer
ed784bc0a7 mb/siemens/mc_ehl: Disable HECI #2 device
HECI #2 is not used for CSE communication. Therefore, it is not
necessary to set the parameter 'Heci2Enable' in devicetree.

Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-15 11:12:22 +00:00
Eric Lai
f005c34172 mb/google/brya/var/felwinter: Disable PCIE port 6
PCIE port 6 is empty as per schematics.

BUG=b:206047996
TEST=PCIE port 6 is disabled.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 10:08:32 +00:00
Eric Lai
fb02f0a55e mb/google/brya/var/felwinter: Remove USB2 port 0
USB2 port 0 is empty as per schematics.

BUG=b:206047996
TEST=USB2 port 0 is disabled.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 10:08:12 +00:00
Eric Lai
91c3ace5af mb/google/brya/var/felwinter: Enable garage pen detection
Enable garage pen detection.

BUG=b:197912223
TEST=Check evtest can trigger event when toggling the switch.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib5929c876d1a0da34dadd7997a61ab8e75acbbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 10:07:29 +00:00
Malik_Hsu
434fa6367f mb/google/brya/variants/primus: enable RTD3 for PCIe-eMMC bridge
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less
than 1, do not enable RTD3 driver.

BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed

Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 10:03:06 +00:00
Sumeet Pawnikar
f1d0c828d7 mb/google/brya/variants/gimble: Update PL1 min value
Update PL1 minimum value from 3W to 12W as per the thermal design
discussed in this bug 203371203 comment #10.

BUG=b:203371203
BRANCH=None
TEST=Build and boot the gimble system

Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 09:58:50 +00:00
David Wu
53075c720b mb/google/brya/var/kano: Add thermal sensor settings
Kano has 3 thermal sensors, so add the missing sensor settings.

BUG=b:205648035
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I0da25f142149f94c83fdf7b2ba2cb8694cddb412
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-11-15 09:46:30 +00:00
Shon Wang
b8f0539d2d mb/google/brya: Create vell variant
Create the vell variant of the brya0 reference board by copying
the template files to a new directory named for the variant.

(Auto-Generated by create_coreboot_variant.sh version 4.5.0).

BUG=b:205908918
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_VELL

Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-15 04:45:03 +00:00
Rex-BC Chen
66bed5495b mb/google/corsola: Add VMCH and VMC for regulator interface
Add VMCH and VMC for providing power of SDCard.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I50fc87415086eb22ff35d157dba38cfd7594cc40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 03:08:00 +00:00
Rex-BC Chen
2f9e5b9e34 soc/mediatek/mt8186: add USB support
1. Enable and setup USB drivers.
2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset
   the hub via GPIO149.

TEST=boot kernel from USB ok
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 03:07:15 +00:00
Rex-BC Chen
ea0b13205a mb/google/corsola: Implement regulator interface
Use regulator interface to use regulator more easily.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ied43cba51036c62a120df2afffeb63b5d73f012b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 03:07:08 +00:00
Rex-BC Chen
fb06ca0aa7 mb/google/corsola: add configuration for kingler and krabby
The 'corsola' reference design will include two implementations
with different BOM selections - 'krabby' and 'kingler'.

TEST=none
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 03:07:00 +00:00
James Lo
1e0765d85c soc/mediatek/mt8186: Add support for PMIC MT6366
Add basic support for VCORE/VDRAM1/VDDQ of MT6366.

TEST=build pass
BUG=b:202871018

Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I22e30421560a32f4a9e15899e8150376b1414494
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-15 03:06:25 +00:00
Rob Barnes
f6e421ffc9 mb/google/guybrush: Add variant_espi_gpio_table
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.

BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush

Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13 00:54:21 +00:00
David Wu
999f9e3487 Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"
This reverts commit ba6fdc892d.

Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic.

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-13 00:19:33 +00:00
Kyösti Mälkki
d1598991a3 google/stout: Remove duplicate recovery mode switch entry
Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12 19:30:13 +00:00
Kyösti Mälkki
071d1787fd google/butterfly: Refactor get_recovery_mode_switch()
Do not place console output in low-level GPIO functions.

The caller of get_recovery_mode_switch() is in vboot_logic.c
that is linked in romstage. So presumably recovery mode
is broken and is not fixed with this commit either.

Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12 19:29:23 +00:00
Zanxi Chen
4f021e554f mb/google/trogdor: Modify BOE panel_id for mrbland
Modify BOE panel_id for mrbland due to hardware changes.

BUG=b:205166230,b:198548221
BRANCH=trogdor
TEST=emerge-strongbad coreboot

Change-Id: I65fecd854c4e3443edc07a44a1d43572d5030e4c
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58995
Reviewed-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-12 17:20:51 +00:00
Casper Chang
b139e6b2a3 mb/google/brya/var/primus: Disable autonomous GPIO power management
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M

BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.

Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12 14:55:15 +00:00
Kyösti Mälkki
09a66ace7e google/deltaur,drallion,sarien: Refactor ChromeOS GPIOs
Low-level GPIOs should not depend on late cros_gpios that
should be guarded with CHROMEOS and implemented for the
purpose of ACPI \OIPG package generation.

Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12 11:24:58 +00:00
Kyösti Mälkki
4bcc275d71 mb/google,intel: Add ChromeOS GPIOs to onboard.h
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12 11:23:00 +00:00
Eric Lai
d4c7735930 mb/google/brya/var/felwinter: Enable SaGv
Enable SaGv.

BUG=b:198235324
TEST=Boot into without issues.

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 22:46:03 +00:00
Jeremy Soller
8065c6d729 mb/system76/gaze16: Add System76 Gazelle 16
https://tech-docs.system76.com/models/gaze16/README.html

The gaze16 comes in 3 variants due to differences in the discrete GPU
and network controller used.

- NVIDIA RTX 3050, using Realtek Ethernet controller
- NVIDIA RTX 3060, using Realtek Ethernet controller
- NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller

Tested on the 3050 variant.
Tested with TianoCore (UefiPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- M.2 NVMe SSD
- M.2 SATA SSD
- 2.5" SSD
- All USB ports
- SD card reader
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- HDMI output
- Internal microphone
- Internal speakers
- Combined headphone + mic 3.5mm audio*
- 3.5mm microphone input*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.04 and Windows 10 20H2
- Flashing with flashrom

Not working:

- Discrete/Hybrid graphics
- Mini DisplayPort output (requires NVIDIA GPU)
- 3.5mm audio input/output detection on Windows

Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11 22:45:55 +00:00
David Wu
bfc4d8ef1c mb/google/brya/var/kano: Configure USB2 and USB3 port
Disable unused USB2 and USB3 port

BUG=b:192370253
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 22:45:42 +00:00
David Wu
6db243acd0 mb/google/brya/var/kano: Add gpio-keys ACPI node for PENH
Use gpio_keys driver to add ACPI node for pen eject event.  Also
setting gpio wake pin for wake events.

BUG=b:192415743
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11 22:40:20 +00:00
Karthikeyan Ramasubramanian
f8fe39baca mb/google/guybrush: Define ACPI Power Resources for FPMCU
Currently all the power sequencing for FPMCU is done explicitly in
different stages of coreboot. This can all be done by adding ACPI power
resources for FPMCU and clean up the unused code. Here is the expected
power sequence:
PowerUp  : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL
Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL
Reboot   : Shutdown -> 200 ms delay -> PowerUp

BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to
unlock the system after the first login attempt. Ensure that the FP is
able to wakeup the system. Observed that the power resource is added
correctly in the FPMCU ACPI object
            Name (_PR0, Package (0x01)  // _PR0: Power Resources for D0
            {
                PR01
            })
            Name (_PR3, Package (0x01)  // _PR3: Power Resources for D3hot
            {
                PR01
            })
            PowerResource (PR01, 0x00, 0x0000)
            {
                Method (_STA, 0, NotSerialized)  // _STA: Status
                {
                    Return (0x01)
                }

                Method (_ON, 0, Serialized)  // _ON_: Power On
                {
                    \_SB.CTXS (0x0B)
                    \_SB.STXS (0x20)
                    \_SB.STXS (0x0B)
                }

                Method (_OFF, 0, Serialized)  // _OFF: Power Off
                {
                     \_SB.CTXS (0x0B)
                     \_SB.CTXS (0x20)
                }
            }

Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11 18:05:12 +00:00
Joey Peng
7bca1e474c mb/google/brya/var/taeko: Enable CPU PCIE RP 1
Modify settings to enable CPU PCIE RP 1 according to schematics.

BUG=b:205504257
TEST=emerge-brya coreboot and can successfully boot with ssd and emmc.

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 16:18:01 +00:00
Chris.Wang
ca69152579 mb/google/guybrush/dewatt: update dewatt config
copy config from guybrush reference board.

BUG=b:204151079
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11 16:01:15 +00:00
Mark Hsieh
03c3d5d68e mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C port
- Set MAX OC1 to USB2_C1

BUG=b:205676803
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-11-11 15:50:42 +00:00
Eric Lai
67b91b9344 mb/google/brya/var/felwinter: Update typeC EC mux port
We need to put USB setting in mux order.

BUG=b:204230406
TEST=Type C mux configuration is correct.
Wrong:
added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
Correct:
added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11 14:33:39 +00:00
Mark Hsieh
b11de6fa09 mb/google/brya/variants/gimble: Update audio setting for SmartAMP
Divide dsm_param_file_name into dsm_param_R and dsm_param_L

BUG=b:205684021
TEST=build and check SSDT

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11 14:33:12 +00:00
FrankChu
fb05b820eb mb/google/dedede/var/galtic: update Wifi SAR for convertibles
Add wifi sar for galtic/galtic360/galith360
Using convertible mode of SKU ID to load wifi table.

Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)

BUG=b:203741126
TEST=emerge-dedede coreboot chromeos-bootimage \
     coreboot-private-files-baseboard-dedede
     verify the SAR table is correct in each project

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11 14:32:57 +00:00
Kyösti Mälkki
4b6ad4efe3 samsung/lumpy,stumpy: Add get_power_switch()
Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11 13:28:41 +00:00
Kyösti Mälkki
51df45f0f9 samsung/lumpy: Add get_lid_switch()
Change-Id: Ib360a6fa00d0ebda4635b96f1b671a66c1ca11c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11 13:27:41 +00:00
Kyösti Mälkki
8355e6e723 google/beltino,jecht: Refactor ChromeOS GPIOs
Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11 13:18:09 +00:00
Kyösti Mälkki
0cb116647e samsung/lumpy,stumpy: Refactor ChromeOS GPIOs
Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11 13:17:38 +00:00
Subrata Banik
6de8b42482 arch/x86: Refactor the SMBIOS type 17 write function
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).

Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.

BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Unknown
        ....

With this code change:

Handle 0x0012, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 16 bits
        Data Width: 16 bits
        Size: 2048 MB
        Form Factor: Row Of Chips
        ....

Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 09:10:10 +00:00
Kyösti Mälkki
9a3bde0581 ChromeOS: Replace with or add <types.h>
It's commented in <types.h> that it shall provide <commonlib/helpers.h>.

Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.

Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 06:25:12 +00:00
Kyösti Mälkki
bc94d60924 intel/strago: Fix some CHROMEOS guards
MAINBOARD_HAS_CHROMEOS always evaluates true for this board.

The commentary about get_write_protect_state() was wrong, it's
currently only called in ramstage.

Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-11 06:22:19 +00:00
Sumeet Pawnikar
6df98f066b mb/google/brya: Enable thermal control functionality for tpch
Enable DPTF based thermal control functionality for tpch device
on brya device.

BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board

Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11 04:32:20 +00:00
Shelley Chen
4e9bb3308e Rename ECAM-specific MMCONF Kconfigs
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space.  Some platforms have a different way of mapping the PCI config
space to memory.  This patch renames the following configs to
make it clear that these configs are ECAM-specific:

- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH

Please refer to CB:57861 "Proposed coreboot Changes" for more
details.

BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
     Make sure Jenkins verifies that builds on other boards

Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10 17:24:16 +00:00
Wisley Chen
90d79a751b mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%
Set RFI Spread Spectrum to 6% for Redrix as RF team request.
The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.

BUG=b:200886627
TEST=build

Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09 20:48:26 +00:00
Reka Norman
6d27905e03 mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/B
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.

BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-09 19:19:51 +00:00
xuxinxiong
ba2b1139f1 google/trogdor: Update the power on sequence of ps8640
For the Qualcomm PBL configuration of GPIO, we need to initial the
GPIOs for VDD33# and RST# at the beginning of coreboot. According to
the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#.

BUG=b:204637643
BRANCH=trogdor
TEST=verified the waveform of ps8640 at coreboot phase.

Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09 18:42:33 +00:00
David Wu
a003c33aa1 mb/google/dedede/var/metaknight: Probe and enable amplifier operation mode
Probe the fw_config for RT1015 speaker amplifier operation mode and
enable it accordingly in the device tree.

BUG=none
BRANCH=dedede
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09 18:41:40 +00:00
Seunghwan Kim
8fbfc080fc mb/google/dedede/var/bugzzy: Adjust I2C speed
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns
and fall_time_ns values for each port are capured by a scope.

BUG=None
BRANCH=dedede
TEST=built and verified adjusted I2C speed < 400KHz

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09 18:40:59 +00:00
Tyler Wang
e9654a857f mb/google/dedede/var/magolor: Enable ELAN touchscreen for magneto
Add ELAN touchscreen support for magneto.

BUG=b:203122673
TEST=Build and verify that touchscreen works.

Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09 18:40:44 +00:00
Seunghwan Kim
8295cddfd2 mb/google/dedede/var/bugzzy: Update charger performance control table
Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.

BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09 18:40:32 +00:00
Seunghwan Kim
1d63714dae mb/google/dedede/var/bugzzy: Enable Wifi SAR
BUG=None
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
     emerge-dedede coreboot chromeos-bootimage

Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09 18:40:13 +00:00
Kyösti Mälkki
085fdd8559 emulation/qemu-i440fx,q35: Split chromeos.c
This drops VBOOT_NO_BOARD_SUPPORT.

There is little impact of always having recovery_mode_switch()
implemented in bootmode.c. A weak write_protect_state() is not
necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation.
Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS)
so the weak implementation would not be referenced.

Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09 14:55:01 +00:00
Nico Huber
f4f365fdd0 pci_mmio_cfg: Always use pci_s_* functions
When MMIO functions are available, the pci_s_* functions do exactly
the same thing. Drop the redundant pci_mmio_* versions.

Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09 11:05:33 +00:00
Kyösti Mälkki
91c077f6e2 ChromeOS: Fix <vc/google/chromeos/chromeos.h>
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09 00:14:46 +00:00
Kyösti Mälkki
f40a25bb11 soc/nvidia,qualcomm: Fix indirect includes
Avoid indirect <vc/google/chromeos/chromeos.h> as the
files really only need <security/vboot/vboot_common.h>.

Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09 00:13:25 +00:00
Kyösti Mälkki
381860454f google/guybrush: Move SPI speed override
SPI speed override is not related to ChromeOS, thus the
location in chromeos.c was poor choice.

Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-06 10:46:01 +00:00
Kyösti Mälkki
be7692a20c mb/google,intel: Fix indirect include bootmode.h
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05 15:39:54 +00:00
Angel Pons
d16d00b71a mb/emulation/qemu-i440fx: Refactor fw_cfg_max_cpus()
Return 0 instead of -1 in case of error. Both values indicate an error
has happened. Adapt `cpu_bus_scan()` accordingly.

Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05 15:31:26 +00:00
Kyösti Mälkki
f1226963a1 mb/google: Fix indirect include bootmode.h
Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05 13:00:52 +00:00
Rex-BC Chen
c4db2db3bf mb/google/corsola: Add NOR-Flash support
Add NOR-Flash drivers to pass verification of flash at verstage.

TEST=boot to romstage
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05 13:00:07 +00:00
Kevin Chang
70701eba8d mb/google/taeko: Update the FIVR configurations
This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.

BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test

Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05 12:57:42 +00:00
Eric Lai
d74f6f5a5d mb/google/brya/var/felwinter: Correct typeC EC mux port
Type C port2 uses EC mux port0 as per schematics.

BUG=b:204230406
TEST=No error message in depthahrge.
update_port_state: port C2: get_usb_pd_mux_info failed

Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05 12:57:25 +00:00
Angel Pons
32d09be655 treewide: Replace bad uses of find_resource
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.

Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
2021-11-04 17:37:13 +00:00
Felix Singer
19b16a089e mb/google/sarien: Add OEM product names
Add OEM product names from public sources.

Change-Id: Ic051aa9c8afabd47e7e9f6ac878190d9904ef757
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04 14:13:21 +00:00
Werner Zeh
9f7e018f0f mb/siemens/mc_ehl: Disable PMC low power modes
All the mainboard variants of mc_ehl do not use the external switches
for the bypass rails. Disable the matching UPDs and all the low power
modes of the PMC.

Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04 11:05:03 +00:00
Werner Zeh
9916eb400f mb/siemens/mc_ehl: Disable all P-States
In order to get a reliable real-time performance disable all P-States
for all mc_ehl based mainboard.

Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04 11:04:46 +00:00
Werner Zeh
2d04693640 mb/siemens/mc_ehl: Disable C-States for CPU and package
Disable all C-states other than C0/C1 for CPU and package.

Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04 11:04:27 +00:00
Mario Scheithauer
e5be13e46b mb/siemens/mc_ehl2: Clean up devicetree
There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).

This commit cleans up devicetree.cb and removes all unused and disabled
devices.

Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04 10:41:51 +00:00
Matt Papageorge
7d6b4e3ae5 mb/google/guybrush: Set Gen3 default for all PCIe devices
Currently link_speed_capability is not specified within the DXIO
descriptors sent to FSP. This value specifies the maximum speed that
a PCIe device should train up to. The only device on Monkey Island that
is not currently running at full speed is the NVME but this may not
always be the case.

BUG=b:204791296
TEST=Boot to OS and check link speed with LSPCI to verify
NVME link speed goes from 2.5 GT/s to 5 GT/s

Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-04 10:31:27 +00:00
David Wu
a3260fde92 mb/google/brya/var/kano: Update GPIO table for speak and dmic
Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1)
Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3.

BUG=b:204844177 b:202913826
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04 10:30:18 +00:00
Martin Roth
663a61ed91 mb/google: Add OEM product names for various boards
All of these names came from public sources.

Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-04 10:29:41 +00:00
Mario Scheithauer
bb03e763de mb/siemens/mc_ehl: Enable Row-Hammer prevention
As a prevention of Row-Hammer attacks enable the FSP-M parameter
'RhPrevention'.

Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04 10:22:37 +00:00
Mario Scheithauer
5c65ec1ee5 mb/siemens/mc_ehl2: Configure SD card detect pin in devicetree
This configures GPIO GPP_G5 as an input pin for SD card detect.

Change-Id: I708eb112fa054f2f88857001c409fb62493b6206
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04 10:22:30 +00:00
Mario Scheithauer
8aac54d43a mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetree
PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on
this mainboard and are not routed either, so remove them from the
devicetree completely. PCIe root port #7 (00:1c.6) is connected and
used. Add the missing settings for L1 substates and latency reporting to
disable these features for this port as well.

Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04 10:22:20 +00:00
Mario Scheithauer
17641208f5 mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetree
On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-04 10:22:07 +00:00
Felix Held
f9014bbb60 mb/google/guybrush/bootblock: add comment on selecting eSPI interface
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the
eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04 04:51:37 +00:00
Felix Held
26806aed5c soc/amd/cezanne/include/gpio: fix GPIO 106 native function names
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed
that the native function names don't have the EMMC_ prefix.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04 03:50:45 +00:00
Tim Crawford
c3ced8fa4e mb/system76/*: Enable HECI device
The HECI device needs to be enabled to send the commands to have the
CSME change between Soft Temporary Disable mode and Normal mode.

Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-04 01:58:07 +00:00
Angel Pons
ca6e95ce55 mb/purism/librem_skl: Clean up hda_verb.c
Use the `AZALIA_RESET` macro, write hex values in lowercase and remove
redundant comments. Also express verb length in decimal.

Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains identical.

Change-Id: Id9f5ff9614a8f8c0b7f3a3c633a1dcdda8c5876c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-04 00:24:53 +00:00
Angel Pons
e13d3548d8 mb/purism/librem_bdw/hda_verb.c: Rewrite using macros
Rewrite the HDA configuration using macros for clarity.

Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical.

Change-Id: I987a41329425a5c8c7169a7fa66a34de5742532e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-04 00:24:15 +00:00
Kevin Chiu
b8fa1d389a mb/google/trogdor: Mark kingoftown as supporting Parade PS84640
BUG=b:204272905
BRANCH=master
TEST=emerge-trogdor coreboot

Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03 18:56:29 +00:00
Rex-BC Chen
74a0629660 mb/google/corsola: Add MediaTek MT8186 reference board
Add mainboard folder and drivers for new reference board 'Corsola'.

TEST=build pass
BUG=b:200134633

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03 08:26:28 +00:00
Werner Zeh
e4b2d7da4f mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetree
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe
devices. None of the used clock output is dedicated to a special device
(CLK0 drives several devices on the mainboard, CLK1 and CLK2 are
connected to a PCIe switch). Therefore do not use a port mapping of the
clocks to avoid a stopping clock once a device is missing and the
matching root port is disabled. Instead set the mapping to
'PCIE_CLK_FREE' to have a free running clock.

In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.

Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-03 08:22:05 +00:00
Jeremy Soller
b44202b29a mb/system76/oryp8: Add System76 Oryx Pro 8
https://tech-docs.system76.com/models/oryp8/README.html

Tested with TianoCore (UeifPayloadPkg).

Working:

- PS/2 keyboard, touchpad
- Both DIMM slots
- Both M.2 SSD slots
- All USB ports
- Webcam
- Ethernet
- WiFi/Bluetooth
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- Combined 3.5mm headphone & microphone jack
- Combined 3.5mm microphone & S/PDIF jack*
- S3 suspend/resume
- Booting to Pop!_OS Linux 21.10 and Windows 10 20H2
- Flashing with flashrom

Not working:

- Discrete/Hybrid graphics

Not tested:

- Thunderbolt functionality
- S/PDIF output

Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:37 +00:00
Jeremy Soller
fdaccd875d mb/system76/bonw14: Add System76 Bonobo Workstation 14
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 20:48:29 +00:00
Jeremy Soller
f74e42a542 mb/system76/kbl-u: Add Galago Pro 2 as a variant
Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 20:31:12 +00:00
Jeremy Soller
be43b13543 mb/system76/kbl-u: Add Galago Pro 3 as a variant
Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02 20:30:03 +00:00
Jeremy Soller
9037f0a831 mb/system76/kbl-u: Add System76 Galago Pro 3 Rev B
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:23:15 +00:00
Tim Crawford
e747bdda1b mb/system76/gaze15: Add Gazelle 14 as a variant
Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:22:26 +00:00
Tim Crawford
0893b871c6 mb/system76/gaze15: Convert to variant setup
Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:22:05 +00:00
Jeremy Soller
c840bc4e32 mb/system76/oryp6: Add Oryx Pro 7 as a variant
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:21:41 +00:00
Tim Crawford
c1481e0863 mb/system76/oryp6: Convert to variant setup
The Oryx Pro 6 has the same board layout as the next model in series,
Oryx Pro 7. The primary difference between the two is the dGPU (20
series to 30 series). Convert oryp6 to a variant setup in preparation
for adding the oryp7.

Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02 19:21:27 +00:00
David Wu
67d62fdfed Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"
This reverts commit 287cc02c00.

Reason for revert: it will break s0ix.

BUG=b:201266532
TEST=build pass

Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 16:02:54 +00:00
FrankChu
0d7e2a461a mb/google/volteer: allow MKBP devices and disable TBMC device
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family
to use for buttons and switches. Disable TBMC (Tablet Mode Switch
device), as it is not needed anymore.

BUG=b:171365305
TEST=manual test on Volteer:
Volume Up/Down and Power buttons, Tablet Mode switch

Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:22:39 +00:00
Anil Kumar
49ebce6777 mb/intel/adlrvp: Configure EC in RW GPIO
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO
can be used to check EC status
trusted (LOW: in RO) or untrusted (HIGH: in RW).

Branch=none
Bug=none
Test=Issue manual recovery and confirm DUT is entering recovery mode on
ADL-M RVP.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:22:10 +00:00
Jason Glenesk
c47835d599 mb/google/guybrush: Update STT coefficients
Update guybrush STT (Skin Temperature Tracking) configuration settings
to values provided by power team after tuning.

BUG=b:203123658

Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02 08:21:51 +00:00
Tim Crawford
dd30f4b112 mb/system76/*: CMOS: Drop power_on_after_fail option
Our boards do not boot if power_on_after_fail=Disable. Drop the option
and use the default of powering on.

Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02 08:20:54 +00:00
Varshit B Pandya
73161c644e mb/google/brya: Correct AT24 NVM address size
Currently, the address size field of AT24 NVM is incorrect, and
Linux v5.10 kernel logs the message below:

	at24 i2c-PRP0001:01: Bad "address-width" property: 14

The valid size of the AT24 NVM is 16 bits so modify the value from
0x0E to 0x10.

TEST=Boot brya and check the kernel log and see "Bad address-width"
error message is not shown.

Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02 08:16:30 +00:00
Zhuohao Lee
fe3189dc91 mb/google/brask: add the mkbp device
In order to let the ec passing the key event like recovery and power key
to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP
device.

BUG=b:204519353, b:204512547
BRANCH=None
TEST=pressed recovery key and power button in the OS and checked the UI
     behavior.

Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02 08:15:45 +00:00