All TGL mainboards are setting DIMM_SPD_SIZE to 512. Thus, default to
512 in the SoC Kconfig and drop it from the mainboard Kconfigs.
Change-Id: I9fd947b61c984e10bd5fba20b73280b08623a008
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62766
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
update the thermal setting value by measurement and
pass the thermal performance test
Change-Id: I3ba3ab990d5362c6f02d2ee5a023f4c5cca7fa45
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Using the GPP_F19 as privacy switch for camera in banshee.
BUG=b:223712143, b:216110896
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I67d65347ceac7152f1951018a633a2e93ee84e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
C1-state auto demotion feature allows hardware to determine C1-state as
per platform policy. Since Brya sets performance policy to balanced from
hardware, auto demotion can be disabled without performance impact.
Also, disabling this feature results in 110 mW power savings during
video playback.
Note that C1state Autodemotion feature is not applicable for ADL-P SoC.
Hence recommendation is to keep it disabled.
BUG=b:221876248
BRANCH=firmware-brya-14505.B
TEST=Code compiles and correct value of c1-state auto demotion is passed
to FSP. Also power and performance impact has been measure by respective
teams.
Change-Id: I41eea916cdfe4a86e4d263e3191f5cb40fa33a90
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
coreboot chip.h files mainly contains variable which allows board to
fill platform configuration through devicetree.
Since many of this configuration involves FSP UPDs, variable names were
in camel case which aligned with UPD naming convention.
By default coreboot follow snake case variable naming, so cleaning up
file to align all variable names as per coreboot convention.
During renaming process, this patch also removes unused variables
listed below:
-> SataEnable // Checked in SoC code based on PCI dev enabled status
-> ITbtConnectTopologyTimeoutInMs // SoC always passes 0, so not used
Note: Since separating out changes into smaller CL might break the
compilation for the patch set, this is being pushed as a single big CL.
BUG=None
BRANCH=firmware-brya-14505.B
TEST=All boards using ADL SoC compiles with the CL.
Change-Id: Ieda567a89ec9287e3d988d489f3b3769dffcf9e0
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Commit hash b8b40964 ( mb, soc: Add the SPD_CACHE_ENABLE) introduced
per mainboard logic to invalidate the mrc_cache.
This patch moves mrc_cache invalidating logic into IA common code and
cleans up the code to remove unused argument `dimms_changed` from SoC
and mainboard directory.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I6f18e18adc6572571871dd6da1698186e4e3d671
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
This patch modifies `memcfg_init` and `variant_memory_init`functions
argument from FSP_M_CONFIG to FSPM_UPD.
This change in `memcfg_init()` argument will help to update the
architectural FSP-M UPDs from common code blocks rather than going
into SoC and/or mainboard implementation.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=Able to build and boot redrix without any visible failure/errors.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3002dd5c2f3703de41f38512976296f63e54d0c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Hoglin and Herobrine (proto1) should share majority of GPIOs.
Conslidating the QUP initializations in mainboard. Also, putting
fingerprint init in a conditional as not all devices will have an FP
sensor.
BUG=b:182963902,b:223826899
BRANCH=None
TEST=booted BIOS on hoglin and check for i2c errors in dmesg
Change-Id: I48ce42760f2c75f04619b967a05909d2b3f28e2c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently the BayHub eMMC enable pin is using the default
configuration from the baseboard, which leads to RTD3 not being able
to control the GPIO when exiting and entering suspend. To fix this,
program the GPIO in the ramstage GPIO table.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
scope enable pin while performing suspend stress and enable pin
works as expected.
test suspend stress 1000 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I1b6f164cc326bd368addb1e143ad2cbd449bb08d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Pull GPP_D16 to low when suspending, otherwise it will remain active
and use power.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2cbe7caf66e8d8c27414aca3b74416c2b8115ea1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
DDR4 SPD data needs to be 512 byte to comply with the spec.
Though there is no vital timing data used beyond 256 byte there are some
part information which will be used to show the part info in the
coreboot log. If the buffer is too small this log shows garbage.
This patch increases the SPD buffer size from 256 byte to 512 to avoid
side effects.
Change-Id: I5b88df7818cfd62b3579d69f9f5bb14880f49c8c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The verstage.c file contains PSP verstage specific code. We don't need
it when using x86 verstage.
BUG=b:193050286
TEST=Build and boot guybrush with x86 verstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6dc928cdce0c922bb18f4479b993c89dff106070
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62740
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This sets EPP value to be 45% for all Brya variants.
Historically, EPP Ratio has always been 50% (128) on Chrome platforms.
But on Intel Alderlake EPP ratio of 45% is recommended for optimal
power and performance on Chrome platforms.
BUG=b:219785001
BRANCH=firmware-brya-14505.B
TEST=
Use 'iotools rdmsr [cpu id] 0x774' command and check field 32:24 = 0x73.
Signed-off-by: Cliff Huang <cliff.huang@intel.corp-partner.google.com>
Change-Id: I973cfec72a0be24c56c4cd3283d2fe6e18400d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update PL1, PL2, and temperature sensor values from thermal team,
as well as, we remove unused temperature sensors according to
baseboard/devicetree.cb and mainboard schematic. After we check
DTT setting, the thermal and performance test pass.
BRANCH=dedede
BUG=b:204229229
TEST=on beadrix, run following commands:
localhost /tmp # cat /sys/class/thermal/thermal_zone*/type
x86_pkg_temp
INT3400 Thermal
TSR0
TSR1
TCPU
localhost /tmp # cat /sys/class/thermal/thermal_zone*/temp
45000
20000
32800
32800
39000
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ibc59c4aa431f600158e744f5bbdc6d59a07a1ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62729
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The one USB2 port on the XHCI2 controller should have the port ID 2.0,
since it's the first USB2 port on that XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4a370132960939bccec4eb69a6590d0880b04137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62713
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GFX HDA is the audio controller that provides audio output via the
external display connection, ACP is the audio coporcessor for the on-
board audio codec and XHCI2 is the third XHCI controller that provides
one USB 2.0 port. All those devices are used, so enable them in the
board's devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I186797a832470eb17752e06aa2fcc0b5c9db0398
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62571
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select GL9750 driver and add power sequence according to datasheet:
GL9750S-OIY04 rev1.22.
BUG=b:223304292
TEST=check GL9750 can get enumerated by kernel 5.15.
01:00.0 SD Host controller: Genesys Logic, Inc Device 9750 (rev 01)
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ib6d461a56f6aeba30994daafe8993c36df4b309d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Enable pen garage. Pen detect is active low. And wake system when
eject.
BUG=b:223476974
TEST=evtest work as expected.
Input driver version is 1.0.1
Input device ID: bus 0x19 vendor 0x1 product 0x1 version 0x100
Input device name: "PRP0001:00"
Supported events:
Event type 0 (EV_SYN)
Event type 5 (EV_SW)
Event code 15 (SW_PEN_INSERTED) state 0
Properties:
Testing ... (interrupt to exit)
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 1
Event: -------------- SYN_REPORT ------------
Event: type 5 (EV_SW), code 15 (SW_PEN_INSERTED), value 0
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2f676301c3372a4760853ce9c10b75f94e22bbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
GPIO 32 was not allocated correctly, updating to reflect the native
function use of the pin
BUG=b:214412172
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Idadd2a802b3244eba8ee83f80d8f10baebe4ca40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62717
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to copy the PSP verstage logs into x86 cbmem, we need to enable
DEBUG_SMI. This will include the CBMEM console code in SMM. I only
enable DEBUG_SMI when UART is disabled because SMM doesn't currently
save/restore the UART registers. This will result in clearing the
interrupt enable bits and makes it so you can no longer use the TTY.
BUG=b:221231786, b:217968734
BRANCH=guybrush
TEST=Build serial and non serial firmware and verify DEBUG_SMI is set
correctly.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85a7933e8eb49ff920d00e43a494aaeab555ef3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Sets GPIO 42 to high to turn off WWAN DPR
BUG=b:216735313
BRANCH=guybrush
TEST=emerge-guybrush coreboot
make sure GPIO42 is high
Change-Id: Id0fcf27f086f98b2d42b47c8a871252b52d204ba
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
GPIO_18 is used for LCD_PRIVACY_SCREEN feature starting board phase 2.
But it is programmed incorrectly in the concerned ACPI device. Pass the
correct GPIO.
BUG=b:204401306
TEST=Build and boot to OS in Nipperkin. Ensure that the ACPI object
contains the right GPIO. Ensure that the screen visibility gets updated
by pressing the privacy screen button.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I99d40b49f4e97063f1ec2e15ac3da21f700a93eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
The Brask DDR4 setting are interleave, due to Moli PCB layer limited and the routing need to smooth, we will use non-interleave for Moli DDR4.
BUG=b:219831754
Signed-off-by: zoey wu <zoey_wu@wistron.corp-partner.google.com>
Change-Id: Iab153f16a3b729e7fa9daaa3dbfbccc70e6d789d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Decrease PSysMax from 13.52 A to 11 A for Moli variant according to its power circuitry, implying Psys_Pmax = 11A * 19.5V = 214.5W
BUG=b:215258941
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I61f4813f3527123a590d80b4a6e49d76ebb71c99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Don't return 0x00 when running MWAK as it is not needed.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic62eab8ae5319aff37c61fc29d701d9a36ada919
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove the dependency on Arg0 so PTS always runs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I96c44397d62848231039330a32de781f75bb56bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Some non-SoC code might want to know whether or not the CNVi DDR RFIM
feature is enabled. Also note that future SoCs may also support this
feature. To make the CnviDdrRfim property generic, move it from
soc/intel/alderlake to drivers/wifi/generic instead.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Idf9fba0a79d1f431269be5851b026ed966600160
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Based on testing results from the thermal team, they have decided
to update PL1, PL2 and PL4 for U28 SKUs.
BUG=b:221338290
TEST=Run with U28 and ensure the PL1/PL2/PL4 settings are correct
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib82e2dbacd6cbc39390eb28f27ca9db48d6c215c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Fix stylus UI behavior bug.
1) it appears the kernel's gpio_key driver is not expecting
an IRQ descriptor for the `gpio` property, therefore change
to an active-low input.
2) The wakeup event was configured backwards.
Change list
- Configure GPP_A7 as "ACPI_GPIO_INPUT_ACTIVE_LOW".
- Change wakeup_event_action from ASSERTED to DEASSERTED.
BUG=b:220992812
TEST=emerge-brya coreboot chromeos-bootimage and verify pass
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I6f5e2992584d759eb1a559684d1cda08c7cbe3f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Config VR_DOMAIN_GT's slew rate to 1/8 as well.
BUG=b:204009588
TEST=build and verified by Power team.
Change-Id: I766b828ad83710913323cf1485e09c1e0fd5e4c2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Acoustic noise mitigation and set slew rate to 1/8
BUG=b:223082189
TEST=build and verified by power team
Change-Id: I256cc57fb54e5d62e22470a01e7efef359d57083
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Nissa boards are curretly using chromeos.fmd file of brya. The SPI flash
layout for brya is of 32MB size, and nissa is expected to have 16MB SPI
NOR flash. The current composition of AP firmware exceeds 16MB. To get
an estimate of the unutilized region in the current flash layout for
nissa, added RW_UNUSED regions. The idea is to reduce the AP firmware
size to under 16MB and to remove the RW_UNUSED regions from the final
fmd file.
Below table gives the size reduction from brya fmd to nissa fmd:
+----------------+-------------------+---------------+
| Region | Earlier size (KB) | New size (KB) |
+================+===================+===============+
| SI_ME | 5116 | 3772 |
+----------------+-------------------+---------------+
| RW_SECTION_A/B | 8192 | 4344 |
+----------------+-------------------+---------------+
| VBLOCK_A/B | 64 | 8 |
+----------------+-------------------+---------------+
| ME_RW_A/B* | 3008 | 1434 |
+----------------+-------------------+---------------+
| RW_LEGACY | 2048 | 1024 |
+----------------+-------------------+---------------+
| RW_ELOG | 16 | 4 |
+----------------+-------------------+---------------+
| SHARED_DATA | 8 | 4 |
+----------------+-------------------+---------------+
| VBLOCK_DEV | 8 | 0 |
+----------------+-------------------+---------------+
| RW_SPD_CACHE | 4 | 0 |
+----------------+-------------------+---------------+
| RW_NVRAM | 24 | 8 |
+----------------+-------------------+---------------+
| WP_RO | 8192 | 4096 |
+----------------+-------------------+---------------+
| GBB | 448 | 12 |
+----------------+-------------------+---------------+
*Based on LZMA compression on ME_RW_A/B regions. With LZMA compression,
this region can be 1434K. Without this, ~665K will be more in each of
these regions.
Patch: https://review.coreboot.org/c/coreboot/+/62358/
BUG=b:202783191
BRANCH=None
TEST=Build and boot Nivviks.
Cq-Depend: chrome-internal:4584911
Change-Id: I24b1c19cb71a54fc916a12668f72193f9689e755
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Discovered this chassis identification number on Dell Precision
T1650 which is much OptiPlex 9010 alike. Precision T1650 is a Mid
Tower (MT) chassis.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2266fe39606b947a3d30a9462377fd56c39c2fa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Guard Max Charge EC write in Kconfig so it's only used on
platforms that support it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7be39cd9543c8253d53070950edc6908a21e864a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch aims to make timestamps more consistent in naming,
to follow one pattern. Until now there were many naming patterns:
- TS_START_*/TS_END_*
- TS_BEFORE_*/TS_AFTER_*
- TS_*_START/TS_*_END
This change also aims to indicate, that these timestamps can be used
to create time-ranges, e.g. from TS_BOOTBLOCK_START to TS_BOOTBLOCK_END.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I533e32392224d9b67c37e6a67987b09bf1cf51c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Set the GPIO configuration of moli
BUG=b:220821454
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I7ec41cb843419c32337b66f3877eda5d730cea35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
When using CNVi WLAN on ADL-N, the internal USB2 port 10 is used for
bluetooth. So update the nivviks overridetree to enable port 10 instead
of port 8, which is the external port used for bluetooth with PCIe WLAN.
BUG=b:222595137
TEST=Bluetooth works on nivviks
Change-Id: Ica2067023125c04fc753eabc944ae29ff59dc864
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Currently the BayHub eMMC controller is only going into its reset
state when the RTD3 sequence is initiated. This causes it to
still consume too much power in suspend states. This CL adds the
power enable GPIO into the RTD3 sequence as well, which will turn
off the eMMC controller (a true D3cold state) during the RTD3
sequence.
BUG=b:222436260
TEST=USE="project_primus" emerge-brya coreboot chromeos-bootimage
test suspend stress 100 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I2fec6a30707fb1a258cdcc73b0ce38252b6f77c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
cr50 firmware revisions starting at 0.5.5 and later are able to extend
their IRQ pulses to be a minimum of 100us long. This change will enable
cr50 long interrupt pulses when it detects the feature is supported by
the detected firmware version. If the capability was detected, then
GPIO PM will be enabled for the device, otherwise it will be disabled.
BUG=b:202246591
TEST=boot brya0, check console logs for the correct message, and
verify the GPIO PM registers.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iaf333dc0f177e17cd03b36ec7e487fc33bde2b93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61722
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboards accessing the cr50 over an I2C bus may want to reuse some of
the same firmware version and BOARD_CFG logic, therefore refactor this
logic out into a bus-agnostic file, drivers/tpm/cr50.c. This file uses
the new tis_vendor_read/write() functions in order to access the cr50
regardless of the bus which is physically used. In order to leave SPI
devices intact, the tis_vendor_* functions are added to the SPI driver.
BUG=b:202246591
TEST=boot to OS on google/dratini, see the same FW version and board_cfg
console prints as before the change.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie68618cbe026a2b9221f93d0fe41d0b2054e8091
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
ChromeOS considers the WWAN devices to be untrusted, therefore enable
the new DmaProperty in the WWAN's _DSD to indicate to the OS that these
devices should have IOMMU restrictions applied to them.
BUG=b:215424986
BRANCH=brya
TEST=dump SSDT
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9c9e73b7ea0575ab87cc980fb4786338047155de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Commit ebf14826
[mb/google/hatch/var/jinlon: Switch to using device pointers]
broke jinlon boards without an electronic privacy screen (EPS) by
disabling the parent device (iGPU) instead of the EPS when determined to
be not present via SKU ID.
Commit c5a3a4a6
[mb/google/hatch (baseboard): add ACPI backlight support]
broke EPS detection by adding a duplicate iGPU device to the devicetree,
resulting in the EPS entry being skipped.
Fix both of these issues by assigning the device alias to the EPS child
device, not the parent (iGPU). Rename the alias for clarity, and combine
the duplicate device definitions for the iGPU.
Test: build/boot google/jinlon SKU w/o EPS, observe GPU functional
in both firmware boot screens and Linux OS.
Change-Id: I0615ce361497abe6872085b0dec83292607e53dd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62593
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 017b5c453a
[ec/google/chromeec/acpi: Rename EC_ENABLE_TABLET_EVENT config]
broke tablet mode on google/caroline and cave in mainline Linux kernels
by changing the inclusion of the ChromeEC tablet mode ACPI handler. Fix
this by addding it back (using the updated name guarding the inclusion
of the tmbc ACPI).
Test: build/boot google/cave under Linux 5.16, observe tablet mode
handled correctly.
Change-Id: Ie0ae5b6a61f104b5e973383344d289cc2e2a7b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BT didn't work due to commit 03c0853f4d.
Commit 03c0853f4d accidentally set the Bluetooth USB2 port
to "empty", therefore re-enable USB2 port 9.
BUG=b:217238553, b:222238381
TEST=build and verfied BT work/suspend successfully
Change-Id: Ie94ef847fc130019f1e06983fc5039f1f564cd3a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change is to move MPTS (Mainboard Prepare To Sleep) method from
wwan_power.asl to SSDT.
MPTS is mainboard-specific method, while wwan_power.asl is meant for
WWAN from its name.
Having fixed MPTS method (i.e. DSDT) can not cover the case where device
only presents and certain CBI bit(s) is(are) set.
In Redrix and Brya, there are SKUs with or without 5G, 4G device. For
those with 4G, MPTS method should be different. For those with no WWAN
device, no MPTS is needed.
Having MPTS generating in SSDT also eliminates the need for introducing
Kconfig flags to support different devices in the future.
MPTS method is created inside mainboard_fill_ssdt function in which the
corresponding variant function is called.
This will generate the following for the mainboard:
Scope (\_SB)
{
Method (MPTS, 1, Serialized)
{
Local0 = \_SB.PCI0.RP01.RTD3._STA ()
If ((Local0 == One))
{
\_SB.PCI0.RP01.PXSX.DPTS (Arg0)
}
}
}
Test:
Check the SSDT for MPTS method under \_SB after boot to OS
Use shutdown command and check the GPIO pins from logical analyzer
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I0f0b7638e90a7862173fca99305398bb250373e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add HID driver for i2c-1 for Ilitek touchscreen.
BRANCH=None
BUG=b:187289163
TEST=Build and flash coreboot; confirm an entry for hidraw for I2C-1 for
Ilitek touchscreen.
Change-Id: I9e42c36a35654cf3e2b41f78b209f4b89e8b05bd
Signed-off-by: Rehan Ghori <rehang@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Shorten define names containing PCI_{DEVICE,VENDOR}_ID_ with
PCI_{DID,VID}_ using the commands below, which also take care of some
spacing issues. An additional clean up of pci_ids.h is done in
CB:61531.
Used commands:
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]\{2\}\([_0-9A-Za-z]\{8\}\)*[_0-9A-Za-z]\{0,5\}\)\t/PCI_\1ID_\3\t\t/g'
* find -type f -exec sed -i 's/PCI_\([DV]\)\(EVICE\|ENDOR\)_ID_\([_0-9A-Za-z]*\)/PCI_\1ID_\3/g'
Change-Id: If9027700f53b6d0d3964c26a41a1f9b8f62be178
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
This revert commit acb17fec34.
This issue was fixed in the OS, therefore the workaround can be
reverted.
BUG=b:210497855
BRANCH=firmware-brya-14505.B
TEST=build coreboot and boot into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ic836e0cf53c2f9d30bd12851be285d864b2256b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SMMSTORE needs to have 64k size (minimum) and have 64k alignment as
enforced by asserts added in commit 1ba6049
[drivers/smmstore/store.c: Add static assertion based on fmap].
Adjust size and alignment of SMMSTORE region in FMAP to ensure those conditions are met.
Test: build google/morphius without asserts being tripped for above conditions.
Change-Id: Ied04e93379e1507f5e6b2a1b71e4098a4561e5d8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
GPP_S6 was accidentally configured twice instead of configuring GPP_S7.
So configure GPP_S7 according to the schematics.
BUG=b:222218450
TEST=WCAM DMIC works on nivviks
Change-Id: I5de36aaa504a8856803c783564162c36416b50b7
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62511
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Infineon TPM 1.2 used on glados boards doesn't use a PIRQ;
Linux only works with 'tpm.tis_interrupts=0" and Windows fails to
init the TPM citing a lack of available resources. With the PIRQ
removed, both Linux and Windows are happy / the TPM is available
for use.
Test: build/boot Linux 5.16.x and Windows 11 on google/chell
Change-Id: I544695505291bbebe062df636cc8ddd139c08c2b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
After the patch that moved the generation of the PPKG object to
Stoneyridge's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0deb2d75cae98b8fcd31297d7fac5f27525efe65
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Stoneyridge with the other AMD SoCs. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=None, but equivalent change on Picasso was verified to not break
anything on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib42d718102151a72a5fe812e83eb2eb4f9e7b611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
After the patch that moved the generation of the PPKG object to
Picasso's acpi.c, only the PNOT object remained in its cpu.asl, so
rename it to pnot.asl.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic77dacb146aa823fc99f779f465fff28b2aead68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Generate the PPKG object in the generate_cpu_entries function instead of
generating the PCNT object that is the used in the PPKG method in
cpu.asl to provide the PPKG object. This both simplifies the code and
aligns Picasso with Cezanne and Sabrina. This will also make the code
behave correctly in a case where the number of CPU cores/threads isn't a
power of two.
TEST=Mandolin still boots successfully to Linux desktop and dmesg
doesn't show any any possibly related problems.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifb84435345c6d8c5d11a8b42e5538cfb86432780
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Disabled G2touch driver and add ELAN touchpanel driver for vell.
Due to incorrect BIOS setting, touch screen IC FW can't update and work.
According to ELAN's recommendations, we coreect the ELAN2513 driver's setting and change I2C address to 0x10
BUG=b:221340736
TEST=emerge-brya coreboot and can flash touch screen FW
Change-Id: I22f04fa21b542e21e88c46547779cfb55beb5c12
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
In order to achieve a stable eMMC interface disable the HS400 capability
of the host controller. This will result in an operating mode of maximum
HS200 (200 MHz single data rate) which leads to a more relaxed timing.
Change-Id: I0e125dd569b00f59ae0fd2f76169c4461291b47a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
google/brask is using SODIMMs for DRAM. Reading spd data is
surprisingly slow (~170 ms), therefore enable the SPD cache.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=run on the device and measure the boot time decrease.
Change-Id: If0a0072160a48b607ad17c0a1819ab49eaad92db
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Align the setting with the adlrvp
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and works correctly in the brask
Change-Id: Ia4c889e7dd065632e180cf983c7c5ece0c461edd
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In order to cache the spd data which reads from the memory module, we
add SPD_CACHE_ENABLE option to enable the cache for the spd data. If
this option is enabled, the RW_SPD_CACHE region needs to be added to
the flash layout for caching the data.
Since the user may remove the memory module after the bios caching the
data, we need to add the invalidate flag to invalidate the mrc cache.
Otherwise, the bios will use the mrc cache and can make the device
malfunction.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass and enable this feature to the brask
the device could speed up around 150ms with this feature.
Change-Id: If7625a00c865dc268e2a22efd71b34b40c40877b
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62294
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes Rcomp settings. In MRC design, it checks if the
Rcomp settings from the board is 0 or null, if so, it uses the
recommended Rcomp values. Otherwise, it uses the Rcomp settings passed
from the UPD. From the change history of MRC, we're chasing a moving
target. This RCOMP setting in coreboot is an old setting while the
Rcomp settins in MRC are optimized settings. Moving forward, if there
is a new stepping, it might be changed again which increases the
maintenance effort in coreboot. IMHO, we should let MRC to set the
optimized RCOMP values for the design.
BUG=b:219378758
TEST=emerge-byra coreboot chromeos-bootimage and boots up with QS and
PRQ CPUs. Checks with MRC log and ensure the RCOMP settings are
filled properly by MRC.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I8547e187b74f9b2cee57ddad2883d60c05d0b9fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With GPP_B3 locked, primus eMMC SKU encounter eMMC storage lost after
warm reboot.
Config GPP_B3 unlocked to make reboot works on primus. Also set
GPP_B3 to low in early_gpio_table to meet eMMC-PCIe bridge IC power
on sequence.
BUG=b:221488504
TEST=USE="project_primus" emerge-brya coreboo chromeos-bootimage
test reboot 30 cycles passed on primus.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: Ifd5f9d59d33cd1c5ebe0454ab3aa4c5641c16ff6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Chausie doesn't have recovery mode buttons so it's impossible to
manually enter recovery mode to enable developer mode. This means we
need to force developer mode.
BUG=none
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id0b08ee8e009e8603f63e691b5a7a2ac04e1fc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enable STT and decrease sustained_power_limit_mW to 12W
BUG=b:219616787
BRANCH=guybrush
TEST=emerge-guybrush coreboot
update the thermal setting value by measurement and
pass the thermal performance test
Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Change-Id: I5b7b0156fb4a1e2be8528a5787ed82acff93f06c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Include chausie EC and EFS only in the RO region when building with
vboot. Without this, the EC is also added to the FW_MAIN_A and FW_MAIN_B
regions.
Change-Id: I78de8bd639232b9fb6d775b77ecd892f28514614
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Kano changes load switch of touch screen to TPS22914C (is not with
discharge) on DVT board, EE suggests to add enable_off_delay_ms to 30ms
to fix DUT can't enter S0ix issue.
BUG=b:220811619
TEST=Boot kano to OS and run S0iX test 2500 cycles.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7ea5693d457c5f60246348d2d8fa1f4130b7d4c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: YH Lin <yueherngl@google.com>
The USB port configuration was derived from the PPR and schematics.
This board has 6(some multi-purpose) ports.
Primary functions are:
2 USB-C ports
1 USB SS+ type A port
2 Cameras
1 Bluetooth transceiver
BUG=b:214413631
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Ie1b05f190f25dca1566e1023011cc70c2d32f461
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62153
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The power rails discharge time of brask has been measured, the longest
discharge time of the power rails are smaller than 150ms so it is safe
to set the pwr_cyc_dur to 1 second. Since the brask is derived from the
brya, we could apply the same setting from the brya. The setting is
copied from commit dee834aa.
BUG=b:214454454
BRANCH=firmware-brya-14505.B
TEST=`test_that firmware_ECPowerButton` passed.
Change-Id: I5e5eebb79e99a52fc3e4128213c6986f20100b8d
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The mainboard_memory_init_params takes the struct FSP_M_CONFIG as the
input which make the board has no chance to modify data in the
FSPM_UPD, for example, set FspmArchUpd.NvsBufferPtr = 0. After changing
the FSP_M_CONFIG to FSPM_UPD, the board can modify the value based on
its requirement.
BUG=b:200243989
BRANCH=firmware-brya-14505.B
TEST=build pass
Change-Id: Id552b1f4662f5300f19a3fa2c1f43084ba846706
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Add configurability using FW_CONFIG field in CBI, to enable/disable
I2S codec support for MAX98373 codecs
- AUDIO=ADL_MAX98373_ALC5682I_I2S: enable max98373 codec using expansion
board
Bug=None
Test=With CBI FW_CONFIG set to 0x100, check I2S audio output on
expansion card
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I94dfe500b99a669e9b981cdf15e360f22f33d2ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Both the HPET_BASE_ADDRESS define from arch/x86/include/arch/hpet.h and
the HPET_ADDRESS Kconfig option define the base address of the HPET MMIO
region which is 0xfed00000 on all chipsets and SoCs in the coreboot
tree. Since these two different constants are used in different places
that however might end up used in the same coreboot build, drop the
Kconfig option and use the definition from arch/x86 instead. Since it's
no longer needed to check for a mismatch of those two constants, the
corresponding checks are dropped too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia797bb8ac150ae75807cb3bd1f9db5b25dfca35e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62307
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable guybrush based platforms to send fuse spl command to PSP when
required.
BUG=b:180701885
TEST=On a platform that supports SPL fusing. Confirm that PSP indicates
fusing is required, and confirm coreboot sends command. Fusing is
required when the image is built with an SPL table requiring newer
minimum versions. A message indicating fusing was requested will appear
in the serial log. "PSP: Fuse SPL requested"
Change-Id: I7bce01513af4e613f546e491d9577c92f50cb85c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30fa886a39bd7082442a3a2b95fdf2d2b84ddd1c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add a mem_parts_used.txt for Crota, containing the
memory parts used in proto builds. Generate Makefile.inc and
dram_id.generated.txt using part_id_gen.
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
H9JCNNNCP3MLYR-N6E 0 (0000)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:215443524
TEST=emerge-brya coreboot
Change-Id: I0ff6ffea4b879b6e1287e1e3cb9fd36a80f52ed6
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
While on it, use tab for indent.
Change-Id: I6cb0b4183db819d721f4882ab2168d22bcd664e3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reconfigure the GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I27ecf066685f2a81ac884a9f276c518544449443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reconfigure the CNVi GPIO's so that they are configured correctly.
The original configuration was based on the AMI firmware, and
whilst it worked, it wasn't optimal.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9fc9963e91da0267c8740fee20a3ec41895b4953
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Update trackpad GPIO to avoid IRQ Storm, that causes high power
consumption when idling or in S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieee27bd9079617ab95f4f1e27ef98b49e89e5b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Configure the TPM IRQ GPIO for TGL (StarBook Mk V) so that the
hardware TPM can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ife88075e70184b46e69f2e24c70b85ec254edd64
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60756
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't configure ESPI GPIOs as the default values are correct.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I052fbfccd075d19340d3e27ad0c62965c80badaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
Rework edkii makefile so that the various build options are
unified between CorebootPayloadPkg, uefipayload_202107 and
upstream.
This sets the project directory based on the git repository name
i.e. https://github.com/mrchromebox/edk2 becomes mrchomebox
Also builds to $(obj)/UEFIPAYLOAD.fd and allows using a commit
ID without a branch.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3cc274e7385dd71c2aae315162cc48444b7eaa5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth - Personal <martinroth@google.com>
On mc_apl2 the external RTC is connected to I2C bus 3. All other I2C bus
devices (16.0, 16.1 and 16.2) have been disabled as they are not used.
While coreboot can handle the case where a PCI device does not have
function 0 enabled but a later one (here function 3), Linux seems to
check for function 0 first and ignores the rest if function 0
is missing. So enable PCI device 16.0 in order to let Linux use 16.3
again.
Test=Boot into Linux and make sure that PCI device 16.0 and 16.3 are
visible and I2C attached RTC works properly.
Change-Id: I55a748b6de8128f4b26b908118feff9f06d3fb7c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62215
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ic37e7e6757476f1d30bea31fcde4deebebd488a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I36e35522aba2463124b7e6e7046b1a56758b534d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Modify function to set default audio codec HID
to be original setting 10EC5682.
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I30a1fe2ef8d750616f6907f86a5329f035920504
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add the information of substance and instance in the string for PMUI
and PMUD. It is amdfwtool's job to extract the number from the string.
Change-Id: I43235fefcbff5f730efaf0a8e70b906e62cee42e
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Based on the nivviks and nereid schematics, nissa is using eMMC HS400
mode, so enable this in devicetree.
BUG=b:197479026
TEST=Build test nivviks and nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ie9772385276d3629079b95024d3ffa04438f22c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Only the info about the location of the EC firmware will be stored right
at the beginning of the flash, so the size can be reduced to 4kByte
which is the erase block size of the flash. The CHAUSIE_MCHP_SIG_FILE
file itself is smaller than this.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icde5f7071183cd8423fc022caf49e2c9ee288527
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62189
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for
audio, TPM, touchscreen, and touchpad.
Audio CLK: 385 kHz
TPM CLK: 380.5 kHz
Touch Screen CLK: 373.3 kHz
Touch Pad CLK: 372.7 kHz
BUG=b:218577918
BRANCH=master
TEST=emerge-brya coreboot chromeos-bootimage
measure by scope with felwinter.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3e5cc10d6605f9cc41fa6b31da07a81364b72fe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Move the EC to a location that does not conflict with where the main
CBFS is in the chromeos FMAP
Change-Id: I28c84cbe2ff10d45383d896ae4f942ee49eb15c0
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62190
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Sabrina SoCs the size of the APOB has increased, so the size of the
RW_MRC_CACHE FMAP sections needs to be increased in order for the data
to still fit in the corresponding FMAP partition.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib31b918aba90dd507b47aec9e1f75c138857cd02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62155
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I61f8f39ce7651d499756f4975840f32f89b04ca7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Follow thermal team design to remove TSR3 sensor and update thermal
table for next build. The DPTF parameters were verified by thermal
team.
BUG=b:219690502
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I0e34fabe546b6eabb3d3adad583668a15a1d908b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The CIO2 port was incorrectly set to 2, while the correct port is 1
BUG=b:210801553
TEST=Build and boot on vell, camera works correctly now
Change-Id: I53d8448ed0e12777456af9b0bc65a04595b47e37
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61946
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1e0b51ee4db73bdff79365d4954a3245a430f140
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62051
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9e4837489d90c2edd7deaa2af0533085f1ff5ae6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62049
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Id44213c7dd4d0df97a6c57d7f1b9d950baaf0e1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62047
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie304b08b0b1bbad5547a0169ea8056d703141391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61830
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1a4bc1aae8e815b882a607432e40caf1066453b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61828
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I07cef3b619991afb6337c38a631ee159677d30a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61826
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0274f03926d97fc543b98f3fb961580283202806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61825
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I33e4501fd689d642682891c7f5bc9cb7ca5e331c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61824
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1940246fd88db29054f85c43672adc97dc90fa04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61823
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3d8a8a7e2b1e490726986139014cdfcf1271c64b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61805
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses ACPI _PLD macros for USB Type A and C ports.
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Idb8f30b2d1069aea1d5ce7c5dda7f99de33a7c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61803
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iddf0727a538f2063cfabbec1f900c488331f33c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0d1be34775c5eacf6cd9b0ec400bd42a93c59e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia9bc235c257abce2a3cd63cfd1b17ac356267d8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic3fbf307bfa42bd377c8f23c1837a6d15cb378e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I80d9038d1f41d65201d6bfdb808708f997d71faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic97d48633ef1f246c181046ec32ab81614ba5ceb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I78734f685672347b06783f834643347a35c59e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4e051b21ca55d25c6fc6cfb529078b18adaab2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62028
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I0c72a5c5306d63c5fce24bf727704d212d0ad0f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
In ec/google/chromeec: Add PLD to EC conn in ACPI table
(667471b8d8), PLD is added to ACPI table.
This patch ensures USB _PLD group numbers are appear in order.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9cef57bbaf3e3519b7f6a7e3d86979722b598ad7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Guybrush platforms have I2C3 controller which is shared between PSP and
X86. In order to enable cooperation, PSP acts as an arbitrator. Enable
SOC_AMD_COMMON_BLOCK_I2C3_TPM_SHARED_WITH_PSP, so that proper driver is
binded on the OS side.
With this change in place it is important to use correct kernel version
which has I2C-amdpsp driver [1] enabled. Otherwise, we won't have I2C3
available and thus TPM device available in OS, what may end up as a
serious error - guybrush refuses to boot without access to TPM.
BUG=b:204508404
BRANCH=guybrush
TEST=Build proper kernel and firmware. Run on guybrush and verify TPM
functionality.
[1]: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?id=78d5e9e299e31bc2deaaa94a45bf8ea024f27e8c
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I9dd94e47e1a02e790427b67adff84de3eb3ee387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61965
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Qualcomm CRD devices do not have a fingerprint sensor so removing the
QUP configuration for it. This QUP also coincidentally is the same as
the one used for the TPM, so this initially was also causing TPM
communication issues during bootup as the QUP was being reconfigured
during the later stages after QcLib execution.
BUG=b:206581077
BRANCH=None
TEST=Boot to kernel without any CR50 communication errors
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Change-Id: I8d13b67796b70b0b7e9a4721cca0b8a54b2b27c1
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61716
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch corrects the DQ mapping and enable ECT. In Vell design,
the DQS is swapped in Mc0.ch1, Mc0.ch3, Mc1.ch0, Mc1.ch1 and Mc1.ch2
but the DQ mappings are not swapped and that causes ECT training
failure.
BUT=b:208719081
TEST=emerge-brya coreboot chromeos-bootimage && ensure the system
passes ECT training and all the way booting to the OS.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: Idd2ad16151f0b2b93b00295b75a66ba65cba23cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Clang does not seem to work with 'fall through' in comments.
Change-Id: Idcbe373be33ef7247548f856bfaba7ceb7f749b5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The google/agah variant will use a peripheral that will require the use
of the PCIe Resizable BAR feature from the PCIe spec. Thus, select
the new Kconfig option to enable it. The appropriate Resizable BAR size
will be updated later.
BUG=b:214443809
TEST=build
Change-Id: I9cf86ba3160ae5018655b5d366e89f4273b30b94
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Change to use i2c/generic to match ELAN FW update script.
BUG=b:210970640
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: Ib416da6000d9e99f9c37cf497fb1c43e3fca0220
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add an option to build skiboot as a payload. This makes QEMU Power9
board simpler to use as skiboot is necessary anyway.
Change-Id: I0b49ea7464c97cc2ff0d5030629deed549851372
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Follow latest schematic to update the DQ map.
BUG=b:218939997
TEST=boot into OS without issue.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If29cc22b1749fb5d602d3ce64bcc1182593d673f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Disconnect all GPIO's that aren't connected to anything.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2050da62f73c0f99fbfef013c22e35225cc480c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Add comment for each GPIO details its endpoint based
on the schematic.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia3678274dcd52285019fb3cf8ccd22617268ce1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The SPI ROM REQ/GNT pins are used in systems where the EC and the APU
share one flash chip to make sure that not both devices will try to
access the flash at the same time. The firmware running before the x86
cores are released from reset has likely already done this, but do it
again in bootblock just to be sure. The KBRST_L pin can be used to reset
the APU from the EC.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5af285ac222ed6625f498d82360f2d1cc522df2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Commit 805956bce [soc/intel/cnl: Use Kconfig to disable HECI1]
moved HECI1 disablement out of mainboard devicetree and into SoC Kconfig,
but in doing so inadvertently disabled HECI1 for Puff-based boards which
previously had HECI1 enabled by default. To correct this, move the Kconfig
selection back into the mainboard Kconfig, and set defaults to match values
prior to refactoring in 805956bce.
Test: run menuconfig for boards google/{drallion,hatch,puff,sarien} and
ensure Disable HECI1 option defaults to selected for all except Puff.
Change-Id: Idf7001fb8b0dd94677cf2b5527a61b7a29679492
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Chromebook needs to do some additional check, which is not
available in the AMD's PI released SPL table.
BUG=b:216096562
Change-Id: Ib8074641b9fc9b38239a6e3837b8569e14af3342
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Nereid does not support the LTE sub-board, so disable the LTE-related
GPIOs.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I6d6b5babeefb7c4b79adab5e756f37616c2338d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add an initial overridetree for nereid based on the pre-proto schematic
and build matrix.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nereid
Change-Id: I7d313439337c84ab1024b3570cc7b57b4255af5d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Nereid P1 will also use Hynix H9JCNNNBK3MLYR-N6E. Add it to the parts
list and regenerate the memory IDs using part_id_gen.
BUG=b:217096008
TEST=abuild -a -x -c max -p none -t google/brya -b nereid
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ibacb9dfb336967dd7fffe351d785cbbff9ba8b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Create the kinox variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:215049181
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_KINOX
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I68cac421f6299a5f82f2ab51633173648c993060
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61789
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Data on channel 0 & 1 are normal (from DMIC)
but there is noise on channel 2 & 3, so change to NF
PAD_CFG_NF(GPP_R6, NONE, DEEP, NF4) to PAD_NC(GPP_R6, NONE),
PAD_CFG_NF(GPP_R7, NONE, DEEP, NF4) to PAD_NC(GPP_R7, NONE),
BUG=b:210802722
TEST=FW_NAME=vell emerge-brya coreboot
Change-Id: I1b5ccd2c239e526e4f1ce2d5ed6c1386303590c8
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61033
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `reset` gpio is currently being consumed by the btusb kernel driver.
The functionality was added in https://crrev.com/c/3342774. The goal of
the patch was to reset the BT device when command timeouts occur. This
works, but it doesn't support the case where the BT device is having
problems with USB enumeration. In that case the device can't enumerate
so the driver can't help resetting the device.
If we instead switch to using an ACPI power resource, the kernel can
control the BT device's power. This is beneficial when the device is
having USB communication problems since the kernel will try and power
cycle the device.
We don't lose the ability to reset the device on command timeouts
either since `btusb_qca_cmd_timeout` will enqueue a USB port reset if
there is no `reset` GPIO. So win / win.
This results in the following power resource:
PowerResource (PR02, 0x00, 0x0000)
{
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x01)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
\_SB.CTXS (0x84)
Sleep (0x01F4)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.STXS (0x84)
Sleep (0x0A)
}
}
I switched the device tree entry from using reset_gpio to enable_gpio
because the acpi_device_add_power_res method asserts the reset in the
_ON method unconditionally. This results in a small glitch on the line.
By using the enable_gpio we get the correct behavior.
I don't have a datasheet right now, so I just picked some values for the
reset timing. The kernel driver was using 200ms. We can revisit the
numbers when we get a datasheet.
BUG=b:218295688
TEST=Suspend stress test on nipperkin with 600+ cycles. Verify power
resource is created on the kernel. This should allow the kernel to
power cycle the device via usb_acpi_set_power_state.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib1eff86db76929f76432cd6f765880c892e7a786
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
When brya boards that use ChromeOS autoupdate update their firmware,
devices with SOC_INTEL_CSE_SUB_PART_UPDATE will end up attempting to
replace IOM and NPHY BPDT firmware in the CSE region. However, because
of the way the autoupdate works, the CSE RO will not be updated during
autoupdate. This means that these boards now have different stitching
schemes between CSE RO and RW and this causes the sub-partition update
to fail and the boot hangs. To remedy the situation for these boards,
a separate FMD files is provided so they can continue to use the
cse_serger tool for stitching. The only boards affected were kano and
brask, so they are updated here.
BUG=b:218376385
TEST=use flashrom to downgrade to 14474 then use futility to update to
image with this patch and system boots.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: Ia8bdf6b28d952f6d983b84e39da96e159027a822
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Brask cannot pass powerd_dbus_suspend test because the NIC does not
enter ASPM L1.2. Here we add "enable_aspm_l1_2" in devicetree for
RTL8125 to enable ASPM L1.2.
BUG=b:204309459
BRANCH=None
TEST=emerge and test with command powerd_dbus_suspend
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9a56df1d68696f409f9ee681d37de6759a588d80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Agah port 0 does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
Add the "TcssAuxOri" and "typec_aux_bias_pads" to lets the SoC IOM firmware control the Aux DC bias voltages.
BUG=b:210970640
BRANCH=NONE
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I1fa5c4574b1a0e8dd2f66f3f6382436337c530fa
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Alder Lake N has single memory controller with 64-bit bus width. Alder
Lake common meminit block driver considers bus width to be 128-bit and
populates the meminit data accordingly. By setting half_populated to
true, only the bottom half is populated.
Ideally, half_populated is used in platforms with multiple channels to
enable only one half of the channel. Alder Lake N has single channel,
and it would require for new structures to be defined in meminit block
driver for LPx memory configurations. In order to avoid adding new
structures, set half_populated to true. This has the same effect as
having single channel with 64-bit width.
Change-Id: I414e5dc82caf47b6b96c474b3ef6e01c2ce0226e
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The mainboards mc_apl{2,4,5,6} use VBOOT for verification and can be in
a recovery state for different reasons. In this case we still want the
MRC cache to be around to avoid the DRAM retraining on every boot.
This patch enables the Kconfig switch HAS_RECOVERY_MRC_CACHE which makes
the already available MRC recovery region in FMAP useable.
Test=Boot mc_apl2 in recovery mode and make sure the recovery MRC
cache is used.
Change-Id: I2ea4993f05dd87a0e637f55e84b4fc06f5e29ecc
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This IRQ routing info is taken from mb/google/guybrush. The IRQ routing
on Chausie that was a 1:1 copy caused some issues with the I2C driver,
so port the Chausie IRQ mapping change back to Majolica.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieb958639dd8aef7c60c050ad107dde7d1cd6a8bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This IRQ routing info is taken from mb/google/guybrush. This should fix
these errors:
[ 0.655051] i2c_designware AMDI0010:00: IRQ index 0 not found
[ 0.659239] i2c_designware AMDI0010:01: IRQ index 0 not found
[ 0.663198] i2c_designware AMDI0010:02: IRQ index 0 not found
[ 0.667200] i2c_designware AMDI0010:03: IRQ index 0 not found
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8c85c8e4b1c860d6ca25060353355f703a49e1e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Config USE_PM_ACPI_TIMER to y for primus4es only as
commit 1ce0f3aab7 (mb/google/brya: Fix S0i3 regression)
breaks suspend stress test on ES CPU SKU.
BUG=b:211377699
TEST=USE="project_primus emerge-brya coreboot" and verified
the suspend stress test works on primus4es.
Change-Id: I8d19c10e2029e233542a8ceec272f8ede2b4bfac
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It's available in %r3 in bootblock and needs to be passed to payload in
%r27. We use one of two hypervisor's special registers as a buffer,
which aren't used for anything by the code.
Change-Id: I0911f4b534c6f8cacfa057a5bad7576fec711637
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.
QEMU for PPC64 can run initial program in two different modes:
* hb-mode=off with load address 0x00000000
* hb-mode=on with load address 0x08000000
Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.
Memory layout is updated to reflect change of load address.
Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds mem_parts_uesd.txt that contains the new memory parts
used (H54G46CYRBX267,H54G56CYRBX247) by primus and Makefile.inc
generated by gen_part_id using mem_parts_used.txt.
BUG=b:218415732
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d236c51f0c996a22954046876f3494ba9e62693
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently apu/amdfw_a-position and apu/amdfw_b-position currently depend on CEZANNE_FW_A_POSITION and CEZANNE_FW_B_POSITION. This causes error messages from awk as these variables are sourced from fmap_config.h and these variables are expanded before fmap_config.h is built. However these variables should not be set to CEZANNE_FW_*_POSITION. These files end up in the FW_MAIN_* fmap regions. These regions are placed at the proper locations through the chromeos.fmd file. The apu/amdfw_*-position variables are the positions within these regions where the files end up. These variables should be set to 0x40 to coincide with the beginning of the FW_MAIN_* regions, accounting for the size of struct cbfs_file + filename + metadata, aligned to 64 bytes. Currently they end up in the correct locations only because fmap_config.h does not exist when the apu/amdfw_*-position variables are expanded.
This change explicity sets the value of these variables to 0x40, removing the errors from awk and ensuring that these files end up in the correct location in the resulting image. These changes are also applied to the Picasso and Sabrina makefiles as well.
BUG=b:198322933
TEST=Verified that the apu/amdfw_* files end up in the correct locations as reported by cbfstool during the build, did timeless builds and confirmed that coreboot.rom images were identical, tested AP firmware on guybrush and zork devices
Signed-off-by: Robert Zieba <robertzieba@google.com>
Change-Id: If1c2b61c5be0bcab52e19349dacbcc391e8aa909
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Nissa is using the FM101, which has the following power sequencing
requirements:
Power on: assert WWAN_EN, delay 20 ms, deassert WWAN_RST_L
Power off: assert WWAN_RST_L, delay 20 ms, deassert WWAN_EN
Add a power resource to the USB device, and use wwan_power.asl to
handle the power off sequence.
BUG=b:217092522
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Ibe1b863a550c6af1ac3eb98f2aaa3db15b149ada
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Nissa is using the FM101 which is USB only. To allow us to reuse the
existing wwan_power.asl for power sequencing, move the PCIe-specific
part behind a new Kconfig HAVE_PCIE_WWAN.
BUG=b:217092522
TEST=Build brya0 and check that generated dsdt.asl doesn't change.
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Icb6db91ce00deb2b30379f5ff7a974d1feb62ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If the LTE USB DB is not connected, disable the LTE-related GPIOs.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I86251d8ad58d82ff2112ac5f2dfafdabbff4c76f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add an initial overridetree for nivviks based on the pre-proto schematic
and build matrix.
BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: Id3ecd184415a20a3a52da8bb5e60fe2ce0495b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
The SMMSTORE region needs to be 64K aligned or error will be thrown.
Change-Id: I5d4f71f80c3219ac2c7000e1fa95fd04100d9cfe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Several commits were made to the Chromium coral branch
(firmware-coral-10068.B) which were not committed upstream first.
Pull them in here:
486ce56 mainboard/google/coral: Override VBT selection for babymako
c1d7720 Babymako: add touchpad i2c speed config
911d547 mainboard/google/coral: Override VBT selection for babytiger
730a5af Babytiger: add touchpad i2c speed config
724711e rabbid: add the touchpad i2c speed config
80c5d16 mainboard/google/coral: Override VBT selection for babymega
e8931a4 Babymega: add touchpad i2c speed config
These add support for additional coral sub-variants. The I2C speed config
changes were adapted to account for upstream changes not present in the
coral Chromium branch.
Change-Id: Idf2a53a351138aff310385f4026197d74ab6848b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Release firmware on Nasher/Nasher360 are built as coral
sub-variants; remove the old/unused code
Change-Id: Ie8d10a31e663230b7deabf92e1c06cd991bbdccb
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Create the moli variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:214439135
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_MOLI
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I3f3bfd3db12cba8b73b351e7c700b6a58797c906
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
When booting ADL RVP, coreboot is unable to load VBT binary as
makefile will rename VBT binary to "vbt.bin" when building
coreboot.rom.
The reason for having this function is that chromeOS has emerge
tool to streamline the VBT stitching process to support multiple
VBTs for different RVP boards; while we only need 1 vbt for generic
non-chromeOS usage. Hence add a chomeos kconfig to guard this.
TEST=Able to boot ADL RVP DDR5 with DP display.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I5f6f9554b75f4d62198aac9938e65c71c3e7cee9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add wifi sar for magneto.
Due to fw-config cannot distinguish between magolor and magneto.
Using sku_id to decide to load magneto custom wifi sar.
BUG=b:208261420
TEST= emerge-dedede coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I77f141372ba8e7b8f5849b00e115ad8bb1e7ca00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204517112
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I5c1c9819af1e0bc2278dadeffb6b19c3f9068f30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ALC5682-VD/ALC5682I-VS load different kernel driver by different _HID
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:218245715
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I081dcf5451c82c03592f954ee25267b31ad81753
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
use DEV_PTR to get codec HID for simplify the variant.c code
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:204523176
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Idf5b3661e74a189390d25381e03448c28a966f38
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
volmar boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I36355af771fbf97e655f2fd6e0505c657e0420b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
vell boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0c39d06e3b2f39db88d924205786bfa1b27df3fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taniks boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Icf6cb0d057f9ad3cbcc1155423ed7efa58a46d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taeko4es boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I82bdf8a1bfe2df0fc1d50d154def8742714321ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
taeko boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib30815dbe99342b6afd9af9f1aa9ff61c9a4fe80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
redrix boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifd69a9c2f1a71aefc19adf6931e10de62d05fb2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
redrix boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If08ae5c96232efd03d77090c3c6979c77f95c998
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
primus boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I71f7391df6d827b75f87e54e17f6f7983a9e829b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
primus boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3133a992617c833fd13df97795c46ec04ebb8bf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
kano boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1d8c003b19381e6a76aff8c844546694c5710e53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If71ceb07a9894a0571a9983d008058598693986f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
gimble boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Idd398d819dcb30a3ec588ce2ef4562a728f99405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
felwinter boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic1e0bfc53b74bd5af9ac8d598bb80833499dd997
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage'
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id5a2136e57e842fbd0b2c2836833106e7344afee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera4es boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a73aca1c364dcbc3f3957cd4193d86f399a40bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
Also fix the gpio order of GPP_F19.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
anahera boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie50ba20a10ded184fd880be9ed288b90d346c22b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Variant should honor locked gpios from baseboard, but not the last.
Variant can add more gpios to lock if needed.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
agah boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia9272f704e5656e6d0dc318dd1b51d50fc549839
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add rest of soc sensitive gpios to lock for brask.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brask boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Iad87d13d3df0ad87c075027e3fcc4c75aa711159
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add rest of soc sensitive gpios to lock for brya.
BUG=b:216583542
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I41393e7a0e8bacb3cc98610f7101dabe66308f94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
The ChromiumOS kernel has the ability to restrict devices to their own
IOMMU security domains when ACPI passes this property to a device
downstream of a PCIe RP.
BUG=b:215424986
TEST=verified the property is found and WWAN is restricted to its own
IOMMU domain as expected.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1717c0976d1d961772245fd420368fe5a9c1262e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Enable USB Port A on daughterboard for Taeko
BUG=b:216533764
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1a43c256757f3fc4b53ba1f794587d6a00ba0aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:192535692
BRANCH=volteer
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ia6089441dc1ba04c3f7427dda065b85bd295af0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
The patch selects USB2_PORT_MAX_TYPE_C macro for usb2 port#2 in
the device tree of Gimble DVT and Gimble EVT. The macro modifies the
USB2 configuration to indicate the port is mapped to Type-C and sets
Max TX and Pre-emp settings.
The change is required to enable port reset event on the USB2 port#2.
This event is passed to USB3 upstream ports to upgrade back to super
speed (USB3) after a downgrade during low power state. The change is
done for Gimble DVT and EVT boards.
BUG=b:193287279
TEST=Built coreboot for Gimble and tested type A pen drive detect as
super speed device on both the Type-C ports.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: If54faa63a983c859bf26a6a779751a6c3c85c43d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61586
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nivviks P1 will also use Micron MT62F512M32D2DR-031 WT:B. Add it to the
parts list and regenerate the memory IDs using part_id_gen.
BUG=b:217095281
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I2b56b0844e70a2712923b197436dd2d668e58a27
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
