This reverts commit f83b7d494e.
It turns out we have tests which use `futility validate_rec_mrc` to
validate the MRC cache, which includes verifying the data checksum.
Revert this to allow the tests to pass while we figure out how to fix
this.
BUG=b:245277259, b:242667207
TEST=None
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Id913d00584444c21cb94668bdc96f4de51af7cee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The following boards are setting DTPC tablet mode values without
corresponding device tree values, meaning they are effectively setting
"random" values for tablet mode:
1. Cezanne
2. Mendocino
The device tree has tablet mode disabled, so the code should never be
exercised, but this CL removes it entirely to cleanup "dead" code.
BRANCH=none
BUG=b:217911928
TEST=Build nipperkin
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Refer to PCI Express Base rev6.0 v1.0, 4.2.7 Link Training and Status
State Rules, Lane Error Status is normal to record the error when link
training. To make sure Lane Error Status is correct in OS runtime,
add a Kconfig PCIEXP_LANE_ERR_STAT_CLEAR that clears the PCIe lane error
status register at the end of PCIe link training.
Test=On Crater Lake, lspci -vvv shows
bb:01.0 PCI bridge: Intel Corporation Device 352a (rev 03)
(prog-if 00 [Normal decode])
Capabilities: [a30 v1] Secondary PCI Express
LnkCtl3: LnkEquIntrruptEn- PerformEqu-
LaneErrStat: LaneErr at lane: 0
Signed-off-by: Wilson Chou <Wilson.Chou@quantatw.com>
Change-Id: I6344223636409d8fc25e365a6375fc81e69f41a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
This change removes all references to HybridStorageMode
UPD since it has been deprecated starting from FSP v2344_00
BUG=b:245167089
TEST=build coreboot mtlrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Linux always "turns on" a PowerResource when it boots, regardless of
_STA, so the _ON routine should be idempotent. In this case, it all is,
except for the LTR restore, which would restore a value of 0 when _ON is
run the first time, which means that LTR is disabled on the root port
from then on, as the save/restore routines will keep saving/restoring
that 0. THis patch fixes the problem by moving the power checks from
PGON/PGOF to GCOO/GCOI.
BUG=b:244409563
TEST=boot agah and verify that LTR is still enabled on the root port
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4ed78323608eede5b8310598f1f1115497ab2b5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67278
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The Linux kernel runtime D3 framework expects a PCIe device to have a
power resource in order to be properly power-manageable. The _PR0/_PR3
values were pointing at the PEG0 Device, which is not a PowerResource,
so this must have confused the RTD3 framework and RTD3 was not
functional. Removing the _PR0/_PR3 fixes the problem.
BUG=b:243888246
TEST=echo auto > /sys/bus/pci/devices/0000:01:00.0/power/control;
sleep 10;
echo on > /sys/bus/pci/devices/0000:01:00.0/power/control
After this there are no longer errors seen in dmesg about failing
to place the device into D0.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I83fa1e5fabd3257b097c10e7a13c9861872685ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Mostly there are too many extraneous `\_SB.PCI0.` prefixes, also a few
minor cleanups, but nothing functional.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I79d919d2f04f57232f8f6a4e4d0690833faeb834
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Similar to the prior CL (commit db8ad5e), do the same register dance
before/after GCOFF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8fecba40c5a5af11e24f82db07face3ce10481bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67086
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On some platforms the HFSTS4 bit 19 does not indicate active PTT.
Instead of ME HFSTS4, use TXT FTIF register to check active TPM for
the current boot. Discrete TPM shall be deactivated when PTT is
enabled so this always should return true value of PTT state.
Leave the old method for backwards compatibility if TXT FTIF would not
be applicable for older microarchitectures.
Based on DOC #560297.
TEST=Check if PTT is detected as active on MSI PRO Z690-A DDR4 WIFI
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3a55c9f38f5bb94fb1186592446a28e675c1207c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Instead of just printing the fatal errors, do early return so that
boot up time will be reduced during display init failure. Remove malloc
allocation and make tu a local variable.
Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.
1. Refactor and simplify acpigen_write_alib_dptc() into the following
functions:
- acpigen_write_alib_dptc_default()
- acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enable to control
whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
the DPTC settings.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim
Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Thermal configuration registers are now located behind PMC PWRMBASE
for MeteorLake as well (same as ADL). Hence, using thermal common code
to sets the thermal low threshold as per mainboard provided
`pch_thermal_trip`.
Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on
Google/rex prior to FSP-S shows that registers are now programmed
based on 'pch_thermal_trip' and lock register BIT31 is set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch updates `pch_thermal_trip` as per Intel MTL vol1
chapter 14.
Additionally, dropped the `FIXME` tag for `pch_thermal_trip`.
TEST=Able to boot the Google/rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch drops redundant MCHBAR programming in romstage as bootblock
already done with MCHBAR setting up.
TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct
value as per iomap.h
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add functionality such that the FPMCU is power cycled and has its reset
sequenced on boot.
This has been added such that we do not need to update the bootblock.
We are required to do this as bootblock exists in read-only flash for
devices that have already been manufactured and so have no method of
updating the sequencing there.
Power remains off during coreboot (after briefly being turned on in the
unchangeable bootblock).
Once control is handed over to the Kernel, it takes care of sequencing
the power and reset appropriately and ensures the FPMCU is unpowered for
>200ms on boot.
BUG=b:240626388
TEST=Confirmed FPMCU is still functional on Vell and Anahera.
Confirmed power is off for approximately 6 seconds on boot (target
>200ms).
Confirmed reset is de-asserted approx 5ms after power application
(target >2.5ms)
Change-Id: I9694f8837e0a72eaed42a5eeee92b0f120269086
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66915
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Enable Acoustic noise mitigation
- Set slow slew rate to fast/4 for VCCIA and VCCGT
- Disable fast slew rate for deep package C states for VCCIA and VCCGT
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia344d9d939c3323bac82afdf25d5fff81081f9c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67380
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out for bus hanging
analysis.
TEST=build pass.
BUG=none
Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. There are two power sources for CPU:
- Logic power (VPROC).
- SRAM power (VSRAM_PROC).
2. There is a constraint between VPROC and VSRAM_PROC:
- 0mV <= VSRAM_PROC - VPROC <= 250mV.
With software control, the constraint might not always hold. Therefore,
we enable hardware tracking from PMIC MT6366 to ensure the constraint
is met automatically.
BUG=b:236353282, b:241615706
TEST=meet the constrain correctly when adjusting the voltage.
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=Boot to OS on nivviks/nirwen and check that stylus GPIOs are
configured based on fw_config.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ibbe9f379abe10a741642e11d4833d3a53489693a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66929
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
EE measured touchscreen/audio runs at 385.5/397.9kHz after tuning.
BUG=b:244403643
BRANCH=firmware-dedede-13606.B
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: I7d9503e5f92295432e31f09ae791eaa18eac9d4d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:194979741
BRANCH=firmware-brya-14505.B
TEST=Build and boot skolas to OS. Verify entries in SSDT.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I3c32dd71ab454227b15913bda7f542230e5568db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Historically, ChromeOS devices have worked around the problem of OEMs
using several different parts for touchpads/touchscreens by using a
ChromeOS kernel-specific 'probed' flag (rejected by the upstream kernel)
to indicate that the device may or may not be present, and that the
driver should probe to confirm device presence.
Since c636142b, coreboot now supports detection for i2c devices at
runtime when creating the device entries for the ACPI/SSDT tables,
rendering the 'probed' flag obsolete for touchpads. Switch all touchpads
in the tree from using the 'probed' flag to the 'detect' flag.
Touchscreens require more involved power sequencing, which will be done
at some future time, after which they will switch over as well.
TEST: build/boot at least one variant for each baseboard in the tree.
Verify touchpad works under Linux and Windows. Verify only a single
touchpad device is present in the ACPI tables.
Change-Id: I47c6eed37eb34c044e27963532e544d3940a7c15
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67305
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The previous VBT binary was not properly configured, there were DP
display issues on some of the ports and resulted in hangs when FSP
debug was used. The updated VBT fixes all the issues.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I788240e36a9a90a5342ee9761f2c61ebf4caa9a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67426
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for multimedia
content) to Kconfig.
TEST=Able to boot Google/rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416346995d744990054c8e0c839ada82c84b7550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow the Thermal_paramters_list-0902.xlsx to modify DPTF parameters
and fan table.
1. Modify CRT of TSR0 - TSR3 to 97.
2. Modify TCC offset to 6.
3. Update new fan table.
BUG=b:244657172
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I751bc5442f64428c383034755cd5d74fbd0ea91e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67314
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify fan speed/duty table follow "Duty table.xlsx".
BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then
system feedback fan speed.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id5e885b96624d5fc31f1d42e3582c3ab01e08458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The Kinox fan speed/duty table has 20 elements so raise the
DPTF_MAX_FAN_PERF_STATES from 10 to 20.
BUG=b:244262869
TEST=Boot to ChromeOS. Using SDV system, enter duty value, and then
system feedback fan speed.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iacd3ef0da926df5d174b215ab8ea4adc1a8b672e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67390
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The PCIe WWAN module used on rex requires control over 4 signals to
successfully power it on. It is desirable to do this before passing
control to the payload, because the modem requires a ~10 seconds
initialization phase before it can be used.
The corrected sequence looks like:
1) Drive device into full reset and enable power in bootblock
2) Deassert FCPO in romstage, after power rails stabilize
3) Deassert WWAN_RST#, then WWAN_PERST# in ramstage
BUG=b:244077118
TEST=FM350 could be enumerated via lspci
Measured signals to check start-up Timing Sequence, tpr/ton1/ton2.
Tpr = 572mS
Ton1 = 6.3s
Ton2 = 6.3+4.17ms
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I6cda9348ef7f54efe5ba2358040596a1c2da1b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67332
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable SRAM in devicetree so that resources are allocated properly
for it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibdd2ee455f5bf6cd95bba6bab8689da664bfcf54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Use the BIT() macro instead of reinventing the wheel.
TEST=timeless builds are identical
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I873013feebd30c86290dda692c7b137d5f3c4729
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the missing spaces to two log message, like the one below.
WARNING: Device PCI: 03:00.0 requests a BAR with34 bits of address space, which coreboot is notconfigured to hand out, truncating to 29 bits
Change-Id: If933d8fb0db5b58ff12f043cc73172a3f6ffc624
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929
BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This area relates to storing of AP RO verification information.
CONFIG_VBOOT_GSCVD is enabled by default for TPM_GOOGLE_TI50 and
guybrush is using TPM_GOOGLE_CR50.
Signed-off-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Change-Id: I896b871bf2ac64e334514b979add9b8ac2c43945
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Change the name of the CALIBRATION_REGION definitions used in two
separate locations. This conflict was causing an error for the
lint-001-no-global-config-in-romstage test.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Currently, the "loading FSP-S" timestamp is added in fsp_silicon_init().
However, most Intel platforms actually load FSP-S earlier than this, in
soc_fsp_load(). So the timestamp is added in the wrong place.
Add the timestamp in fsps_load() instead, after the load_done early
return so that it will only be added for the first call.
Before:
949:finished CSE firmware sync 961,833 (17,998)
17:starting LZ4 decompress (ignore for x86) 1,018,328 (56,495)
18:finished LZ4 decompress (ignore for x86) 1,018,797 (469)
30:device enumeration 1,035,096 (16,298)
971:loading FSP-S 1,048,082 (12,986)
954:calling FspSiliconInit 1,049,331 (1,249)
After:
949:finished CSE firmware sync 959,355 (16,370)
971:loading FSP-S 978,139 (18,784)
17:starting LZ4 decompress (ignore for x86) 1,015,796 (37,656)
18:finished LZ4 decompress (ignore for x86) 1,016,271 (475)
30:device enumeration 1,032,567 (16,295)
954:calling FspSiliconInit 1,046,867 (14,300)
BUG=b:239769975
TEST="loading FSP-S" is added in the right place on nivviks (see above).
Change-Id: Ib26cf96ae97766333fe75ae44381d4f7c6cc7b61
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Having a CSE Lite SKU's firmware is not necessarily depending
on the underlying hardware nor on having ChromeOS installed as
already mentioned in commit f3419b29b7 ("soc/intel/common/cse:
Drop dependency on CHROMEOS for SOC_INTEL_CSE_LITE_SKU").
For example RVP Boards sometimes have a CSE LITE FW, if Chrome board
related stuff is tested, which doesn't necessarily imply a ChromeOS
being used. It is therefore changed to an option, which can be
changed in menuconfig.
Change-Id: I4da7feab881ae43528c9d852cc842ac93fa9c6de
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67078
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the APOB_HASH feature. This improves boot times by ~10ms.
BUG=b:193557430
TEST=boot to OS and verify boot time improvement
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9628b67cd3206ffdbef23162c453dc183c69e5a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67377
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Comparing the APOB in RAM to flash takes a significant amount of time
(~11ms). Instead of comparing the entire APOB, use a fast hash function
and compare just that. Reading, hashing, and comparing the hash take
~70 microseconds.
BUG=b:193557430
TEST=compile and boot to OS in chausie with and without this option set
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I241968b115aaf41af63445410660bdd5199ceaba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Add xxhash functions. This is a very fast hash function, running at RAM
speed limits.
This code was adapted from the linux kernel with minor modifications to
make it fit in coreboot.
BUG=b:193557430
TEST=compile
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I8108af5ab14d8e6c6f5859bd36155c7d254e892c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
dptc_enable is being treated as a bool, so convert to explicitly be a
bool.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build guybrush
TEST=Build skyrim
Change-Id: I0e93d892b3b8016221812c8b9ec6c257dcf13ef5
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67188
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to layout restrictions on mc_ehl2, the SD-card interface is limited
to operate in DDR50 mode. The alternative modes SDR104 and SDR50 are not
supported. Limit the capabilities in the SD card controller to DDR50
mode only so that the SD card driver in OS will choose the right mode
for operation even if the attached SD card supports higher modes.
Change-Id: Idc7f1466ec71f4218f6b957cadeeffadd069eb2d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Since the new RTC is located in I2C bus 1 now, set the bus speed to
100 kHz as well.
Change-Id: Ica9468e559bc654545592a9b4d23f3164eafca8a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67102
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the latest redesign a new RTC was introduced on mc_ehl2. Instead
of the old RX6110SA the new Micro Crystal RTC RV3028 is used now. Since
the address of this new RTC conflicts with an EEPROM on I2C bus 2, the
new RTC was moved to I2C bus 1.
As the mainboard is not finished yet, there are no incompatibility
issues with this change. Every new mainboard will have the new RTC and
the older mainboards are not delivered yet.
Change-Id: I3dd00855b8c9b22bdea21d3c8563cdb392868751
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
With a redesign of mc_ehl2 the used RTC was changed. In order to be able
to select a different RTC type for every variant move the RTC Kconfig
switch into the variant's Kconfig file.
Change-Id: Ia24703ede6a935e3b9886df87237857baec7d6a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67100
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a driver for a new RTC from Micro Crystal. Supported
features are:
* configure backup voltage switchover via devicetree
* configure backup capacitor charging mode via devicetree
* set date if a voltage drop on backup voltage was detected
to either a user definable (devicetree) or coreboot build date
Change-Id: I37176ea726e50e4e74d409488981d7618ecff8bb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.
BUG=None
TEST=build pass
Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some of the pll settings are incorrect, which cause problems in GPU
after booting into kernel.
- MFGPLL opp_ck_en bit isn't located at MFGPLL_CON1, so we need to fix
it to enable MFGPLL properly.
- Switch SPMI clock muxes to 260M to avoid kernel hang while probing
SPMI kernel driver.
TEST=GPU bringup correctly.
BUG=b:233720142
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I971109a5f72e3307899daaf5a5f26022124b559b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67355
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The T4 of ANX7625 power on sequence should be larger than 0ms, but it's
-59ms now. So add 70ms delay between DSI_TE and LCM_RST.
BUG=b:242352915
TEST=The sequence T4 is larger than 0ms when power on.
Change-Id: I6b888707ec3c0612e396564e77c4cdbe92614dc5
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The header file `compiler.h` is automatically included in the build by
the top level makefile using the command:
`-include $(src)/commonlib/bsd/include/commonlib/bsd/compiler.h`.
Similar to `config.h`, 'kconfig.h`, and 'rules.h`, this file does not
need to be included manually, so remove it.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5d3eb3f5e5f940910b2d45e0a2ae508e5ce91609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
The header file `rules.h` is automatically included in the build by the
top level makefile using the command:
`-include src/soc/intel/common/block/scs/early_mmc.c`.
Similar to `config.h` and 'kconfig.h`, this file does not need to be
included manually, so remove it.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I23a1876b4b671d8565cf9b391d3babf800c074db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67348
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without these, all SuperSpeed ports are wired to EHCI #2.
"superspeed_capable_ports" and "xhci_switchable_ports" should fit both
CMT and SFF variants, while "xhci_overcurrent_mapping" should be
consistent with the first 4 elements of mainboard_usb_ports[].
With this commit, SuperSpeed devices plugged in SuperSpeed ports are
wired to the XHCI on my own Z220 SFF.
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Change-Id: Ifddecfd1d32ed6ab84d7eed8dc2d85d83cbebbcc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67089
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The top-down allocation feature was merged prematurely before
platforms that don't report their resources correctly were fixed.
Let's turn it off by default.
Change-Id: I982e6d7355b9e689de10357d6c16ed718705270e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67328
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
This reverts commit 117e436115.
Depends on top-down allocation to keep the behavior to place
hot-plug reservations above 4G. The latter was merged prema-
turely, though.
Change-Id: I5721cb84b29fc42240dff94f49a94461d88e7fbc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67329
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This patch fixes a hidden issue present inside FSP-S while coreboot
decides to skip performing MP initialization by overriding FSP-S UPDs
as below:
1. CpuMpPpi ------> Passing `NULL` as coreboot assume FSP don't need
to use coreboot wrapper for performing any
operation over APs.
2. SkipMpInit -----> Set `1` to let FSP know that coreboot decided
to skip FSP running CPU feature programming.
Unfortunately, the assumption of coreboot is not aligned with FSP when
it comes to the behaviour of `CpuMpPpi` UPD. FSP assumes ownership of
the APs (Application Processors) upon passing `NULL` pointer to the
`CpuMpPpi` FSP-S UPD.
FSP-S creates its own infrastructure code after seeing the CpuMpPpi
UPD is set to `NULL`. FSP requires the CpuMpPei module, file name `UefiCpuPkg/CpuMpPei/CpuMpPei.c`, function name `InitializeCpuMpWorker`
to perform those additional initialization which is not relevant for
the coreboot upon selecting the SkipMpInit UPD to 1 (a.k.a avoid
running CPU feature programming on APs).
Additionally, FSP-S binary size has increased by ~30KB (irrespective of
being compressed) with the inclusion of the CpuMpPei module, which is
eventually not meaningful for coreboot.
Hence, this patch selects `MP_SERVICES_PPI_V2_NOOP` config
unconditionally to ensure pass a valid pointer to the `CpuMpPpi` UPD
and avoid APs getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
Ideally, FSP should have avoided all AP related operations when
coreboot requested FSP to skip MP init by overriding required UPDs.
TEST=Able to drop CpuMpPei Module from FSP and boot to Chrome OS on
Google/Redrix, Kano, Taeko devices with SkipMpInit=1.
Without this patch:
Here is the CPU AP logs coming from the EDK2 (open-source)
[UefiCpuPkg/CpuMpPei/CpuMpPei.c] when coreboot sets `NULL` to the
CpuMpPpi UPD.
[SPEW ] Loading PEIM EDADEB9D-DDBA-48BD-9D22-C1C169C8C5C6
[SPEW ] Loading PEIM at 0x00076F9A000 EntryPoint=0x00076FA24E2
CpuMpPei.efi PROGRESS CODE: V03020002 I0
[SPEW ] Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE
[SPEW ] Notify: PPI Guid: F894643D-C449-42D1-8EA8-85BDD8C65BDE,
Peim notify entry point: 76FA0239
AP Loop Mode is 2
GetMicrocodePatchInfoFromHob: Microcode patch cache HOB is not found.
CPU[0000]: Microcode revision = 00000000, expected = 00000000
[SPEW ] Register PPI Notify: 8F9D4825-797D-48FC-8471-845025792EF6
Does not find any stored CPU BIST information from PPI!
APICID - 0x00000000, BIST - 0x00000000
[SPEW ] Install PPI: 9E9F374B-8F16-4230-9824-5846EE766A97
[SPEW ] Install PPI: 5CB9CB3D-31A4-480C-9498-29D269BACFBA
[SPEW ] Install PPI: EE16160A-E8BE-47A6-820A-C6900DB0250A
PROGRESS CODE: V03020003 I0
With this patch:
No instance of `CpuMpPei` has been found in the AP UART log with FSP
debug enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8ebe0bcfda513e79e791df7ab54b357aa23d295c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66706
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In order to fix the USB port of type-C dongle has no function after
reboot/shutdown, modify ufp which is in google_chromeec_usb_pd_get_info
from the bit1 of type-c role (PD_CTRL_RESP_ROLE_DATA).
BUG=b:239138412
TEST=Built coreboot image and verified that using this patch can detect
usb drive after reboot.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I73a4a6ec37129388783599125f067068d155d93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67168
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GSPI0 pads required muxing to NF8. Support for extended
native functions was added in
commit b6c32d7fe4
BUG=b:244610269
TEST=build and booted on Rex
Change-Id: Iab4e0bc6890cd8e976c513fe87dda0da9b5f2ee0
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Add multiple fan support for dptf policies
BUG=b:235254828
BRANCH=None
TEST=Built and tested on Redrix system for two fans
Change-Id: I96ead90e3b805bd20de03e4bef4fa4b9fbaaaedd
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update DPTF parameters from internal thermal team.
BUG=b:244373677
BRANCH=firmware-dedede-13606.B
TEST=Build image and verified by thermal team.
Change-Id: I8415e0d25a79764f0c1d11688728b7caa3b3d6a4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
We currently have two competing mechanisms to limit the placement of
resources:
1. the explicit `.limit` field of a resource, and
2. the IORESOURCE_ABOVE_4G flag.
This makes the resource allocator unnecessarily complex. Ideally, we
would always reduce the `.limit` field if we want to "pin" a specific
resource below 4G. However, as that's not done across the tree yet,
we will use the _absence_ of the IORESOURCE_ABOVE_4G flag as a hint
to implicitly lower the `limit` of a resource. In this patch, this
is done inside the effective_limit() function that hides the flag
from the rest of the allocator.
To automatically place resources above 4G if their limit allows it,
we have to allocate from top down. Hence, we disable the prompt for
RESOURCE_ALLOCATION_TOP_DOWN if resources above 4G are requested.
One implication of the changes is that we act differently when a
cold-plugged device reports a prefetchable resource with 32-bit
limit. Before this change, we would fail to allocate the resource.
After this change, it forces everything on the same root port below
the 4G line.
A possible solution to get completely rid of the IORESOURCE_ABOVE_4G
flag would be rules to place resources of certain devices below 4G.
For instance, the primary VGA device and storage and HID devices
could be made available to a payload that can only address 32 bits.
For now, effective_limit() provides us enough abstraction as if the
`limit` would be the only variable to consider. With this, we get
rid of all the special handling of above 4G resources during phase 2
of the allocator. Which saves us about 20% of the code :D
Change-Id: I4c7fcd1f5146f6cc287bd3aa5582da55bc5d6955
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65413
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `IORESOURCE_ABOVE_4G` flag was only explicitly set for our dummy
device that reserves resources behind a hotplug port. The current re-
source allocator implicitly extends this to all devices below the port,
including real ones. Let's make that explicit, so future changes to the
allocator can't break this rule.
Change-Id: Id4c90b60682cf5c8949cde25362d286625b3e953
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66719
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add option to resource allocator v4 that restores the top-down
allocation approach at the domain level.
This makes it easier to handle 64-bit resources natively. With
the top-down approach, resources that can be placed either above
or below 4G would be placed above, to save precious space below
the 4G boundary.
Change-Id: Iaf463d3e6b37d52e46761d8e210034fded58a8a4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There's no reason to use camel case for EEPROM region names or local
variables. Use snake case for consistency with coreboot's code style.
Change-Id: Id1200a0c778095b109d824a1ca4e3e69591e4165
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Some devices require that several bytes are written with a single I2C
write command. Extend the i2c_bus interface functions and add both, read
and write for more than one byte at a defined byte offset.
Change-Id: I0eec2e1d4185170f02b4ab35aa6546dc69569303
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67098
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
For TPM2, vb2api_secdata_firmware_create() is already called from
setup_firmware_space() from _factory_initialize_tpm(). Therefore move
the duplicate call from factory_initialize_tpm() to TPM1's
_factory_initialize_tpm().
Change-Id: I892df65c847e1aeeabef8a7578bec743b639a127
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Intel platforms have soft straps stored in the SI_DESC FMAP section
which can alter boot behavior and may open up a security risk if they
can be modified by an attacker. This patch adds the SI_DESC region to
the list of ranges covered by GSC verification (CONFIG_VBOOT_GSCVD).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0f1b297e207d3c6152bf99ec5a5b0983f01b2d0b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66346
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CL:3825558 changes all vb2_digest and vb2_hash functions to take a new
hwcrypto_allowed argument, to potentially let them try to call the
vb2ex_hwcrypto API for hash calculation. This change will open hardware
crypto acceleration up to all hash calculations in coreboot (most
notably CBFS verification). As part of this change, the
vb2_digest_buffer() function has been removed, so replace existing
instances in coreboot with the newer vb2_hash_calculate() API.
Due to the circular dependency of these changes with vboot, this patch
also needs to update the vboot submodule:
Updating from commit id 18cb85b5:
2load_kernel.c: Expose load kernel as vb2_api
to commit id b827ddb9:
tests: Ensure auxfw sync runs after EC sync
This brings in 15 new commits.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I287d8dac3c49ad7ea3e18a015874ce8d610ec67e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Add additional DPTC parameter IDs that are necessary when throttling the
SOC due to low/no battery.
These additional parameters are used in later CLs.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I9e944d7c620414ec92d08a3d1173ba281d593ffc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67182
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
elog_gsmi_cb_mainboard_log_wake_source is called from SMI and causes
eSPI transactions. If the SMI interrupts an ongoing eSPI transaction
from the OS it will conflict and cause failures. Removing this call to
avoid conflicts. This can be re-enabled after refactoring
google_chromeec_get_mask to use ACPI MMIO.
This is a copy of CB:63280 but for skyrim.
BUG=b:227163985, b:243557044
TEST=suspend/resume skyrim and no longer see EC wake sources in elog.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iac56840fe15101bc556d8cce9960f761c6ea7181
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Enable DSP setting. Make sure the SSP can work as expected.
BUG=b:243123156
TEST=Dev beep working on Rex.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I6ae28e414ac4ac33f596df57691c979eac5fe132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67270
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Enabling Bus Master isn't required by the hardware, so we shouldn't
need to enable it at all. However, some payloads do not set this bit
before attempting DMA transfers, which results in functionality
failure. For example: in this case, unable to see the developer screen
in Depthcharge.
In the prior IA SoC platform, FSP/GFX PEIM does the BM enabling for
the IGD BAR resources but starting with the MTL platform, it fails
to do so resulting into inability to see the Pre-OS display.
BUG=b:243919230 ([Rex] Unable to see Pre-OS display although GFX
PEIM Display Init is successful during AP boot)
TEST=Able to see the developer screen with eDP/HDMI while booting
the Google/Rex.
Also, this change doesn't impact the previous platforms
(ADL, TGL, CML etc.) where the BM is default enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I9ad9eee8379b7ea1e50224e3fabb347e5f14c25b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67273
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select SYSTEM_TYPE_LAPTOP so the FADT PM profile is correctly set to
mobile (vs the default of desktop).
TEST=build/boot google/dewatt, run FWTS and verify FADT PM profile correct
Change-Id: I480fbe85782e2c63efa8d2212d503a47d8149ab9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As part of investigating b/240690391 I noticed that we were missing
the daughter board ports. Not all SKUs have these ports connected,
but it doesn't hurt to have the extra ACPI nodes.
BUG=none
TEST=build
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id6fc34acbfa30bc15e697043bf93bcf584256128
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Definition of FIRMWARE_LOCATION, POUND_SIGN, DEP_FILES,
amd_microcode_bins are moved to common Makefile.inc.
Change-Id: I5a0ea27002e09d0b879bafad37a5d418ddb4e644
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62658
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Add the headers for 2.2.3.1, which includes the following changes
over 2.2.0.0:
• [Implemented]GLK: XHCLKGTEN Register setting causes S0ix entry
failure in less than 5 cycles when a USB2 Ethernet Dongle is
connected. Refer GLK BIOS Spec Volume1 CDI# 571118 under chapter
7.20.6 for new Register settings.
• [Implemented] [GLK/GLK-R] DDR4 16Gb SDP Memory support for Gemini
Lake/Gemini Lake – R
• [Update] MRC new version update to 1.38.
• [Fixed][GLK-R][WLAN] Removed the DSW function - Wake on LAN from
S4 issue with latest Wifi driver.
[Update] MRC new version update to 1.39. Included fix for
MinRefRate2xEnable and support for Rowhammer mitigation.
• [Fixed] Disable Dynamic DiffAmp and set CTLE from 7 to 5. This
change specific to DDR4 memory configuration.
• GLK Klocwork Fix
• [Update] MRC new version update to 1.40.
Added in a separate directory as the default. The 2.2.0.0 headers
were left and will be used for Google boards, as some offsets have
moved.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I09498368b116c2add816eeada2fa4d0dba6e5765
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Nvidia recommends saving and restoring the LTR Enable bit in PCIe config
space for the PCIe root port before/after GC6 entry. Also the detectable
error bit should be cleared, as there may be errors expected during the
GC6 flow.
BUG=b:214581763
TEST=no more correctable errors after GC6 entry/exit
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I058ce1b3f17fb6cc59785a85efaf9ea0504cf2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
BUG=b:238937091
TEST=Dump SSDT on nereid and check that the wifi device contains the
DmaProperty. Also check that the kernel marks the device as untrusted.
Change-Id: I0725ea18d52420a3161d6fcfa3bcb72ebe35f3a5
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES and remove the
TODO from SOC_AMD_COMMON_BLOCK_HAS_ESPI.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I90e3bf3f196e22b428b01ea0437c1224702d2b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Compile-time support of DPTC is controlled by
EC_ENABLE_AMD_DPTC_SUPPORT in each variant's ec.h file. This CL removes
EC_ENABLE_AMD_DPTC_SUPPORT and replaces it with the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
Each variant's run-time support of DPTC continues to be controlled by
the variant's overridetree.cb "dptc_enable" value.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic101e74bab88e20be0cb5aaf66e4349baa1432e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Pcie5_1 is added for DID 0xA72Dh and BDF 0/1/1.
References:
RaptorLake External Design Specification Volume 1 (640555)
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Id7440bf202d5560ff92807877d48b94054cb1de9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Chausie fails to boot without this option set. Enable in the mainboard
rather than the SoC Kconfig to not impact Skyrim.
TEST=boot to OS
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9f2a1be9eddb9e17407d00ff50ceb70a2718ce3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for loading SPM firmware from CBFS to SPM SRAM. SPM needs
its own firmware to enable SPM suspend/resume function which turns off
several resources such as DRAM/mainpll/26M clk when linux system
suspend.
SPM is an essential component on MediaTek SoC, so we initialize PPM
in soc_init(). For MT8188, SPM will handshake with DPM to do
initialization, so we need to call spm_init() after dpm_init().
This SPM flow adds 33ms to the boot time.
firmware log:
mtk_init_mcu: Loaded (and reset) spm_firmware.bin in 25 msecs
SPM: spm_init done in 33 msecs, spm pc = 0x400
TEST=spm pc is 0x400 which is in idle state.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I1a1f49383e0ceadc259a18272fc1c277b65406ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some functions are the same in spm.c for MT8192, MT8195, MT8186 and
MT8188, so we move them to common/spm.c.
TEST=build pass.
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I29ddefc47d8bd156fa1ca0cedd4deaed676ae7e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The unit of current_clk in pmif_ulposc_check() should be MHz. We use
pmif_get_ulposc_freq_mhz() to get the default hardware value in MHz.
Without this modification, the judgement in pmif_ulposc_check() is
alway wrong due to the wrong unit.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bf80a23bb35ff657023eb4b7e009fa233f61244
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add basic DEVAPC (device access permission control) driver.
DEVAPC driver is used to set up bus fabric security and data protection
among hardwares. DEVAPC driver groups the master hardwares into
different domains and gives secure and non-secure property. The slave
hardware can configure different access permissions for different
domains via DEVAPC driver.
1. Initialize DEVAPC.
2. Set master domain and secure side band.
3. Set default permission.
TEST=check logs of DEVAPC ok.
BUG=b:236331724
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Change-Id: Iad3569bc6f8ba032d478934ba839dc4b5387bafc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some enums and functions are the same in DEVAPC driver for MT8195,
MT8186, and MT8188, so we move them to common folder.
TEST=build pass.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia7d2145780780fd54b76952db96424b8ea477594
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add initialization of DPM drvier for DRAM low power mode.
DPM is an essential component on MediaTek SoC, so we initialize DPM
in soc_init().
This DPM flow adds 22ms to the boot time.
coreboot logs:
CBFS: Found 'dpm.dm' @0x156c0 size 0xfc in mcache @0xfffdd110
mtk_init_mcu: Loaded (and reset) dpm.dm in 6 msecs (422 bytes)
CBFS: Found 'dpm.pm' @0x15800 size 0x3c59 in mcache @0xfffdd140
mtk_init_mcu: Loaded (and reset) dpm.pm in 16 msecs (18910 bytes)
TEST=build pass
BUG=b:236331724
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I46baa7b49e90d53dd4d1d95af9c46622faf30419
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66969
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPM is a hardware module for DRAM power management, which is used for
DRAM low power mode.
TEST=build pass
BUG=b:236331724
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I872396fe2c5accd92ba5c14b124125bd58257771
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66967
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8195 and MT8188 share the same dpm_4ch.c, so we move it to common
folder.
TEST=build pass
BUG=b:236331724
Signed-off-by: Xi Chen <xixi.chen@mediatek.corp-partner.google.com>
Change-Id: I13406707d3b331ced57af62f4ba4f365e9ac4f84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66966
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
It seems pass 1 and 2 were inconsistent. The first would account for
resources with a limit of 0 even though the second can't assign anything
for them.
Change-Id: I86fb8edc8d4b3c9310517e07f29f73a6b859a7c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65402
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Fix EC_IN_RW config for Rex. Dauntless on Rex does not have an EC_IN_RW GPIO pin.
Port of commit 7f339c6050 ("mb/google/corsola: Correct EC-is-trusted logic")
BUG=b:243950850
TEST=Built and booted to Google Rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I97e5c752b4f36c9221137903f755837880f6b1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67208
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This reverts commit 47fee08fc3.
The required EC changes are now in place to revert this W/A that
disables the LID based shutdown.
BUG=b:243920003
TEST=No shutdown request has triggered while booting AP at
depthcharge.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5ae56912f030f6f0e3cb49282bbffc920fb389c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The headers added are generated as per FSP v3301.03
In the future, when Alder Lake and Raptor Lake fsp align, Raptor Lake
fsp headers can be deleted and Raptor Lake soc will also use headers
from alderlake/ folder.
BUG=b:243693364
BRANCH=firmware-brya-14505.B
TEST=Boot to OS
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Change-Id: Idbd39ed53d4ba05248a0e83c104846960253931e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
CB:66978 introduced an incorrect condition to check for the presence of
SPD binaries to be injected into APCB_SBR_D5.gen. This caused the SPDs
to be not injected into the APCB and hence the system fails to boot. Fix
it by updating the path of the SPD binaries correctly.
BUG=b:244173966
TEST=Build and boot to OS in Skyrim.
Change-Id: I5efa634fafdcc4769dfad5f533d5512e7c03644f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Ths new Method, GSCI, allows control over whether or not IRQs are routed
as SCI#s for the given GPIO.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic61caaf77d2c6e295e67a1501544e8b8fc6f3b6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Override bluetooth enable_delay_ms to 10ms, per advise from vendor.
BUG=b:233369179
BRANCH=guybrush
TEST=Boot nipperkin, connect to headset, suspend and reboot,
headset still functions.
Change-Id: Ic00de6704018f27339512929f85531aa72205b0e
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67177
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Set bluetooth enable_delay_ms to 200ms. 200ms is the lowest common
denominator between the two BT chipsets.
BUG=b:233369179,b:236289478
BRANCH=guybrush
TEST=Connect to headset, suspend and reboot, headset still functions
Change-Id: Id4c23de37351d28d02aaa797fa19ff49e9dfa76c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65180
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
IMHO, using bitfields directly in the Field declaration makes the ASL
code more readable then directly manipulating the entire 32-bit dword.
TEST=ACPI code using several of these Methods still works
(google/agah dGPU ACPI code)
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9909700022d8b55db3f5208010bdff11ddaf4e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66812
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Added DPTF passive, critical, active policies for Nirwen.
Added additional TSR for Nivviks and updated the PL2 time window
Ref: EDS doc#645550
BUG=b:238713292
TEST= Boot to OS and verify dptf policies are set based on fw_config.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iae46736d8d7723a20983dcaad42a7007d76cfad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change adds support to configure the DPTF policies based
on the fw_config THERMAL_SOLUTION.
BUG=b:238713292
TEST=Boot to OS and verify that dptf policies are set based on
fw_config.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I0ffb9d7cc6c963add001a31ba23a6d6c351dd621
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The current subsystem ID used by the amps may end up getting used
again for future products, therefore this CL updates the subsystem
ID to 103C8C08, which was specifically generated for this amp.
BUG=b:202484541
BRANCH=brya
TEST='FW_NAME=vell emerge-brya coreboot'
Change-Id: I399d8d99ead4fb6fdfa24c2a7a3e3d5e63603b8b
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To match byra commit 7c2514fc07 (mb/google/brya: Change GPP_F17 programming), update A17 pad
configuration to the APIC only.
TEST=Verified booting to OS on Google/Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ie9f071dc4a2755dd1f396e2afe730ead66bb1dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67183
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CPPC table value for UEFI BIOS has been changed. The code has been
merged to AGESA. We can get the value by dumping ACPI table. Then we
align the coreboot code with the new value.
BUG=b:190420984
Change-Id: I091ab3bbc5f94961f8b366a3fa00f50f5c9fa182
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
BUG=b:238937091
TEST=Dump the SSDT on nivviks and check that the wifi device has the
DmaProperty.
Change-Id: I910b7da7050f9aebfe0eb58552c82b1b29de3772
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Commit 0e7cf3d81d (soc/intel/alderlake:
Fix DDR5 channel mapping) fixed a bug in SoC code that messed up DDR5
SPD address mapping. Atlas uses the 0x50/0x52 addresses. However, the
SoC code bug required commit 044883615d
(mb/prodrive/atlas: Update correct SPD address) so that at least some
RAM would work. Now that the SoC code bug is fixed, the workaround is
no longer needed, so use the correct SPD address mapping.
TEST=Boot Atlas and verify that both memory channels work
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I352d8f36eec63cffd3f63ab6e7421db16ca30163
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename pcie5 alias as pcie5_0 since raptorlake is adding a new pcie5 RC.
BRANCH=firmware-brya-14505.B
TEST=none
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: Iee669e68e3607b7ffec9f0800e9f0a916defd498
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The size of the input parameter to RESET_SYSTEM svc call is expected to
be 4 bytes. Fix the reset_system type from enum to uint32_t.
BUG=b:243476183
TEST=Build and boot to OS in Skyrim with PSP verstage. Trigger a system
reset to ensure that the system is reset successfully.
Change-Id: I6319a1dfc89602722c1c2b1c4ee744493ae8b33f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67117
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If we have a PCIe root port without `ops_pci` or without
`get_ltr_max_latencies`, the parent device wouldn't be PCI.
Hence, check for a PCI path early.
Change-Id: I358cb6756750bb10d0a23ab7133b917bfa25988b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This workaround was added since reading the firmware version on Ti50
versions < 0.0.15 will cause the Ti50 to become unresponsive. No one is
using Ti50 this old anymore, so remove the workaround.
BUG=b:224650720,b:236911319
TEST=Boot to OS on nivviks with Ti50 0.22.4. Check the log contains the
firmware version:
[INFO ] Firmware version: Ti50/D3C1 RO_B:0.0.26/- RW_B:0.22.4/ti50_common:v095c
Change-Id: I3628b799e436a80d0512dabd356c4b2566ed600a
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
The feature "USE_CBMEM_DRAM_INFO" is supported in MT8188. Therefore,
we select this configuration to enable it.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I14f3d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66280
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The emi.c is the same for MT8186 and MT8188, so we could move it to
the common folder and reuse it.
TEST=build pass
BUG=b:236331724
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I225f1d07c973129172f01bf7f4d7f5d5abe7c02b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66328
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When MRC_SAVE_HASH_IN_TPM is selected, mrc_data_valid() uses the TPM
hash to verify the MRC cache data, not the checksum. However, we still
calculate the checksum when updating the cache. Skip this calculation
when MRC_SAVE_HASH_IN_TPM is selected to save boot time.
On nissa, this reduces boot time by ~14 ms:
Before:
3:after RAM initialization 854,298 (28,226)
After:
3:after RAM initialization 849,626 (14,463)
Note, the reason the calculation is so slow is that the new MRC data
lives in CBMEM, which is not yet marked as cacheable in romstage.
BUG=b:242667207
TEST=MRC caching still works as expected on nivviks. After clearing
the MRC cache, memory training happens on the next boot, but doesn't on
subsequent boots.
Change-Id: Ifbb75ecfa17421c0565aec1f3eb48d950244f821
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Define fields of sdram_params and enable MEDIATEK_BLOB_FAST_INIT to
run fast calibration for MT8188 using blob.
DRAM fast calibration logs:
DRAM-K: Fast calibration passed in 19530 msecs
dram size (romstage): 0x200000000
TEST=Fast calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2468d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Initialize and calibrate DRAM in romstage.
DRAM full calibration logs:
dram_init: dram init end (result: 0)
DRAM-K: Full calibration passed in 50176 msecs
TEST=Full calibration pass.
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I31f5693ffe4a1e30defbc8a96dc128de03d6b7e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66278
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Use common SoC drivers for DRAM calibration support.
- Remove emi.h because sdram_size() is already declared in
common/include/soc/emi.h.
- Add dramc_param.h and dramc_soc.h to prepare for implementation of
DRAM full calibration.
TEST=build pass
BUG=b:233720142
Signed-off-by: Xi Chen <xixi.chen@mediatek.com>
Change-Id: I2f88d971fe861cbd09cc86c8a5a1fb531bfe78d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch disables LID based shutdown requests.
Google/Rex platform receives a forced shutdown request while
booting to depthcharge due to EC wrongly detecting the LID is being
closed.
For now disable the LID based shutdown behaviour in depthcharge unless
the EC issue gets resolved.
BUG=b:243920003
TEST=Depthcharge no longer sees the force shutdown request now.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I03e33ea4d04dc48331d1cf98c47786b2a184c258
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
PNOT() should be called when the battery status changes, to give the SOC
an opportunity to handle it. This is in preparation for the low/no
battery boot changes.
This CL also updates the PNOT() comments to better match the name of the
function and why it's called.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Change-Id: I8b74313d242fd4959315a67579eb6c5f49a31a76
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66993
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Clear the SMBIOS region before writing SMBIOS tables.
On librem_mini and librem_mini_v2, CBMEM allocations are offset by 4K
for reboots relative to the cold boot. This means the unused SMBIOS
region could contain the first 4K of the ACPI tables from the last boot
(including the signature), which prevents Linux from booting.
The CBMEM 4K offset appears to be due to FSP allocating memory
differently between cold boot and reboot, this appears to be normal and
causes the CBMEM base address to change.
It is not clear why Linux examines an ACPI signature found in this
region, but boot logs over serial confirm that it sees the corrupt
table. The table is supposed to be found just below 1M, and kernel
source appears to look in this region, but it is definitely finding the
corrupt table in CBMEM.
Normal cold boot:
[ 0.008615] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4)
[ 0.008619] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008624] ACPI: FACP 0x0000000099B4A2A0 000114 (v06 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008634] ACPI: DSDT 0x0000000099B48280 00201F (v02 COREv4 COREBOOT 20110725 INTL 20220331)
...
Reboot with corrupt table:
[ 0.008820] ACPI: RSDP 0x00000000000F6190 000024 (v02 COREv4)
[ 0.008823] ACPI: XSDT 0x0000000099B480E0 00005C (v01 COREv4 COREBOOT 00000000 CORE 20220331)
[ 0.008828] ACPI: ???G 0x0000000099B4A2A0 20002001 (v00 ?G?$ 47020100 ?, 47020100)
[ 0.008831] ACPI: �y 0x0000000099B4A3C0 54523882 (v67 ?_HID? A�? 65520D4E al T 20656D69)
...
There are no specific errors but it returns to the firmware soon after,
presumably due to a fault. This appears to be so early in the boot
that panic=0 on the kernel command line has no effect.
Test: build/boot Librem Mini, Librem Mini v2 and reboot.
Change-Id: Ia20d0b30160e89e8d96add34d7e0e881f070ec61
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66377
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add FW_CONFIG probe for new audio sku:
ALC5682I + MAX98357
BUG=b:243474931
TEST=Boot to OS and verify audio devices are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I16af6cf4644c473034e184e95ff2038ca31b20de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67016
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as
per MTL processor EDS.
TEST= Able to build and boot RVP.
Confirmed TME supported mode detected via temporary debug prints and MSR 0x9ff indicates activated.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Id368925504d81025239e94698d2cb0e2266a5a96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66949
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:239670216
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ibc7116e8dc5367fd94d29aba36b91778d0c21e4f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
The offset for Max Charge is located at 0x1a, so correct this in the
definitions and EC memory ACPI.
Change-Id: I92cc452d1189e62db78aed787f2de65fd5096564
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Follow the "619907 Alder Lake-S and Raptor Lake-S Platform" and "685472 Intel® Dynamic Tuning Technology (Intel® DTT)" to override tdp pl1 in 15w cpu MSR to 55w and in 28w cpu MSR to 64w.
BUG=b:236294162
TEST=emerge-brask coreboot and check MSR_Package Power Limit-1 in 15w and 28w CPU is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Icb3d7c72b672fbd3e2a9f7ad1f2d1cb2ffc798c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66910
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This register has a 1MiB granularity. The lowest bit is a lock bit.
Change-Id: I688cb7818fc849784026ca0bc6acb7ef1ae92133
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66256
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The define GPIO_PCH_WP needs to be mapped to GPP_H10 based on
the Rex schematics 24/6/2022.
TEST=Built and booted on Google Rex.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I2489c244bd4cbd9e10ed3db981a6e56a954b5e20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67083
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The define EC_SYNC_IRQ needs to be mapped to A17 based on
the Rex schematics 24/6/2022.
BUG=b:243781237
TEST=Successfully build rex and tested to ensure EC is now functional.
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ib61ddc9f73dd7b817d3b990bef8f0169f7cafbcd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67082
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
This change provides access to IOE through P2SB Sideband interface for
Meteor Lake TCSS functions of pad configuration and Thunderbolt
authentication. There is a policy of locking the P2SB access at the end
of platform initialization. The tbt_authentication is read from IOM
register through IOE P2SB at early silicon initialization phase and its
usage is deferred to usb4 driver.
BUG=b:213574324
TEST=Built coreboot and validated booting to OS successfully on MTLRVP
board. No boot hung was observed.
Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8dcee90080c6e70dadc011cc1dbef3659fdbc8f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66951
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors p2sb_execute_sideband_access() to be able to
handle SBI operations in both SMM and non-SMM scenarios.
Prior to FSP-S operation being done, the IOE P2SB device will be
visible on the PCI bus hence, performing the SBI operation using IOE
P2SB doesn't involve unhide/hide operation.
Post FSP-S, the IOE P2SB device is hidden.
Additionally, SBI operations can't be performed as is. The only
possible way to send SBI is inside SMM mode and to do that, coreboot
needs to unhide the P2SB device prior to sending the SBI and hide
it post sending SBI.
As a result, the p2sb_execute_sideband_access() function has been
refactored to manage these cases seamlessly without users of the
p2sb_execute_sideband_access() actually being bothered about the
calling mode.
BUG=b:239806774
TEST=Able to perform p2sb_execute_sideband_access() function call in
both SMM and non-SMM mode without any hang/die.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iafebd5190deb50fd95382f17bf0248fcbfb23cb8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Only 16 MByte of the SPI flash can be mapped right below the 4 GB
boundary.
In case of a larger SPI flash size, still only the 16 MByte region
starting at 0xff000000 can be configured as WRPROT and be reserved for
the MMIO mapped SPI flash region. The next 16 MByte MMIO region starting
at address 0xfe000000 contain for example the LAPIC MMIO region, the
ACPIMMIO region and the UART/I2C controller MMIO regions which shouldn't
be configured as WRPROT. Reserving this region for the MMIO mapped SPI
flash would also result in an overlap with the MMIO resources mentioned
above.
In the case of a smaller SPI flash, reserving the full 16 MByte flash
MMIO region makes sure that the resource allocator won't try to put
anything else in the lower parts of the 16 MByte SPI mapping region.
To avoid the issues described above, always reserve/cache the maximum
amount of 16 MBytes of flash that can be mapped below 4 GB.
TEST=On boards with 16 MByte SPI flash chips, the resulting image of a
timeless build doesn't change with this patch. Verified this on Chausie
(Mendocino), Majolica (Cezanne), Cereme (Picasso) and Google/Careena
(Stoneyridge). On Mandolin (Picasso) with an 8 MByte flash, the
resulting image of a timeless build is different, but neither the
coreboot console output nor the Linux dmesg output shows any errors that
might be related to this change.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie12bd48e48e267a84dc494f67e8e0c7a4a01a320
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66700
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the poweron state of some of the WWAN GPIOs is the
asserted state, this patch fixes the poweron sequence so that the
WWAN module is always correctly powered on, in both cold and warm
reboot scenarios.
BUG=b:233564770
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I4ec8312c30392b9ca0a3e0321cb4578e76ec5787
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Hook up Lp5CccConfig FSP UPD for Intel MeteorLake.
BUG=b:243734885
TEST=Built and booted on Google Rex. Verified the UPD value in MRC log.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3d7ff8e08546f06cf7807ee825cfef84c14a6c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67052
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Hook up ECT FSP UPD for Intel MeteorLake.
BUG=b:243734885
TEST=Built and booted on Google Rex. Verified the UPD value in MRC log.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idc23717c3ce52e3635e2da41733058f912545e5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67051
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik Vaghela <maulikvaghela@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch resolves the SoC programming dependency order where enabling
extended bios support requires MCHBASE to be enabled.
BUG=b:243693375
TEST=Able to boot from RW-A slot which is mapped to extended BIOS range.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8bd9c3d3fb5e82e34f2d6af8548452c744d4b3c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67046
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch configures GPP_E03 (GSC_SOC_INT_ODL) as GPI/APIC in early
GPIO tables.
BUG=b:243641061
TEST=Able to build rex image.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I4aa180c7105be3f356a0bbd5b92b4ced628c34fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67017
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Voltage set based on standard configuration for each type.
TEST=build/boot google/skyrim, verify output in cbmem console log,
DMI type 17 table.
Change-Id: I9b1e68a9417e43cbb9c55b4c471664f3f9090342
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66981
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the frequency field is deprecated, print the max/configured MT/s
speeds instead.
TEST=build/boot google/skyrim, verify output in cbmem console log
Change-Id: Icee5af762ca37c3b2ec8c9a52a7f32fb848390b0
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Hook up newly-added method to convert from frequency to MT/s so that
boards which use (LP)DDR5 report their capability properly.
BUG=b:239000826
TEST=build/boot google/skyrim, verify SMBIOS Type 17 table reports
DRAM speeds correctly.
Change-Id: I694b6c227a8d8fb40c897053808bc79df330ed0c
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66954
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
As the frequency field in the SMBIOS type 17 table is deprecated,
we need to provide the maximum and configured speed in MT/s. Add
a method to convert from frequency to MT/s using a lookup table.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I0402b33a667f7d72918365a6a79b13c5b1719c0d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Create the morthal variant of the skyrim reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:240970782
BRANCH=None
TEST=util/abuild/abuild -p none -t google/skyrim -x -a
make sure the build includes GOOGLE_MORTHAL
Signed-off-by: Moises <moisesgarcia@google.com>
Change-Id: I25c25f067a040e6930f4fc60fadb8be85dc8eda6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Update the build script to check if SPD exists, and only if SPD exists
the APCB_SBR_D5.gen could be executed.
BUG=None
TEST=Build
Change-Id: Ib7b977a89d403242e8bb1f684269e70082125e88
Signed-off-by: Isaac Lee <isaaclee@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66978
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Now that the GPU CLKREQ# signal is working correctly, ASPM L1 substates
can be enabled and appear functional.
BUG=b:240390998
TEST=lspci reports them as functional, MODS does not hang
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I8297f6bbf7f5a1f7d4ac519bc5b7b3112a74a9a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66811
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converge as many of the GPU's GPIOs to use PLTRST# as the reset signal
explicitly, as the hardware engineers requested this.
BUG=none
TEST=boot and reboot agah, dGPU still visible on PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I78e58eb17cadc95083571affbecb4e1ce0adf16a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66809
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The agah EC code will monitor adapter current to choose corresponding
DPTF oem variable table. When it changes, this event will send to the
ACPI FW through host event and then pass onto the DPTF kernel driver.
This patch adds support for that feature.
BUG=b:238921409
TEST=add Printf() calls to the ACPI,
and check these Printf() will show up in the kernel log
when EC send oem variable table change notify.
Change-Id: I1dbbfd9b3d65b56d77050c9ba9957e54530c3a0e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66574
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch brings INTEL_TME config check prior programming
TME Set Activation Core MSR on all cores.
TEST=Able to boot Google/Taeko to OS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8af7e305da1050f443929ab33be556e713e53e9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66976
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the P2SB so that the SPI is discoverable by the OS.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c12161d4868deae5b8900cfa2f42517a9f0b7e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch implements EFI_PEI_MP_SERVICES_PPI structure definitions
with APIs that return mp_api_unsupported().
The reason behind this change is to fix an FSP issue where FSP assumes
ownership of the APs (Application Processors) upon passing a `NULL`
pointer to the CpuMpPpi FSP-S UPD.Hence, this patch implements
`MP_SERVICES_PPI_DEFAULT` config to fill EFI_PEI_MP_SERVICES_PPI with
`mp_api_unsupported` APIs.
Later this data structure can be passed to the CpuMpPpi UPD to avoid
APs from getting hijacked by FSP while coreboot decides to set
SkipMpInit UPD.
TEST=Able to build and boot Google/Taeko with this patch.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I31fcaa2aa633071b6d6bfa05dbe891ef87978d2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
BIOS must send the IP_LOAD HECI command to fetch the firmware for CPU
PCIe Gen5 and upload it via CPU REG BAR prior FSP Silicon Init.
Implementation based on public Slimbootloader's
"Silicon/AlderlakePkg/Library/CpuPcieHsPhyInitLib".
TEST=Boot MSI PRO Z690-A and see the HSPHY FW is loaded.
PCIe x16 Gen3 GPU card started working in the PCIE 5.0 slot.
[DEBUG] HECI: Sending Get IP firmware command
[DEBUG] HECI: Get IP firmware success. Response:
[DEBUG] Payload size = 0x6944
[DEBUG] Hash type used for signing payload = 0x3
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I6c6c11581e3d3d9bab0131fae6ef487cafe98080
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This enables SOC_INTEL_COMMON_BLOCK_GPIO_PMODE_4BITS to support 4 bits
GPIO pad mode to configure native function 8 to 15.
BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ibf4b13a3d19095d15bf857c7fe4ec0affb54a4e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66391
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Intel GPIO pad supports 4 bits pad mode, PAD_CFG_DW0[13:10] for pins
that native function 8 to 15 is assigned. This adds native function
definitions from NF8 to NF15 and updates PAD_CFG0_MODE_MASK to support
4 bits pad mode configuration.
Since PAD_CFG_DW0[16:13] is reserved for pins that NF8 or higher is not
assigned, this change would not cause an issue but Kconfig option is
added to minimize an impact and support 4 bits pad mode configuration.
BUG=b:239690757
TEST=build and verify pad mode configuration with Meteor Lake mtlrvp
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Iefd2daa92a86402f2154de2a013ea30f95d98108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This comment header is necessary for supporting propagation of overrides
to variants.
Change-Id: Iee92fa4fbc4851c7032401cff99ea49f87717c7f
Signed-off-by: Kevin Chowski <chowski@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
fix the following checkpatch errors:
WARNING:BRACES: braces {} are not necessary for any arm of this statement
354: FILE: src/arch/x86/smbios.c:354:
+ if (CONFIG_ROM_SIZE >= 1 * GiB) {
[...]
+ } else {
[...]
WARNING:BRACES: braces {} are not necessary for single statement blocks
561: FILE: src/arch/x86/smbios.c:561:
+ if (leaf_b_threads == 0) {
+ leaf_b_threads = 1;
+ }
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I14c29e4358cad4cd5ef169ebab7079db2129d8fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Synchronize with AGESA/AgesaModulePkg/Include/MemDmi.h.
Add/correct values for DDR5, LPDDR5, LPDDR5X.
BUG=b:239000826
TEST=Build and verify with other patches in train
Change-Id: I127f21bfe2dfcd7794eb543185ea3fb362ff3914
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add a new skolas variant, which is a variant of brya's skolas
baseboard.
BUG=b:242869976
BRANCH=firmware-brya-14505.B
TEST=none
Change-Id: I7f9f0389d8b1bf75d8652cbcc9d0c15d3a529802
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch runs `set_tme_core_activate()` on all CPUs (BSP+APs) as
per Alder Lake Processor EDS.
TEST= Able to build and boot Google/Redrix.
Dumping MSR 0x9FF on all logical processors shows zero value being
set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I130480d4fba413d47d0d0137932ec1fb041a88d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66753
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements API to program TME core activation MSR 0x9FF.
Write zero to TME core activate MSR will translate the
TME_ACTIVATE[MK_TME_KEYID_BITS] value into PMH mask register.
Note: TME_ACTIVATE[MK_TME_KEYID_BITS] = MSR 0x982 Bits[32-35]
TEST=Able to build and boot Google/Redrix.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I48cf8e255b294828ac683ab96eb61ad86578e852
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Firmware is typically delivered as one large binary image that gets
flashed. Since this final image consists of binaries and data from
a vast number of different people and companies, it's hard to
determine what all the small parts included in it are. The goal of
the software bill of materials (SBOM) is to take a firmware image
and make it easy to find out what it consists of and where those
pieces came from. Basically, this answers the question, who supplied
the code that's running on my system right now? For example, buyers
of a system can use an SBOM to perform an automated vulnerability
check or license analysis, both of which can be used to evaluate
risk in a product. Furthermore, one can quickly check to see if the
firmware is subject to a new vulnerability included in one of the
software parts (with the specified version) of the firmware.
Further reference:
https://web.archive.org/web/20220310104905/https://blogs.gnome.org/hughsie/2022/03/10/firmware-software-bill-of-materials/
- Add Makefile.inc to generate and build coswid tags
- Add templates for most payloads, coreboot, intel-microcode,
amd-microcode. intel FSP-S/M/T, EC, BIOS_ACM, SINIT_ACM,
intel ME and compiler (gcc,clang,other)
- Add Kconfig entries to optionally supply a path to CoSWID tags
instead of using the default CoSWID tags
- Add CBFS entry called SBOM to each build via Makefile.inc
- Add goswid utility tool to generate SBOM data
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Icb7481d4903f95d200eddbfed7728fbec51819d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch removes the static kconfig being used to fill in TME enable
FSP UPD. Instead use`is_tme_supported()` and `CONFIG(INTEL_TME)` to check
if the CPU has required TME support rather than hardcoding.
TEST=FSP debug log shows `TmeEnable` UPD is set appropriately for the
TME-supported CPU SKUs.
As per FSP-M debug log:
Without this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x1
With this CL, Alder Lake-P CPU SKU without TME support:
[SPEW ] TmeEnable = 0x0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8aa2922baaf2a49e6e2762d31eaffa7bdcd43b0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66750
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reading firmware_version register is supported on Ti50 version
0.22.4. Therefore correct the help text of the Kconfig option
TI50_FIRMWARE_VERSION_NOT_SUPPORTED.
Also change the message level to BIOS_WARNING.
BUG=b:234533588
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I66a0ef896c9dc4cd0f586555a55dbcd1cfd863f9
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66906
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
1. Moved CHROMEEC_* to common (required for all boards)
2. added missing EC_GOOGLE_CHROMEEC_SKUID
TEST=Verified with simics on RVP
Change-Id: I26a01e5d1c78d4cd83b1aa53e68b2c3059da6061
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66762
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per the Alder Lake FAS coreboot shall detect the existence of TME
feature by running the CPUID instruction:
CPUID leaf 7/sub-leaf 0
Return Value in ECX [bit 13]=1
If TME is supported then only access to TME MSRs are allowed otherwise
accessing those MSRs would result in GP#.
TEST=Able to detect the existence of TME feature across different
Alder Lake and Meteor Lake CPU SKUs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibd4fcf15a66d27748ac7fbb52b18d7264b901cd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66749
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The `INTEL_TME` Kconfig option has a prompt, which means it is meant to
be user-configurable. However, it has been selected from Alder Lake and
Meteor Lake Kconfig, so `INTEL_TME` cannot be disabled on them. Replace
the `select INTEL_TME` statements with default values in order for this
option to be user-configurable on all platforms that support it.
Change-Id: Ib37c108fcc1004840b82be18fd23c340a68ca748
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66756
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This reverts commit 2b19d547c0.
A power and performance analysis performed on Alder Lake demonstrated
that with an EPP (Energy Performance Preference) at 50% along with
EET (Energy Efficient Turbo) disabled, the overall SoC performance are
similar or better and the SoC uses less power.
For instance some browser benchmark results improved by 2% and some
multi-core tests by 4% while at the same time power consumption
lowered by approximately 7.6%.
BUG=b:240669428
TEST=verify that EPP is back to the by default 50% setting
`iotools rdmsr 0 0x774'
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I76d3914e51c5320af4c202558e1e7c57b7c0de54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-by: Usha P <usha.p@intel.com>
Enable DPTF oem_variables and override based on CPU match id.
BUG=b:236294162
TEST=emerge-brask coreboot and check the value in odvp0 is correct.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Ic935ec42f4de0cbec996da37b44f354978fe4b62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66907
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
bypass power
Add FW_CONFIG probe to separate ext fivr settings for Pujjoteen
and others(Pujjo and Pujjoflex)
BUG=b:242663554
TEST=Boot to OS and verify that ext_fivr_settings are set based on
fw_config.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I6bb6d1701c55459cf331dd2f3ffe07f91bca2fa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The current reset delay is not enough to make touchscreen IC ready,
ILITEK feedback their requiremt is 400ms in spec T2.
After changing the reset_delay_ms and check touchscreen works,
ILITE also change the IRO to low level trigger.
This CL is to reflect that.
BUG=b:235929123
BRANCH=firmware-dedede-13606.B
TEST=check touchscreen function work
Change-Id: I126b2d74c1d7a1799e2f67a8ab01cba074447c06
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Disable INTEL_LPSS_UART_FOR_CONSOLE to stop debug output on UART 2.
This decreases boot time on all boards by around 60%.
TGL before:
Total Time: 10,110,807
TGL after:
Total Time: 3,851,641
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8f8d5cd46e87e7dafe0669b4a29c872b1789eb60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The ALC269 does not support the hardware equaliser, so remove the
entries related to this, as they have no effect.
Revert to the ALC269 defaults which work correctly with Linux. This
also corrects the subsystem id from 0x10ec111e to 0x10ec10d0.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I82647f67730ec344591f7dbd759a421c116d4fdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add ELAN touch support
BUG=b:243120074
TEST=emerge coreboot and check ELAN touch screen is workable
Change-Id: If30232b3da9af0015d6d87535b53f905c5a30bcb
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66912
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Isaac Lee <isaaclee@google.com>
smn_read32 is used in this file, so include the header file with the
function prototype so that the file compiles successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5bef96cd08f22b3475e8b5ba4e984a6e1ab4da36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Since the I2C controller is part of the FCH, move the early
initialization from bootblock.c to early_fch.c which also matches what
the newer AMD SoCs do.
TEST=Successfully boots on google/liara and all I2C/cr50/TPM functions
appear to work properly
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22d3a8888eaa34ea612da719c408c0083769e806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66866
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The functionality of sb_enable_lpc is implemented in the common LPC
support code as lpc_enable_controller. This gets called by the common
lpc_early_init which also calls lpc_disable_decodes and lpc_set_spibase.
The lpc_set_spibase call was already done in bootblock_fch_early_init,
so the main change in code behavior is that now lpc_disable_decodes gets
called during early FCH initialization. The lpc_enable_port80 and
sb_lpc_decode calls after the lpc_early_init code will reenable some of
the decodes.
TEST=Successfully boots on google/liara, cbmem and dmesg logs look clean
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia58a6f609fa149a6c09ed99f08bdc4f05eb56f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66841
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI config space of the SMBus device has a secondary mapping as an
ACPIMMIO bank. Since the PCI device is on bus 0, it's already available
early in boot after the enable_pci_mmconf call, so there's no need to
use the ACPIMMIO mapping instead of the PCI config space mapping.
Verstage on PSP could theoretically access the PCI config space via the
0xcf8/0xcfc register pair, but since verstage on PSP doesn't have the
ACPIMMIO mapping anyway, we won't loose any functionality here.
Change-Id: I5c8ce8de0a6ab0ed41e7e8a5980d0f0510aaa993
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
GLKs chipset configures the devices, so use these aliases and remove
the entries when they are identical.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic29e5305346c3b7fbf66b027754a9ddd16b16269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66195
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF Policy and temperature sensor values from thermal team.
BUG=b:242797681
TEST=build FW and boot to OS.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4365f87843a4408ae457e7ef27291fdaa0d5bde
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66827
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N.
Boot time data:
Before:
* 955:returning from FspSiliconInit 956,832 (110,268)
After:
* 955:returning from FspSiliconInit 944,528 (74,213)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I05d226fb5f05463341358cd20655f06376778bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change is to skip sending the MBP HOB since coreboot doesn't
use it and also helps to reduce the boot time by ~40msec on ADL-N
variants.
Boot time data:
Before:
* 955:returning from FspSiliconInit 1,231,364 (117,051)
After:
* 955:returning from FspSiliconInit 1,198,221 (79,497)
BUG=b:241850107
TEST=Verified that boot time is reduced by ~40msec and also S0i3
is working.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iaeaa8bcdf8467fdd467a10a98dd7582e8e0b067c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Only ADL-N FSP has the required support to skip the MBP HOB and
enabling it is saving the Boot time.
BUG=b:241850107
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iddeb2c652fac9513b14139d6f732d333bbb989d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The infrastructure for selecting an appropriate firmware image to use
the right descriptor is now ready so runtime descriptor updates are no
longer necessary. Since the different descriptor builds split along
HDMI/USB-C lines for nereid, a single VBT file can be used for each,
removing the need for runtime VBT selection as well.
BUG=b:229022567
TEST=Nereid type-C and HDMI outputs work as expected
Signed-off-by: Sam McNally <sammc@chromium.org>
Change-Id: Idf1fbd6c26203adbda002dec3f11e54a7b9f9b82
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Split `gpio.h` into `gpio_early.c` for bootblock and `gpio.c` for
ramstage to match other System76 boards.
Change-Id: I24398ad459754ac80d92d70687ab70b22894a01c
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit feb551a92550fcc28b32aca77117aa743018b233.
Adding new variant "pazquel360" is not needed.
BUG=b:239599467
TEST=emerge-trogdor coreboot
Signed-off-by: chaogui@google.com
BRANCH=none
Change-Id: I4878d3a54f96fb9d38f2da1a1c918dfdef80a301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66805
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DPTF Policy and temperature sensor values update from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I45b4f80cbec0723c63ac7fc7176e13ae5a2b54c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66365
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Debian 11 reports ´0:6:0 can´t derive routing for PCI INT D´.
Use FIXED_INT_PIRQ for INT D to PIRQ routing table.
BUG=NA
TEST=Boot Debian 11 on Siemens AS_TGL1 and verify no PIRQ error message
in ´dmesg´
Change-Id: If38c7b6f664e0f6533e583ce62504281a4092720
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch adds support for turning the PCIe SRCCLK# on and off during
RTD3 (just like the soc/intel/common/block/pcie/rtd3 driver).
TEST=GC6 and GCOFF sequences still work
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4b369cfcc7245a1c212fa65f65fdab542f60e196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
For board revs 3 and later, the PG pin for the NVVDD VR moved from
GPP_E16 to GPP_E3. To accommodate this, the DSDT contains a Name that
this code will write the correct GPIO # to depending on the board rev,
and we'll use that instead.
BUG=b:239721380
TEST=still works on board rev 2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I11aec6069da8e086789419303871c6d0f5fb29af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
spm_set_power_control() is already called in spm_init(). It is not
necessary to call spm_set_power_control() again in the mtk_mcu reset
callback.
TEST=check SPM PC value (0x250) after SPM is loaded.
[INFO ] SPM: spm_init done in 54 msecs, spm pc = 0x250
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Change-Id: I7ee517e1eb6485c52155a69d05781a61ddfe4cad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66785
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify GPP_D17 setting for SD_WAKE_N.
BUG=b:242647845
TEST=Build and boot on pujjo
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Iacd89d27174869e34c48d1f62793ddc45b43f3f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
The DPTF power participant device needs to be notified when power
source changes so it can re-evaluate power source and power source
change count, this can be later used by DPTF along with methods
provided by EC.
Corresponding changes in EC are https://crrev.com/c/3545778 and
https://crrev.com/c/3547317
BUG=b:205928013
TEST=Build, boot brya0 and dump DSDT to check change
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I07f58b928a0dba92bec3817177142c586e5014b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This is sort-of reverts commit cbf290c692 ("soc/amd/sabrina: drop
CPPC code"), since it turned out that the CPPC feature is supported
on Sabrina (now Mendocino) despite this being missing from the
documentation I looked at when writing the patch referenced above.
Since the CPPC ACPI code generation functionality has been moved to
common code, this isn't a direct revert.
BUG=b:237336330
TEST=None
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1c059653eeae207d723c77e8a78b19c86e362296
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch provides a mitigation path for having different size SPINOR
parts across Rex board revisions. Rex Proto 0 only has 64MB SPINOR
mounted on the board, and the plan is to use 32MB later with Proto 1
onwards.
Hence, the idea here is to maintain a 32MB SPI Flash layout across all
Rex board revisions, but the Proto 0 build only selects
BOARD_ROMSIZE_KB_65536 config for adding padding at the end of the
32MB range.
BUG=b:242825380
TEST=Able to create 64MB AP Firmware for Rex with below layout:
SI_ALL: 0-9MB
SI_BIOS: 9MB-32MB
Padding/Unused: 32MB-64MB
Additionally, able to hit CPU reset on MTLRVP (has 64MB SPINOR) with
Rex AP Firmware binary.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcc2206456639ef4ff22e0c4069521e583be58cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66828
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently, to enable/disable LTE based on fw_config on nissa, we have
two sets of GPIOs: lte_enable_pads and lte_disable_pads. This was to
prevent the SAR interrupt pin GPP_H19 from floating for the short period
of time between enabling it in gpio.c and disabling it in fw_config.c
(see CB:64270 for more details).
With the new pad-based GPIO overrides (CB:64712), this is no longer an
issue since the gpio.c and fw_config.c overrides are applied at the same
time. So simplify the LTE GPIO configuration by enabling all the LTE
pins in the variant gpio.c, then disabling them in fw_config.c if
needed.
BUG=b:231690996
TEST=LTE still works on nivviks
Change-Id: I5bf20a027414ea5e7c1f198d69e355c76f467244
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66776
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the SoC that was upstreamed as Sabrina was finally renamed to
Mendocino, also adjust the abbreviation used for the DXIO/DDI descriptor
struct array names.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I14ecf98e4a94376a70e783774c8f7b8701581220
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66815
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The flag EC_BATT_FLAG_CUT_OFF was added with the CL:
3704470: battery: Set battery cutoff flag
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3704470
This flag is set in the ACPI memory mapped area when the command
`ectool batterycutoff` is issued so ACPI code can respond
appriopriately. This CL adds the flags to coreboot ACPI.
BRANCH=none
BUG=b:217911928
TEST=Boot nipperkin with low & no battery
TEST=Boot skyrim with low & no battery
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I4e63ff4fc2d6b0ecf767a6bffd81f823c74c15bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66803
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I added this header in commit a6c8b4becb
(nb/intel/sandybridge: Rewrite get_FRQ). Relicense it as "BSD-3-Clause
OR GPL-2.0-or-later" and move it into the BSD-licensed commonlib part.
Change-Id: I89ebdcdf8d06e78e624e37a443696981b3b17b7d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66711
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the Shadow Registers from 2 through 5 and print information
from them accordingly. All values were taken from Intel document
number 571993.
Tested on the StarLite Mk III and the correct values are
shown:
[DEBUG] CSE: IBB Verification Result: PASS
[DEBUG] CSE: IBB Verification Done : YES
[DEBUG] CSE: Actual IBB Size : 88
[DEBUG] CSE: Verified Boot Valid : FAIL
[DEBUG] CSE: Verified Boot Test : NO
[DEBUG] CSE: FPF status : FUSED
Please note, the values shown are in an error state.
This replaces the Fuse check that is done via Heci, as this will only
work whilst the CSE is in a normal state.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8a9e7b329010fae1a2ed9c3fefc9765e617cdfe4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
coreboot is unable to disable certain devices, whilst many are hidden
DPTF and SMBus are not. Set this to enabled chipset so that it is
enabled by default.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I85d74179b6fe3c6126566422f82f7b806f80d0c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add supported memory parts in mem_parts_used list, and generate SPD ID
for these parts.
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 0 (0000)
H58G56AK6BX069 2 (0010)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:242277219
BRANCH=None
TEST=run part_id_gen to generate SPD id
Change-Id: I46c168482113beb7cd28f387ed495847aba8602f
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Create the yaviks variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:242277219
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_YAVIKS
Change-Id: Id60fe0e54a8e0196a302141f58c6695779ac251a
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Build error for platforms using Intel FSP for TGL_IOT (FSP_TYPE_IOT). File FirmwareVersionInfoHob.h does not exist in Intel FSP TGL IOT package.
File FirmwareVersionInfoHob.h is included when DISPLAY_FSP_VERSION_INFO is enabled. Enable this config for non TGL_IOT only.
BUG = NA
TEST = Verify that DISPLAY_FSP_VERSION_INFO is disabled by default for TGL_IOT
configuration (Build Siemens AS_TGL1).
Change-Id: Ief5a7222daf6f1658e8dc04f97b4ddc2bcb74905
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66636
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mendocino has more eSPI decode ranges than Picasso or Cezanne. To
support these additional ranges, introduce a new Kconfig option
SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES that can be selected by
the SoCs that support the additional eSPI IO/MMIO decode ranges.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib761cdf201c35805d68cf5e8e462607ffd9fa017
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add GPIO configuration and device tree to enable the chip.
BUG=b:240607130
BRANCH=firmware-brya-14505.B
TEST=Patch linux with NXP's pending drivers
UWB device is probed and can respond to a simple hello packet
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I83be712d243c365a5cbfe6f69a6bd85440c5bec7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The patch updates the comments on return values and heci_reset()
triggering during error scenarios of heci_receive() and heci_send()
functions to reflect the current implementation.
Test=Build the code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I6c6c3312602c772147cb315db9ea1753d84a0fb3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
- Set FastPkgCRampDisable VCCIA and VCCGT to 1
- Set pre-wake randomization time (DPA) to 100
BUG=b:241349500
TEST=build FW and checked fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Id4a1540de8c3ee74695631acc8181dcc446fe137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66783
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add FW_CONFIG probe based on pujjoteen boxster of below devices:
LTE, SD card, stylus, WFC camera, AUDIO
BUG=b:236158122
TEST=Boot to OS and verify that above devices are set based on
fw_cofnig.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I49fc5461e7affba68a6b89bf166c84598fbfa088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66741
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ghost has two amps and address are 0x3c and 0x3d.
BUG=b:231581723
BRANCH=firmware-brya-14505.B
TEST=max98396 driver can get the DSD property correctly.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3b6a331ca42e97f984f3a585726c02452bb067f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mac Chiang <mac.chiang@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
