Commit Graph

3469 Commits

Author SHA1 Message Date
Kyösti Mälkki 005028e0a9 AGESA: Add agesawrapper_post_device()
NOTE: The procedure is moved across a collected timestamp
TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
for in an earlier entry in cbmem -t output.

Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6132
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:47:48 +02:00
Kyösti Mälkki e1b468e1a7 AGESA boards: Use acpi_s3_resume_allowed()
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.

We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.

Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:46:50 +02:00
Kyösti Mälkki 23b4f0c734 AGESA boards: Add prepare_for_resume()
Use one common implementation for all AGESA platforms.

Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6084
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03 09:45:58 +02:00
Dave Frodin 2093c4f7c2 AMD/agesa: Add functions for AMD PCI IRQ routing
Port the changes that were made in amd/cimx to amd/agesa
as were done in:
   commit c93a75a5ab
   Author: Mike Loptien <mike.loptien@se-eng.com>
   Date:   Fri Jun 6 15:16:29 2014 -0600

      AMD/CIMx: Add functions for AMD PCI IRQ routing

This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.

Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-02 21:47:28 +02:00
Kyösti Mälkki faaa253660 amd/persimmon jetway/nf81-t56n-lf: Fix whitespace and alignment
Change-Id: I76f017b0919e301eeb84e73eff21170bbc921ae2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6113
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:35:26 +02:00
Kyösti Mälkki 8f87c3f397 AMD boards: Fix typos
Change-Id: If1dc4fd2204a2e4b6f84c75f385b8ff958d2251d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:31:55 +02:00
Kyösti Mälkki efa8a9dc21 AMD boards: Fix typos
Change-Id: I22180c3c2987396717864f04c59560029d088d53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6111
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:31:19 +02:00
Kyösti Mälkki d874757a4f AMD boards: Fix typos
Change-Id: I92f3877b58d9acaa9578337e66107e9cd9f46043
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6110
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:30:03 +02:00
Kyösti Mälkki 6533b83c82 AMD boards: Fix typos
Change-Id: I090e98fbf28595d3917ef84e19bd6d6742f11b94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6108
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:29:31 +02:00
Kyösti Mälkki 9533d836d7 PIRQ tables: Fix typos
Change-Id: I4d8abe3841378e06515e1b3a8f22d78425d08449
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6109
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-26 20:28:18 +02:00
Martin Roth 0b4b230163 bayleybay_fsp: Switch from EHCI controller to XHCI
- Disable the EHCI controller and enable the XHCI controller.

SeaBIOS has been tested on the board and boots an OS from a
flashdrive at SuperSpeed.
This also enables the top USB port on the 2-port stack, which goes
through a High Speed Inter-Chip port.  The HSIC port is only enabled
through the XHCI device.

Change-Id: Ic3dfc55028fa5e081a30819fe9596b1a9f57fd9c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6106
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
2014-06-26 01:32:28 +02:00
Kyösti Mälkki e3c65b97b4 gm45 boards: Switch to use DYNAMIC_CBMEM
Change-Id: Id19d31a2d114bb796b31ad61802d40c8608e4020
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6038
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:04 +02:00
Kyösti Mälkki 502e1dc7ca nehalem boards: Switch to use DYNAMIC_CBMEM
Change-Id: Ie4df2199e746de58c926f35bc9000752d399aa37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:03 +02:00
Kyösti Mälkki 6455b01fe1 i945 boards: Switch to use DYNAMIC_CBMEM
Change-Id: I1bbcba086f841a90544b827ae807a3c351d19d21
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6036
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:02 +02:00
Kyösti Mälkki 56bd2005e6 emulation/qemu: Switch x86 to DYNAMIC_CBMEM
Change-Id: I00055064003c814b86fd1400d50bfd02fdfdf475
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6035
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:12:00 +02:00
Kyösti Mälkki d9cf38fdcb sandy/ivy boards: Switch to use DYNAMIC_CBMEM
Like with other more recent boards already using DYNAMIC_CBMEM,
the pointer to TOC is no longer stored in GNVS for ACPI.

Change-Id: If2e11294202c40793ec985e2c0c006bbfcd03d3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6034
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-25 12:11:59 +02:00
Kyösti Mälkki 207880cd11 Declare acpi_is_wakeup_early() only once
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 05:43:18 +02:00
Kyösti Mälkki 206f37043e i945 boards: Drop disabled ram_check() calls
This code would not get enabled just by flipping the options in menuconfig,
also ramcheck() no longer test the range like the parameters would imply.

We should add non-destructive ram_check() on S3 resume path to verify
memory controller configuration has been properly recovered.

Change-Id: Ie4675c4770146c4312cdfbc81afa19f243f90ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6027
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 05:41:40 +02:00
Martin Roth 2c28ee83cb bayleybay_fsp: Add comments for the MMC/SD devices in devicetree
This just adds some additional comments for the EMMC / SD / SDIO PCI
devices in devicetree.

The documentation states that the EMMC 4.1 device shouldn't be used,
but it's available to enable in the FSP.  Because it can be enabled,
I've included it in the devicetree even though its use is discouraged.

Change-Id: I64633fe1908368f69a8d4031aa900b0bceb2189e
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6089
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-23 05:48:34 +02:00
Edward O'Callaghan a173a6255b Remove guarding #includes by CONFIG_FOO combinations
First of many to remove guarding the inclusion of headers based on
CONFIG_ options. This *potentially* could hide issues such as functions
being swapped from under our feet, since different runtime behaviour
could be declared with the function same name and type-signature. Hence,
depending on the header we happen to get may change runtime behaviour.

Change-Id: Ife56801c783c44e1882abef711e09b85b7f295a4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6055
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:07:22 +02:00
Kyösti Mälkki c3ed88636a intel boards: Use acpi_is_wakeup_s3()
Change-Id: Icab0aeb2d5bf19b4029ca29b8a1e7564ef59a538
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6071
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:52 +02:00
Edward O'Callaghan 114f0ee9d4 src/mainboard/google/*/mainboard_smi.c: Remove #include .c's
No need for these.

Change-Id: I1df6e2ef06bd5546a66ee05a15fa2f7c3daf8853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6039
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-06-20 22:36:19 +02:00
Paul Menzel 4c960d4ebe google/link, lenovo/x60: i915io.c: Use define `ARRAY_SIZE`
Change-Id: I8ddd46a573b61eba685efcc15456f288645d214d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5936
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-20 22:29:50 +02:00
Edward O'Callaghan d309eb145d mainboard/jetway/nf81-t56n-lf: Port recent Persimmon changes
Port to recent reference board (AMD Persimmon) changes in commits:

c93a75a AMD/CIMx: Add functions for AMD PCI IRQ routing

Change-Id: I307709bfee554bc64788a973da6d9313ca7c0de2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5882
Tested-by: build bot (Jenkins)
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
2014-06-20 19:54:39 +02:00
Kyösti Mälkki 6722f8da40 sandy/ivy boards: Use acpi_s3_resume_allowed()
Change-Id: I8e0d43293e095c1c76c3cfef1f426737624ea37f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6063
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:51:16 +02:00
Kyösti Mälkki bb805e156a nehalem boards: Use acpi_s3_resume_allowed()
Also update packardbell/ms2290 to match lenovo/x201.

Change-Id: I6bda740cadd81ebe47e57742c507bff322a9fb0e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6062
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:51:04 +02:00
Kyösti Mälkki 12d681b23f intel/i945 gm45: Use acpi_s3_resume_allowed()
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6061
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-20 19:50:50 +02:00
Kyösti Mälkki 3722f3c3f5 supermicro/h8scm: Fix Kconfig
Change-Id: I0ecc3c5a26251f248234244bf305d3e13e41b9e9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6069
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-19 23:05:10 +02:00
Kyösti Mälkki 17290e4b6c intel/bayleybay_fsp: Drop redundant EARLY_CBMEM_INIT
This is implied from DYNAMIC_CBMEM from soc/.

Change-Id: I8cd8c2dff723950377998750377a3168f1f5fc5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6029
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-06-18 23:15:20 +02:00
Edward O'Callaghan c94d73e0e6 mainboard: Clear up remaining SIO_PORT from Kconfig
Push back any board specific values back into romstage.c #defines and
drop any remaining fragments of CONFIG_SIO_PORT in-tree.

Change-Id: Ieb63fb0c2ab1a82b53bafd86686de7b21ac226c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6045
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:27 +02:00
Edward O'Callaghan 401b8accf8 mainboard/amd,lippert: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.

Change-Id: I39eb2d668f1da9f89b7ff6eb219af1a48cb29232
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:21 +02:00
Edward O'Callaghan dfc0c13b1a mainboard/jetway/nf81-t56n-lf: Drop SIO_PORT from Kconfig
CONFIG_SIO_PORT is not used anywhere and should not be here any way.

Change-Id: I2e7be4337f7f46298b9ca5bd613c58deec2cb01a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6043
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-18 21:17:14 +02:00
Kyösti Mälkki a0b4a8d819 ACPI: Remove CBMEM TOC from GNVS
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.

Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-18 20:37:34 +02:00
Kyösti Mälkki aac45febc7 emulation/x86 : Drop HAVE_ACPI_RESUME
S3 resume detection not implemented in romstage.c.

Change-Id: I98277cb483825af2e6c5c8eefa4598b117613478
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6028
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-18 20:30:45 +02:00
Kyösti Mälkki a1e924ca6b mainboard/supermicro/h8dme: Drop unused code
Clang complains about a unused debug function, so remove dead code.
We have copy of dump_smbus_registers() in amdk8/debug.c.

Change-Id: Ibf46deb1de1589d81760841b1d4ba319707915aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5942
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-06-18 20:29:24 +02:00
Mike Loptien cbc783f3e1 Persimmon: Change MPTable to use mainboard IRQ routing
With the addition of the mainboard PCI IRQ routing tables
for AMD Persimmon, the MPTables can be set to use this
information to accurately reflect the real hardware settings
of the system.  Additionally, the IOAPIC gets defined before
the MPTable gets generated so the settings can be read
directly from the IOAPIC registers instead of 'guessing' at
them as was done before.

Change-Id: I96ec046a2208eddf4b5e442214ff43d2a349ca4d
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5878
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-16 18:38:47 +02:00
Edward O'Callaghan f7d8f09d76 amd/agesa,cimx: Rename ACPI OS detection methods
Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.

Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:47:57 +02:00
Edward O'Callaghan 3628f93cf5 mainboard/ibase/mb899: Break out superio hwm conf from mainboard
Break out the PNP Super I/O HWM configuration from mainboard.c

Change-Id: Ib4c7f26c7fa2a9845250a61a23c75cb9e440ab93
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5797
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-06-14 20:42:11 +02:00
Edward O'Callaghan cd30951e32 mainboard/amd: De-ASCIIartify reference boards
For anyone who knows the difference between a header and a variable in C
these depictions are rather useless. Thus, these lines wast essential
screen real estate while working on coreboot.

Change-Id: I7fe55d936c035ef83832716c45bfc57d73c0edc7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5979
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-14 20:32:27 +02:00
Martin Roth d866e5872d fsp_baytrail: Fix CONFIG_ENABLE_FSP_FAST_BOOT
While pushing the fsp_baytrail code, it was requested that we change
CONFIG_ENABLE_FAST_BOOT to CONFIG_ENABLE_FSP_FAST_BOOT.

These were missed in the change.

Change-Id: If8af3f90b0f5cc9154ff1d3a387f442430f42dee
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5972
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-13 18:34:04 +02:00
Paul Menzel 4dfc50b877 mainboard.c: Fix typo in appro*p*riate in comment
Use the following command to fix all occurences.

	$ git grep -l approriate | xargs sed -i 's/approriate/appropriate/g'

Change-Id: I4cbba972bb445c2407ef2e63ffb3068fc948f1c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5987
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-13 09:39:28 +02:00
Martin Roth 41ea7230f7 bayleybay_fsp Kconfig: Remove unnecessary overrides
Use the default mmconf base address and fsp locations.

Change-Id: Ia9116b0f0fc799592df2a10b10e086cfc88b394c
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5982
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-12 20:10:23 +02:00
Mike Loptien c93a75a5ab AMD/CIMx: Add functions for AMD PCI IRQ routing
The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01.  This table is responsible for physically
routing IRQs to the PIC and IOAPIC.  The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.

The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately.  This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts.  It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table.  It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE.  Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.

For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2.  This corresponds to PIN B.  On the
Persimmon mainboard, I want the USB device to use IRQ 11.  I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11.  This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read.  It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.

Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.

Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.

Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-11 17:07:50 +02:00
Kyösti Mälkki f5a2d2607f lippert/toucan-af: Fix comment on HAVE_ACPI_RESUME
S3 resume is expected to work now, however the 3s delay and flash wear
is still there.

Change-Id: I7edbce7bcf9c2160099fd5e371562b1ec63d45d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5971
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-11 15:52:45 +02:00
Kyösti Mälkki 1b6aef754e lippert/frontrunner-af: Fix comment on HAVE_ACPI_RESUME
S3 resume now works, however the 3s delay and flash wear is still there.

Change-Id: I9d2eda5454baf7704807cf67f3aca94a67de3406
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5970
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-06-11 15:52:35 +02:00
Kyösti Mälkki ef9343cac1 AGESA: Use common heap allocator
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:31:31 +02:00
Kyösti Mälkki 6025efa347 AGESA: Use common GetBiosCallout()
Change-Id: I9c8f7cc98c65102486e17ec49fa2246211dffc4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5688
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:52 +02:00
Kyösti Mälkki 83cc3b0ed5 AGESA fam15tn fam16kb: Use shared default callouts
Change-Id: Ibbb07ef308c7e92a8a8dfe066f5e3866d5f8aee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5687
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:38 +02:00
Kyösti Mälkki cb989f2c3c AGESA fam15tn fam16kb: Use common handler for GNB_GFX_GET_VBIOS_IMAGE
Change-Id: I158993bcb654ef27a9fc6b7e9dc3fc955fb740fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5686
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:30:24 +02:00
Kyösti Mälkki bc84450082 Drop unused change_i2c_mux()
Change-Id: I3ac39441746d739ac19e831bb67c76405c24ba27
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-06 07:30:23 +02:00
Edward O'Callaghan f5bde44df2 superio/smsc/kbc1100: Virtually rewrite support and fix mainboards
1. Remove #include .c in romstage.
2. Make romstage component symbols linker-time.
3. Provide header guards and prototypes in superio romstage support.
4. Correct function type-signatures to be static/non-static where
appropriate, avoid 'pretend optimisations' by unnecessarily inlining
functions.
5. Separate out UART enable from various other PNP hard coding

Change-Id: I9b8dad7c02d802e97db73ddf2913d5c6bb33a419
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5916
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-06 01:46:19 +02:00
Edward O'Callaghan fdceb48b36 superio/smsc/smscsuperio: Make romstage linkable with header
Rewrite smsc/smscsuperio romstage component to be more consistent and
provide header there-by removing #include's of early_serial.c's in
mainboard's.

Change-Id: I572e0c76422f09d4de88935a36c0a59e5350e6e0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5915
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:37:57 +02:00
Edward O'Callaghan 6fb379a1db mainboard: Remove #include early_serial.c from w83977tf boards
These non-ROMCC boards #include the model specific w83977tf Super I/O
romstage component. The generic winbond_early_serial() function serves
well here to further tighten integration into the new Super I/O
framework and drop dependence on #include'ing .c files, leaving only
ROMCC boards.

Change-Id: Ib63c0f29f994c54e6112702506f288535799706c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5898
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:36:33 +02:00
Edward O'Callaghan 1b3acb13e4 superio/ite/it8772f: Move towards removing #include .c
Move samsung/stumpy board towards generic romstage component and away
from poorly written hard-coded model specific Super I/O component. This
is an incremental step towards getting obj-level abstraction between
board and Super I/O.

Change-Id: I358c5abef85c2ffa1b7178025cde8834a35b0a51
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5899
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-03 09:35:38 +02:00
Vladimir Serbinenko 12fcb86bba sandybridge: Pass chip info to i915lightup.
Change-Id: I280441aadb0575dc0b99584cdcd48cc76a0289a2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5284
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-02 21:47:39 +02:00
Edward O'Callaghan 9c65978f38 mainboard/ibase/mb899: Trivial, Non-local header treated as local
Change-Id: I5cb496d0d582d3dc5c0c0635f632561f8a3dd853
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5897
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-06-01 13:35:24 +02:00
Vladimir Serbinenko ee62164bb2 lenovo/x201: Fix order of SPI init.
The lock bit for UVSVC/LVSVC was set before both registers were programmed.

Change-Id: I000440db5c8dd2f260ebc1b69108b75621faf7b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5167
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 11:11:26 +02:00
Vladimir Serbinenko 25b55f3d1c lenovo/t60: Implement intel VGA callbacks.
Without it option ROM run results in just a black screen.

Change-Id: Id203f55ca0f02c290a3f40ac1ec7c5f23c5580bf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5344
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 02:16:25 +02:00
Vladimir Serbinenko 63acd22dc5 lenovo: Make version look like something thinkpad_acpi would accept
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.

Not cleaned up as the idea of this patch seems to be met with resistance.
Can make it Thinkpad-specific if the idea is accepted.

Change-Id: I15e33e87e7a7f42d6a06f12fb39b5172153af8a1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4650
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-06-01 01:58:47 +02:00
Edward O'Callaghan 32da8d900e superio/nsc/pc87309: Avoid .c includes in mainboard
Make superio romstage component link-time symbols.

Change-Id: Icde27465a05946498ff7b8f1aaa7a9e8ba074272
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5880
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:18:05 +02:00
Edward O'Callaghan beb0f2631f superio/winbond/w83627hf: Avoid .c includes in mainboards
Move towards the removal of the superio model specific xxx_serial_enable
implementation. Make remaining superio romstage parts link-time symbols
and fix corresponding mainboards to match.

The following mainboards remain unconverted as they are ROMCC:
 - mainboard/supermicro/x6dai_g
 - mainboard/supermicro/x6dhe_g
 - mainboard/supermicro/x6dhr_ig
 - mainboard/supermicro/x6dhr_ig2
and so block the final removal of w83627hf_serial_enable().

Special cases:
 - mainboard/supermicro/h8qme_fam10: Provide local pnp_ sio func
Provide local superio pnp_ programming entry/exit functions as to avoid
making superio implementation global symbols. Although this is not the
proper/final solution, it does mitigate possible symbol collisions and
allow for continued superio refactorisation.

Change-Id: Iaefb25d77512503050cb38313ca90855ebb538ad
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5601
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:17:37 +02:00
Edward O'Callaghan 9068788a8f superio/winbond/w83627ehg: Depreciate romstage component
Part 1/2: These are actually not necessary if Super I/O support is
properly utilized.

Change-Id: I39b621e582f8d0762276d29492c91dce500f0665
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5870
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-31 21:16:39 +02:00
Martin Roth d75800c7f2 intel/bayleybay: Add Intel's Bayley Bay mainboard
Bay Trail-I Platform – Bayley Bay-I Customer Reference Board

The Bayley Bay CRB-I is a dual-channel DDR3L SO-DIMM non-ECC platform.
It is designed to support the Bay Trail-I SoC.

This implementation uses the Intel FSP (Vist the Intel FSP
website for details on FSP architecture and support).
This code does not currently support S3. All other features and IO
ports are functional. Booted on Ubuntu 14.04, Mint 16,
Fedora 20 with SeaBIOS payload. Memtest86, FWTS, and
other tests pass.

Notes:
- Generates a 2MB binary to be flashed to the upper 2MB of the ROM,
to preserve the existing Intel Flash Descriptor & TXE binary.
- Tested with B0 & B3 Baytrail I parts

Board support page will be updated on acceptance.

Change-Id: I80c836c7590f2dc25ec854e7a0bb939024cea600
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5792
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-30 17:34:22 +02:00
Edward O'Callaghan 2c55b70d1a superio/winbond/w83627thg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Change-Id: I22775dc9b6341c8994d21591b7176abe4dd99911
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5724
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:53:33 +02:00
Edward O'Callaghan 92da206532 superio/winbond/w83627uhg: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Convert dependent board to generic winbond serial init. Note the clock
function is actually invalid since it never enters into PNP config mode
to twiddle the register. Further, 48MHz is the default (page 9 of
data-sheet) and so romstage.c need not do anything to the clock rate
hence why it presumably works with this invalid function.

Change-Id: I4706a1446c1b391b8390ac0361700ce6f15b9206
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5725
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:53:30 +02:00
Edward O'Callaghan b918623f2e superio/ite/it8712f: Depreciate model specific early_serial.c
We now have common ite_*_*() functions for romstage and hence no longer
require the model specific portion of this superio support.

Change-Id: I30400abf27008a88072673075bba445f100d9ad3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5838
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-28 22:51:49 +02:00
Edward O'Callaghan 76d8fd6095 mainboard/*: Convert to generic ITE superio romstage component
Convert mainboard's that use model specific romstage functions of
it8712f to the generic framework by following the reasoning of:

a7d14a1 ite/common: Introduce common watchdog and 3.3V VSB helpers

Change-Id: I1485306a951103c9a4bc0dbe87c416c91f46c36f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5737
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-28 20:08:21 +02:00
Kyösti Mälkki c009601f29 AGESA fam12 fam14 fam15: Declare local callouts static
Change-Id: I2ff70cafdd808a235ed4f0663e182d306f493c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:29:43 +02:00
Kyösti Mälkki f646f6d582 amd/dinar: Handle empty HOOKBEFORE_DRAM_INIT
Removed function only read ACPI MMIO base address from a couple of
registers in IO space.

Change-Id: I25a31b7ac1706b9eebc5db0b9604039928328b0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5683
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:29:18 +02:00
Kyösti Mälkki 6b4b1513a5 AGESA fam12 fam14 fam15: Common handler for AGESA_RUNFUNC_ONAP
Change-Id: I9f27e1e814a80864d8ca315fe816a083c55708c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5682
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:38 +02:00
Kyösti Mälkki 838e211013 AGESA fam12 fam15: Unify agesawrapper_amdlaterunaptask
Pass parameter Func like fam14, fam15tn and fam16kb.

Change-Id: I262bf88e431f7035e668ac8f3fb29ac0690b3e52
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5681
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:23 +02:00
Kyösti Mälkki 5e19fa4c51 AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET
This is x86 "standard" 0xcf9 reset mechanism.

Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5680
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:09 +02:00
Kyösti Mälkki f1bb19abee AGESA fam14: Comment lack of PCI-e slot resets
These boards return with AGESA_UNSUPPORTED, while other boards return
AGESA_SUCCESS here when there is no hardware for external reset signalling.

Change-Id: I5aed211b1812888af55a691cfbfa8d7b5aff91bc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5679
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:27:51 +02:00
Kyösti Mälkki c459f9658b AGESA: Add common callouts
Most of the callouts are not specific to board or even family.
Start new file with default callouts doing nothing and returning
either AGESA_SUCCESS or AGESA_UNSUPPORTED.

Also add callout for returning empty IdsIdData. This feature is
not used and could be easily overriden at board-level at later time.

Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:27:31 +02:00
Edward O'Callaghan 8102a9afb8 mainboard/google/slippy: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I219ae74d60fd7211de2edee96e74bbe13130bb94
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5849
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 04:37:08 +02:00
Edward O'Callaghan 6224c31860 mainboard/google/bolt: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I31841e7bf578c77d08d452779936fcf5b3026d4f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5848
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-25 04:36:48 +02:00
Edward O'Callaghan 8f9132fab1 mainboard/amd: Incorrect usage of logical vs. bitwise and
Spotted by Clang

Change-Id: I26201c7f5e421c38d3965d8e7e62c4a8e670e449
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5833
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-24 21:02:14 +02:00
Edward O'Callaghan 6cec824a28 mainboard/google/link: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Id967f6057759cf0603c84514d32b067c3658306f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5831
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23 22:24:11 +02:00
Edward O'Callaghan 0f2355a090 mainboard/google/falco: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I4e5f2d7e8e6b76703fccce38fc7e3165d763e97f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5830
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-23 22:23:53 +02:00
Edward O'Callaghan 9492b9dab4 superio/winbond/w83697hf: Depreciate romstage component
Depreciate the model specific early_serial.c romstage component for this
Super I/O in favor of the recent generic winbond romstage framework.

Change-Id: I529c9cd1d8d63db3035b4828b3c3fc43911f49ce
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5727
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-23 20:14:41 +02:00
Edward O'Callaghan 1704637719 mainboard/asus/k8v-x: Remove dubious SIO PNP programming in romstage
Remove bogus attempt to double program the Super I/O. Remove also a
questionable function that enters Super I/O LDN config space, does no
actual LDN programming, rather multi-function register programming and
then never leaves the config space. Further, we don't export pnp_
symbols from the early_serial.c component into the global namespace.

Change-Id: I7d6b97b174249ae16fe881728da5ca3dd069b696
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5800
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2014-05-23 20:13:38 +02:00
Rudolf Marek 80b627eb4d Asus F2A85-M: Move to ther proper SIO
The F2A85-M has IT8603E which is a strip down version of IT8728F.
Change configuration from provisional IT8712F to the IT8728F.
While at it also enable only needed LPC bridge decodes.
As the side effect, this change also implements setup of environmental
controller, thus it87 driver can detect the temperatures/fans.

Change-Id: I22067b13ea27ee37e959a246718d9559c2a3215d
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4499
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-05-23 20:09:36 +02:00
Edward O'Callaghan b27d3602e0 mainboard/samsung/stumpy: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I6c5cc46385581d6b69d20f6bc9b016b799765d9e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:42:03 +02:00
Edward O'Callaghan ea4ae2f02b mainboard/intel/emeraldlake2 Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Idda1a49277c156670014fac27b9f1c378f8df0cd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5827
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:42:00 +02:00
Edward O'Callaghan c686c95c98 mainboard/intel/baskingridge Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I61fe91e467c29f144323af9c4612420f322098b4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5826
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:59 +02:00
Edward O'Callaghan 6aa6509cae mainboard/intel/wtm2: Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I46fad8d236c620ee5dbeb24f4517f20f00db839f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:57 +02:00
Edward O'Callaghan 6f49f69ed0 mainboard/kontron/ktqm77: Fix usage of GNU field designator ext
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: If948960abbd927aa6d2b471a42a2321a04d992f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5824
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 19:41:56 +02:00
Edward O'Callaghan 8084e5b6da mainboard/google/peppy Fix usage of GNU field designator extension
Following the reasoning in,
8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: Idd7305cb34be77894ca4b6062bc0a2dc61126347
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5822
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 15:38:35 +02:00
Edward O'Callaghan f5037bd570 mainboard/google/parrot Fix usage of GNU field designator extension
Following the reasoning in:

8089f17 mainboard/lenovo/x230 Fix usage of GNU field designator extension

In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: I5be77fe6670601e103260077fae07a5b9fd41f1d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5821
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-23 15:38:34 +02:00
Edward O'Callaghan 2c9e370646 mainboard/ibase/mb899: Sanitize headers
These are not local headers.

Change-Id: Ie0b0a682565a08dbfa089986dc7860fdb0846949
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5796
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-21 02:29:28 +02:00
Edward O'Callaghan 61113de923 mainboard/ibase/mb899: Indent devicetree.cb
Change-Id: I29037c322dac5ed9ebc36b95bc1981acf21e5bd0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5778
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20 13:47:38 +02:00
Edward O'Callaghan fb8df3240f drivers: Drop GbE stub drivers
These NIC stub drivers were to initialize the Gigabit Ethernet adapters
just enough to keep coreboot from trying to execute an option ROM.
However this is no longer required as non-VGA option roms are not ran;
See:

b32816e Remove PCI_ROM_RUN option

Change-Id: Idc44619767c631c5fcf550a5948c8947bde5e218
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5777
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-20 13:46:35 +02:00
Kyösti Mälkki f7bfc34942 intel: Remove GFXUMA and related global variables
Remove use of global variables uma_memory_base and uma_memory_size
from builds with Intel northbridges, as these variables can be kept
within the chipset or even as stack locals.

Intel platforms have no functional implemenation for option GFXUMA.
If we did implement some choice between external and integrated graphics,
it needs to be named in less obscure fashion.

Change-Id: I12f18c4ee6bc89e65a561db6c2b514956f3e2d03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5720
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 17:20:13 +02:00
Kyösti Mälkki a6b6172ae3 Add aliases for Chromebooks in board_info
This defines new board_info entry 'Vendor name' to be displayed in place of, or
in addition to, the CONFIG_VENDOR string 'Google'.

Also flag these as flashrom accessible SPI without socket. Instructions to
disable flash write-protection can be found at Chromium developer documentation.

Change-Id: I69791a091417a80d01e0ba2c6462417730a07be0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5750
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-19 14:57:54 +02:00
Kyösti Mälkki ee96c2ccbb LiPPERT: Add aliases for board_status wiki
While at it, fix frontrunner-af board URL.

Change-Id: I3b631830d679abc20f8a72411f2402689d9f9aac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5706
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
2014-05-19 14:57:14 +02:00
Damien Zammit 40788c6a4e lenovo/t60: Enable dock serial port when undocked and redocked
When the system is started with dock, the serial port works.
As soon as the laptop is undocked and redocked, the serial port
no longer works.  See below superiotool dump snippet:

Upon bootup: SIO @ 0x2e
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 01 03 f8 04 03 04 04 02

Redocked:    SIO @ 0x2e
LDN 0x03 (COM1)
idx 30 60 61 70 71 74 75 f0
val 00 03 f8 04 03 04 04 02

Since the function dock_connect is executed every time the
dock is reconnected, starting without a dock and then attaching
it to a dock is now also fixed.

Change-Id: Ibd97589a8c743673a55e382a5db2ba62656c595e
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5761
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:27:11 +02:00
Duncan Laurie 469b5205c3 rambi: Add ACPI devices and interrupts for codec and ALS
The Codec and ALS both have interrupt sources that can be configured.
The ALS kernel driver currently does not try to use it but the codec
driver does for things like jack detect.

ACPI Devices are added, but as with other ACPI devices the HID may
need to be updated once more official strings are decided.

BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual: build and boot on rambi and check for functional lightsensor

Change-Id: Ib51a2aaf32d5597926fcbe9183947e9ac53e1468
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182366
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5049
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:06:38 +02:00
Duncan Laurie 5a45c9529a rambi: Add ACPI table support for I2C devices
In order to support probing I2C devices when the controller is
in ACPI mode the mainboard needs to decalre them in the proper
scope with the address/interrupt information.  The touchpad devices
are ATML0000/ELAN0000 and the touchscreen is ATML0001 so they can
be distinguished in userland scripts based on ID.  There is also
a special "ISTP" node that indicates whether the devices is a
touchpad (=1) or touchscreen (=0) in case this is useful to drivers.

These names may not be final but they are a starting point and can
be easily changed.

Atmel devices also have a bootloader mode which needs to be
declared as a separate device.  Unfortunately it does not work as
expected to have multiple I2cSerialBus() resources declared in a
single device and have it select properly, even with the use of
StartDependentFn(), so bootloader devices are declared separately.

The original devices are left in \_SB scope and are only enabled
if the I2C controllers are in PCI mode.  The new devices are only
enabled if the I2C controllers are in ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=baytrail
TEST=manual

1) Ensure there is no change in functionality by default and that
the devices are still probed by chromeos_laptop in the kernel.
2) Enable lpss_acpi_mode=1 in devicetree.cb and kernel changes to
add _HID entries for devices in appropriate drivers.  Ensure that
the devices are probed successfully.  Further changes are needed
to the chromeos-touch-firmware scripts to load config and update
firmware based on the new ACPI _HID entries.
3) Put touchpad in bootloader mode (by flashing bad firmware) and
ensure that it is detected at address 0x25 and the firmware is
able to be updated.

Change-Id: I5b9b47ddc94474a677497271e963f62cb09438e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182259
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5045
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:31 +02:00
Aaron Durbin 58d6e18f0c rambi: disable SERIRQ native functionality
Nothing can actually use this as the EC cannot speak
using baytrail's SERIRQ protocol. Also, the voltage
bridge is going away so nothing will be hooked up to it.
Therefore disable this it.

BUG=chrome-os-partner:24693
BRANCH=rambi
TEST=Built and booted.

Change-Id: I406bb9c227578ec0a75eaf67143b3b27cb7880ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182082
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5042
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-15 05:05:00 +02:00
Edward O'Callaghan f6ba9f6a65 mainboard/lenovo/t520: too many arguments to pc_keyboard_init
Fix build regression introduced in:
a823f9b mainboard/lenovo: Add Lenovo Thinkpad T520 support

Change-Id: I60d92f8cceda6427f43e6be9d78c2af82af4b061
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5738
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-14 13:10:43 +02:00
Zaolin a823f9b545 mainboard/lenovo: Add Lenovo Thinkpad T520 support
Short list of known issues for this patchset:

* Suspend/Resume - does not work
* Combi pci card for SD/MMC card reader with IEEE1394 - not found
* Shutdown - sometimes does not work as expected
* At least mysterious harddrive i/o

Change-Id: Iaba8d1f5e471cfeca20d82f4e1b416641e1f2ae9
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/5672
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-05-13 22:00:10 +02:00
Duncan Laurie dec0148100 rambi: dptf: Set critical thresholds
Set critical temperature thresdholds to 70C.  This will cause DPTF
framework to shut down the system so it may need to be higher or
lower but will need some testing.

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi, start DPTF framework and observe it
using specified critical thresholds.

Change-Id: Ibbf6d814295eb5ff006cb879676b7613f5eb56a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182025
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5038
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 21:01:28 +02:00
Duncan Laurie 063b2c4df7 rambi: Update the DPTF configuration
- Add passive thresholds for thermal participants
- Disable the charger participant and remove from _TRT

BUG=chrome-os-partner:17279
BRANCH=rambi
TEST=build and boot on rambi and start ESIF framework

Change-Id: Ie5917413aceadee6e39594257aaafb0bcb399d09
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181663
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5029
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 20:59:02 +02:00
Shawn Nematbakhsh b697eab938 rambi: Move KBD_IRQ pin for Rambi 2.0 board
KBD_IRQ# is moved to GPIO SC101, with SC50 going back to its original
SERIRQ function.

Note that this change breaks Rambi 1.5 keyboard functionality.

BUG=chrome-os-partner:24424
TEST=Manual on Rambi 2.0. Verify KB functions in OS with SC50 / SERIRQ KB
interrupt toggling removed from EC code.
BRANCH=Rambi, Glimmer, Clapper

Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: I3fa40441741ea9d52a6e2ff15925570510b5b82b
Reviewed-on: https://chromium-review.googlesource.com/181757
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5030
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 16:10:41 +02:00
Edward O'Callaghan def00be41d src/drivers/pc80: Remove empty struct keyboard
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.

Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-13 10:03:51 +02:00
Edward O'Callaghan e61dd0f7a2 southbridge/amd/sb?00/lpc.c: Move i8254/i8259 down in southbridge
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.

Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-13 10:03:38 +02:00
Kyösti Mälkki 216a619a74 Rambi: Enable 32k SUSCLK signal
The SoC needs to provide a 32k clock signal SUSCLK for
some modems to work properly, so this enables the signal.

BUG=chrome-os-partner:24425
TEST=Manual, check SUSCLK pin with a scope.

Change-Id: Ibc0d5bb38a2c3e16f381dfc256097fdced67fd1c
Reviewed-on: https://chromium-review.googlesource.com/180101
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5722
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:38:42 +02:00
Shawn Nematbakhsh 6a70258c69 rambi: Make eMMC CLK pull-down and change pull strengths to 20K
eMMC CLK was incorrectly configured as PULL_UP, but should have been
PULL_DOWN. 2K pulls somehow masked this problem.

BUG=chrome-os-partner:24353
TEST=Verify eMMC is bootable on Rambi on boards that previously failed
with an all-20K, all-PU eMMC pin configuration.
BRANCH=None

Change-Id: I0cbb6ebbb6818f83402b99330728266b09a0f5d6
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5026
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:11:37 +02:00
Aaron Durbin 68530cdb7c rambi: specify reference code index in vboot area
Rambi's reference code will live at slot 3 in the
verified firmware section.

BUG=chrome-os-partner:22867
BRANCH=None
TEST=Built and booted. Verified correct area where
     reference code was loaded from.

Change-Id: I8bee46600429ac8f732fe334852f69aff1324150
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180027
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/5024
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:10:55 +02:00
Duncan Laurie 73c0a05bc7 rambi: Disable HSUART2 and SPI interfaces
Not used currently on rambi board.  Disable in case it
saves power.

BUG=chrome-os-partner:23862
BRANCH=none
TEST=build and boot on rambi

Change-Id: Idb870c2cfa88cb6c3f1ada3caf0db566e33ec1eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180084
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5020
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:09:49 +02:00
Duncan Laurie 7e647f596c rambi: Enable SCC devices in ACPI mode
With the ACPI GNVS exported and depthcharge changed to
initialize eMMC in ACPI mode we can now put the SCC
devices into ACPI mode.

BUG=chrome-os-partner:24380
BRANCH=none
TEST=build and boot on rambi, test eMMC and SD card

Change-Id: I39716198f8227c0c3293ac23eb09660792e2c51b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179901
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5018
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-12 22:08:30 +02:00
Edward O'Callaghan 2e4dea663c superio/ite/it8718f: Remove hard coding from romstage
Make use of the ITE common Super I/O framework and there-by removing any
hard coding of Super I/O base address.

Change-Id: I14af89d2727d7c6bac0f9840043c430726297429
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5717
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-12 17:43:46 +02:00
Edward O'Callaghan f29200240e superio/ite/*: Factor out generic romstage component
Following the reasoning of:
cf7b498 superio/fintek/*: Factor out generic romstage component

Change-Id: I4c0a9a5a7786eb8fcb0c3ed6251c7fe9bbbadae7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5585
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-05-11 17:52:08 +02:00
Kyösti Mälkki 5c3f384f06 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT
Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.

This squelches Kconfig warnings about unmet dependencies.

Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-10 11:27:25 +02:00
Edward O'Callaghan a7e2cc507b mainboard/jetway/nf81-t56n-lf: Toggle WDT and CIR in devicetree.cb
Turn on WDT support in the devicetree. Turn off CIR support.
Dispense with old commentary.

Change-Id: Icf0c0e12a0ed7ce6c3b6176653e076ffc2ba937e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5698
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-10 06:34:34 +02:00
Martin Roth 2dd3f877cc cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.

These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda

Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:36:12 +02:00
Edward O'Callaghan f18abab200 superio/serverengines/pilot: Avoid .c includes
Following the same reasoning as commit
d3043313a9 superio/fintek/f81865f: Avoid
.c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ia6ed36c8517a95b651fefdd855eec0ec91d73187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5439
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09 08:26:14 +02:00
Kyösti Mälkki 618de689c3 Squelch some warnings from Kconfig
Overriding global config entries in mainboard directory Kconfig
files often raise unnecessary warnings. Squelch some of those.

Change-Id: Ib5127672ae068670028aa25c8ccb5366277622f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5699
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-09 08:24:40 +02:00
Duncan Laurie 4acd3c05d6 rambi: Enable DPTF
This enables the DPTF framework, but it doesn't do much
without some sort of kernel+user components to drive it.

BUG=chrome-os-partner:17279
BRANCH=none
TEST=build and boot on rambi, dump DSDT and look over \_SB.DPTF

Change-Id: Icb632a6e70c3912bbdfa6ef3f5c87cd79d2b8a3a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179480
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5003
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-09 05:43:01 +02:00
Duncan Laurie 4cc4b04d8a rambi: Set panel power timings
These are the values that are seen with VBIOS and
may need tweaked for derivative panels.

BUG=chrome-os-partner:24367
BRANCH=none
TEST=boot on rambi in normal mode and see the panel come up

Change-Id: Ie3120ab3c5298135626e8534d3954acd263dc74b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179365
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5001
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:42:47 +02:00
Aaron Durbin 7b35706cf3 rambi: change SD card pulls to 20K
Now that the SD card controller is limited to the SD card
2.0 spec it's possible to use 20K pulls for the pads.

BUG=chrome-os-partner:24423
BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Able to dd to/from /dev/mmcblk1 without
     any errors.

Change-Id: Id5396c55330a84bf7a09d227507d2bfcde66a1a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179423
Reviewed-on: http://review.coreboot.org/4999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:42:33 +02:00
Aaron Durbin 40b7455f93 rambi: limit SD card controller to 2.0 spec
The rambi board can only meet the SD card 2.0 specification.
Therefore, the controller capabilities need to be overridden
to match.

BUG=chrome-os-partner:24423
BRANCH=None
TEST=Built and booted. /sys/kernel/debug/mmc0/ios shows
     high speed as maximum timing as well as 3.3V signal voltage.

Change-Id: Ib3824800852376e0f15a70584917d6692087ccfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179415
Reviewed-on: http://review.coreboot.org/4998
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-09 05:41:59 +02:00
Aaron Durbin 7538937d6e rambi: export SPI write-protect GPIO correctly
Bay Trail has 3 banks of gpios. Therefore, in order to
properly identify a gpio the specific bank number as well
as the GPIO within that bank is needed. The SPI
write-protect GPIO is GPIO 6 within the SUS bank (offset
0x2000).

BUG=chrome-os-partner:24324
BUG=chrome-os-partner:24408
BRANCH=None
TEST=Built and booted. Looked at GPIO sysfs in the
     chromeos_acpi directory.

Change-Id: Ic51b5abe3bacf6cf9b6a90cf666f1a63b098a0e3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179195
Reviewed-on: http://review.coreboot.org/4995
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-09 05:41:29 +02:00
Kyösti Mälkki 5c4b8483d2 ChromeOS boards: Always build code for bootmode straps
Leave it under BOOTMODE_STRAPS to control whether these have
any functional meaning on the build.

Change-Id: Ieb59aa7ab4b1e8da6a1002e7a8e5462eb7988d35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 16:26:58 +02:00
Kyösti Mälkki ab7280970a ChromeOS boards: Fix includes
Change-Id: Ib8448f3d36a23538cd9fea897f09da3ec4ad007a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5647
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 16:25:57 +02:00
Kyösti Mälkki 1645589ce7 Declare get_write_protect_state() without ChromeOS
Change-Id: I72471ac68088cd26f8277b27b75b7d44ad72cfc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5642
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:30 +02:00
Kyösti Mälkki e3ddee0437 Rename from save_chromeos_gpios() to init_bootmode_straps()
This feature is no longer specific to ChromeOS builds.

Change-Id: If27d4dc7caff8a551b5b325cdebdd05c079ec921
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5641
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:16 +02:00
Kyösti Mälkki ff402e3aeb ChromeOS boards: Use explicit include of chromeos.c
Change-Id: I7b3d044fad1d6973910e9bef347478a45c149a4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-05-08 16:25:05 +02:00
Edward O'Callaghan 63f28c00aa superio/fintek/f71869ad: Make hwm devicetree configurable
Provision the configuration of the Fintek F71869AD Hardware Monitor's
configuration by way of devicetree.cb. Make use of this in the
jetway/nf81-t56n-lf board to properly control fan's.

Change-Id: Ic25b29d1b7a9145e0e209b490b25a2cbc46cb75c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5580
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08 12:10:55 +02:00
Edward O'Callaghan dd2e8c35fb superio/fintek/f71869ad: Configure multi-func reg in devicetree
Facilitate for the configuration of so called "Multi-function Select
Registers" with devicetree.cb in ramstage.

Make use of this new functionality in, mainboard/jetway/nf81-t56n-lf to
correctly configure the Fintek's multiplexed GPIO pins to be in AMD TSI
mode. This allows the Fintek to correctly talk to the Southbridge over
the SMBus for CPU temperature data as to control fans and so on.

Change-Id: I80abcd8b767fc4b22d00d1384ce4ef89fe837e3d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5576
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 12:10:37 +02:00
Edward O'Callaghan 708be1a453 mainboard/jetway/nf81-t56n-lf: Improve diags in romstage
romstage reports a completely unintelligible printf of "error level:",
fix this and document meaning of the return values in source.

Change-Id: Ia2fb9a6206e08822f6c2f62b69bf22cdae2ba819
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5465
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-08 12:10:29 +02:00
Shawn Nematbakhsh 9928197c26 rambi: Make ec_in_rw a legacy GPIO
ec_in_rw needs to be read by depthcharge, which only supports legacy
GPIOs.

BUG=chrome-os-partner:24408
TEST=Manual on Rambi. Cold + warm boot device, verify that depthcharge
detects the proper ec_in_ro state.
BRANCH=None

Change-Id: I25802b445c795eb85580c22d880efee8eeb21318
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4993
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
2014-05-08 07:07:28 +02:00
Shawn Nematbakhsh 70cc9084a5 rambi: Change eMMC pin PUs to 2K
Strengthen PUs on all eMMC pins to fix problems with eMMC not coming up
on certain boards.

BUG=chrome-os-partner:24353
TEST=Manual. Burn FW on board that previously failed to boot eMMC,
verify chromeos can now install + boot from eMMC.
BRANCH=none

Change-Id: I7a9742968b8b8c2c42285ffc21de46aed9c87fb7
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4991
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:07:07 +02:00
Aaron Durbin fad3703ce8 rambi: configure SD card signals
Rambi 1.5 boards use the native SD card controller on baytrail.
Therefore, enable those signals. The CLK, D*, and CMD pins use
2K pulls as these were shown to not exhibit any errors when
doing reads or writes to a DDR50 sd card.

Note that if a servo is connected on needs to enable the
sd_vref_sel rail to pp1800 as this causes issues with card
detect if it is not set to pp1800.

BUG=chrome-os-partner:24312
BRANCH=None
TEST=Built and booted. Tested sd card read and write works in kernel.
     Also noted that write protect detection works as well.

Change-Id: I520e2808acbd8494534fcb710411dbc0e12fc874
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178961
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4990
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-08 07:06:59 +02:00
Aaron Durbin ac9a905cf1 rambi: configure the LPE audio codec clock
Rambi has the LPE audio codec connected to PMC_PLT_CLK[0].
Configure it for 25MHz.

BUG=chrome-os-partner:23791
BRANCH=None
TEST=Built and booted. Noted message in console output.

Change-Id: I11297ba951149e5831c65ca70ac7bdbbed113098
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178781
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4987
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-08 07:06:00 +02:00
Patrick Georgi 802a8ece3f rambi: Remove outdated comment
Change-Id: Ic555d23a9112677a784dd814601f8202d4d17261
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5691
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-07 22:08:19 +02:00
Aaron Durbin 100b14d12b rambi: handle single channel configs
Some 1.5 boards have a single channel ram configuration.
Accomodate such configs.

BUG=chrome-os-partner:22865
BRANCH=None
TEST=Built and booted ChromeOS.

Change-Id: I513327e47b9211d2dd1ea960d7da671a3773cb91
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/178340
Reviewed-by: Nick Sanders <nsanders@chromium.org>
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Tested-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: http://review.coreboot.org/4983
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:08:04 +02:00
Aaron Durbin 21565cac1b rambi: use SERIRQ pad as keyboard irq in gpio mode
The level shifting between 3.3V and 1.8V for the SERIRQ
signal is not working. Instead use the SERIRQ pad as
a gpio which is used as a direct IRQ signal for the
keyboard interupt.

BUG=chrome-os-partner:23965
BRANCH=None
TEST=Built and booted rambi. Keyboard works with associated EC change.
CQ-DEPEND=CL:177189

Change-Id: Ifc270ca38207828a6d4711551d4bde9121559cca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177223
Tested-by: Bernie Thompson <bhthompson@chromium.org>
Reviewed-on: http://review.coreboot.org/4979
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:34 +02:00
Aaron Durbin baa1e38217 rambi: make ramids non-legacy gpio inputs
The romstage code for rambi uses the mmio way of reading
inputs. However, this is a problem is the GPIOs are set up
as legacy mode. Subsequent warm resets mean the ram_id is
read incorrectly. Ensure the ram_id is read consistently
by keeping the GPIOs for ram_id in mmio mode.

BUG=chrome-os-partner:24085
BRANCH=None
TEST=Built and booted. And rebooted. Now seeing consistent ram_id
     values on warm resets.

Change-Id: Ieff98c000be80998854f325754f1e819975d2be5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/177230
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:06:10 +02:00
Aaron Durbin ee3ec728d8 rambi: distribute IRQs away from PIRQA on pci devices
Some of the drivers in the kernel were not so happy about
having shared IRQs. Also, sharing IRQs means more code
needs to be run in interrupt context to determine if the IRQ
was meant for a particular device. Fix this.

No more 'mmc1: got irq while runtime suspended' messages.

BUG=chrome-os-partner:24056
BRANCH=None
TEST=Built and booted. Looked at /proc/interrupts and noted no
     more sharing between pci devices.

Change-Id: Ie5da102204ffe3156dd55ab17af77df245a57c97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176792
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4973
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 22:05:40 +02:00
Aaron Durbin afaaa3a618 rambi: fixup settings so trackpad can be found in kernel
The kernel chromeos_laptop driver nomenclature expects the
board name to not be in all caps. Fix this as well as the i2c
address for the trackpad.

BUG=chrome-os-partner:24307
BRANCH=None
TEST=Built and booted. trackpad device is found. IRQs still not
     working yet.

Change-Id: Id6be8ee4bce2835e303ea4fe63944be80d2d7ec2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176680
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4970
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:05:19 +02:00
Shawn Nematbakhsh 9547f8d799 rambi: Add DIRQs for trackpad and touchscreen
Also add the relevant info about these pins to the ASL tables + add
SMBIOS type 41 data for these parts.

BUG=chrome-os-partner:22863
TEST=Manual on Rambi. Set some pins to GPIO_DIRQ, and then verify DIRQ
regwrites w/ GPIO_DEBUG look correct.

Change-Id: Id40655f9fb2ea7b10e1ff58d0b2a8b4cc6f05ff8
Reviewed-on: https://chromium-review.googlesource.com/176299
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4963
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-07 12:03:54 +02:00
Furquan Shaikh 99ac98f7e1 Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.

These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.

In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.

Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.

We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.

Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-06 20:23:31 +02:00
Aaron Durbin 7e9634ffc0 rambi: disable HDA device
For some reason HDA can now be disabled. It's unclear what changes
in the baytrail code allowed this to happen, sadly.

BUG=chrome-os-partner:22871
BRANCH=None
TEST=Noted hda is not in lspci.

Change-Id: I64e2560533be6f701fa66cd53c906b62b09012ed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176394
Reviewed-on: http://review.coreboot.org/4961
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:55 +02:00
Aaron Durbin 59cd6216dd rambi: enable SCI and SMI gpios
Rambi has 3 pins that need to be configured for SCI and SMI:

1. GPIO_CORE[0] - runtime SCI pin
2. GPIO_SUS[7] - SMI for firmware lid events
3. GPIO_SUS[0] - wake pin for S3 wakes from EC.

Configure these pins now that the rest of the infrastructure
is in place. The one thing that is yet to work is runtime SCI
for lid events once booted.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=built and booted. lid close at rec screen works. And wake
     from S3 with a keyboard press works.

Change-Id: I5f8e38ec5f4cf1a8ef7aa7fcee9abc344d9b184f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176393
Reviewed-on: http://review.coreboot.org/4960
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:49 +02:00
Aaron Durbin 3fbf671194 rambi: mainboard EC - SCI and SMI fixes
As rambi is a baytrail board it doesn't have a dedicated wake pin.
Therefore, one needs to enable the proper GPIO to wake up the sytem
before going into S3.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Put system into S3. Keyboard press created wake event. Also, typed
     'lidclose' on EC console while at recovery screen. Machine properly
     shutdown.

Change-Id: Ic67b6bce93d57c620f498505d83197e4ae34a07d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176392
Reviewed-on: http://review.coreboot.org/4959
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 18:39:38 +02:00
Aaron Durbin 9e68fe68ff rambi: include the EC devices normally on superio
The superio.asl file allows for the mainboard to hang
devices off of the LPC bus in ACPI. Include the keyboard
controller, EC memory map, and host interface's resources.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted resource reservations in dmesg.

Change-Id: Ida6481cd4c4725b5d3946bc64179ee99c93b0106
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176134
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4950
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:19:19 +02:00
Aaron Durbin 84da959c69 rambi: update EC support
Fix the SMI and SCI gpios for Rambi. Also, add in the
EC callbacks for the SMI handler. Note that the handler
for GPI SMIs has not been tested yet as baytrail chipset
code  doesn't yet support setting up those configurations
yet.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Noted that SCI was enabled in /sys/firmware/acpi/interrupts
     for the EC's SCI GPI. Also was able to see Chrome EC messages
     with CONFIG_DEBUG_SMI and powering down at the dev screen.

Change-Id: I67b278fd38e1c09271d2c1e16e42f6e8c49e3a70
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176077
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4948
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:18:54 +02:00
Aaron Durbin 1af366322e baytrail: configure acpi SCI irq
Baytrail has a configurable SCI irq. Add support for
properly configuring SCI irq. Note that it is currently
fixed to IRQ9, but the code supports setting it to the
other supported values. The current mainboards using
baytrail defer the madt IRQ override information to the
chipset.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted. Noted 'SCI is IRQ9' message.

Change-Id: I7b307bd58f9de944f0cb4c116107a15345499f2e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176075
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:40 +02:00
Aaron Durbin 952d85e5f2 rambi: mirror bayleybay's eMMC gpio setup
These changes to the eMMC pads allows the kernel to see the
eMMC device. One is able to install onto the eMMC device, and
the kernel is loaded and booted from eMMC device. Note, that
it may not fully boot because of other issues such as
not-completely working ACPI support.

BUG=chrome-os-partner:22580
BRANCH=None
TEST=booted off of usb drive. can see eMMC device.

Change-Id: I9c088398297a0b559383bdf4a389dd19a1110e0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/176073
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4945
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:27 +02:00
Duncan Laurie 8de0ca435e rambi: Fix eDP panel functionality
For some mysterious reason GPIO_S0_NC22 is making the eDP panel
go entirely white when it is configured with internal pullup.
Since these (supposedly XDP related) pins are unknown functionality
lets set them to GPIO_DEFAULT instead of GPIO_NC.

Additionally the VBIOS is being changed to issue int15 callback
to determine the boot graphics device.  If we list both LFP and EFP
then the dev/rec screens will show on the panel when HDMI is not
attached and otherwise will display on HDMI.

BUG=chrome-os-partner:23507
BRANCH=rambi
TEST=build and boot on rambi, see firmware/kernel screens on the panel
when HDMI is not attached, and firmware screens on the panel and
kernel screens on both when HDMI is attached.

Change-Id: Ieb05a591d63c4f8e09fa154eeb76004d32579508
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175952
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4944
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 17:17:17 +02:00
Trevor Mosey 2237324e77 lenovo/t60: Add "IBM ThinkPad Embedded Controller" SMBIOS OEM String
linux/drivers/platform/x86/thinkpad_acpi.c looks for an EC
version string before loading, this code copies the vendor BIOS by
exposing this string. This was originally part of x60's mainboard.c 

Change-Id: I5e54ea2833252bc4dbba46ceb67d78c435b34845
Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
Reviewed-on: http://review.coreboot.org/5638
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-06 14:17:44 +02:00
Aaron Durbin 303525b446 baytrail: fix up FADT
The FADT for baytrail had incorrect offsets leading to
the kernel spewing a huge mess of ACPI errors. Fix these offsets
to be initialized in the chipset code.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted into kernel on rambi. Login screen comes up.

Change-Id: I89fc2a4fd800ff01cedf89b51cfb1369aceb9f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175663
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4941
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 23:38:56 +02:00
Aaron Durbin 3bde3d74c5 baytrail: interrupt routing support
This provides the initial support for interrupt routing
in bay trail. It includes both acpi changes and board changes
to ensure the interdependencies are met with the current ASL
code. The PIRQ routing is handled by the mainboard exporting
an irqroute.h header that describes the per device and PIRQ
PCI settings.

There are still a lot of ACPI errors in the kernel with this
change, though.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted rambi into kernel.

Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id8a865a24fc8d49743c0b54efdb64aaef52fcd8e
Reviewed-on: https://chromium-review.googlesource.com/175700
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4940
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 23:38:38 +02:00
Kyösti Mälkki 08df7326e6 AGESA: Fix BiosCallouts table formatting
Already done for fam15tn and fam16kb.

Change-Id: I3da36bfe6fd1805867eee5aa1f017c4fda084349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5660
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:57 +02:00
Kyösti Mälkki 088fd67a38 AGESA: Implement EmptyHeap()
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear
the fields individually.

Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5659
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:50 +02:00
Kyösti Mälkki 8ef30253e3 AGESA fam14: Use common callouts
Backported from fam15tn and fam16kb.

This also implements GetHeapBase() to satisfy some requirements
of HAVE_ACPI_RESUME for the following boards:
  amd/inagua
  amd/south_station
  amd/union_station
  asrock/e350m1

Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5658
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:45 +02:00
Kyösti Mälkki 5601922130 AGESA fam14: Add fam14_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5657
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:35 +02:00
Kyösti Mälkki 6711dce552 jetway/nf81-t56n-lf: Revert change on function prototypes
These function prototypes to remain identical across all
AGESA families.

Change-Id: If2a0a08fa7122e6becded37d032d3c40bde2d149
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5656
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:48 +02:00
Kyösti Mälkki f15e53a730 AGESA fam15: Add GetHeapBase()
While fam15 boards do not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:43 +02:00
Kyösti Mälkki 4f998a07b5 AGESA fam12: Add GetHeapBase()
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5654
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:38 +02:00
Kyösti Mälkki e3aef13933 AGESA fam15tn: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:33 +02:00
Kyösti Mälkki 5caa9d9d81 AGESA fam16kb: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:26 +02:00
Kyösti Mälkki 575cf9df66 AGESA fam15: Use common callouts
Backport from fam15tn and fam16kb.

Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:19 +02:00
Kyösti Mälkki 05531a5f44 AGESA fam15: Add fam15_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5650
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:10 +02:00
Kyösti Mälkki 5c96525b6a AGESA fam12: Move dimmSpd
Implemented under northbridge/ on other families.

Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:05 +02:00
Kyösti Mälkki 328ce9a8b4 AGESA fam12: Add fam12_callouts
Although amd/torpedo is only fam12 board at the moment,
backported this from fam15tn and fam16kb.

Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:51:44 +02:00
Edward O'Callaghan 028dc1e151 AMD F14h boards: Sanitise headers in agesawrapper.c
Change-Id: Ic9c5e8abb3da020a642635ee74c9242091923619
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5628
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05 08:51:39 +02:00
Edward O'Callaghan 8864e1c149 AMD F14h boards: Use std memset/memcpy func over AGESA
In amd/{persimmon,inagua} and derived boards avoid using AGESA
reimplementation of memcpy as following the reasoning in:
e2f3bfc jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA

Change-Id: I943b46103c3bf1c5fd88b25e9f9595b9adfcafeb
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5625
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-05 08:51:34 +02:00
Trevor Mosey 8e5435a74b lenovo/t60: Move mainboard_enable() code into a mainboard_init()
mainboard_enable() is now modelled after google/parrot where the
enable function only sets dev->ops->init for the root device to
point to a mainboard_init() function, which in turn is called in a
later pass over the device tree to do the actual initialization.

Change-Id: I89a5192bd45ca8321b2b1ac49b073122e0f6ee2b
Signed-off-by: Trevor Mosey <uberushaximus@gmail.com>
Reviewed-on: http://review.coreboot.org/5637
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:46:16 +02:00
Patrick Georgi f771e569d7 Drop useless mainboard-romstage defines
Some src/mainboard/*/*/romstage.c files use defines which later
modify the behaviour of included .c files.
Since it's a pain to work out what is affected by these, drop
values that are only defined in the board but never used, or
defined to identical values as in spd.h (and use that one instead).

Change-Id: I8143b26fddc32a40ac4e611a6287bf7f144267dc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5639
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 09:44:34 +02:00
Furquan Shaikh fd33781fbf Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:25:20 +02:00
Kyösti Mälkki e93776579d qemu-armv7: Kconfig cleanup
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7.

Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5627
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:22:45 +02:00
Edward O'Callaghan b53b50b8c1 asrock/e350m1: Sanitize #includes
Following similar reasons as:
5ff4b08 jetway/nf81-t56n-lf: Sanitize #includes

Change-Id: Ie88b884bc2d4481bc2583d5be1f4d1376547f3c3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5614
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2014-05-02 12:08:14 +02:00
Edward O'Callaghan dbadb0a827 jetway/nf81-t56n-lf: Set OEM to Jetway in DSDT and mptables
Jetway builds this hardware, so let us be sure to set the truth in the
DSDT Definition block and MPTables.

Change-Id: I2dfb89152aa3b895ec6975293c5a5998ab6b52bd
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5630
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:07:26 +02:00
Paul Menzel e72645a852 asrock/e350m1/devicetree.cb: Correctly indent device line
Fix up commit dfa8a32f [1].

	src/mainboard/asrock/e350m1: Properly indent devicetree.cb

[1] http://review.coreboot.org/5612

Change-Id: I59b3ec2f00d69951aa8a96c4a9c3de5b219acbfb
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5619
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:04:36 +02:00
Edward O'Callaghan bbe3e44310 mainboard/jetway/nf81-t56n-lf: Properly indent devicetree.cb
Following the reasoning in,
dfa8a32 src/mainboard/asrock/e350m1: Properly indent devicetree.cb

Change-Id: I88ca01519c1c47a7eb0d564a55c945589f9d32af
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5629
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-02 12:03:06 +02:00
Edward O'Callaghan 0dd0669c59 mainboard/*: Use generic winbond romstage in place of w83627thg
Use the generic implementation of winbond in place of the model specific
w83627thg_enable_serial() as so that it maybe removed later.

Change-Id: Ice1a0dc428de9a3ddfb79e877fb03c7a8e09665f
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5603
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-02 09:44:44 +02:00
Kyösti Mälkki 6578475d93 ChromeOS: Use common fill_lb_gpio()
Change-Id: I2ba7a1c2b2e6ce2c00c9a2916141bed67930ba2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5586
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:40:11 +02:00
Kyösti Mälkki ab56b3b11c ChromeOS: Remove oprom_is_loaded
A global flag oprom_is_loaded was used to indicate to
U-boot that VGA option ROM was loaded and run, or that
native VGA init was completed on GMA device.

Implement this feature without dependency to CHROMEOS option
and replace use of global variable oprom_is_loaded with call
to gfx_get_init_done().

Change-Id: I7e1afd752f18e5346dabdee62e4f7ea08ada5faf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:26 +02:00
Kyösti Mälkki 926a8d1262 google/stout: Fix build without ChromeOS
Currently we have no developer or recovery mode switches when
building without ChromeOS.

Change-Id: I49adfcd8408838cf581430970be5efcef11ba06b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-01 15:39:05 +02:00
Duncan Laurie abab05cb3c baytrail: Clean up NVS region
There is a lot of NVS allocated to things that are not really
used.  Most of these are removed and some are moved around.
Thermals are expected to be handled with DPTF so I've removed
that bit of code but have not yet cleaned up the thermal zone.

I left in the SIO BARs since I think we will need those still
even though they may need work still.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: Id16ee67e6b3709a303c001afd72947147f938127
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175626
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4936
Tested-by: build bot (Jenkins)
2014-04-30 23:11:34 +02:00
Duncan Laurie 7fbe20bd2c baytrail: Add reserved MMIO regions to ACPI
Add a length define for all the reserved MMIO regions and
use them in the ACPI code to reserve the regions there.

Add a region for the "abort page" documented in the EDS.

BUG=chrome-os-partner:23505
BRANCH=rambi
TEST=build and boot on rambi

Change-Id: I2060dca0636a2fdc0533ddd0826f94add2c272c3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175624
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4934
Tested-by: build bot (Jenkins)
2014-04-30 23:11:11 +02:00
Duncan Laurie a90a59f5a3 baytrail: Fix XHCI problems and re-enable
- a few clock gating bits were set improperly and were preventing
the system from transitioning out of S0 state.
- the XHCC registers were not getting the top byte set properly
which includes things like DMA write request size and request
boundary crossing control.  This was causing memory corruption.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot kernel from USB on rambi with XHCI driver

Change-Id: I8e8135a793dfbaa1f163766702e3a8f19bba9703
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175558
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4933
Tested-by: build bot (Jenkins)
2014-04-30 23:08:35 +02:00
Edward O'Callaghan 8199809079 mainboard/: Avoid including early_serial.c from w83627hf
Following the reasoning of:
dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c

Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5597
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-30 19:06:47 +02:00
Kyösti Mälkki f385ba42e3 console: Move UART port defaults to mainboard
Correct selection of UART depends of board layout, not the CPU
internals, so default setting should originate from mainboard.

Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5618
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:43 +02:00
Kyösti Mälkki 48713a1bf7 console: Drop EARLY_CONSOLE option
We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.

The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.

Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:20 +02:00
Kyösti Mälkki 70342a7f51 uart: Support multiple ports
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.

With this change it is possible to have other than debug console
on different UART port.

Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:05 +02:00
Paul Menzel 68eff4fb1c lenovo/{t60,x60}/devicetree.cb: Fix typo in Controller in comment
$ git grep -l Cnotr | xargs sed -i 's/Cnotr/Contr/g'

Change-Id: Iee826a8092dbf17f8a28b7eb7b6d183464c6e498
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5325
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-29 21:23:52 +02:00
Edward O'Callaghan dfa8a32f1f src/mainboard/asrock/e350m1: Properly indent devicetree.cb
Trivial: clean up spaces to tabs to properly indent devicetree.cb

Change-Id: Id5577139cfa039898af3b2158fdd6869ac9d2ec1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5612
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-29 20:54:03 +02:00
Edward O'Callaghan 178a60b4b3 mainboard/kontron/986lcd-m: Remove a duplicate header
Change-Id: I0dd50722c1ccbcb8a21b8fbab4d706d6b2f2b130
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5602
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 20:18:52 +02:00
Edward O'Callaghan 9e308b9955 superio/winbond/w83627ehg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: Ib9f981f43e047013f9cbe20a22246ee2ed3ecf50
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5589
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 20:14:58 +02:00
Edward O'Callaghan 959adc3fcf mainboard/tyan/s8226: Remove redundant sio header
Change-Id: I8d258c12d03e71fb525251104b4fa81596ad2187
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:40:23 +02:00
Edward O'Callaghan ffe460d77a superio/winbond/w83627dhg: Convert romstage to generic component
Convert the serial init to the generic romstage component and
corresponding boards using this sio.

Change-Id: I36bcf38c4351130be1ed924ecfe606336d0433f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 19:22:14 +02:00
Edward O'Callaghan dbbc136c83 mainboard/asrock/e350m1: Avoid including early_serial.c
Use generic winbond romstage serial init symbols instead of model
specific implementation. We do this on a case by case basis as some
boards are ROMCC and so need to #include .c files. This is a step to
migrate non-romcc boards to a more generic superio framework.

Change-Id: I56f6d9ec77cd21a612cbbdb48634543f34a2e72c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5591
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-28 18:59:39 +02:00
Kyösti Mälkki 2458f42b27 AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-28 18:36:35 +02:00
Edward O'Callaghan cf7b498908 superio/fintek/*: Factor out generic romstage component
The romstage of Fintek Super I/O's is identical, leading to replication
of essentially the same code prone to bitrot. Herein we consolidate the
early pre-ram UART initialisation code into fintek/common, rather we
leave the exceptions to be implemented under model/.

More precisely we provide a well documented version of early_serial.c
under fintek/common and select by way of Kconfig as a generic romstage
component to Super I/O support. We leave future Super I/O's the option
to implement `non-standard` initialisation code should such a (unlikely)
need araise. A primary advantage is that new support for romstage serial
is now trival to add. We also provide some Kconfig documentation while
here.

Change-Id: I3c62561558a62ece944a167ba302fb7076bba001
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5575
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 18:22:11 +02:00
Patrick Georgi f33782fb86 lippert/hurricane-lx: Kconfig cleanup
A Kconfig option defined instead of selected that really comes from
somewhere else.

Change-Id: I8730d12ed053520b794655e943c93583c441f3f1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5542
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 14:13:58 +02:00
Furquan Shaikh 20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Furquan Shaikh 817149643c Get rid of HAVE_INIT_TIMER config option
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use a stub for init_timer in
places where we do not have any init_timer defined. Thus, remove the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include a stub_timer if required.

Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 13:25:28 +02:00
Edward O'Callaghan 5c41ee69ef superio/ite/it8716f: Rewrite from hardcoded base addr
Following the same reasoning as:
HASHHERE superio/ite/it8721f: Rewrite from hardcoded base addr
Removing hard coded magics and expose sio pnp api in romstage.

Change-Id: I27433cb1a84b3641a6110ecf6bd5021e00769aba
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5565
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:06:15 +02:00
Edward O'Callaghan 03ad2a26b0 superio/ite/it8721f: Rewrite from hardcoded base addr
Rewrite early_serial.c implementation to honour a passed base address in
device_t, removing any hard coding of values. We also expose early sio
init functions as romstage symbols to avoid falsely #including
"early_serial.c" in romstage.c of board support.

Change-Id: I521b8f7cf85173345b90745c6f2ab66e25429f5d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5561
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 12:57:04 +02:00
Edward O'Callaghan 392de45ae2 mainboard/*: Remove DUMP_ACPI_TABLES from amd boards
Dumping the ACPI tables in this way has limited use, is not likely to be
used and is poorly implemented. There are much more sophisticated tools
available on Linux for debugging ACPI as such this code is outside the
scope of coreboots 'bring up the hardware only' philosophy.

A more generic implemention could be done with hexdump() in coreboot
proper following on from this cleanup.

Change-Id: Ifd3bfb76338609d18fcf7158d3c9a6d7c06c8847
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-26 12:48:46 +02:00
Kyösti Mälkki 147f703aa9 Drop drivers/generic/debug
Not very popular nor useful nowadays.

Change-Id: I3dc0f7aaf188950a43f5350d3a95669fbbdcfd94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4554
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-22 13:42:48 +02:00
Alexandru Gagniuc cf38facbd2 hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
The PCIE PME pin from the APU is connected to GEVENT8, but the
northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map
accordingly.

Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5556
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:51 +02:00
Alexandru Gagniuc 7efd5fda49 hp/pavilion_m6_1035dx: Map USB and PWRB PME sources to GPE 11
Hudson ASL files assume the USB power event notifications are mapped
to GPE 0xb. Since that GPE is not used on this board, map these events
to GPE11. This GPE is already handled in ACPI via Method(_L0B). We
adjust this method to also notify the XHCI controller at PCI 10:0.

Change-Id: If33dd4bb5830820227f7c8b34594886cfae37282
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5554
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:43 +02:00
Alexandru Gagniuc 44f2fab89a AMD hudson and yangtze boards: Let mainboard declare power button
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.

Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.

Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-21 21:32:34 +02:00
Edward O'Callaghan ce7a8024ff mainboard/asus/m5a88-v/devicetree.cb: Fix formatting
Strip incorrect comments pretaining to the superio, and replace spaces
with tabs.

Change-Id: Ib3f6094c552777552d0ec06e3236210ee2e7b05d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5562
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-21 18:17:39 +02:00
Alexandru Gagniuc 0a57e999b7 hp/pavilion_m6_1035dx: Do not re-init EC and lid SMI on S3 resume
It's not needed, and puts the EC back into APM mode. The EC does not
shut down during S3 sleep, so we don't need to re-initialize it.
Lid SMI will have been disabled in the switch to ACPI mode, don't
re-enable it.

Change-Id: I2c06df140f63427dac32ae095d29e68f64135358
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5555
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:46:26 +02:00
Alexandru Gagniuc c38d991387 hp/pavilion_m6_1035dx: Suspend/resume on lid close/open with ACPI
This patch completes ACPI support for the lid switch. The lid SCI now
notifies the OSPM of the status change when the lid is closed or
opened, allowing system to suspend. The wake source is also declares,
and the system wakes when the lid is opened.

The system resumes successfully, but the display still does not come
back on.

Change-Id: I803c4fc64e15f8d1a90791ec246af66604646d8b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5549
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:34:01 +02:00
Alexandru Gagniuc c4e7db51fc hp/pavilion_m6_1035dx: Add GEVENT to GPE SCI mapping table
Each GEVENT pins can be mapped to a specific GPE via the SCI map.
The default mapping is not appropriate for this laptop, so use the
AGESA functionality to map currently known events.

Change-Id: Ifa50bf000cfc8e77a6a4d84752f89838f165f7a0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5548
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:33:39 +02:00
Alexandru Gagniuc a9a3661710 hp/pavilion_m6_1035dx: Move GEVENT/GPE definitions to common file
These definitions were scattered in a couple of files, and we risk
scattering them all over the place. Provide a common file for these
definitions.

Change-Id: I1fe99e5097cf10a349661f3b2ae2377f5cdd6103
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5547
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-20 21:33:26 +02:00
Kyösti Mälkki a6c525a7d5 AMD AGESA cimx/sb700: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
Following boards use cimx/sb700:
  amd/dinar
  supermicro/h8qgi
  supermicro/h8scm
  tyan/s8226

Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).

Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.

I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.

Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5539
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:03:55 +02:00
Kyösti Mälkki 35546deba6 AMD AGESA cimx/sb800: Drop APIC_ID_OFFSET and MAX_PHYSICAL_CPUS
All boards had APIC_ID_OFFSET=0 and MAX_PHYSICAL_CPUS=1.

Change-Id: I6f08ea6de92a2af79fb3a99c5edd942b3a321c43
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5538
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-20 20:03:46 +02:00
Kyösti Mälkki 9816392337 amd/torpedo: Remove unused Kconfig options
These are not used with cimx/sb900 vendorcode.

Change-Id: I489ee80c739b31edac649491497162c65316996e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5537
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:03:36 +02:00
Vladimir Serbinenko b1ccccc207 mainboard: New port Packard Bell LM85.
Change-Id: I8c1548470c605d06825fe35579879e806bf33542
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5271
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
2014-04-20 18:47:19 +02:00
Alexandru Gagniuc 7f09b754f9 hp/pavilion_m6_1035dx: Implement MB.LIDS ACPI method
Change-Id: I654ca745f7404b86aa25fb2e696751d616d0ca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5517
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:50:15 +02:00
Alexandru Gagniuc 5db38a38c9 hp/pavilion_m6_1035dx: Implement ACPI for wireless toggle hotkey
Change-Id: I2e9ab68263648af8c9d46999e960f0a0711b61d7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5516
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:50:09 +02:00
Alexandru Gagniuc fa840676f5 ec/compal/ene932: Update to use coreboot EC-mainboard API
This patch implements a simple interface between the EC and mainboard
ASL code. This interface does not rely on the preprocessor, and
prevents name conflicts by scoping the interface methods. As this
interface is documented on the coreboot wiki, an in-tree documentation
is not provided.

Change-Id: If0b09be4f5e17cc444539a30f0186590fa0b72b5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5515
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-19 03:49:48 +02:00
Alexandru Gagniuc 91b6d3a6b9 hp/pavilion_m6_1035dx: Rename "LID0" ACPI object to "LID"
There is only one lid switch, so it does not make sense to number it.
This naming is also consistent with the examples in the ACPI spec.

Change-Id: Ida0a4a89ca03b2aad4fc77e52996e86332d370cd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5545
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-19 03:14:35 +02:00
Alexandru Gagniuc 489ff7ef87 hp/pavilion_m6_1035dx: Shutdown when lid is closed on non-ACPI OS
This is handled by generating an SMI when GEVENT22 goes low. This pin
is driven by the EC when the lid opens or closes. This SMI is
disabled when switching to ACPI mode, so ACPI OSes are not affected.

Change-Id: I38193572bf0416fd642002dba94c19257f0f6f5b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/171
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:50 +02:00
Alexandru Gagniuc 599d668cdd southbridge/hudson: Compile refactored SMI setup utilities in SMM
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt
mode and trigger level. Move the utilities which are useful in SMM to
a separate file that is included in both ramstage and SMM. This is
useful for SMI handlers which need to enable or disable GEVENT SMIs
on-the-fly. A follow-up patch makes use of this infrastructure.

Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/170
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:58:39 +02:00
Alexandru Gagniuc dbe6336f90 hp/pavilion_m6_1035dx: Shutdown on low battery with non-ACPI OS
Intercept the low battery SMI from the EC, and shut down the system
immediately. The EC only sends this SMI when the OS did not enable
ACPI mode, so ACPI OSes are not affected by this.
On the other hand, payloads such as GRUB or SeaBIOS will experience
the shutdown. This behavior is helpful for protecting the battery, for
example, when the OS fails to boot and we are stuck in the payload.
The low battery SMI is triggered at 10% charge, at which point the risk
of cell degradation exists.

Change-Id: I4c6c1a4feed8576cbdbb1945768de0805a1f5e42
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-18 21:16:24 +02:00
Patrick Georgi aece3c931e msi/ms9652_fam10: minor Kconfig cleanup
SMP and IOAPIC shouldn't need to be redefined here, select is enough

Change-Id: I8a66374205b671498ce21b3f174af14e98dbfe48
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5541
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-18 15:09:41 +02:00
Kyösti Mälkki 43cb7ca922 AMD hudson yangtze: Drop MAX_PHYSICAL_CPUS in comments
Change-Id: I81de291da7b3db8d04a127d5a304b558f1c75b34
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 23:56:33 +02:00
Alexandru Gagniuc 09fe3f83c5 hp/pavilion_m6_1035dx: Remove code which dumps ACPI tables
Dumping ACPI tables in canonical form has very little value, and is
of questionable use except when debugging acpigen. Remove the code
which dumps the tables.

Change-Id: Id13c88cee8674b13e5cf5b5ed32c26283e586fd9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5526
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-17 16:50:01 +02:00
Alexandru Gagniuc 73639e2717 hp/pavilion_m6_1035dx: Add SMI handler and handle EC requests
The EC may disable some functionality, such as Caps Lock LED and
battery charging if it never receives a command to go in APM mode. If
we start it in APM mode, then immediately switch to ACPI mode, it will
not get its SCIs serviced until an ACPI OS boots. If its SCIs are not
serviced, it may assume the OS has hung.

The way we solve this is to initalize the EC in APM mode, and only
switch it to ACPI when an ACPI-capable OS issues the ACPI_ENABLE
command. The switch has to be handled in SMM.

Although we aren't yet processing SMIs from the EC, we are reading the
status in order to satisfy the EC that the event is handled.

Change-Id: Iffaeb9a6f57841f456c4bce8337dc09b287f8758
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-17 16:48:57 +02:00
Kyösti Mälkki 62abbe909d roda/rk9: Drop MAX_PHYSICAL_CPUS
Change-Id: I9c41cccf9058c48006b247aca705a3f869ae82a6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-17 08:20:24 +02:00
Alexandru Gagniuc 342ac64a5d southbridge/hudson: Use MMIO instead of PIO to access PM space
The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.

Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 22:29:33 +02:00
Kyösti Mälkki 72a1768aba AMD hudson yantgze: Drop MAX_PHYSICAL_CPUS
Not used with AGESA vendorcode.

Change-Id: I4de7e49d513a1bc8d6d4da1eea630b9eedf5de80
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5522
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:58 +02:00
Kyösti Mälkki fd478f92a4 AMD hudson yantgze: Drop APIC_ID_OFFSET
Not used with AGESA vendorcode.

Change-Id: I1c4e1dea8836143334d336f99afcee2ca326b0c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5521
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:55 +02:00
Kyösti Mälkki 740862c7d3 AMD AGESA: Drop SB_HT_CHAIN_UNITID_OFFSET_ONLY
Not used with AGESA vendorcode.

Change-Id: Ic9a0513641bf76d748bb106675bccc33c7abe21e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5520
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-16 14:38:30 +02:00
Kyösti Mälkki aeb48934d4 AMD AGESA: Drop LIFT_BSP_APIC_ID
Not used with AGESA vendorcode.

Change-Id: Ie99abf5bcffd740e2e7ed6d78937ab32935ef214
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5519
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
2014-04-16 14:38:05 +02:00
Kyösti Mälkki ef5ce9a832 AMD AGESA: Drop AMDMCT
This config option is fam10 only.

Change-Id: I7f4619d2d4e7e7695a8ee691d879df2748f1c0c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5518
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-16 14:37:56 +02:00
WANG Siyuan 65f0dbc064 AMD Thatcher: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Thatcher.

Change-Id: I959721b4fd8787ac0824f9f873efd4788682eedb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/5359
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-16 13:35:51 +02:00
Alexandru Gagniuc 6ac7f5301f hp/pavilion_m6_1035dx: Add EC keyboard controller to devicetree
This causes coreboot to call the keyboard initialization code for the
KBC. This is only needed for payloads which do not initialize the
keyboard.

Change-Id: Id0bb77f2a8115fafc0cd6165a8431a7e07f0fac1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5514
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-16 03:05:10 +02:00
Edward O'Callaghan 00b6146030 hp/pavilion_m6_1035dx: Use hexdump() for dumping ACPI tables
Following the rational of:
5188d40 jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
Use "Debugging -> Output verbose ACPI debug messages" in menuconfig to
toggle.

Change-Id: Ibf03ef916a789d0f049190755213ba93191d4662
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5507
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:21:53 +02:00
Edward O'Callaghan ef4dcc09bb mainboard/jetway/nf81-t56n-lf: Make ACPI debug menuconfigable
Turns out we have a CONFIG_DEBUG_ACPI definition under:
Debugging -> Output verbose ACPI debug messages
Hence, let us make use of this definition.

Change-Id: I1b673feb6d9b2ee51c832a1cef159cd80e5c3517
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5506
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:21:31 +02:00
Edward O'Callaghan feebd86ad2 mainboard/jetway/nf81-t56n-lf: Documentation cosmetics
Keep under 80 colums and Doxygen'ify inline documentation somewhat.
Strip some whitespace bulk while here and refactor a little as to line
wrap.

Additionally, following the reasoning of:
0b2fa34 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
remove some fluff from buildOpts.c

Change-Id: Icb38f087724d3e3511df1d554a620eb637ce286a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5481
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-15 05:16:21 +02:00
Alexandru Gagniuc 5405d3fe91 hp/pavilion_m6_1035dx: Fix GPIO map and add WLAN pin
Change-Id: I07725b71508c8b08451022307ae934c1b227f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5491
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-14 16:31:34 +02:00
Edward O'Callaghan 5188d4008b jetway/nf81-t56n-lf: Use hexdump() for dumping ACPI tables
Use hexdump() instead of a local implementation for dumping ACPI_TABLES.

Change-Id: I20354a4f9dff4105de5af696bb9da4a4f6cca788
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5466
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-14 06:59:38 +02:00
Alexandru Gagniuc cd96e829f1 hudson boards: Don't require ide.asl file on boards without IDE
Not all boards which use the AMD Hudson southbridge have IDE. However,
the southbridge's asl included an 'ide.asl' file which had to be
present in $(mainboard_dir)/acpi.

Address this issue by removing the inclusion of 'ide.asl' from the
southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none
of which have IDE.

If future hudosn board will come with IDE, the device can be declared
in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'.

Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5459
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 21:51:19 +02:00
Alexandru Gagniuc b4417fb139 hp/pavilion_m6_1035dx: Add basic EC initialization
The EC is now set to ACPI mode, and properly generates SCIs on
external events. This fixes the issue where battery notifications were
not working.
The keyboard matrix type is also explicitly set up.

Change-Id: Ib6f0d23984d4ed1320340282469b8325c83547d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5471
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-13 15:29:50 +02:00
Edward O'Callaghan 99e2bf87ef cimx/sb800 boards: Don't require ide.asl on boards without IDE
Not all boards which use the AMD cimx/sb800 southbridge have IDE.
However, the southbridge's asl included an 'ide.asl' file which had to
be present in $(mainboard_dir)/acpi.

Address this issue by including ide.asl only in boards which have IDE,
and remove it from all other cimx/sb800 boards.

Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 09:06:15 +02:00
Edward O'Callaghan 0e3ca27315 mainboard/*/acpi/ide.asl: Serialize ACPI methods to avoid races.
Serialize methods against the construction of same (named) objects by
competing threads. See ACPICA BZ 909 for further details.

This change fixes issues that show up with the Ubuntu firmware test
suite (fwts) ACPI table sanity checker.

Change-Id: I49e3050a2a5aece6f031122b0211c056938d1a89
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5458
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 08:25:44 +02:00
Edward O'Callaghan c21bd8839b jetway/nf81-t56n-lf: Replace AGESA types with stdint types
Try to use void and uint*_t type specifiers in place of VOID and UINT*
respectively. Use const in place of CONST type modifier. Remove some
useless type casts.
A few unneeded comments containing the AGESA redefenied types are also
removed.

Change-Id: I4bff96a222507fc35333488331c3f35ef1158132
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5486
Tested-by: build bot (Jenkins)
2014-04-13 05:32:09 +02:00
Edward O'Callaghan e2f3bfc5b3 jetway/nf81-t56n-lf: Use std memset/memcpy func over AGESA
Replace usage of AGESA poor reinvention of memset/memcpy functions with
the usual standard ones.

Change-Id: Ibfe9ee253d57140b06a4fca6b47b2051308ad012
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5484
Tested-by: build bot (Jenkins)
2014-04-13 05:31:51 +02:00
Alexandru Gagniuc ac138976df hp/pavilion_m6_1035dx: Add ACPI support for lid switch
This is sufficient to at least allow linux to recognize the lid switch
and read its state correctly.

Change-Id: Id5bd92466c72559f263c7ca8d23cbc741377a762
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5464
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12 21:37:38 +02:00
Alexandru Gagniuc 27bb6ad046 hp/pavilion_m6_1035dx: Declare GPIO control block in ACPI
Only the WLAN control pin and the lid switch input are declared, as
those are the only pins whose function is known and tested.

Change-Id: Ia5871882884ba9bb6d63418b34e33f92ead669eb
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5463
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-12 21:16:19 +02:00
Alexandru Gagniuc f0504352b1 hp/pavilion_m6_1035dx: Add ACPI support for reading battery level
Hook in the EC ASL code. This provides just enough information for the
OS to be able to read the battery information.

EC notifications (_Qxx) do not yet work, and it is unclear if the
issue is in the ACPI code, or if the EC is not set up properly. Thus,
the OS must boot with the battery inserted in order to be able to read
its status.

The _L03 ACPI method is also removed, as the EC SCI uses this event.

Change-Id: I85cbaeb9c77e60bd1c68d928412f897de50c6329
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5445
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-12 20:31:22 +02:00
Alexandru Gagniuc 1a3872f7a4 ec/compal/ene932/acpi: Let mainboard define the ACPI lid object
The GP15 ACPI object was used to get the state of the lid. However
GP15 is specific to certain Intel chipsets, and will not always be in
the ACPI namespace. Instead of hardcoding this object, let the
mainboard define it.

Also, document the ACPI interface for the EC.

Change-Id: I02a2eb3116af61ea5701f84507327aa40218597a
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5444
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-12 20:26:04 +02:00
Konstantin Aladyshev 8395e90bc0 supermicro/h8qgi/dsdt: Use PIC as default interrupt model
According ACPI specification:

"""
The \_PIC optional method is used to report to the BIOS the current
interrupt model used by the OS. The argument passed into the method
signifies the interrupt model OSPM has chosen, PIC mode, APIC mode,
or SAPIC mode. Notice that calling this method is optional for OSPM.
If the method is never called, the BIOS must assume PIC mode.

Arguments: (1)
Arg0 – An Integer containing a code for the current interrupt model:
0 –PIC mode
1 –APIC mode
2 –SAPIC mode
"""

In current configuration with default value of interrupt model
PMOD equal 1 (APIC mode), Linux can't boot with "noapic" option.
Kernel never call _PIC method and PMOD stays equal 1, indicatind
that APIC routing objects should be evaluated. This mix of PIC
and APIC leads to boot fail.

Change default value of interrupt model PMOD to 0, for correct
"noapic" boot.

Change-Id: I7fa6f0c24802751202ed2e7f13411001a600e772
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/5473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 20:52:12 +02:00
Edward O'Callaghan fe365ac7e8 mainboard/lenovo: [2/2] implement initial T530 support
Step 2: change the Lenovo X230 code to adapt it to the new board's
hardware with the great guidance from Vladimir (phcoder) to find the
correct GPIO's.

The machine has:
 - Chipset: Intel QM77
 - GPU's: Intel Integrated HD Graphics
        : Discrete NVIDIA NVS 5400M (1 GB VRAM) with Optimus Technology

Change-Id: Iee12c3edc22df4a7935b7fb7ff4a320c21c4239b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5391
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 16:41:14 +02:00
Edward O'Callaghan 956c298233 mainboard/lenovo: [1/2] fork X230 to T530
Step 1: copy all files unmodified from Lenovo X230.  This makes it much
easier later to see how the two boards actually and deliberately differ
when porting bugfixes from one to the other.

Change-Id: I3151c7848440ea6c240b959379a8eb369d35f3de
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5390
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-04-09 16:40:55 +02:00
Idwer Vollering a09dad0c77 asus/f2a85-m: conditionally show POST codes
Change-Id: I61e55601676c0825815d6520a874ccade8942379
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5362
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 14:04:01 +02:00
Kyösti Mälkki 4c686f2106 OxPCIe uart: Split PCI bridge control
None of the PCI bridge management here is specific to the PCI UART
device/function. Also the Kconfig variable defaults are not globally
valid, fill samsung/lumpy with working values.

Change-Id: Id22631412379af1d6bf62c996357d36d7ec47ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5237
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:29:45 +02:00
Kyösti Mälkki afa7b13b93 uart: Redefine Kconfig options
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.

Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.

Removes:
  CONSOLE_SERIAL_UART
  HAVE_UART_IO_MAPPED
  HAVE_UART_MEMORY_MAPPED

Renames:
  CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
  CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM

Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:24:43 +02:00
Edward O'Callaghan 597cc45aa9 jetway/nf81-t56n-lf: Simplify agesawrapper_amdinitcpuio()
Follow same reasoning as:
12fd779 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
Use coreboot variants for PCI and MSR access over AGESA's.

Change-Id: Ic0d8bbd0faf6423605567564ad216b79e1331cc9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5472
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 07:13:43 +02:00
Alexandru Gagniuc 0b2fa34d31 hp/pavilion_m6_1035dx/buildOpts.c: Remove commented out tables
Change-Id: I181da410490a92760ae1328a4286e805f5388886
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5462
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 05:25:21 +02:00
Konstantin Aladyshev 05ba1bb6d4 supermicro/h8qgi/dsdt: Move _PIC method to root scope
_PIC method should be declared under root scope (\_PIC),
otherwise Linux kernel doesn't use it.

Change-Id: I29b6ca60191507ac8edf99fdf173617bd6446934
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/5478
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 05:00:06 +02:00
Alexandru Gagniuc 12fd779176 hp/pavilion_m6_1035dx: Simplify agesawrapper_amdinitcpuio()
TRIVIAL. Rather than using the AGESA functions for PCI and MSR access,
use the coreboot variants, which are cleaner and more readable.

Change-Id: I4f24820606900e16f0d159df019f4560f1592489
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5468
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-09 04:59:14 +02:00
Alexandru Gagniuc 011341d126 hp/pavilion_m6_1035dx: Remove inexistent devices from devicetree
This removes ominous "PCI: xx:xx.x not found" messages from coreboot
console.

Change-Id: I13a6f2497c04464e8dd0c4c5e7f40a1582f7f26c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5461
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-07 01:40:37 +02:00
Idwer Vollering fa02e16c76 asus/f2a85-m: Sanitize #includes
Based on the same reasoning as this commit:
1d87dac hp/pavilion_m6_1035dx: Sanitize #includes

Change-Id: I383f79b5392ee1ca244e403f755213fa7b32c0af
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/5420
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-06 18:18:46 +02:00
Edward O'Callaghan 4f5a5254c5 superio/winbond/w83627thg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: I1f7c20ac7841874125b6bfcd9f9db25d96355881
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5449
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:23:08 +02:00
Edward O'Callaghan 5ff4b086ba jetway/nf81-t56n-lf: Sanitize #includes
Following the same reasoning as commit
1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
Clean up the #include directives in this board support.

Change-Id: I97b73a349ca7e49b413d7c04900f25076488dde4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5414
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:12:45 +02:00
Edward O'Callaghan 793a429eb5 superio/winbond/w83627ehg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage
code.

Change-Id: Ib3a12fb8160729008bdaa8026365675a11325da0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-06 06:08:20 +02:00
Alexandru Gagniuc 1d87dac4e4 hp/pavilion_m6_1035dx: Sanitize #includes
There were a number of things wrong with the includes. First, The
includes did not use paths to AGESA files, thus relying on the
compiler include paths to find the correct file. This made it unclear
where the file included was located, and whether it was local, under
vendorcode, or under a different directory. Instead, use full paths
for each non-local include.

Second, the local includes were mixed with the rest, making it unclear
which file is local and which one is not. Keep the local includes at
the top. This also prevents us from polluting the namespace of local
headers, with library definitions, and allows us to catch if we missed
an otherwise needed external header.

Thirdly, alphabetize the order of includes where possible.

Change-Id: I22c543291beabb83c16d912ea0a490be6ca4e03c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5412
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-03 20:19:22 +02:00
Kyösti Mälkki cb3ba5fdbc lenovo/x60: Remove duplicate console_init()
For romstage, console_init() was called twice. The one in dock_connect()
should have done only UART programming and not touch CBMEM console and/or
USBDEBUG when those are enabled.

Second case where dock_connect() is called is in SMI handler.
If DEBUG_SMI is not enabled, console_init() does nothing in SMM.
If DEBUG_SMI is enabled, console_init() is already called every time when
enterining SMM.

Change-Id: Ib3a842442cb7a5be9d6b71682cd6f368930af886
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5433
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-04-03 10:04:19 +02:00
Edward O'Callaghan a270586d4b superio/fintek/f71859: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I3577ca3f761fb699dc51141a02e1f853bf1f1a21
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5417
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:08:32 +02:00
Edward O'Callaghan ade70a0482 superio/fintek/f71863fg: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: I863c16634873224c17e43100271e9b91419724d0
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:57 +02:00
Edward O'Callaghan fbdc3ef7d9 superio/fintek/f71805f: Avoid .c includes
Following the same reasoning as commit
d304331 superio/fintek/f81865f: Avoid .c includes
Clean up the early_serial #include directives in mainboard/romstage code.

Change-Id: Ibf743f7a5dd4a424a4513014fc9a896b87ecf3b1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5434
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-02 01:07:27 +02:00
Kyösti Mälkki deb2cb27e9 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the
board properly implements EARLY_CBMEM_INIT.

Flag vulnerable boards that only do cbmem_recovery() in romstage on S3
resume and implementation with Intel FSP that invalidates cache before
we have a chance to copy the contents.

Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-01 11:36:00 +02:00
Edward O'Callaghan d3043313a9 superio/fintek/f81865f: Avoid .c includes
We should not be #include .c files, instead link early_serial into
romstage and provide a prototype.

Change-Id: Ia9277169ce1592e1fc72f8849f0982741daec567
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5416
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-31 01:05:40 +02:00
Alexandru Gagniuc 01c44000be cubieboard: Enable the SD controller and mux SD pins
This step needs to be done before calling any MMC functionality.

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-29 22:28:44 +01:00
Alexandru Gagniuc fccfee3bce mainboard/hp: Add initial support for Pavilion m6-1035dx
This was a pathetically easy port, where all the components are
already supported. This is basically a verbatim copy of amd/parmer.
The EC is an ENE KB932, which is a part that does surprisingly little
for an EC. This also means we need almost no code to get it working.
I've "select"ed the EC in Kconfig, which is the only difference from
parmer, although the keyboard worked fine without it.

I haven't coupled in the ACPI code from the EC yet, so battery level
is not readable from the OS. Hotkeys work except for brightness
control, and the CapsLock LED blinks at regular intervals instead of
following the CapsLock key.

Change-Id: Idfec6f848b99a52e73eac22d516f3550477ad822
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5409
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-28 20:59:57 +01:00
Paul Menzel 35a4901d3a mainboard/*/*/ec.c: Do not include `chromeos/chromeos.h`
It's not needed and causes build failures without CONFIG_CHROMEOS.

Change-Id: I7923717bfc5c84698044008e5f2441206041e0dd
Reported-by: Idwer Vollering <vidwer@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5398
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-03-28 19:28:31 +01:00
Edward O'Callaghan 024822f26d mainboard/jetway/nf81-t56n-lf: Enable ACPI S3 support in Kconfig
Switch on ACPI suspend/resume support which now works after many cycles.

Change-Id: I94a9bc9f23c2b4482d940018d542ab89e6c76f09
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5406
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-03-26 13:15:13 +01:00
Edward O'Callaghan 1547ef2362 mainboard/jetway/nf81-t56n-lf: Turn on PME in devicetree.cb
Change-Id: Ia58994d14ebf488a9200b02ec7af9c71ef4de9e6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5401
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-24 07:10:55 +01:00
Edward O'Callaghan 8089f17806 mainboard/lenovo/x230 Fix usage of GNU field designator extension
In C99 we defined a syntax for this. GCC's old syntax was deprecated.

Change-Id: If8c53b5370be9101b9e5f2dfa88a6229f500a0f6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5392
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-17 19:14:30 +01:00
Edward O'Callaghan ed2bcaa731 mainboard/jetway/nf81-t56n-lf: Fix HWM base addr.
The target board has a different base addr. for its hardware
monitor (fans, temp, etc) from the Fintek Super I/O datasheet.

Change-Id: Ifc025cb92d0fc4e8f813091d00a6c87deae05863
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5383
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:44 +01:00
Edward O'Callaghan 236cf47513 mainboard/jetway/nf81-t56n-lf: Remove hard-coded IMC fan craft.
Fan controls in 0x400-0x4ff are not programmed here. Thus fan
control from amd/persimmon in the devicetree.cb does not apply
to this board.

Change-Id: I9156143476df0a7b44c7af90fa2107e8a8ba851e
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5381
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-13 20:25:22 +01:00
Duncan Laurie 714b1e8b6c rambi: Enable USB boot with EHCI controller
This adds the EHCI driver back to libpayload and configures
the devicetree to route ports to EHCI.

This is hopefully just temporary until the issues with XHCI
can be worked out.

BUG=chrome-os-partner:23635
BRANCH=rambi
TEST=build and boot from USB on rambi

Change-Id: I0549661f5e5fd83477f4839a05e7e21175b24b64
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/175513
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-11 19:55:58 +01:00
WANG Siyuan 62a3f6f665 AMD Olive Hill: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Olive Hill.

Change-Id: I1748e8c92fb72a82bac0506ecdf98304a5bd8239
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4301
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:07:53 +01:00
WANG Siyuan d5813530fa AMD Parmer: add IMC fan control
There are 3 steps to enable the IMC fan control:
1. Enable fan control related registers on Hudson using oem_fan_control().
2. Set EcStruct.
3. Enable thermal zone using enable_imc_thermal_zone().
I have tested on Parmer.

Change-Id: Id11d5c5da30346c034d155a73749e7f4c9c980eb
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4302
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-03-10 18:06:09 +01:00
Edward O'Callaghan b66d53ac10 mainboard/jetway/nf81-t56n-lf: Turn PS/2 driver on by default.
This board has a working PS/2 port for a keyboard. Thus, it
makes for a good option to have on by default.

Change-Id: Ifcde0474d7be26152f1b5e19fe4906e87732b9a4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5357
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-09 16:20:09 +01:00
Edward O'Callaghan bfa29dc021 mainboard/jetway/nf81-t56n-lf: Fix GPP missing CLK on PCI bridge.
The platform dependent mainboard.c was incorrectly disabling the
second clock signal feeding the GPP ports. This results in
spurious hangs by calling the set_pcie_dereset() SB CIMx callback
many times. This also stops coreboot from finding the second NIC
behind the pci 15.0 bridge.

Change-Id: I9f2370f6e05d1c5532fbca8203e32ab1ff15266a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5355
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-03-09 13:38:49 +01:00
Kyösti Mälkki 8340666cb1 intel/jarrell: Apply ROMCC workaround
Taken from intel/xe7501devkit, maybe it had same symptoms once.

The call to ich5_watchdog_on() has side-effect of exploding the
requirements for ROMCC internal arrays at compile-time. The hard-coded
limit in question is MAX_RHS in util/romcc.c, the default of 127 comes
from the rhs field defined with 7 bits.

Before this patch intel/jarrell builds were using upto MAX_RHS=102, while
other ROMCC boards built even with MAX_RHS=10. This workaround brings
intel/jarrell to the same level.

Change-Id: I162d801f81d9196403d88636eb9cb291c950ded0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5348
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-09 13:09:48 +01:00
Kyösti Mälkki 233f5b3b0e ROMCC: Trigger internal compiler failure and apply the workaround
These boards first failed when attempting to change print_err() from
direct function call to console_tx_XX() to a code block in the form of

 do { if (y) console_tx_XX(x); } while(0)

Removing the label dummy_romcc_workaround_label added here will
trigger the following compiler error for the two boards:

  Internal compiler error: no edge to block->last->next

Change-Id: I997adfaf586d7fa2096401dd574b07ce676d0ac6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5349
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-08 19:24:22 +01:00
Patrick Georgi 946923b0fb qemu-i440fx: add a prototype for main()
This probably belongs elsewhere, but I haven't found a nice place yet.

Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-08 15:05:53 +01:00
Kyösti Mälkki 1d7541feeb console: Fix includes
Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.

Move prototypes for UARTs next to other consoles.

Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:26:08 +01:00
Kyösti Mälkki 7e75f20477 pl011 UART: Move under drivers/uart
Currently this is only a minimal stub to get console on qemu-armv7.

Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5162
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:25:15 +01:00
Kyösti Mälkki c76b3d6cca uart: Drop HAVE_UART_MEMORY_MAPPED
This option is used to make uart8250mem option visible in menuconfig.
Showing it for these ARMs is incorrect.

Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5259
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:19:28 +01:00
Edward O'Callaghan 93fa422dea jetway/nf81-t56n-lf: Minor corrections to devicetree.cb
The miniPCIe ports hanging off 15.0 are infact x1, as are the two
onboard NIC's on 6.0 and 15.0.

Change-Id: I6247838f6b5823369543e338975a4c5c6fd00d7c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5328
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04 15:01:34 +01:00
Edward O'Callaghan ba88506812 jetway/nf81-t56n-lf: Fix PS/2 ACPI for KBC & Mouse.
Provide ACPI table node so that the PS/2 keyboard/mouse port works
in GNU/Linux.

Change-Id: If73b8d37a81bb9066cbcc650b518d25e243b84e7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5327
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-04 15:00:19 +01:00
Vladimir Serbinenko 131573056f nehalem: Replace video init.
Old video init just replayed the sequence.
This one actually computes the values.

Change-Id: Ic1fe7a2e90dc2cc36ac0d8bcea5cfabc583f09a3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5270
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-03-04 00:41:05 +01:00
Vladimir Serbinenko db7d04d1b7 qemu: Support textmode gfx init.
Change-Id: I8b6b14b4fcf8df21d8bbf988d640b1efa013bd7f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5283
Tested-by: build bot (Jenkins)
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-03-03 23:14:04 +01:00
Vladimir Serbinenko 9817a37416 nehalem/raminit: Don't touch clock generator in raminit.
Clock generator is mobo-specific. Don't touch it in raminit.

Change-Id: Ie114696b7fb13b8daee8dd1393d43bc609e149b3
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5265
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-03-03 20:55:26 +01:00
Vladimir Serbinenko 5ca914bc64 lenovo/x60: Unify volume button handling with common code.
Change-Id: I45fe44a91f9f83a510b204e01dbaff9e8a9696ca
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5099
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-03-01 21:59:15 +01:00
Vladimir Serbinenko 770c71f3ec lenovo/x201: Move mainboard init to mainboard_init.
Rather than having it inside mainboard_enable.

Change-Id: Ie8bd25eb49b919b4e25c4628e3557fc66b2ba4d9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4840
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-01 00:45:28 +01:00
Aaron Durbin 61cd57ba36 baytrail: fix uninitialized acpi structures
The callers of the following functions assume the storage
area provided by the pointers is initialized. That's not the
case as these were just place holders.
- void acpi_create_intel_hpet(acpi_hpet_t * hpet);
- void acpi_create_serialio_ssdt(acpi_header_t *ssdt);

To fix this properly initialize the hpet entry, and just remove
the serialio_ssdt function entirely.

BUG=chrome-os-partner:23505
BRANCH=None
TEST=Built and booted through depthcharge on rambi. Noted no more
     ACPI errors relating to invalid length.

Change-Id: If56ab033562ef2d755e9c9de42f507c95d291aba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/174716
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4917
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-27 06:34:05 +01:00