This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.
Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope
Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPP_B4 to low in S5 to meet touch panel power sequence
BUG=b:124197348
BRANCH=master
TEST=Verify GPP_B4 is low.
Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding Kohaku as a variant of hatch.
BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_KOHAKU is built as well.
Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This option is duplicated in depthcharge:
https://crrev.com/c/1545144
BUG=b:124141368, b:124192753, chromium:943150
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1545144
BRANCH=none
Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Follow thermal table for second tunning.
BUG=b:129509918
TEST=Built and tested on sarien system
Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The sku ids are updated for Pantheon.
Sync'ing the sku_ids list in the master sku sheet for Pantheon.
BUG=b:121207221
BRANCH=firmware-nami-10775.B
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: Ibf683ca8219b2980ea9d9c40b06db264d58440b0
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
For HW require to change GPIO_E1.
Change GOIO_E1 setting from NF2(SATAGP1) to NF1(SATAPCIE1).
BUG=b:123730924
TEST=flash BIOS and make sure hatch boots up properly
Change-Id: I0f5569e13b17a2dc713be5031a63436e8f31f911
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32099
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_A12 has a Native3 (SX_EXIT_HOLDOFF#) mode, which allows to delay
resuming to S0. If this pad is not locked and platform was not initially
designed for this functionality, malware could reconfigure this pads
setting under OS (switch to Native3), which would make platform not able
to resume until G3 is applied. To prevent misuse of this pad,
re-configure this pad before entering S3 and S5 to guarantee that the
pad configuration is correct.
BUG=b:128686027
Change-Id: I1e7979baa491acf2c56d223afb4618f0f6429e37
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The dead_code() macro can be used to ensure that a certain code path is
compile-time eliminated (e.g. if you want to make sure it's never
executed for certain Kconfig combinations). Unfortunately, the current
implementation via __attribute__((error)) hits only at the GCC level.
This can catch code that can be compile-time eliminated based on state
within the same file, but it cannot be used in cases where a certain
library function is built but then garbage collected at link time.
This patch improves the macro by relying solely on the linker finding an
undefined reference. Unfortunately this makes the error message a little
less expressive (can no longer pass a custom string), but it is still
readable and one can add code comments next to the assertion to
elaborate further if necessary
Change-Id: I63399dc484e2150d8c027bc0256d9285e471f7cc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.
Bug=b:129375810
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in. Also confirm bluetooth itself is
functional.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I79a310a55d94d7d20d1705afc11fe47cbb81abc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
GPP_A12 is being used as FPMCU_RST in hatch. This GPIO is being padlocked in
FSP and cannot used in kernel. Hence unlock the GPIO pads to export this pin
in kernel to be used as FPMCU_RST.
BUG=b:128686027
BRANCH=None
TEST=Read Pad Configuration Lock (PADCFGLOCK_GPP_A_0) register.
localhost /sys/class/gpio # iotools mmio_read32 0xfd6e0080
0x00000000
localhost /sys/class/gpio # echo 212 > export
Change-Id: Ie0439956e6c8e386435e535665ccaf2ab82adeb0
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32126
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select support in Kconfig and configure device in devicetree
Tested with ASUS addon TPM modules, v1.2 (ASUS TPM-L FW3.19 rev1.02H) and v2.0 (ASUS TPM-L R2.0 rev1.00) using SeaBIOS and Linux OS
Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7
Signed-off-by: Simon Newton <simon.newton@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Touchscreen lost function after boot with stylus
touching the screen
BUG=b:128554235
Signed-off-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Change-Id: I692fc6f245b7fade67862da4986a83d11a2cd51f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32100
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Deassert EN_PP3300_WWAN to turn the WWAN module completely off when
entering S5. This is the same fix in commit eeb475c5c for coral board.
BUG=none
BRANCH=none
TEST=On hatch, Perform a quick system power cycle, verify that the modem
is powered cycle and the SIM with PIN lock enabled requests unlocking.
Change-Id: I3ec8ccb7618189b9e8586f5571a68d3309597ee7
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When in romstage call into the EC init function so it can send a
progress code to the EC before memory training starts.
BUG=b:127875364
TEST=boot with FSP debug and ensure EC does not try to turn off the
system while it is still booting.
Change-Id: I5d99fb16bae250a82b652c530c13977e74c3378b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable USB support for mistral in romstage.
TEST=build & run
Change-Id: I5c2bbe16aa3601e014a2b77d192565402ed23794
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
As part of chromium:942901, physical dev switch functionality
is being deprecated.
Remove remaining references as well as helper macros.
BUG=chromium:942901
TEST=Build locally
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ib4eec083eb76d41b47685701f9394c684ddc6b37
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This adds DPTF based Fan speed control for CML based Hatch system.
BUG=None
BRANCH=None
TEST=Built and tested fan speed with different temperatures
Change-Id: I3c2a679dc67eecb17098ce0f0c9703c679473a2d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Rowan board is dead, dissect it out of Oak.
Signed-off-by: Evan Green <evgreen@chromium.org>
BUG=chromium:840888
BRANCH=none
TEST=emerge-oak coreboot chromeos-bootimage
CQ-DEPEND=CL:1538915,CL:*1087044
Change-Id: Ifb19fa0cd814853270847bc14fc21c841d905146
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32061
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the latest hatch schematics, BOOT1 for the FP MCU is now connected
to the AP. Configuring it to be the same as BOOT0.
BUG=b:126455006
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/hatch -x -a -c max
Change-Id: Ibb451983674a7d812dc562cb8addb1dc50fb155c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set tcc_offset value to 10C. It configures the Thermal Control Circuit (TCC)
activation value to 90C. This prevents any abrupt thermal shutdown by taking
early thermal throttling action when CPU temperature goes above 90C.
Change-Id: Ifee0fcc326530622b04e60af0f3b9cb9e3aea7ea
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31984
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After raminit completes, do a read-modify-write test
just below CBMEM top address. If test fails, die().
Change-Id: I33d4153a5ce0908b8889517394afb46f1ca28f92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove bip, as it is no longer actively developed, and its EC
overflowed storage, so the EC build is no longer viable.
BUG=b:129283539
BRANCH=none
TEST=emerge-octopus coreboot chromeos-bootimage
CQ-DEPEND=CL:1538819,CL:*1086038
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: Ie9ffa704af3523908858d382e2c188422323550e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of manually filling out the lb_gpios struct,
use the newer lb_add_gpios notation, which is more
compact and less error-prone.
BUG=b:124141368
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
BRANCH=none
Change-Id: I90795f32be5de881c94519933f36127098c184df
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32031
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently only two devices make use of physical dev switch:
stumpy, lumpy
Deprecate this switch. If these devices are flashed to ToT,
they may still make use of virtual dev switch, activated
via recovery screen.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I87ec0db6148c1727b95475d94e3e3f6e7ec83193
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31943
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This option has been relocated to depthcharge:
https://crrev.com/c/1524806
BUG=b:124141368, b:124192753
TEST=Build and deploy to eve
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1524806
BRANCH=none
Change-Id: Ib4a83af2ba143577a064fc0d72c9bc318db56adc
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31909
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch cleans up remaining uses of raw boolean Kconfig values I
could find by wrapping them with CONFIG(). The remaining naked config
value warnings in the code should all be false positives now (although
the process was semi-manual and involved some eyeballing so I may have
missed a few).
Change-Id: Ifa0573a535addc3354a74e944c0920befb0666be
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to
the first three functions of 1c.
Confirmed on a p5q_pro board.
Change-Id: I779400494e27bf046996512d1f772311e6e4e091
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
gale has a button which is essentially used as a
"physical presence" button. Its only use is to emulate
^D or ^U on boot when the button is pressed.
(See depthcharge src/board/gale/board.c)
Previously (and currently in CrOS firmware branch) this
GPIO was defined as the physical developer switch,
and read as such in depthcharge. It was removed in
cleanup patch CB:18980.
Add the GPIO back as physical presence ("presence"),
which will be read by depthcharge in CL:1532492.
BUG=b:124141368, b:124192753, chromium:942901
TEST=util/lint/checkpatch.pl -g origin/master..HEAD
TEST=util/abuild/abuild -B -e -y -c 50 -p none -x
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic144f839b7f9933d573db8f84c4bf5905eea96f6
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
The TPM driver isn't loaded in other stages but verstage so when we try
to communicate with the TPM it fails. We don't need to communicate with
it anyway since the TPM won't continue to tell us that recovery was
requested, only the first query responds with the recovery request.
BRANCH=none
BUG=b:129150074,b:123360379
TEST=1)boot arcada without recovery and notice that the "tpm transaction
failed" log lines are no longer present. 2) boot into recovery using the
ESC refresh power key combination and verify that the recovery reason
was "recovery button pressed"
Change-Id: I13284483d069ed50b0d16b36d0120d006485f7f4
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.
The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.
Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We have more test data now so update the DPTF accordingly.
* Change passive temp to 50/57/55/52 C
* Change critical temp to 75C
* All interval to 20 secs
BUG=b:113101335
TEST=temp/perf looks better in thermal chamber test.
Change-Id: I872c3f1875d0cbac148c44c449954e6871c9d0b0
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
AP communicates with FP MCU through gspi1.
BUG=b:126455006
BRANCH=None
TEST=ensure during bootup we see spi id spi-PRP0001:01 in dmesg
FP MCU fw is not ready yet, so not much testing to be done yet.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I2eba205d5e63664dca684fbd849454c5a2fe0d0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32017
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bloog supports keyboard backlight feature, so enable the ASL code.
BUG=b:127736039
BRANCH=octopus
TEST=Build and boot bloog, verify that the string 'KBLT' is in the DSDT.
Change-Id: Iba66aade090816ea2376cae4baf4aae019cc97f4
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These signatures need to be consistent across different
architectures.
Change-Id: Ide8502ee8cda8995828c77fe1674d8ba6f3aa15f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add SAR0, which is an SX9310. The schematics and layout have a second
SAR1 sensor provisioned on I2C4, with an interrupt of GPP_A6, but this
is not populated.
Signed-off-by: Evan Green <evgreen@chromium.org>
BUG=b:128540461
BRANCH=none
TEST=Boot kernel with sx9310 driver, see it come up happily
Change-Id: I63943cc7da5ff56f6ef6dcbd99bb8f8f031e8bf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable the HUNG_TASK as a wakeup host event, as it's used by S0ix failure
detection to wake the system back up if a suspend to S0ix never
asserted S0_SLP#.
BUG=b:123716513
BRANCH=None
TEST=Test S0ix on Hatch with appropriate EC and kernel changes.
Signed-off-by: Evan Green <evgreen@chromium.org>
Change-Id: I447211892df210af97e8df0380bab032b14cbee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32004
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Depthcharge is changing how the RW_LEGACY CBFS is handled for alternate
bootloaders, see https://crrev.com/c/1528550 and
https://crrev.com/c/1530303. This means that RW_LEGACY must be marked as
CBFS in the fmap in order to work. All boards except for kahlee(grunt)
have CBFS marked.
BUG=b:128703316
TEST=Build and ran on grunt along with chromium patches on grunt and was
able to list alternate bootloader with ctrl+l
BRANCH=none
Change-Id: I843d565a9503d27e666a34e59aba263ec490c81f
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32019
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Assign the FSP UPDs for HPD and DDC of DDI ports. FSP assumes that all
DDI ports are enabled and hence configures the HPD and CLK for DDI ports.
This patch initializes only the required UPDs to enable display ports.
BUG=b:123907904
TEST=DP devices working correctly.
Change-Id: Ic0c172cd3d087fc8f49b01ab23feffdababf7166
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Motivation is to reduce use of !__PRE_RAM__, it does not
mean ENV_RAMSTAGE but we also exclude ENV_SMM with the change.
Change-Id: I1f96bb8c055a3da63274e1ab7f7d4bc70867cbf1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
To support both boards with the same firmware add a SKU for
each variant that is used to include the proper EC firmware
image to match what the EC is expecting.
BUG=b:119490232
TEST=tested by faking the EC response to ensure that the OS
and firmware update tools are able to determine the correct
model based on the value returned by the EC.
Change-Id: Iaa677975e0bccbee5ec8a39821fe1637f08270fa
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch adds support to copy the wifi calibration
data to CBMEM so that the depthcharge can use it to
populate the data into wifi dt node.
Change-Id: Ia8184e48a7176bb3b52e4d43866b7d065952c13e
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This board is compatible with Intel Skylake and Kaby Lake generation
processors. This patch contains the minimum configuration for booting
and stable operation of the Ubuntu OS (18.04.1, Linux kernel 4.15).
It is based on Intel RVP8 mainboard.
Intel Kaby Lake FSP 3.6.0 is used to initialize CPU and PCH.
Graphics init with libgfxinit.
Works:
- Integrated graphics (only DVI port, tested with 1920x1080);
- PEG x16 (FSP must be configured with BCT to enable PEG);
- all PCIe x1 slots;
- all USB and SATA ports;
- SuperIO COM port for console;
- onboard audio.
TODO:
- other SuperIO functions;
- onboard network chip;
- suspend and resume;
- documentation.
Tested on Intel Core i5-6600 processor with Seabios (rel-1.12.0-10-
g171fc89) and Tianocore/edk2 (vUDK2018-8-ge6eccfc) as a payload.
Change-Id: I69396edc50948cf1d0da649241ce92171d32daf7
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Adding a new board variant 'Mistral' based on qcs405 soc.
TEST=build
Change-Id: I7ecfad68bb50f42acf36f51bc3433add56597c3d
Signed-off-by: Sricharan R <sricharan@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
V1CAP is a write-once register, and it is already programmed in
intel/i945/early_init.c.
Tested on 945G-M4 board (i945G + 82801GB).
Change-Id: I4469cb7505d584f10c98aec579a2d78bf1950bf3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add bluetooth Rfkill function to recover the Bluetooth controller in
cases where itself has entered a bad state and needs to be recovered.
Bug=b:123342945
TEST=Boot up into OS and dump SSDT table, check there's _DSD entry under
Bluetooth devices with GPIO in.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibbe67887227af42b6c040deade7bf5da4ce3227f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disable the use of AMD's Secure OS through the Kconfig option.
BUG=chromium:903833
TEST=Build google/aleena, verify types 02, 0c, 0d are removed
from PSP directory table
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iabb0632eef88170dde45dea2e2e15b54b3a06f7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This patch overrides required LPSS FSP UPDs for CMLRVP from devicetree.cb
File devicetree-override.cb will override required UPDs and is only
applicable to CML soc for now
Change-Id: I82e3323df952762e2d9c14f1e3cfa75872ccc9b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31285
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We were used to set the same values in the system and board tables.
We'll keep the mainboard values as defaults for the system tables,
so nothing changes unless somebody overrides the system table hooks.
Change-Id: I3c9c95a1307529c3137647a161a698a4c3daa0ae
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Accoriding to 574354, we need to tune each port to pass eye diagram
other than just use recommanded setting as they are base guidence only.
Bug=b:124407280
TEST=Build and boot up on arcada board.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I587695809b368edd33852c4241de097ca31e9d66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31632
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The copyright notices of Eltan B.V. have been removed by mistake before
sending the patch with board support. Revert back to be consent with the
license.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic5948ab60a661ef78e4e5c8571535a096fc88ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
From doc#573387 CML System Memory DQ DQS Rcomp Mapping Information
User Guide, RCompResistor[0] should be 121.
BUG=b:122959294
BRANCH=None
TEST=emerge coreboot and make sure boots up
Change-Id: If69e7fb41e79d88d21b0e50fb65107a1686d696a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31868
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MEM_CH_SEL is used to indicate whether we are on a single or dual
channel device, where MEM_CH_SEL = 1 for single channel skus and
MEM_CH_SEL = 0 for dual channel skus. Initialize single_channel field
(from GPP_F2), which will in turn initialize MemorySpdPtr pointers in
cannonlake soc code. In the first build, we did not use GPP_F2, so we
need to add an internal pulldown as those early devices were all dual
channel devices.
BUG=b:123062346, b:122959294
BRANCH=None
TEST=Boot into current boards and ensure that we have 2 channels as expected
Also, verify that GPP_F2 is set to 0.
Change-Id: I89d022793580be603a93d0b177d73ce968529b5c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The board version is part of EC's EEPROM, select Kconfig items to enable
requesting the EC for board version.
BUG=b:128385395
TEST=Verified the mainboard version is from EC's EEPROM.
Change-Id: I4bc1cac43c6cf73522f3a4bee89cc000a430d996
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31858
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On" to the Thinkpad
x1_carbon_gen1 board as well, as it seems to work fine on all
generations.
See also commit 7ffb329f with Change-Id
I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281 ("mb/lenovo/*/cmos: Port USB
Always On").
Note that we don't need to call h8_usb_always_on() directly since commit
4f4322dd with Change-Id If812cd1ef8fb1a24d7fadbe834f574b40cbcd56a
("lenovo/h8,thinkpads: Re-do USB Always On").
Change-Id: Ib9070b659b0c9ad5dde4200ec2845c6fa2b78b25
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Like with any other Thinkpad, call MUTE(1) and USBP(0) on _PTS on the
Lenovo Thinkpad X1 Carbon 1st generation.
Without MUTE(1) the speakers sometimes glitch before going into S3 (if not
muted), while without USBP(0) the USB ports are always powered in S3,
regardless of the USB Always-On mode selected.
Change-Id: I86f3c5a72e2589c5570303bf68f39df3ef874cb8
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change reads DRAM part number from EEPROM if available and
returns it using the SoC callback (mainboard_get_dram_part_number).
BUG=b:127609572
TEST=Verify that DRAM part number from EEPROM is added to DMI table
17 (dmidecode -t 17).
Change-Id: I6ade6999828b6d67aa78d04199138f195a97ba8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adding Hatch_whl as a variant of hatch. This is a snapshot of the WHL
version of hatch so that we can rebuild the bios images for Hatch with
WHL SoC.
BUG=b:127310803
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_WHL is built as well.
Change-Id: I24510fa226878582a61f1846f0b56a2c65204a92
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Following changes are done to enable audio support on hatch
1. Enable I2C4 device at 400Khz at 1.8V
2. Configure GPIO for HP INT and SPKR_PA_EN
3. Add ACPI entry for RT5682 and MAX98357A
4. Enable I2S0 and I2S1 lines
5. Enable generic max98357a driver in Kconfig
BUG=b:123738217
BRANCH=none
TEST=Check SSDT table for RT5682 & MAX98357a entry.
Verify audio using Sound Open firmware (SOF)
Change-Id: I93f3917c19cc3f0f8fd7b5e1b4d9b24a59f45f84
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In preparation for the transition of hatch from WHL to CML, we are
creating a checkpoint called hatch_whl that we can use for creating
firmware compatible with the WHL hatch variant.
BUG=b:127310803
BRANCH=NONE
TEST=NONE
Change-Id: Iecae584ee6feefcf29955a4720e9c24bdc8abe6d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add new Pantheon sku-id for loading vbt-pantheon.bin
BUG=b:78663963
BRANCH=firmware-nami-10775.B
TEST=Boots to OS and display comes up.
Change-Id: Icd56905e1e04de6f307393ae23f741b93ff23a4c
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31747
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We want to publish "arcada_ish.bin" as the fw name for Integrated
Sensor Hub (ISH) so the kernel shim loader code can use it to
construct the correct path in /lib/firmware/intel for the firmware
load process.
BUG=b:122722008
TEST=Verify that shim loader CLs use new value when constructing
firmware path
Change-Id: I6299de82566a3bad8521f8158bb047d5c1ff0cf8
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are two known reverse-engineered ways to manage battery
thresholds.
This patch implements them and adds a way to enable them for
different mainboards.
Tested on W530 with 4.18.3-gentoo kernel and X220 with 4.20.11.
Works fine with new Linux userspace API for controlling battery
thresholds, available since 4.17.
(/sys/class/power_supply/BAT0/charge_(start|stop)_threshold).
The new API is supported by TLP (you might need to set NATACPI_ENABLE=1
in /etc/tlp.conf).
tpacpi-bat works fine too.
Signed-off-by: Alexey Kharlamov <der@2-47.ru>
Signed-off-by: Evgeny Zinoviev <me@ch1p.com>
Change-Id: I2a90f9e9b32462b8a5e9bc8d3087ae0fea563ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/23178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
For Chrome OS (or vboot), The PRESERVE flags should be applied on
following sections:
RO_PRESERVE, RO_VPD, RW_PRESERVE, RW_ELOG, RW_NVRAM, RW_SMMSTORE,
RW_VPD, RO_FSG (b:116326638), SI_GBE (chromium:936768),
SI_PDR (chromium:936768)
With the new PRESERVE flag, we don't need RO_PRESERVE and RW_PRESERVE in
the future. But it's still no harm to use it if there are multiple
sections all needing to be preserved.
BUG=chromium:936768
TEST=Builds google/eve and google/kukui inside Chrome OS source tree.
Also boots successfully on eve and kukui devices.
Change-Id: I6664ae3d955001ed14374e2788d400ba5fb9b7f8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Qemu does not have a real CAR but postcar stage is still useful
for testing the stage.
The postcar stage is also mandatory for x86_64 to setup
pagetables for x86_64 ramstage.
Do not set up MTRRs, as qemu ignores them anyways.
Tested on qemu-i440fx and qemu-q35.
Change-Id: I6638534d99fde312e55b6a6be8c95e4cb25cca80
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The function (preprocessor macro) we need is defined
in <endian.h> not <swab.h>.
Change-Id: I3a86c7050bf853e3a56a15421132240e19f40912
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enable the support for providing a MAC address for a dock to use based on
the VPD values set in the platform.
BUG=b:123925776
TEST=tested on sarien by setting VPD values and observing the string
returned by the AMAC() method:
> vpd -i RO_VPD -s "ethernet_mac0"="AA:AA:AA:AA:AA:AA"
> vpd -i RO_VPD -s "dock_mac"="BB:BB:BB:BB:BB:BB"
1) Test with no policy set, returns "dock_mac"
ACPI Debug: "VPD region RW did not verify"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
2) Test with policy set to "builtin", returns nothing
> vpd -i RW_VPD -s "dock_passthru"="builtin"
ACPI Debug: "Found VPD KEY dock_passthru = builtin" [AMAC returns Zero]
3) Test with policy set to "ethernet_mac0"
> vpd -i RW_VPD -s "dock_passthru"="ethernet_mac0"
ACPI Debug: "Found VPD KEY dock_passthru = ethernet_mac0"
ACPI Debug: "Found VPD KEY ethernet_mac0 = AA:AA:AA:AA:AA:AA"
ACPI Debug: "MAC address returned from VPD: AA:AA:AA:AA:AA:AA"
ACPI Debug: "AMAC = _AUXMAC_#AAAAAAAAAAAA#"
4) Test with policy set to "dock_mac"
> vpd -i RW_VPD -s "dock_passthru"="dock_mac"
ACPI Debug: "Found VPD KEY dock_passthru = dock_mac"
ACPI Debug: "Found VPD KEY dock_mac = BB:BB:BB:BB:BB:BB"
ACPI Debug: "MAC address returned from VPD: BB:BB:BB:BB:BB:BB"
ACPI Debug: "AMAC = _AUXMAC_#BBBBBBBBBBBB#"
Change-Id: I90474e264cc433c0fd1a4b0dbaf98e5f74180d54
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Since ACPI v2.c, this field is access_size.
Currently, coreboot is using ACPI v3,so we can drop '.resv' field.
Change-Id: I7b3b930861669bb05cdc8e81f6502476a0568fe0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In order to prevent keyboard keys pressed at boot from causing issues
in the payload remove the PS2 keyboard driver so it does not get
initialized until it is needed in libpayload.
This was enabled initially because the keyboard controller on this
platform does not come up in translated mode, so unless coreboot
called keyboard_init() the keyboard would never work properly in the
kernel because it would come up as an "AT Raw" device instead of an
"AT Translated" device.
Instead of initializing the keyboard in coreboot a workaround is
added to the payload to put the keyboard into translated mode.
BUG=b:126633269
TEST=boot on sarien while pressing keys and ensure libpayload and/or
the kernel does not have any issues initializing the keyboard.
Change-Id: I765e808f0d2589cf23c0349798a07e2706a2a7a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We had two ways to configure the serial IRQ mode. One time in the
devicetree for FSP and one time through Kconfig for coreboot. We'll
use `enum serirq_mode` from soc/intel/common/ as a devicetree option
instead. As the default is `quiet mode` here and that is the most
common mode, this saves us a lot of lines.
In four cases kblrvp8, 11 and librem 13v2, 15v3, we had conflicting
settings in devicetree and Kconfig. We'll maintain the `continuous`
selection, although it might be that coreboot overrode this earlier
on the kblrvps.
Note: A lot of Google boards have serial IRQ enabled, while the pin
seems to be unconnected?
Change-Id: I79f0cd302e335d8dcf8bf6bc32f3d40ca6713e5c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
INT_MODEL defined in ACPI 1.0 and renamed to reserved since V 2.0.
The value for this field is zero but 1 is allowed to maintain
compatibility with ACPI 1.0.
So set this value to zero as we are using greater version than ACPI 1.0.
Change-Id: I910ead4e5618c958a7989f4c309a3a4bb938e31a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: David Guckian
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This mainboard has a TPM located on the LPC bus. Enable the driver for
it so that it is initialized and the ACPI table entry is generated.
Change-Id: I2eae63932658c2a9f752d28d7c08c27f48531360
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On Sarien, change pin config of 0x19 (headset mic) and
0x21(headset headphone) to change jack location so that naming does
not use "Front" in the name."Front Headphone" --> "Headphone" so it
matches naming on Arcada.
BUG=b:126334749
TEST= verify with 'evtest' command that jack name is
"HDA Intel PCH Headphone" not "HDA Intel PCH Front Headphone"
Change-Id: I36ccf0c0a3952ab363fe6ee313fac8f0cce4dd61
Signed-off-by: Joyce Toh <joyce.toh@intel.com>
Reviewed-on: https://review.coreboot.org/c/31624
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The fdt in the maskrom cannot be used to start linux. The correct fdt
is dumped by replacing the bbl of the original firmware and used in
coreboot.
Correct the mac address in fdt by reading otp
Change-Id: Ic29f0e590311360b85fafd12ebc36cd189fbbc38
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/c/31047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Preliminary dptf change for Atlas
- Throttle charger using all temp sensors (not just ambient)
- Throttle charger with higher priority than CPU
- Update throttle temperature using data from surface thermistor
in thermal chamber test
BUG=b:113101335
BRANCH=None
TEST=based on preliminary data from thermal chamber test
Change-Id: Ic1ab72f569e8a4f7bffc5560518fb703d32f4b21
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
These marketing names are much easier to distinguish. My
mnemonic: Socket M => up to Merom, Socket P => up to Penryn.
Change-Id: I3c2a59596cf7f3cd763bd79962ad326ab080677b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31645
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The name was wrong. mFCPGA478 is actually a pseudonym for mPGA478MN,
the successor of the socket that was meant.
The official name of this socket is mPGA478MT. But "Socket M" is much
easier to distinguish.
Change-Id: I4efeaca69acddfcdc5e957b0b521544314d46eeb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
coreboot did not program all GPIOs from C0 to C7 correctly which are
SMBUS GPIO. Some of the GPIOs are left in default mode which is
native function but we need to configure as GPIO mode and provide proper
configuration as per schematic.
After fixing GPIO, CSME power gating issue also gets fixed since SMBUS was not
getting idle due to GPIO configuration and CSME was not getting power
gated due to SMBUS.
BUG=b:123702553
BRANCH=none
TEST=Check on hatch board. CSME was not getting power gated for s0ix.
After applying this patch CSME is power gated now
Change-Id: I5c6b9310dcc7bade0023abd5524781ce71df28be
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Initialize RTC at ROM stage.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: I9d9c68755e8a6ac65dd794211e6ccf06e5057567
Signed-off-by: Ran Bi <ran.bi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/31508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.
Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of using 2, 0 is now used for non-CBI provisioned board or
corrupted CBI board to confrom to the sku encoding.
BUG=b:123676982
BRANCH=kukui
TEST=test with un-provisioned board to verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I66f29f8a46cd774b40354def7d3623ec44cb96ce
Reviewed-on: https://review.coreboot.org/c/31623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Hatch implements active high SD_PWR_EN and requires a workaround
in _PS0 and _PS3 control methods to make sure SD_PWR_EN stays low
in D3. Select MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE to enable the same.
BUG=b:123350329
Change-Id: I96ab9660eb50100207fe9a237f5924b65eae0928
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SD_CD# in Cannonlake PCH is also wired to an internal virtual GPIO,
expose that GPIO for kernel to configure card detect IRQ.
BUG=b:123350329
Change-Id: I566cc2eb11dc257366897a1efba905b8ddcf493d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/31553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from Chromium commit 5351dc0d
[Edgar: To set the RX ODT limit and dram geometry with RAMID detection]
Several cyan variants require memory init parameters be passed to FSP
for handling of specific Micron modules; without these, RAM init will
fail when loading training data from the MRC cache, and boot will halt.
This was missed when I upstreamed edgar along with the other cyan
variants, so add the required memory init parameters for edgar as per
its source Chromium branch.
Test: build/boot on edgar board with affected Micron memory
modules, verify boot successful with populated MRC cache.
Change-Id: I6a2bc30b54ff1a17c854a90dfcb2308d27ee2be7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31615
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On flapjack, retrieve the board information via CBI interface.
Also reserving 0x2 sku_id for the case of un-provisioned board as this is the id
used prior to the readiness of cbi.
BUG=b:123676982
BRANCH=kukui
TEST=provisioned cbi info and verify the sku_id.
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iad7a52df38e2045abbdded8ba0a1f1544de961fc
Reviewed-on: https://review.coreboot.org/c/31586
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The change bcd84fe "mb/emulation/qemu-i440fx: change file handling"
introduced a regression where it loads only 4 bytes of the
ACPI and SMBIOS table, instead of the whole table.
Load the whole ACPI and SMBIOS table.
Tested on Qemu using GNU/Linux.
Change-Id: Ibacbf7caab9be5f181c12e9dd39a2893b13cf6c9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/31593
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For some reason, wake does not currently work from GPP_D21, but IRQs
are working fine from that gpio. Thus, we have to switch IRQ to
GPP_D21 and wake to GPP_A21, which was previously used for IRQs from
the trackpad. Additionally, we need to use two gpios for irqs and
wake source at the moment because of b:123967687, where FSP is locking
down PCR and configuring ITSS. We need to configure the wake source
gpio as inverted and the IRQ gpio as non-inverted until the bug is
resolved.
BUG=b:121212459
BRANCH=None
TEST=run evtest with trackpad
Use trackpad with ChromeOS UI and make sure it reacts as expected.
Run powerd_dbus_suspend and press trackpad and make sure DUT
wakes.
Change-Id: I7b236136befc05c6586d9ba69185ed4b5d385273
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest rev. of the atlas board moves the WiFi wake source from
WAKE# to GPP_B7. The original GPP_A0 in the device tree is just
wrong. This also reconfigures DW1 to the GPP_B group so we can use
GPP_B7 as a wake source.
GPP_B7 is still configured as a no-connect in gpio.c, so this doesn't
actually enable WiFi wake. We'll follow up with another patch to set
up GPP_B7 properly on boards that support it.
BUG=b:122327852
BRANCH=none
TEST=atlas still boots
Change-Id: I1816500dd0ab6186fd51aa6945faf73d00c152fe
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We experienced booting issues during FSP-M phase. Applying fix that was
introduced for wedge100s - 817994c1be (mb/ocp/wedge100s/romstage:
Workaround broken platform state) - helped and systems started to
boot properly.
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ibfbe9d19c7413098c56d1b6131640097fdf731ab
Reviewed-on: https://review.coreboot.org/c/31435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When <symbols.h> was first introduced, it only declared a handful of
regions and we didn't expect that too many architectures and platforms
would need to add their own later. However, our amount of platforms has
greatly expanded since, and with them the need for more special memory
regions. The amount of code duplication is starting to get unsightly,
and platforms keep defining their own <soc/symbols.h> files that need
this as well.
This patch adds another macro to cut down the definition boilerplate.
Unfortunately, macros cannot define other macros when they're called, so
referring to region sizes as _name_size doesn't work anymore. This patch
replaces the scheme with REGION_SIZE(name).
Not touching the regions in the x86-specific <arch/symbols.h> yet since
they don't follow the standard _region/_eregion naming scheme. They can
be converted later if desired.
Change-Id: I44727d77d1de75882c72a94f29bd7e2c27741dd8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
EC software sync had been disabled because BIOS was not bundling a
useful EC image. This is no longer required. This CL removes that
change so EC software sync is enabled by default.
BUG=b:124208414
BRANCH=None
TEST=Tested with a system that have a different RW image and verified
that this image was overwritten to the one bundled in the BIOS and
that the EC was running its RW image.
Signed-off-by: Scott Collyer <scollyer@chromium.org>
Change-Id: Ic1ffdb62e9fa2cacb3296cb3807082f23e171ab5
Reviewed-on: https://review.coreboot.org/c/31537
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I139c5c7b33671e7ed0c04c06fb290e001e57a687
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Error spotted using IASL 20190215:
"Object is created temporarily in another method
and cannot be accessed"
Change-Id: I7da9dcd68f5eec6383de7370bc8ab35f96a90c06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch adds the _DSM method 5 and 6 for entering and exiting S0ix.
The _DSM method gets injected into DSDT table and called from kernel.
LPIT table is hardcoded in this patch but the proper way to implement
is to use inject_dsdt to make the _DSM methods available for soc's to
implement.
Calling the LPIT table from mainboard here so that with the current
implementation the platforms which do not have lpit support throw
compilation error.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ia908969decf7cf12f505becb4f4a4a9caa7ed6db
Reviewed-on: https://review.coreboot.org/c/31101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Every printk() call already does console_tx_flush()
so there should not be anything in transmit buffer
when we return from console_init().
Change-Id: Iff2927c02d2c8031907620a056782bb014f20162
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31369
Reviewed-by: Xiang Wang <wxjstz@126.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow b:123461432#5 to update GPIO H3(CNVI_EN#) for DVT1.
Update setting GPIO H3 to output and low level.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I6a56df9a7bf75f49133a646312ae5093c2652698
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Follow thermal table (b:123383634 comment#1) for EVT1 tunning.
BUG=b:123383634
TEST=Built and tested on sarien system
Change-Id: I22908e4bf39aedb8cf31a9060084f6f36bff56ca
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Use the common VMX implementation, and set IA32_FEATURE_CONTROL
lock bit per Kconfig *after* SGX is configured (as SGX also sets
bits on the IA32_FEATURE_CONTROL register).
As it is now correctly based on a Kconfig, the `VmxEnable` devicetree
setting vanishes.
Test: build/boot google/[chell,fizz], observe Virtualization enabled
under Windows 10 when VMX enabled and lock bit set.
Change-Id: Iea598cf74ba542a650433719f29cb5c9df700c0f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29682
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Intel SOC can only shadow the top 16MB of SPI into memory so
in order to make it easier to access the NVRAM region with memory
mapped interface move it above the much larger RW_LEGACY region.
I tested to confirm that this region can now be read via MMIO
interface and does not need to use the hwseq SPI controller.
Change-Id: Iafacb01eec07beaf474b6a1f2b36a77117e327da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Create VR settings configuration as per board design.
BUG=N/A
TEST=Build and boot up into sarien platform.
Change-Id: Ic196fd80e5211bd5146158d4d340b52c850a4e62
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/31404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Replace all instances, where 0 is used by the macro/define
`ACPI_FADT_LEGACY_FREE`.
Change-Id: I226b334620e0cdafc7639c7a76ea3a523ae53a74
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/31289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
CNVi Bluetooth module is at port 8 (zero-indexed) and not at port 9. Fix
the device configuration in the devicetree.
BUG=b:123296264
BRANCH=octopus
TEST=Boots to ChromeOS. Checked the SSDT table to ensure that the reset
gpio is exported under the device \_SB_.PCI0.XHCI.RHUB.HS09. Ensured
that the kernel btusb driver is able to find the exported GPIO in the
devices with CNVi BT module.
Change-Id: I302bc87b18a1aaad77bfb73d607ba28b89b79c14
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to request of comment 35, setting ELAN as the default.
BUG=b:122019253
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: Iee5e7a21545ca798c0c22f86906acc8e7d81e945
Reviewed-on: https://review.coreboot.org/c/31430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Eanble Elan touch for sarien EVT build
BUG=b:119763054
BRANCH=master
TEST=Verify touchscreen on sarien works with this change.
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Change-Id: I790436338705fc9d68f714245e9b9bb518ddb30a
Reviewed-on: https://review.coreboot.org/c/31413
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change bumps up the BIOS region to 28MiB to use the hole
between SI_ALL and SI_BIOS. Since this SPI flash part is 32MiB, only
the top 16MiB actually gets memory mapped. Thus, the change ensures
that only RW_LEGACY lies in the 12MiB that is not memory mapped.
BUG=b:123443737
TEST=Verified that hatch still boots up. Ensured that fmap dump looks
correct.
Change-Id: I5832d2b89c7eedfc270755e2add16131cfbddff4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This change enables mode change as a wake source for S3 and S0ix.
Change-Id: I2e7f9997776b1e024ea417eb69e6c2ffa8c62580
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Sarien board may have different touchscreen devices that use the
same I2C slave address but have different requirements such as needing
a special driver or ACPI configuration.
In order to support this the devicetree may be configured with multiple
devices at the same address and at boot time the unused devices will be
disabled.
Because there is no GPIO for selecting the device that is present it can
instead be selected with Kconfig, or by setting a VPD key to the HID of
the touchscreen device that is present. The default for Sarien devices
is to not enable a touchscreen for the OS.
The touchscreen selection is currently limited to the Sarien variant but
this also adds the touchscreen HID for Arcada to Kconfig so it would not
complain about the key not being set.
BUG=b:122019253
TEST=This was tested on a Sarien board by adding a second entry to the
devicetree at the same address. Without this change the SSDT is not
loaded by the kernel because of the address conflict. After this change
no touchscreen is enabled by default, but one can be selected with
Kconfig or by setting the 'touchscreen_hid' VPD key.
Change-Id: I4da12b1de0c551bcd89325fe0d8c66c6ffeb7afc
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/31295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Follow Northbay and intermal project to add GPIO H3(CNVI_EN#) for DVT1.
BUG=b:123461432
TEST=Built and tested on sarien system
Change-Id: I580a6e094d84a7bada534b14c2b65ecf4b9942b0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Follow b:123342945 to add GPIO H15(BT_RADIO_DIS#) for DVT1.
BUG=b:123342945
TEST=Built and tested on sarien system
Change-Id: I0caf97f6a2a8abf2914667350c76300733ead1b8
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/31330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Under some scenarios the key ladder on the Cr50 can get disabled. If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.
BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>
Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This implementation configures GPIO (GPP_A21, GPP_C21, GPP_D16)
pad in non-inversion mode i.e Rx PAD state is not inverted as
it is sent from GPIO to IOAPIC.
BUG=b:123315212
TEST=Tested for below:
-> Verify touchpad is working fine.
-> TPM init is successful and boot with fixed boot media.
Change-Id: I6034fd07ccc96a19218d57ef8bb9049c4b963ea5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/31328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I72effa93e36156ad35b3e45db449d8d0d0cabf06
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch enables TPM2 on LPC and adds the needed devicetree entry for
TPM for mc_apl4.
Test=mc_apl4 flashed, booted into Linux and checked via dmesg if TPM is
present
Change-Id: I9af7e1a8623302eca46f5ecd8e498678ccda92ad
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/31344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* Adding separate targets for 32bit and 64bit qemu
* Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv
* rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage.
This should probably be changed later.
TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands:
util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf
qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf
Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0
Signed-off-by: Philipp Hug <philipp@hug.cx>
Reviewed-on: https://review.coreboot.org/c/31253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
SPD data needs to remain within same chip -block
with device 0:18.2.
Change-Id: Ic12481b637ee5f5119faec3239b477f613e4e511
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
It needs to tune usb2eye setting for these ports:
USB2[4] - type-c port
USB2[6] - camera
BUG=b:122878632
BRANCH=octopus
TEST=built and passed usb2eye SI test
Change-Id: Iaa3adaab2f391e95730b141dc0237ca62c459e5a
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/31359
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We leave it to linker garbage collection to drop
unreferenced code and symbols from final object files.
Function declarations and definitions are to be guarded
with preprocessor directives only as a last resort.
Change-Id: Ie8748ccddc8e31569c58deba5d08c98a04326fa8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This board is EOL and has FSP2.0 support, so drop the older
version.
Change-Id: If5297e87c7a7422e1a129a2d8687fc86a5015a77
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
On this platform, interrupts are routed via the GPIO controller so need to be
registered using GpioInt instead of Interrupt.
BUG=b:123750725
BRANCH=grunt
TEST=MKBP events still received (with matching EC and kernel changes)
Change-Id: If499d24511bbaa7054207b7e0b98445723332c4f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable Core Performance Boost feature in automatic mode.
Also enable C6 state which is a dependency for proper CPB operation.
CPB allows to raise single core frequency from 1000MHz to 1400MHz
during high load if other cores idle. The processor has additional
boosted P-states when CPB is enabled, but these are hidden from OS.
TEST: Higher single-core CPU performance is indicated by increased
memory bandwidth as reported by memtest86+.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5e080bfaee06fd13cedf5151d4a598ec212213f2
Reviewed-on: https://review.coreboot.org/c/31229
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Traditionally, we have always allocated 1 DRAM ID per part number.
However, on nami, we have run out of DRAM IDs because we have
supported so many different parts. We are now adopting the use of
generic SPD files that are feature-based rather than specific to each
part, allowing us to support multiple parts with a single SPD.
The common SPDs were created by taking current SPDs in Nami (which is
using the same DDR4 parts as Hatch) and zeroing out all the
manufacturer information and part names. Additionally, we zeroed out
bytes 128 (raw card extension, module nominal height), 129 (module
maximum thickness), and 130 (reference raw card used) after verifying
that they are not used in FSP. We verified with these fields zeroed
out, all nami devices could boot up without errors. We also verified
on the two Hatch skus that we have (4G 2400, 8G 2666) that the generic
SPDs boot properly.
BUG=b:122959294
BRANCH=None
TEST=Make sure that we can boot up on both 4G Samsung and 8G Hynix DDR4
devices that we currently have.
Change-Id: I14d9e6b13975b6a65b506e6cd475160711b8f6d4
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/31261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Match devicetree what's present and in use.
Tested on wedge100s:
All PCI devices show up.
Change-Id: I669d059da1876ed669793db8c7eb1b96b481cb4c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/31228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Also includes lines sorted
Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"is_wakeup_source" flag is used to indicate if the concerned device can
trigger a wakeup. This flag is redundant with the "wake" GPE event
definition. So remove the redundant flag and use the "wake" GPE event to
mark the wakeup source.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS. Ensure that the device is marked as wakeup-source
in SSDT if wake GPE is configured. Ensure that the system can suspend
and the device acts as a wakeup source
Change-Id: I99237323639df1cb72e3a81bcfed869900a2eefa
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/31258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses cnl_configure_pads to configure GPIOs in ramstage so
that cannonlake SoC code can re-configure the GPIOs after FSP-S is
run. This is just adding a workaround until FSP-S is fixed.
BUG=b:123721147
BRANCH=None
TEST=Verified that there are no TPM IRQ timeouts in boot log on hatch.
Change-Id: I9973c6c49154f1225f0ac34a3240a0d19f911f18
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch performs below tasks
1. Create SOC_INTEL_COMMON_CANNONLAKE_BASE kconfig.
2. Allow required SoC to select this kconfig to extend CANNONLAKE
SoC support and add incremental changes.
3. Select correct SoC support for hatch, sarien, cflrvps
and whlrvp.
* Hatch is WHL SoC based board
* Sarien is WHL SoC based board
* CFLRVP U/8/11 are CFL SoC based board
* WHLRVP is based on WHL SoC
4. Add correct FSP blobs path for WHL SoC based designs.
Change-Id: I66b63361841f5a16615ddce4225c4f6182eabdb3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables I2C bus 2, 3 and 4 in devicetree and configures
GPIO pads for the same. It also configures pads for I2C5 as
no-connect.
BUG=b:123711244
TEST=Verified that i2c shows up in "i2cdetect -l" after booting to OS.
Change-Id: Ib4714a670d73228332115415e4393f82802c6475
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/31237
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
