There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is Garrett's patch with a bit of cleanup.
BUG=b:65442212
TEST=Was able to boot, suspend and resume on grunt.
Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Most things still need to be filled in, but this will allow us to build
boards which use this SOC.
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26659
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform.
BUG=b:79559085
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0
flag is set in FACP table - FADT.Flags[21] bit.
Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/26940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a glue layer between SOC and common block IPs in terms
of PCH. All common IP blocks now can be selected based on
SOC_INTEL_COMMON_PCH_BASE config option.
BUG=none
BRANCH=b:78109109
TEST=Build and boot Cannonlake RVP and EVE.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).
All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.
A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.
BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option
Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit
64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect
this.
BUG=b:77224247
Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After FSP-S, a device on PCI function n will be function swapped
to function 0 if there is no device presnet on function 0.
It needs some modification for DT and causes mismatches between
software configuration and hardware schematic. This patch is
from d779605, which swaps the devfn of the first enabled device
in DT and function 0 resides in a PCI device.
BUG=b:80105785
BRANCH=None
TEST=Make sure the device is still enabled after coalescence with
device on bus 0 and w/o device on bus 0. Test with suspend
and resume and ensure it's consistent.
Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/26479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Id41279a1cdc7c68d3dcc44e238863f2f4a452499
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia36b4ef7d66c50a044bc51f452ac8b7c7ff14323
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I6db25850d46ea3a940ea2a6f263303d4b5304cb3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ifadb894f98ce60cf0778de7fbcec67d125e48fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ibf21100eb2232932ea52740bd5250319d3c9adfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Idf47ea3b29c3fab7256d7a6722c7978594001d8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I15e624b40d11f61a3870a6083be82d062690498d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Idf00c029331aba30c8bfca71546cad62ff6bb0a7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26541
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Id6bcf98892c1944ec9c7e637f63c4c05fe9a0c07
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I05a46ab0ae6b4493895c1231fedb59c96efdf793
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I68c455d4bc524c2dd2d3ba87ab6641e70c78521c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I52534b67cd3cd8489925941f45a756b3d430e072
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Since we do not know before hand the memory range initialized by FSP memory
init until it completes and as memory gets accessed from within FSP memory
init to migrate FSP from CAR to memory, we need to add this mapping in
coreboot.
Change-Id: I1ce2d489240e6e3686ceb7f6e824e5a94398d47e
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/26745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Iea56a6560bb23d48d19211304e57fc08e1c27fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26584
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I043f4169ad080f9a449c8780500332c9512b62ff
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26583
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup
function.
BUG=b:80280671
TEST=Add ACPI method to specific GPP bridge. Boot and verify method
with ACPI dump.
Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/26698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Recent changes to field lengths in include/memory_info.h resulted in
a mismatch between the memory_info struct the MRC blob writes to and
the struct used by coreboot to parse out data for the SMBIOS tables.
This mismatch caused type 17 SMBIOS tables to be filled incorrectly.
The solution used here is to define the memory_info struct as expected
by MRC in the pei_data header, and manually copy the data field by field
into the coreboot memory_info struct, observing the more restrictive
lengths for the two structs.
Test: build/boot google/lulu, verify SMBIOS type 17 tables correctly
populated.
Change-Id: I932b7b41ae1e3fd364d056a8c91f7ed5d25dbafc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/26598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds and updates headers in all of the soc files that
had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all soc directories.
Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This is currently selected by each derivative board's Kconfig even
though it's really an SoC-specific option.
Change-Id: Iad135261915a0857c53c18aaebde7e46c97a8f40
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26344
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Max98373's NHLT capture configuration is used for IV feedback for
DSM algorithm.
Feedback is 4-channel data. Without this configuration below error
is seen in dmesg:
[ 315.784250] snd_soc_skl 0000:00:1f.3: Blob NULL for id 0 type 3 dirn 1
[ 315.784263] snd_soc_skl 0000:00:1f.3: PCM: ch 4, freq 48000, fmt 32
So, update nhlt configuration accordingly.
BUG=b:79362472
TEST=Audio playback works with IV feedback enabled
Change-Id: I75434a63fe030ed9bb963c6d300d833a8e7d2d66
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26384
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I102c9b9b1066064589149388d5ebbcd6d0d81fa7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ib7bcfefaecc053a1ed28d708a614acb81207bccf
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I065ed3a0deab2f59e510717f5d52beb2a62e900d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This won't actually get called yet since the GPIO pin has not been
configured as SMI.
BUG=b:80295434
TEST=grunt: Made sure events could be processed.
Change-Id: I189e26196e4543b3e34bff5d9df8566eff07d585
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are already reporting the Wake source, but we must also report the
ACPI wake itself.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I8b2cfe3e2090fb8eed755e40d337c6049d8dd96e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.
BUG=b:76020953
TEST=Build grunt
Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.
BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.
Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I82089475eb43d58303d1091f35aee06f1f04b4a4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. With
PAGING_IN_CACHE_AS_RAM enabled for GLK, there was no page table
entry for this range which caused a page fault. Since this test
is anyway not exhaustive, we will skip the memory test in FSP.
There is an option to do PCIe power sequence from within FSP if provided
with the GPIOs used for PERST to FSP. Since we do this from coreboot,
will skip the PCIe power sequence done by FSP.
FSP does not know what the clock requirements are for the device on
SPI bus, hence it should not modify what coreboot has set up. Hence
skipping SPI clock programming in FSP.
CQ-DEPEND=CL:*627827
BUG=b:78599939, b:78599576, b:76058338
BRANCH=None
TEST=Build coreboot for Octopus board.
Change-Id: I4fa7a73fbb4676bb7af2416c8a33bf10ef41dd53
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/26284
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add distclean targets so these can be called by the junit.xml test
target needed for jenkins testing.
Change-Id: I5991b43503da1778a6d74a57fbc0daf862e570d7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/26433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add 64KB to the reserved memory used for stage_cache. This corrects
an error observed when using a debug build of the AGESA blob.
Messages on initial boot
AGESA: Saving stage to cache
Error: Can't add stage_cache 57a9e101 to imd
and during resume
AGESA: Loading stage from cache
Error: Can't find stage_cache 57a9e101 in imd
TEST=boot/suspend/resume Grunt with debug and release builds
BUG=b:79154155
Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the new bootblock compression feature on RK3399,
which requires moving MMU initialization into the decompressor stage and
linking the decompressor (rather than the bootblock) into the entry
point jumped to by the masked ROM.
RK3399's masked ROM seems to be using a bitbang SPI driver to load us
(very long pauses between clocking in each byte), with an effective data
rate of about 1Mbit. Bootblock loading time (as measured on a SPI
analyzer) is reduced by almost 100ms (about a third), while the
decompression time is trivial (under 1ms).
Change-Id: I48967ca5bb51cc4481d69dbacb4ca3c6b96cccea
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch ensures that user can select a specific AP to run
a function.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase AP timeout limit for sgx_configure function. As per debug log
sgx_configure was not successful on all cores with given timeout value.
TEST=Ensures no timeout error in AP function execution.
Change-Id: Ia83f7a7eb6cd6c4808d55febfebe32724a633173
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Because thermal table is not included the values of DPTF_TSR1_ACTIVE_AC
from internal nami/vayne thermal team. Add conditional compilation
in _ACx methods if DPTF_ENABLE_FAN_CONTROL is defined in the dptf.asl.
BUG=b:72974136
TEST=Match the result.
Change-Id: I4b593118ca460a59aa49786cb99df417d135112a
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add APIs and required parameters for creating Realtek 5682 SSP
endpoint in NHLT table.
BUG=b:79235534
TEST=check that NHLT table defined is created properly.
With the series merged & required driver support in kernel.
Verify Headset Audio playback.
Change-Id: Ic26a0b881f77af64ba00fd714b08c0f17c0acb3d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/26057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).
- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock
Note: There is no functional change in this patch.
Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TEST=build
Change-Id: Icf934caf8b4584ef2633054a5cc7f5be7cc734ee
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current PCH UART support for console is limited to UART2.
This change adds support for specifying UART0 or UART1 to be
used instead by changing CONFIG_UART_FOR_CONSOLE in the board
level Kconfig. The default is still 2.
This is tested with a board that uses UART0 for debug output.
Change-Id: I91323ed3298f9b2558764aa4b54173833c021a7b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/26140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Advanced Error Reporting capability was hardcoded in the PCIe
extended capability list, but it might not always be possible.
The Librem 13v1 does not seem to have working AER and this option
was needed and tested on the Librem 13v1. Without it, the linux
console gets spammed with AER errrors.
Change-Id: If2e0ec42c93f1fee927eacdf0099004cf9302fbe
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
I finally found out why disabling the L1 sub state option did not
prevent some NVMe drives from locking up in L1 substate. I expect
that the disabled L1 substate initialization that coreboot does
is negated because Linux might itself configure it if it finds the
capability enabled on the PCIe root port.
Removing the capability from the PCIe root port when L1 sub states
are disabled in the configuration should fix the problem.
This was not tested because it's a difficult issue to reproduce and
I do not have the problematic hardware that caused it anymore.
Change-Id: I293a650db307e77cee024a43fbfc81e1d8c86265
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/25325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
According to ACPI 6.1 spec 19.6.44, External informs compiler that
object is external to this TABLE, no necessary for object in same DSDT
tables.
BUG=None
TEST=Build pass Intel mainboard with 20180427 iasl.
Change-Id: I153e7d0e97f9a29919676fbb73a7c26fd22f252c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/26045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Skylake used the inner function, wrapping it in the same set of tests as
the common code does, but expressed differently.
Change-Id: Ifa6912255e7874a6e80301d49128adda6f624209
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26037
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The sb_set_readspeed() was touching the wrong register and
the read speed settings are handled by sb_set_spi100(). Nothing
was using the function, so remove it.
Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
It's pretty well compressible which helps when space is tight.
The code encodes the assumption that the VBT is 8kb or less. Haven't
seen a larger one yet.
BUG=b:77971803,b:78541692
TEST=build, see that vbt.bin is compressed, boot, check log that the
reported VBT size is correct.
Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Frequency set to 19.2 MHz
TEST=build
Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CONFIG_ALT_CBFS_LOAD_PAYLOAD has long since been removed.
Clean up the remnants in braswell.
Change-Id: I88483a4c3a74ed0c7defacf872b1564c3ce7f909
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Function gpio_output() is only setting the pin as an output, when in fact
it should also set the state (high/low) of the pin. Fix the procedure to
set the state of the pin.
BUG=b:78328773
TEST=None
Change-Id: I516192a0782a9bbb40124029f264a2711114c800
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.
BUG=b:78009842
Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support and enalbe cache-as-ram paging for glk to work around
a cache-as-ram corruption issue. glk executes verstage, romstage,
and FSP-M directly out of cache-as-ram (just like apl). However,
the front end on glk is very agressive about pulling cache lines
into L1I for potential execution. When the snoops hit in the L1D
and the cache lines are dirty the processor writes the line back.
However, there is no backing store for the dirty lines to go. As
such when the line is pulled back in the value is all 0xff's,
corrupting cache-as-ram.
To fix the issue one needs to enable paging with NX (no execute)
permissions which prevents the above actions from happening because
the TLB will indicate that shouldn't be fetched into the instruction
cache since data will be marked no execute.
The generated page tables are added to cbfs and only added to the
COREBOOT cbfs as they are only consumed in the early cache-as-ram
stages.
The page tables generated with:
$ go run util/x86/x86_page_tables.go \
--iomap_file=src/soc/intel/apollolake/glk_page_map.txt \
--metadata_base_address=0xfef00000 \
--pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \
--pt_output_c_file=src/soc/intel/apollolake/pt.c
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xfef00000.
BUG=b:72728953
Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.
This is preparation to have GPIO table/code also declare/program SCI/SMI.
BUG=b:72875858
TEST=Build grunt.
Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses the newly added vboot_can_enable_udc to decide if it
is okay to enable xDCI in vboot developer mode.
BUG=b:78577893
BRANCH=poppy
Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was decided to not add the buffers definitions, so the todo message
is obsolete. Replace it with minimum instructions about when a new buffer
will be needed.
It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is
about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO.
BUG=b:77940747
TEST=None.
Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25740
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that an idt is available in every stage utilize it for exception
processing to help catch and debug issues.
BUG=b:72728953
Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).
More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/
Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
smi_sources is a file local array of constants.
Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
It's going to be necessary to know the i/o hole size as well
the amount of memory configured in the sytsem. Therefore, add
two helper functions:
memory_in_system_in_mib()
iohole_in_mib()
Both return values in units of MiB.
BUG=b:72728953
Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25738
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Found-by: Coverity (CID 1387031: Memory - illegal accesses
(BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of
19 bytes on destination array "dimm->module_part_number" of size 19 bytes
might leave the destination string unterminated. Fix the size parameter.
BUG=b:76202696
TEST=Build and boot kahlee, using special debug code to see the output
strings, which was later removed.
Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
On a second look broadcom/cygnus and imgtec/pistachio appear to
support full duplex. Therefore, remove the use of spi_xfer_two_vectors().
For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such
a way that it does not support full duplex. Remove the use of
spi_xfer_two_vectors() and explicitly error out when a full duplex
transaction is requested.
Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check same IO ranges get programmed first, if so just skip it to avoid double
programming.
BUG=b:77944335
TEST=Boot up with mewoth board, and check serial log, there's no error
message about "LPC: Cannot Open IO Window: ".
Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are sections of code that are almost identical and they can be
converted to auxiliary procedures. For allocating heap, 3 sizes (the
buffer size of currently being examined node, the buffer size of the
current best fit node and the minimum size for a buffer that will need
to be split if selected as the best fit) are used often so they could
be stored in temporary variables. These 2 changes will make code shorter,
with less indentation problems and overall easier to read. The actual
logic of the code is not changed.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ib4c69981eab7452228ccae9ed9bc288c8baceffe
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25703
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DRAM Initialization Scratchpad Bit needs to be set after Dram
Initialization finished, according to Cannonlake PCH-LP EDS(#565870)
chapter 5.3.1.
BUG=None
Change-Id: I16dd3787cb743bc5b7492042f3c3757534e1a51c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
Force PCH LPC generic IO ranges are identical between PCH LPC pci config
space and DMI PCR registers. Reference documentation from 570374 chapter
2.4.1.
Bug=77944335
TEST=Boot up in OS in meowth board, using iotools to read LPC pci
config space offset 0x84~0x90 and compare with values read from DMI PCR
private register offset 0x2730~0x273c are identical.
Change-Id: I72a40360ba67f443f24468f10504d8cfd0b099ca
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25668
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Creates a common asl include file for PCIe power state methods. This
allows ports to be enabled independently.
BUG=None
BRANCH=None
TEST=None
Change-Id: I7b1cf4e14ebdfe9ecc7131dfe47c70ed7e2c3dc5
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/25532
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because thermal table is not included the values of DPTF_TSR0_ACTIVE_AC5
and DPTF_TSR0_ACTIVE_AC6 from internal nami/vayne thermal team.
Add conditional compilation in _ACx methods if DPTF_ENABLE_FAN_CONTROL
is defined in the dptf.asl.
BUG=b:72974136
BRANCH=poppy
TEST=emerge-nami coreboot and booted on nami board.
Change-Id: I3e36ce94f714ff13f8ccee65992d7a9c7e0bb5b2
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25614
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Also base the FSP/GOP related bail-out on the correct Kconfig option
to allow adding a VBT along with libgfxinit.
Most things should work, what doesn't is backlight control because
coreboot misses the settings (moved to FSP and need backporting).
Also, Kaby Lake is still unsupported.
TEST=Booted yet to be upstreamed Skylake-S port (Kontron/bSL6) both with
text and linear framebuffer mode and viewed a FILO menu.
Change-Id: I79fbfed7732cf02d054530ea7ec0d34de32836ba
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This makes FSP use the same baud rate as coreboot so that the user can
more easily change it without having to modify the FSP binary.
Change-Id: I0084aa9a0394ad7eabdd88809b66fc21a25ba316
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On glk there's a 4MiB L2 cache all the time. Take advantage of that
by initializing a 1MiB cache-as-ram area.
BUG=b:72728953
Change-Id: Ia4e777a13607d8b70c05534b0a172f0ec6b04c51
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25645
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The pch_smbus_init() function contains code to enable clock gating for
the SMBus controller. Unfortunately this code is buggy and leads to a
hanging system with the latest microcode version.
The hang occurs as follows:
The clock gate register is mapped into RCBA space. After reading the
RCBA address from the LPC device config space no mask is applied to the
value (only bits 31..14 are valid while bit 0 is the enable bit). For
this reason the final address is off by one. The old microcodes at least
allowed this unaligned access to the RCBA space. With the latest
microcode this access leads to CPU hang.
Once this is fixed the next issue occurs: After setting the clock
gating bit for SMBus (bit 5) the SMBus controller disappears from the
PCI bus completely and hence no usage of it is possible anymore.
To fix this issue the clock gating code is completely removed as it was
intentionally meant to enable clock gating on the SMB_CLK line and not
the clock gating on the PCIe interface of the SMBus controller.
This issue is known already and was discussed on the mailinglist:
[coreboot] BDX-DE PCI init fail
https://mail.coreboot.org/pipermail/coreboot/2018-January/085908.html
TEST=Boot mc_bdx1 with microcode version M1050663_07000012.
Change-Id: Icb86f4516f8a6e72552a44618737e682b0fdef33
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25652
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The converter was setting SMBIOS values when dimm_info expects SPD
values.
dmidecode now shows the following:
Memory Device
Array Handle: 0x0000
Error Information Handle: Not Provided
Total Width: 64 bits
Data Width: 64 bits
Size: 8192 MB
Form Factor: SODIMM
Set: None
Locator: Channel-0-DIMM-0
Bank Locator: BANK 0
Type: DDR4
Type Detail: Synchronous
Speed: 933 MT/s
Manufacturer: Hynix/Hyundai
Serial Number: 00000000
Asset Tag: Not Specified
Part Number: HMAA51S6AMR6N-UH
Rank: 1
Configured Clock Speed: 933 MT/s
Minimum Voltage: Unknown
Maximum Voltage: Unknown
Configured Voltage: Unknown
Example debug output:
AGESA TYPE 17 DMI INFO:
Handle: 1
TotalWidth: 64
DataWidth: 64
MemorySize: 8192
DeviceSet: 0
Speed: 1200
ManufacturerIdCode: 44416
Attributes: 1
ExtSize: 0
ConfigSpeed: 933
MemoryType: 0x1a
FormFactor: 0xd
DeviceLocator: DIMM 0
BankLocator: CHANNEL A
SerialNumber(8): ' 00000000'
PartNumber(20): 'HMAA51S6AMR6N-UH '
CBMEM_ID_MEMINFO:
dimm_size: 8192
ddr_type: 0x1a
ddr_frequency: 933
rank_per_dimm: 1
channel_num: 0
dimm_num: 0
bank_locator: 0
mod_id: 44416
mod_type: 0x4
bus_width: 3
serial: 0x00000000
module_part_number(18): 'HMAA51S6AMR6N-UH '
The serial number we get from AGESA (at least on my
board) is always 00000000. I'm assuming this is because the SPD info is
compiled in.
`mosys memory spd print all` is still failing though. I will look into
that next.
BUG=b:65403853
BRANCH=dimm-info
TEST=Test output above
Change-Id: I076bc3f965f81a9374c8976da48c7fdce014dc0c
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To avoid rounding errors with the current data types, the formula in
this function must be converted.
Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required for clock parameter settings to take effect.
BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz
Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The term MTRR has been misspelled in a few places.
Change-Id: I3e3c11f80de331fa45ae89779f2b8a74a0097c74
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On APL and GLK the i2c blocks use 133MHz input clock, but the
SPI blocks use a 100MHz input clock. Fix this so that the proper
target frequencies can be hit on the SPI controllers.
BUG=b:75306520
Change-Id: Iec36579894fa4633ac8d1035e6e7afec01af755f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Correct Cannonlake I2C clock frequency to 133Mhz that will match the
silicon, Cannonlake have I2C clock force to 133Mhz.
BUG=b:75306520
Change-Id: Iaab8851bb00cf27876d4068167a283ed79a28b2d
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25610
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As part of moving AGESA calls from bootblock to romstage, callback function
AGESA_HALT_THIS_AP must be available at romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: I0992b2de5856881c19191ec4f637168727686524
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25527
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MONITOR/MWAIT had an irremediable hardware bug for Apollolake.
This has been fixed for GLK. Therefore, make MONITOR/MWAIT based
C-states the default for GLK and disable IO-Redirection based
C-states used for Apollolake.
Tested on GLK w/kernel 4.14.27 using turbostat to observe C-state
residencies with and without load.
Tested for S0ix entry and exit using:
"echo freeze > /sys/power/state" and "suspend_stress_test -c 500".
BUG=b:77639897
Change-Id: If648c25a9b26c04b278dce4af241d439790288ca
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/19718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.
BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.
Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Move flush_l1d_l2 function to common location within the SoC.
BUG=None:
BRANCH=None
TEST= Build for glkrvp.
Change-Id: I4aaaaccc4f343bc4926111258a33e09e79c76141
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/25547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Broadwell-DE the FSP sets up DCACHE in the early call. The address
does not match the default FSP 1.0 address defined in
src/drivers/intel/fsp1_0/Kconfig which leads to errors when this range
is used in pre-ramstage stages.
This patch provides the matching DCACHE_RAM_BASE value among with a
suitable DCACHE_RAM_SIZE for the FSP based Broadwell-DE implementation.
The include order of Kconfig files makes sure that the Kconfig file in
the soc directory is sourced first and the defined values will override
the ones in src/drivers/intel/fsp1_0/Kconfig.
Change-Id: I2a55b576541a3d974ee2714b198095aa24fc46f5
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide ACPI path names for PCI domain and LPC device so that generated
ACPI tables have valid device paths.
Change-Id: I5a97e45ef50ec5ee9d64c5d2834968a02455cf72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/25534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace an absolute value with a #define value in bootblock. This is
in preparation for using an additional MTRR in a subsequent patch.
Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Add FSP option to enable/disable VT-d (Intel Virtualization Technology
for Directed I/O) and VMX (Virtual Machine Extensions), VMX will be
disabled once VT-d got disabled.
Bug=b:73655383
TEST=Build and flash image on meowth board with debug build FSP, in
serial log search for "VMXEnable" and "VtdDiable".
Change-Id: I589590450aa4b9302ee2f9bb7b879a332f50b73e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clear EMMC timeout register to avoid EMMC issue according to cannonlake
bios writer guide. _PS0 is not called by kernel when boot source is not
EMMC but kernel still initializes emmc. Add _INI to EMMC,SD asl code to
cover cases that the system doesn't boot from EMMC.
BUG=b:76202699
TEST=Install OS into EMMC
Change-Id: I4eef23f637f781b709696951c5bd825530cc1d11
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25290
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Removed 33KB hole in SSRAM
TEST=build & run
Change-Id: I6851860f878d9a0688975fa855980870d657ee1a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25391
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the SoC is VT-d capable, write an ACPI DMAR table. The entry for the
GFXVTBAR is only generated if the IGD is enabled.
Change-Id: I8176401dd19aee7ad09a8a145b7a3801fe5b2ae1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers (maybe, who knows, the blob is undocu-
mented), advertised to FSP and reserved from the OS.
The new devicetree option `ignore_vtd` allows to retain the old beha-
viour (do whatever pre-set UPD values suggest).
We also let FSP set up distinct BDFs for messages originating from the
I/O-APIC and the HPET.
Change-Id: I77f87c385736615c127143760bbd144f97986b37
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.
This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.
Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The <gpio.h> API is supposed to include a gpio_set() function that just
toggles the state of a GPIO already configured as an output, even though
we rarely need it since gpio_output() can already be used to initialze a
GPIO to a default value while configuring it as an output. This function
was forgotten on Rockchip, so this patch adds it now.
Change-Id: I201288139a2870e71f55a7af0d79d4a460b30a0c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25393
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.
Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/chell with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: Icd6b514e531eec6e49dbb03eb765144f41c1e31b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Add global/ACPI nvs variables required for IGD OpRegion.
Add functions necessary to save the ACPI OpRegion table
address in ASLB, and restore table address upon S3 resume.
Implementation modeled on existing Baytrail code.
Test: boot Windows 10 on google/edgar with Tianocore payload and
GOP display init, observe display driver loaded and functional,
display not black screen when resuming from S3 suspend.
Change-Id: I7c1fbf818510949420f70e93ed4780e94e598508
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Get rid of custom opregion implementation and use drivers/intel/gma/opregion
implementation instead.
Test: boot Windows 10 on google/chell and google/edgar using Tianocore
payload with GOP init, observe Intel graphics driver loaded and functional.
Change-Id: I5f78e9030df12da5369d142dda5c59e576ebcef7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21703
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
me_progress_rom_values array provides detailed information maps to ME
HFSTS2 register value.
There is a chance that ME status value might be over the size of
me_progress_rom_values.
This commit adds a check before access the array.
BUG=b:77247550
Change-Id: I5de569c62b94b0595d3d3ea254f50e312e8c11a4
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/25425
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable VMX if supported by CPU and enabled in board devicetree.
Check lock bit unset before enabling VMX.
Change-Id: Ic57eac45e9c65baa4479735c6d70a7eb685f080e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/25331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb.
Change-Id: I34e7d750d3f75757a68977ae8d92bfbee1a10af1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
Change-Id: I5aea15511c52d1191babf551feb237f4144683e4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When CONFIG_VBOOT is enabled then the xDCI controller should only be
enabled if the system is in developer mode. This prevents a system
in normal/verified mode from being used as a USB peripheral device
which could potentially be used to access user data.
This change adds a function to return whether xDCI can be enabled
or not, which will be used by the SOCs.
Change-Id: Ie3ee9dd7077c094a01fd857a2e4033a12ce8979b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the NHLT configuration for the max98373 codec to skylake,
taken directly from cannonlake.
This will allow skylake/kabylake boards to use this codec.
Change-Id: Ifb6bf2d31fda25b18d9b1ce2bb721255335d55e4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/25367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
This change adds a call to heci_reset before attempting to read
ME firmware version. This is important to ensure that both ME and BIOS
are in sync.
BUG=b:76167737
BRANCH=poppy
TEST=Verfied that ME firmware version read does not fail on first boot
after power failure (i.e. removing battery and AC power).
Change-Id: Ib6b39c398d2e1177b087352a4acb8bcf5a9897d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
TEST=build
Change-Id: Ie54e310a94f61b8d86c13261937015e3f5a2ab01
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
