New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Under some scenarios the key ladder on the Cr50 can get disabled. If
this state is detected, trigger a reboot of the Cr50 to restore full
TPM functionality.
BUG=b:121463033
BRANCH=none
TEST=Built coreboot on sarien and grunt platforms.
TEST=Ran 'gsctool -a -m disable' and reboot. Verified coreboot sends
VENDOR_CC_IMMEDIATE_RESET command to Cr50 and that the Cr50 resets and
then the platform boots normally.
TEST=Performed Cr50 rollback to 0.0.22 which does not support the
VENDOR_CC_TPM_MODE command, confirmed that platform boots normally and
the coreboot log captures the unsupported command.
Tested-by: Keith Short <keithshort@chromium.org>
Change-Id: I70e012efaf1079d43890e909bc6b5015bef6835a
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This macro was unnecessarily complex. Trying to avoid an overflow
for unknown reasons, and instead shifted the result into the sign
bit in C. Using a plain number literal that forces C to use an
adequate integer type seems to be safe. We start with 0xffffffff,
subtract `x` and add 1 again. Turned out to be a common pattern
and can't overflow for any positive 32-bit `x`.
Change-Id: Ibb0c5b88a6e42d3ef2990196a5b99ace90ea8ee8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/31322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
To make PCI driver side arch-agnostic, function
declarations have to be in symmetrical header
file locations.
From the driver side, the correct file to include
is now <device/pci_ops.h>
Change-Id: I8076a4867fd7472beaae0a021dcf0d9c7c905871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It is expected that method of accessing PCI configuration
register space via memory-mapped region is arch-agnostic.
Change-Id: Ide6baa00d611953aeb324be0d3561f464395c5eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 6bbc8d8050.
The macro is used in assembly where integer suffixes are not portable.
Also, it is unclear how this can overflow as it's already the macros
purpose to avoid the overflow.
Change-Id: I12c9bfe40891ae3afbfda05f60a20b59e2954aed
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These are defined for __SIMPLE_DEVICE__ when PCI
enumeration has not happened yet. These should not
really try to probe devices other than those on bus 0.
It's hard to track but there maybe cases of southbridge
being located on bus 2 and available for configuration, so
I rather leave the code unchanged. Just move these out of
arch/io.h because they cause build failures if one attempts
to include <arch/pci_ops.h> before <arch/io.h>.
There are two direct copies for ROMCC bootblocks to
avoid inlining them elsewhere.
Change-Id: Ida2919a5d83fe5ea89284ffbd8ead382e4312524
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
With PCI_DEV() always defined it is no longer
necessary to exclude this code from building.
Change-Id: I58a6348750d240aa6024599f7b1af1449f31e8ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
After CL:31122, we can finally define a memory type specific for BL31,
to make sure BL31 is not loaded on other reserved area.
Change-Id: Idbd9a7fe4b12af23de1519892936d8d88a000e2c
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
CB:31139 fixs few ACPI type error. Here is few more typo mistake.
Change-Id: Ieecf0ba8fe09ed5003d5ae766079b8f83cc891b9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/31152
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move functions not available in PRE_RAM into seperate file.
Makes it easier to share code between rom and ramstage.
Change-Id: I0b9833fbf6742d110ee4bfc00cd650f219aebb2c
Signed-off-by: Thomas Heijligen <thomas.heijligen@secunet.com>
Reviewed-on: https://review.coreboot.org/c/31141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Currently, selflock_check() verifies that the binary is loaded in an
usable RAM area.
Extend its functionality so we can also check that BL31 is loaded in
a manually reserved area, and fail early if the range is not protected.
Change-Id: Iecdeedd9e8da67f73ac47d2a82e85b306469a626
Signed-off-by: Ting Shen <phoenixshen@google.com>
Reviewed-on: https://review.coreboot.org/c/31122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This is spotted using ./util/lint/kconfig_lint
To work around the issue, rename the prefix from `CONFIG_` to `CONF_`.
Change-Id: Ia31aed366bf768ab167ed5f8595bee8234aac46b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There's no such limit on 64 Bit coreboot builds.
* Fix comment in cbmem.h
* Remove 4 GiB limit on Cavium SoCs
Tested on opencellular/elgon.
Still boots Linux as payload.
Change-Id: I8c9c6a5ff81bee48311e8bf8e383d1a032ea3a6d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/30609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add API that should be implemented by the boot media drivers
for write-protecting a subregion.
Change-Id: I4c9376e2c2c7a4852f13c65824c6cd64a1c6ac0a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/28724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Pass timestamps and BIST to romstage using the same signature
as C_ENVIRONMENT_BOOTBLOCK will.
Change-Id: Ic90da6b1b5ac3b56c69b593ba447ed8e05c8a4e2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently this needlessly initializes the hardware in the both the
romstage and the bootblock, but it works.
Build option is renamed to USBDEBUG_IN_PRE_RAM to reflect the
use better, related support files can be built to pre-ram stages
regardless of usbdebug being enabled or not.
Tested on Google/peppy (adapted to C_ENVIRONMENT_BOOTBLOCK).
Change-Id: Ib77f2fc7f3d8fa524405601bae15cce9f76ffc6f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Expose the function that can unconditionally re-initialise
EHCI debug host and gadget.
Given the missing header in soc/intel files that prevented
building with USBDEBUG_IN_ROMSTAGE=y, it is not actually
known if those SOCs work at all for usbdebug.
Change-Id: I8ae7e144a89a8f7e5f9d307ba4e73d4f96401a79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
All these boards use the same default initialiser.
As this is initialized late after device enumeration,
it can't really be used to alter platform configuration.
Change-Id: I30fc0298081df0442ec4e9a527340b93a3cd6106
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Semantics of dev_find_slot() are ill in the sense that
it only works after device enumeration has completed in
ramstage. Plan is to declare it as deprecated.
Introduce pcidev_on_root() and pcidev_path_on_root()
functions to replace cases where this was called with
static argument bus == 0. New implementation only walks
the root bus of the PCI tree, while old one walked
the entire linked list of devices.
Introduce pcidev_path_behind() to replace cases where
argument bus != 0. The required parent node is typically
one of the PCIe root functions that you locate using
pcidev_on_root() above.
New forms are safe to use with early devicetree and
before PCI bus numbers have been assigned.
Change-Id: Ie20598d48b4cf6e35e45fc90804bad4728437fc6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Definitions of these types are arch-agnostic. Shared device
subsystem files cannot include arch/pci_ops.h for ARM
and arch/io.h for x86.
Change-Id: I6a3deea676308e2dc703b5e06558b05235191044
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use of device_t is deprecated.
Change-Id: Ie05869901ac33d7089e21110f46c1241f7ee731f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/30047
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The feature is used to enable PCI MMIO accesses behind
PCIe links (or bridges) before PCI enumeration has been
completed.
Add the feature for bootblock, verstage and postcar, it
is required with add-on PCIe serial cards for early
console output. It's up to the board specific code to
configure PCIe root port prior to calling console_init()
for this to work.
Remove feature from ramstage, it bypasses any resource
allocations and bus number assignments.
For the moment PCI configuration support before ramstage
is available only on ARCH_X86.
Also switch from device_t to pci_devfn_t.
Change-Id: I08acec68b6f17f4d73d30039cc41274492ea4f45
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root
ports, all others have 8 [1]. The existing PCIe code assumed that all
non-LP chipsets had 8 root ports, which meant that port 6 would not be
considered the last root port on H81, so `root_port_commit_config()`
would not run. Ultimately, while PCIe still worked on H81, all the root
ports would remain enabled, even if disabled in the devicetree.
Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they
are unused, and the MAX constant is incorrect.
Interestingly, this fixes an issue where GRUB is unable to halt the
system.
Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree
do indeed end up disabled.
[1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub
(PCH) Datasheet, revision 003, document number 328904.
Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/30077
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platforms moved to POSTCAR_STAGE so these are no longer used.
Change-Id: I9a7b5a1f29b402d0e996f2c2f8c6db3800cdddf3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Remove all cases in code where we tested for
EARLY_CBMEM_INIT or LATE_CBMEM_INIT being set.
This also removes all references to LATE_CBMEM_INIT
in comments.
Change-Id: I4e47fb5c8a947d268f4840cfb9c0d3596fb9ab39
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/26827
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using a fixed filename only allows for one SAR configuration to be
checked into CBFS. However, we have devices with shared firmware that
would desire separate SAR configurations. This change allows boards to
define a function to select one of multiple files stored in CBFS to be
used.
BUG=b:120958726
BRANCH=octopus
TEST=build
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Change-Id: Ib852aaaff39f1e9149fa43bf8dc25b2400737ea5
Reviewed-on: https://review.coreboot.org/c/30222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This function returns APIC id for respective cpu core.
BUG=b:74436746
BRANCH=none
TEST=mp_get_apic_id() can be accessed in other files now.
Change-Id: I5c5eda8325f941ab84d8a3fe0dae64be71c44855
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/25620
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in
cpu/x86/smm.h
Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t is deprecated.
Change-Id: I2c88642133d3cbf33015e3e1e855fb2c786878d6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide an reset macro that will use Verb ID 0x7ff and Payload 0 to
execute function reset.
Change-Id: Ie788b7153e25b764cd1d33753af17d5ed4903c36
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This removes CEIL_DIV and div_round_up() altogether and
replace it by DIV_ROUND_UP defined in commonlib/helpers.h.
Change-Id: I9aabc3fbe7834834c92d6ba59ff0005986622a34
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now postcar is a standalone stage give it a
proper type.
Change-Id: Ifa6af9cf20aad27ca87a86817e6ad0a0d1de17c8
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
A very common pattern in drivers is that we need to wait for a condition
to become true (e.g. for a lock bit in a PLL status register to become
set), but we still want to have a maximum timeout before we treat it as
an error. coreboot uses the stopwatch API for this, but it's still a
little verbose for the most simple cases. This patch introduces two new
helper macros that wrap this common application of the stopwatch API in
a single line: wait_ms(XXX, YYY) waits for up to XXX milliseconds to see
if the C condition 'if (YYY)' becomes true. The return value is 0 on
failure (i.e. timeout expires without the condition becoming true) and
the amount of elapsed time on success, so it can be used both in a
boolean context and to log the amount of time waited.
Replace the custom version used in an MTK ADC driver with this new
generic version.
Change-Id: I6de38ee00673c46332ae92b8a11099485de5327a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/29315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The selfboot function was changed at some point to take a parameter
which meant "check the allocated descriptors to see if they target
regions of real memory."
The region check had to be buried deep in the last step of loading since
that is where those descriptors were created and used.
An issue with the use of the parameter was that it was not possible
for compilers to easily divine whether the check code was used,
and it was hence possible for the code, and its dependencies, to be
compiled in even if never used (which caused problems for the
rampayload code).
Now that bounce buffers are gone, we can hoist the check code
to the outermost level. Further, by creating a selfload_check
and selfload function, we can make it easy for compilers
to discard unused code: if selfload_check is never called, all
the code it uses can be discarded too.
Change-Id: Id5b3f450fd18480d54ffb6e395429fba71edcd77
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/29259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
board_reset() replaces the existing common reset API. There is no common
distinction between reset types across platforms, hence, common code
could never decide which one to call.
Currently only hard_reset() is used by common code. We replace these
calls and provide a fall-back to the current hard_reset() implemen-
tation. The fall-back will be removed along with hard_reset() after the
transition of all boards.
Change-Id: I274a8cee9cb38226b5a0bdff6a847c74ef0b3128
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
This change adds two new post codes to indicate start and end of
memory param preparation in callbacks to SoC/mainboard code:
1. 0x34: Start of memory preparation
2. 0x36: End of memory preparation
These post codes are already used in coreboot. This change just
ensures that the codes are defined in post_codes.h for easy lookup.
These post codes are useful if SoC/mainboard decides to do a reset of
the platform before returning back to memory initialization.
Change-Id: I065518caedb7943d960a8a5c8708823b8eb3246d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The dimm_info and memory_info structs are used in devices that
don't strictly use DIMMs. Those platforms have the DRAM soldered
down so there's no DIMM part number that encapsulates the DRAMs
used in the DIMM. The full part number is desired to be exposed in
the SMBIOS tables. As such extend DIMM_INFO_PART_NUMBER_SIZE to 33
to accommodate longer part numbers
'MT53B256M32D1NP-053 WT:C' is one of the longer part numbers that
are desired to be maintained.
BUG=b:115697578
Change-Id: I0c39dd1d1c2f0776d70d8c4d8d56719779ff82ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.
Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table.
BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.
Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/28753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
The helper function to get the board version from EC returns 0 on
failure. But 0 is also a valid board version. Update the helper function
to return -1 on failure and update the use-cases.
BUG=b:114001972,b:114677884,b:114677887
Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/28576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Extend the generic flash interface to probe for write protected regions.
Add Winbond custom code to return flash protection.
Tested on Cavium EVB CN81xx using W25Q128.
Change-Id: I933a8abdc28174ec32acf323c102d606b58c1ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25082
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For devices supporting both Linux and Windows, we may find some ACPI
devices that only need drivers in Linux and should not even be shown in
Windows Device Manager UI.
The new 'hidden' keyword in device tree 'device' statement allows
devices sharing same driver to call acpi_gen_writeSTA with different
values.
BUG=b:72200466
BRANCH=eve
TEST=Builds and boots properly on device eve
Change-Id: Iae881a294b122d3a581b456285d2992ab637fb8e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/28566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a __always_inline macro that wraps __attribute__((always_inline))
and replace current users with the macro, excluding files under
src/vendorcode.
Change-Id: Ic57e474c1d2ca7cc0405ac677869f78a28d3e529
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@google.com>
Add a __noreturn macro that wraps __attribute__((noreturn)) and replace
current users with the macro.
Change-Id: Iddd0728cf79678c3d1c1f7e7946c27375a644a7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/28505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add more definitions to be used for Machine Check Architecture
support, mainly for determining the type of error that is being
interpreted. MCA is described in detail in the BKDG.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0682288aa58c69aee323fb43f74027f7a1905b68
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Define the maximum value of the cper_x86_check_type enum, for use later
in determining a legal function argument.
Change-Id: I73df4c6daa5d232c2d38b0896442b5bcab5aa15f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28533
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definitions from the UEFI appendix on Common Platform Error
Record (appx. N in revision 2.7-A). The structures and fields
defined are the minimum required for generating ACPI Boot Error
Record data in a subsequent patch.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I74d8ec8311de749e891827747b84dce0e737aceb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Duplicate the guid_t and GUID_INIT framework from the Linux
driver. Adapt it for coreboot, and create supporting copy
and compare functions.
Change-Id: Ia1cd7a1f0e0f900858830e1a6a7e2bbbe272fa30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch disables the unused PCI clock outputs on the XIO2001 PCI
Express to PCI Bridge.
Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
* Add const quailifier to arguments and elements.
* Add casts where necessary in cn81xx/soc.
Tested on Cavium CN81xx EVB SFF.
Change-Id: Id27966427fb97457fe883be32685d1397fb0781f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For debug reasons, sometimes you not only want to log an event, but also
some extra information that would help debugging. Create an extended event
reporting event type with a dword complement, and define extended events
for failing to enter S3 due to pending wake event (one for pm1 and one for
gpe0).
BUG=b:111100312
TEST=Add a fake pending wake event, build and boot grunt, see the event in
eventlog.txt.
Change-Id: I3e8df0953db09197d6d8145b0fc1e583379deaa5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy code of depthcharge boot/coreboot.c and adapt it.
Tested on Cavium CN8100 EVB SFF, /sys/firmware/log is readable
and prints the log.
Change-Id: Ib714a021a24f51407558f484cd97aa58ecd43977
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/28104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There's nothing Sandy Bridge specific in this code.
Make it available on all platforms to reduce code duplication.
Tested on Lenovo T430: SMBIOS entry 17 is still valid.
Change-Id: I051c3e07a999d8dad082c24f65b43dce180349fd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There are two SKUs of Whiskey Lake W0, 2-core and 4-core.
Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fill in SMBIOS type 17 DIMM serial number, read from SPD.
Fixes FWTS SMBIOS type 17 test.
Change-Id: Id6e818bfdf4af0fd34af56dc23df052a3f8c348d
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/28191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change adds some MSRs that are needed in a subsequent change to add
support for Continuous Performance Control.
Change-Id: Id4ecff1bc5eedaa90b41de526b9a2e61992ac296
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/28067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Store initrd offset as 64bit integer.
Tested on Cavium CN81XX EVB: The initrd could be loaded when placed
above 4GiB. Previously it failed to find the initrd.
Change-Id: I5d1ae860ae4a4465546bc0ef89937d611d1e56ab
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c
BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.
Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear. The generations should have the following
number of banks:
* Family 10h: 6 banks
* Family 12h: 6
* Family 14h: 6
* Family 15h: 7
* Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its
MC0_STATUS address.
Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch changes the return type of gpio_base2_value() and related
functions from int to uint32_t. This makes more sense now that
board_id() and related functions (which are the primary use case) also
return that type. It's unlikely that we'll ever read a strapping of 32
GPIOs in a row, but if we did, we'd probably want to treat it as
unsigned.
Change-Id: I8fb7e3a7c76cb886aed40d0ada1f545180e43117
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27809
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Specifically PCI device ID for graphics and PCI device ID for northbridge.
Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/27519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
According to the "Intel® 64 and IA-32 Architectures Software Developer’s Manual"
the SMRR MSR are at a different offset for model_6fx and model_1067x.
This still need SMRR enabled and lock bit set in MSR_FEATURE_CONTROL.
Change-Id: I8ee8292ab038e58deb8c24745ec1a9b5da8c31a9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add 4 helper functions to get microcode info.
* get_current_microcode_rev
return the the version of the currently running microcode.
* get_microcode_rev
extract microcode revision from the given patch.
* get_microcode_size
extract microcode size from the given patch.
* get_microcode_checksum
extract checksum from the given patch.
The simpler thing would be to just move the struct microcode
to microcode.h so that the structure members can be dereferenced.
To encapsulate the structure details added the helper functions.
This information will be used in future to compare microcodes for update.
Change-Id: I67a08ba40b393874d8cc17363fefe21e2ea904f3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/27365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a function, dev_bus_each_child(), which walks through all the
children for a given bus of a device. This helper allows one to
walk through all the children of a given device's bus.
BUG=b:111808427,b:111743717
TEST=built
Change-Id: Iedceb0d19c05b7abd5a48f8dc30f85461bef5ec6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
This is how these MSR's are referenced in Intel® 64 and IA-32 Architectures
Software Developer’s Manual.
The purpose is to differentiate with MSR_SMRR_PHYSx.
Change-Id: I54875f3a6d98a28004d5bd3197923862af8f7377
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The write_tables function was void. It is a bit more
useful for loading payloads from the romstage
if it returns a pointer to the table it creates.
Change-Id: I6eeaf3e16bcbaf1e7ec3eada8026c466d2fb6f5a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/27537
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Basic PCI MSI-X table helper functions.
Imported from GNU/Linux kernel PCI subsystem.
To be used on Cavium to configure MSI-X tables.
Change-Id: I94413712e7986efd17e6b11ba59f6eb390384c8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26329
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for SMBIOS table 'IPMI Device Information' and use it on
HP Compaq 8200 Elite SFF.
Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans
for IPMI compatible devices.
Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/25386
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add comments on the ops handling in pnp_enable_devices function and the
pnp_info struct.
Also remove the negation in the check if an LDN-specific override is used.
This patch doesn't change the logic though.
Change-Id: I3e80dbce1f29ee3e95e3b1d71c9b8479561d5c1a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/27384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
To comply with all relevant bodies throughout the world, SAR settings
take into account the lowest common denominator Tx power settings. This
setup may lead to non-optimal performance when the user location is in a
country that may allow higher power setting. The purpose of Wireless Geo
Delta Settings (WGDS) is to provide offset settings for FCC, Europe,
Japan and Rest of the world. These offsets would be added (by Intel wifi
driver) to the base SAR Tx Power as defined in WRDS and EWRD
BUG=b:65155728
BRANCH=none
TEST=WGDS ACPI table gets created as expected.
Change-Id: I4f602e3f95ff3545db6cc6e428beb9a36abd9296
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Will be used on Cavium SoC to delete devicetree entries that aren't
available with the board/configuration.
Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
If CPU 0's stack grows to large, it will overflow into CPU 1's stack.
If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop.
When the stack overflow occurs it will override the return pointer for
CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return
to a random address.
This method is not foolproof. If code allocates some stack variables
that overlap with the canary, and if the variables are never set, then
the canary will not be overwritten, but it will have been skipped. We
could mitigate this by adding a larger canary value if we wanted.
I chose to use the stack bottom pointer value as the canary value
because:
* It will change per CPU stack.
* Doesn't require hard coding a value that must be shared between the
.S and .c.
* Passing the expected canary value as a parameter felt like overkill.
We can explore adding other methods of signaling that a stack overflow
had occurred in a follow up. I limited die() to debug only because
otherwise it would be very hard to track down.
TEST=built on grunt with a small and large stack size. Then verified
that one causes a stack overflow and the other does not.
Stack overflow message:
canary 0x0 != 0xcdeafc00
SMM Handler caused a stack overflow
Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27229
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.
Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method to retrieve a node's phandle.
Useful for board specific devicetree manipulations.
Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The file cache_as_ram_ht.inc is used across a variety
of CPUs and northbridges. We need to split it anyway
for future C_ENVIRONMENT_BOOTBLOCK and verstage work.
Split and rename the files, remove code that is globally
implemented in POSTCAR_STAGE framework already.
Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds PCI ID for Intel TP2 Wi-Fi and adds that to
pci_device_ids in Intel wifi driver.
Change-Id: I51abf615fca6001d564e7cd672cc16f3a0fb8dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most, if not all, chipsets have MMIO between 0xfe000000 and 0xff000000.
So don't try to cache more than 16MiB of the ROM. It's also common that
at most 16MiB are memory mapped.
Change-Id: I5dfa2744190a34c56c86e108a8c50dca9d428268
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26567
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Have boot_count_read() just return 0 if CONFIG_ELOG_BOOT_COUNT is not
enabled.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: I70f16226371324dea37b3f36f85c2037e324ef31
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26526
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make it available early and use it in dev_find_next_pci_device().
Change-Id: I1d0ad07f37ea79dae2b9a592fcccba5e03fd86d5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Masked ROMs are the silent killers of boot speed on devices without
memory-mapped SPI flash. They often contain awfully slow SPI drivers
(presumably bit-banged) that take hundreds of milliseconds to load our
bootblock, and every extra kilobyte of bootblock size has a hugely
disproportionate impact on boot speed. The coreboot timestamps can never
show that component, but it impacts our users all the same.
This patch tries to alleviate that issue a bit by allowing us to
compress the bootblock with LZ4, which can cut its size down to nearly
half. Of course, masked ROMs usually don't come with decompression
algorithms built in, so we need to introduce a little decompression stub
that can decompress the rest of the bootblock. This is done by creating
a new "decompressor" stage which runs before the bootblock, but includes
the compressed bootblock code in its data section. It needs to be as
small as possible to get a real benefit from this approach, which means
no device drivers, no console output, no exception handling, etc.
Besides the decompression algorithm itself we only include the timer
driver so that we can measure the boot speed impact of decompression. On
ARM and ARM64 systems, we also need to give SoC code a chance to
initialize the MMU, since running decompression without MMU is
prohibitively slow on these architectures.
This feature is implemented for ARM and ARM64 architectures for now,
although most of it is architecture-independent and it should be
relatively simple to port to other platforms where a masked ROM loads
the bootblock into SRAM. It is also supposed to be a clean starting
point from which later optimizations can hopefully cut down the
decompression stub size (currently ~4K on RK3399) a bit more.
NOTE: Bootblock compression is not for everyone. Possible side effects
include trying to run LZ4 on CPUs that come out of reset extremely
underclocked or enabling this too early in SoC bring-up and getting
frustrated trying to find issues in an undebuggable environment. Ask
your SoC vendor if bootblock compression is right for you.
Change-Id: I0dc1cad9ae7508892e477739e743cd1afb5945e8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit f3d99b6a65.
Reason for revert: We're now doing this through CBFS types instead, so
this shouldn't be needed anymore.
Change-Id: I9e0d5446365f8ecc045615e4ba1a1313080c9479
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26448
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can select a specific AP to run
a function.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: Iff2f34900ce2a96ef6ff0779b651f25ebfc739ad
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26034
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Store the type of the loaded program after locating the file and add a
method to retrieve the type.
Will be used to distinguish between SELF and FIT payloads.
Change-Id: Ic226e7e028d722ab9e3c6f7f1c22bde2a1cd8a85
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26028
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This will allow loading of programs that are more than one type,
e.g. ramstage type might now be a stage or payload.
Further, unknown types of 0 are dangerous, make it a real value.
Change-Id: Ieb4eeb7c5934bddd9046ece8326342db0d76363c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/26242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This commit adds support for describing USB ports in devicetree.cb.
It allows a USB port location to be described in the tree with
configuration information, and ACPI code to be generated that
provides this information to the OS.
A new scan_usb_bus() is added that will scan bridges for devices so
a tree of ports and hubs can be created.
The device address is computed with a 'port type' and a 'port id'
which is flexible for SOC to handle depending on their specific USB
setup and allows USB2 and USB3 ports to be described separately.
For example a board may have devices on two ports, one with a USB2
device and one with a USB3 device, both of which are connected to an
xHCI controller with a root hub:
xHCI
|
RootHub
| |
USB2[0] USB3[2]
device pci 14.0 on
chip drivers/usb/acpi
register "name" = ""Root Hub""
device usb 0.0 on
chip drivers/usb/acpi
register "name" = ""USB 2.0 Port 0""
device usb 2.0 on end
end
chip drivers/usb/acpi
register "name" = ""USB 3.0 Port 2""
device usb 3.2 on end
end
end
end
end
Change-Id: I64e6eba503cdab49be393465b535e139a8c90ef4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The patch series ending in 64049be (lib/bootmem: Add method to walk OS
POV memory tables) expanded the bootmem framework to also keep track of
memory regions that are only relevant while coreboot is still executing,
such as the ramstage code and data. Mixing this into the exsting bootmem
ranges has already caused an issue on CONFIG_RELOCATEABLE_RAMSTAGE
boards, because the ramstage code in CBMEM is marked as BM_RAMSTAGE
which ends up getting translated back to LB_RAM in the OS tables. This
was fixed in 1ecec5f (lib/bootmem: ensure ramstage memory isn't given to
OS) for this specific case, but unfortunately Arm boards can have a
similar problem where their stack space is sometimes located in an SRAM
region that should not be made available as RAM to the OS.
Since both the resources made available to the OS and the regions
reserved for coreboot can be different for each platform, we should find
a generic solution to this rather than trying to deal with each issue
individually. This patch solves the problem by keeping the OS point of
view and the coreboot-specific ranges separate from the start, rather
than cloning it out later. Ranges only relevant to the coreboot view
will never touch the OS-specific layout, to avoid the problem of losing
information about the original memory type of the underlying region that
needs to be restored for the OS view. This both supersedes the
RELOCATABLE_RAMSTAGE fix and resolves the problems on Arm boards.
Change-Id: I7bb018456b58ad9b0cfb0b8da8c26b791b487fbb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds subsystem_id to nhlt structure whose value is
passed on to the endpoint's structure. Its default value is
retained to be NHLT_SSID.
Change-Id: Iad53f27e958f50e02e928cd8fa60d8397ca0eb06
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/26046
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
barrier_wait_timeout() was not used anywhere in the code. The
remaining two functions, barrier_wait() and release_barrier(), are
not used anywhere but the mp code.
Change-Id: If09991f95306becc68b6008ae6448695fb4a2dca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26021
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add method to walk memory tables from OS point of view.
The tables don't change when modifiying bootmem entries and doesn't contain
bootmem specific tags.
Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a method to walk bootmem memory tables and call a function
for each memory range. The tables might not match with OS sight
of view.
Return true if the callback function returned false.
Required for FIT support in coreboot to find a usable RAM region.
Tested on Cavium SoC.
Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix a function prototype to support PCI on non x86.
The function itself does have the correct argument already.
Change-Id: I564fcfe9b85ed4f841a48fe17a3f5bf80e16560b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There might be certain requirement in user function where user
might not want to pass any timeout value, in those cases
run_ap_work() should consider infinity as timeout and perform
all APs initialization as per specification.
Set expire_us <= 0 to specify an infinite timeout.
BRANCH=none
BUG=b:74436746
TEST=run_ap_work() is running successfully with 0 expire_us.
Change-Id: Iacd67768c8a120f6a01baaa6817468f6b9a3b764
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25622
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Adapt to coreboot coding style.
* Use coreboot's endian conversion functions.
* Fix header and header guards.
* Get rid of unused functions.
* Add Kconfig to build it on ramstage.
* Replace size32 with ALIGN_UP and DIV_ROUND_UP.
* Add NULL pointer checks
* Convert constants to defines
Required for Cavium's BDK and uImage FIT support.
Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Required for general devicetree patching and FIT support.
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For broken devices that spuriously advertise ASPM, make it possible to
decide ASPM activation in the device driver.
Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25617
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When employing PAGING_IN_CACHE_AS_RAM more areas need to be
mapped in at runtime. Therefore, paging_identity_map_addr() is
added to support adding identity mappings. Because there are a
fixed amount of pages in cache-as-ram paging only the existing
paging structures can be used. As such that's a limitation on
what regions and length one can map. Using util/x86/x86_page_tables.go
to generate page tables will always populate all the page directory
pages. Therefore, 2MiB mappings are easy to map in.
BUG=b:72728953
Change-Id: Ibe33aa12972ff678d2e9b80874529380b4ce9fd7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25718
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In some cases it may be useful to be able to bitbang a UART, such as
during early bring-up when a driver for the actual controller isn't
available yet. On some platforms we may even want to use this
permanently, such as on the SDM845 where the hardware UART controller
needs to have firmware loaded and is thus unavailable for most of the
bootblock.
This patch adds some helper code that makes it easy to implement this on
a platform, you just have to pass it a function to control the Tx pin
state and it will do the rest. It relies on the mono_time API and is
thus bound to microsecond timing granularity, but that seems to be
barely good enough for 115200 baud if the bit times are calculated
carefully.
Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
DDR4 reserves 20 bytes for part number without termination. Therefor
coreboot buffer for part number has to be increased to 21 bytes, to
account termination.
BUG=b:77943312
TEST=Build kahlee.
Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add paging_set_default_pat() which sets up the PAT MSR according
to util/x86/x86_page_tables.go. Using page attribute types require
a matching of the PAT values with the page table entries. This function
is just providing the default PAT MSR value to match against the
utility.
BUG=b:72728953
Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add the following functions for use outside of the paging module:
void paging_enable_pae_cr3(uintptr_t cr3);
void paging_enable_pae(void);
void paging_disable_pae(void);
The functions just enable and/or disable paging along with PAE.
Disassembly shows equivalent output for both versions.
BUG=b:72728953
Change-Id: I9665e7ec4795a5f52889791f73cf98a8f4def827
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Make sure to define __SIMPLE_DEVICE__ on x86 only, as other platforms
currently doesn't have support for it.
Fixes static.c devicetree compilation on non x86.
Change-Id: I75fb038681a8edf119415705af5da9f999fd8225
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25721
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Generalize cbfs_boot_load_struct() by passing in CBFS type
Change-Id: I6e5f845cb4ce5b00f01a39619919f85e39028f19
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
- Fix offsets for supported CAS latencies
- Add support for reading CWL and CMD rate from the profile
Change-Id: Ie4f545ed1df92c146be02f56fea0ca9037478649
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Reviewed-on: https://review.coreboot.org/25663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In https://review.coreboot.org/25383 people were confused about the
ordering of bootmem calls w.r.t. when entries are exposed to the OS. To
alleviate this add a notion of bootmem being initialized. In addition to
that, only mark bootmem initialized when bootmem_write_memory_table() is
called. Any other calls to bootmem before that will report an error on
the console.
Change-Id: I5bc31f555038ccabb82d902c54f95858679b1695
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
dimm_info.serial had a strange contract. The SPD spec defines a 4 byte
serial number. dimm_info.serial required a 4 character ascii string with
a null terminator.
This change makes the serial field so it matches the SPD spec.
smbios.c will then translate the byte array into hex and set it on the
smbios table.
There were only two callers that set the serial number:
* haswell/raminit.c: already does a memcpy(serial, spd->serial, 4), so
it already matches the new contract.
* amd_late_init.c: Previously copied the last 4 characters. Requires
decoding the serial number into a byte array.
google/cyan/spd/spd.c: This could be updated to pass the serial number,
but it uses a hard coded spd.bin.
Testing this on grunt, dmidecode now shows the full serial number:
Serial Number: 00000000
BUG=b:65403853
TEST=tested on grunt
Change-Id: Ifc58ad9ea4cdd2abe06a170a39b1f32680e7b299
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new method to clone an existing memrange with all of its entries.
Required for new bootmem type LB_MEM_RAM_DONT_OVERLAP.
Change-Id: I64b27bf2611ca310385ef680f030a3e4aa0c2680
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25582
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD AGESA returns DIMM info in SMBIOS format. dimm_info expects the data
in SPD format. These methods will be used to update amd_late_init.c so
it sets the correct values.
BUG=b:65403853
TEST=Built and booted grunt. Methods are not called in this commit. So
they were tested with the later commit by verifying the output of
dmidecode.
Change-Id: Id9fa98e9aad83dfd0a86f45e18b3c312665dce9b
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/25412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
DDR2 DIMMs are uniquely defined by SPD byte 64 till 72 and 93 till
98. Compute a crc16 over that data to provide a solid way to check
DIMM identify.
Reuse the crc16 function from ddr3.c to do this.
Change-Id: I3c0c42786197f9b4eb3e42261c10ff5e4266120f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
It's a standard function.
Change-Id: I039cce2dfc4e168804eb7d12b76a29af712ac7a1
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23616
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Copy strrchr from libpayload.
To be used by Cavium's BDK or FDT parsers.
Change-Id: Iab7981c25113ed16f1b8130de4935d30c29d2fa5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Sometimes when bringing up a new board it can take a while until you
have all the peripheral drivers ready. For those cases it is nice to be
able to bitbang certain protocols so that you can already get further in
the boot flow while those drivers are still being worked on. We already
have this support for I2C, but it would be nice to have something for
SPI as well, since without SPI you're not going to boot very far.
This patch adds a couple of helper functions that platforms can use to
implement bit-banging SPI with minimal effort. It also adds a proof of
concept implementation using the RK3399.
Change-Id: Ie3551f51cc9a9f8bf3a47fd5cea6d9c064da8a62
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the support for KBL-S MCH and Z270, H270, B250 and
Q250 PCH chips.
BUG=None
BRANCH=None
TEST=Boot with KBL-S CPU and B250/H270 PCHs.
Change-Id: If03abb215f225d648505e05274e2f08ff02cebdc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/25305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
