Rename pcicfg to pci_map_bus and add prototype for the platforms not
supporting ECAM.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id9517c5ec4fa6b7c7a34552bfdc6d509927f6730
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Only scan one device if it's a PCIe downstream port.
A PCIe downstream port normally leads to a link with only device 0 on
it. As an optimization, scan only for device 0 in that case.
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Change-Id: Id184d03b33e1742b18efb3f11aa9b2f81fa03806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.
There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.
Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The section is the same and at root scope.
Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The SMMSTORE_IN_CBFS option was just meant as a workaround for an
attempt to backport SMMSTORE into older Chromebooks that never actually
happened. All current and future users of coreboot should be using
SMMSTORE in an FMAP region. The APIs needed for SMMSTORE_IN_CBFS clash
with the CBFS rdev isolation needed for CBFS_VERIFICATION, so let's just
get rid of it.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ia0604a4ffd20b46774631d585925311b65d5a0e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59680
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dumped using inteltool from the Dell BIOS version A30.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable PS/2 data and clock isolation in order to properly initialize
the PS/2 keyboard and mouse in payload/OS. These bits are set by OS via
ACPI and can survive S5 state. It is necessary to clear them after an
ungraceful shutdown in order to perform PS/2 controller initialization
e.g. in SeaBIOS.
TEST=PS/2 keyboard can always be successfully initialized in SeaBIOS
on Dell OptiPlex 9010
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iac6be095c996b357b5d4e8d75199f94a89bf73e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59673
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable PMEs and clear global PME status to avoid undesired wakeups
or hangs in later stages. These bits are set by OS via ACPI can survive
S5 state so it is necessary to set them back to defaults after an
ungraceful shutdown.
TEST=Dell OptiPlex 9010 does not hang anymore after ungraceful shutdown
when configuring GPE0_EN register in southbridge LPC init
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I790cac3ce1101565b64ed54d9c6b50f5e9aa4cf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IA32_FEATURE_CONTROL does not need to be checked by BIOS, in fact these
bits are needed only by SENTER and SINIT ACM. ACM ENTERACCS does not
check these bits according to Intel SDM. Also noticed that the lock bit
of IA32_FEATURE_CONTROL cannot be cleared by issuing neither global
reset nor full reset on Sandybridge/Ivybridge platforms which results
in a reset loop. However, check the IA32_FEATURE_CONTROL SENTER bits in
ramstage where the register is properly set on all cores already.
TEST=Run ACM SCLEAN on Dell OptiPlex 9010 with i7-3770/Q77
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie9103041498f557b85019a56e1252090a4fcd0c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There is no real code or feature dependency on
CPU_INTEL_FIRMWARE_INTERFACE_TABLE for Intel TXT.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I2858c8de9396449a0ee30837a98fab05570a6259
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Although TXT specification says to do power cycle reset if TXT_RESET
is set, all Intel provided implementations issue a global reset here.
TEST=Perform ungraceful shutdown after SENTER to trigger SCLEAN path
on Dell OptiPlex 9010 and successfully call ACM SCLEAN.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I8ee2400fab20857ff89b14bb7b662a938b775304
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Allow to set global reset bits on other platforms which enable
SOUTHBRIDGE_INTEL_COMMON_ME. In certain Intel TXT flows global reset
instead of full power cycle reset is needed.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I561458044860ee5a26f7d61bcff1c407fa1533f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently there is only a function that dumps GETSEC CAPABILITIES.
Add dumping GETSEC PARAMETER for completeness and additional debug
information.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I3b2c8337a8d86000a5b43788840d15146b662598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Region device is no longer used to locate BIOS ACM. Use new CBFS API
to map and unmap the file. Using rdev_munmap on the uninitialized
region device variable causes the platform to jump to a random address.
TEST=Dell OptiPlex 9010 does not raise #UD exception when Intel TXT is
enabled, ACM SCHECK is successful
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98afba35403d5d2cd9eeb7df6d1ca0171894e9d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Implement the chipset production fuse state reporting as described in
the Intel TXT Software Development Guide. Also fix all occurrences
where the production fuse state is checked.
TEST=Dell OptiPlex 9010 with i7-3770/Q77 reports the chipset is
production fused
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic86c5a9e1d162630a1cf61435d1014edabf104b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59514
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TXT BIOS Data region version is checked by Trusted Boot code. Older
versions of TBoot (e.g. 1.8.2) may refuse to set up the MLE if BDR
version is not known. Provide an option to set the BDR version in
case an older TBoot code is used. This is very useful for platforms
with TPM 1.2.
TEST=Set BDR version to 4 and successfully boot QubesOS 4.0 with
TBoot 1.8.2 on Dell OptiPlex 9010
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic2550bd4008559bd47de9e35f8b1c7b52e6e0f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Include DPR in the memory map calculations if enabled. DPR is required
for Intel TXT support.
TEST=Boot Debian 10 and see the DPR memory being reserved in E820 and
cbmem logs:
"BIOS-e820: [mem 0x000000007fc09000-0x00000000829fffff] reserved"
"TSEG base 0x80000000 size 8M"
"DPR base 0x7fd00000 size 3M"
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ia22e49ba58709acfa0afe0921aa71d83cc06c129
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The types of pwrap_read_field()'s return value and pwrap_write_field()'s
`val` argument are u16, so correct the usage in MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ie05ab65ecd9b8ea1379ef74393285c4f5d2db8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
To raise little CPU frequency, add support for VPROC12 and VSRAM_PROC12 of MT6366.
TEST=build pass
BUG=b:202871018
Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com>
Change-Id: I718fdf36d34969a6e21ddc8c1ec6f525e0e20904
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some boards with the chrome EC will need to support more than 4
temperature sensors, so modify the number of TSRs supported when
generating the ACPI code. Note that the EC memory map already has
support for up to 16 TSRs, so no change is required on the EC
side.
BUG=b:207585491
TEST=with previous patch and some test data in brya0 overridetree.cb,
dump the SSDT and verify that all of the existing Methods for TSR0-TSR3
are also added for TSR4, as well as all Notify, etc.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Id002230bc872b0f818b0bf2b87987298189c973d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59633
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some boards may use more than 4 temperature sensors for DPTF thermal
control, so this patch adds support for one more temperature sensor.
BUG=b:207585491
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ibf9666bade23b9bb4f740c6c4df6ecf5227cfb45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Kano EVT will exchange i2c port for touchscreen and cr50.
BUG=b:195853169
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In different sku, some unused GPIO pins are processed by NC for power
consumption.
BUG=b:196790249
TEST=emerge-brya coreboot chromeos-bootimage and check power
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enabling crashlog helps partners to debug hang issues efficiently.
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in
depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble
Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
At present the default ROM for for QEMU is too small for U-Boot to fit.
Add a condition to catch this and expand it to a 1MB ROM. This allows
booting U-Boot under emulation.
It also matches the size used by other emulation boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia1a8c1109e3ece5fec56255173a2d19d4a130bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Map existing PCI_DEVICE_ID_INTEL_ADL_P_ID_1 to ADLP 4+4+2 45W SKU power
related settings.
Per doc#626774 ADL_MOW_WW46_2021, update PD optimization relaxation for
ADL-P 482(28W) and 442(45W).
BUG=b:193864533
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Change-Id: Ieba738a8ad3da5ae0a115feaa275b997a219d731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Adding the DP_ prefix to the defines for MMIO_NP, MMIO_WE and MMIO_RE
clarifies the scope of those definitions. For consistency also add this
prefix to MMIO_DST_FABRIC_ID_SHIFT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3a509ccc071aa51a67552fb9e7195358a76fe4dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On Picasso the MMIO_NP bit in the D18F0_MMIO_CTRL0 data fabric register
is bit 12, but that has changed to bit 16 in Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I64c06b84e2c0737b259077e7932f418306638e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The bit is called REF_CLK_OK_STATE and not RST_CLK_OK_STATE, so change
the name of the define to FCH_AOAC_REF_CLK_OK_STATE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iae26db94d83ebb2cb799f6d3e0bec37c8e849219
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There were only definitions for removing low, high or both glitches, but
not to not remove glitches, so add this too for completeness.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I650f7754546935539339c02bb6a94bb3f855d4ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
I found the name of the DEB_GLITCH_NONE definition a bit misleading, so
change it to DEB_GLITCH_REMOVE which should clarify what this will do.
The description for this value in the PPR/BKDG is "Remove glitch". This
also puts the define in line with GPIO_DEB_REMOVE_GLITCH which is the
only place where DEB_GLITCH_NONE/DEB_GLITCH_REMOVE is used.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59648710e0ff28c2026e1b2cc7e433cafb2f2807
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The DPTF parameters were verified by the thermal team.
BUG=b:207463762
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I634d6d98c28e75ad41488921df6b8e836e253ff1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Those methods were only in the non-common Stoneyridge GPIO ACPI code
that got dropped, so drop those unused methods too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I519d88ffa1d5d4823cce4876ecf59b9019f676e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Stoneyridge uses the same GPIO bank peripheral as Picasso and Cezanne so
we can use the common AMD SoC GPIO ACPI code.
TEST=none
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa1fc923cd5b779765917b171b5a7222f18a176a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
De-duplicate the definitions for the pin status bit and use this new
definition in both the C and the ACPI code.
TEST=Timeless build results in identical image for amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8b0fe7dbec5dac176cdfa9690862433f202fb552
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIO_WAKE_* definitions are the ones that are used in the code, so
drop the unused GPIO_*_WAKE_EN definitions for the same bits. Also move
the GPIO_WAKE_* definitions to the place the GPIO_*_WAKE_EN ones were
before this patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I622673cc72107908b525a65212061062f32e13dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
All bits covered by the bit masks GPIO_INT_ENABLE_MASK, GPIO_PULL_MASK,
GPIO_STATUS_MASK and GPIO_WAKE_MASK already have definitions in the code
so use those instead of magic numbers.
TEST=Timeless build results in identical image for amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0bc9e1cecf2f063b42de3f8875fee421dd256648
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The definitions of GPIO_INT_ENABLE_STATUS_DELIVERY and
GPIO_TIMEBASE_62440uS fit into 96 characters, so remove the unneeded
line breaks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4b9c3885259b9acf0539eed14e23fbbb0deccea7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding bit is marked as reserved in the following versions of
the documentation for all SoCs using this code:
Mullins: BKDG #52740 Rev 3.05
Stoneyridge: BKDG #55072 Rev 3.04
Raven1, Picasso: PPR #55570 Rev 3.16 & 3.18
Raven2: PPR #55772 Rev 3.08
Cezanne: PPR #56569 Rev 3.03
The old Rev 3.14 of the Picasso PPR #55570 had the bit 19 defined as
PullUpSel, but this is no longer the case in newer versions. It is
unclear if this got de-featured or if it was never present in the
silicon. To be consistent with the current documentation, drop this
define.
This patch also change the definition of GPIO_PULL_MASK to only cover
the bits used for the feature. The Cezanne PPR #56569 Rev 3.03 states a
default value of 0 for this bit after reset, so the resulting values in
the register aren't expected change. The other PPRs/BKDGs don't specify
a reset value for this bit, but it's likely safe to assume that all SoCs
that use the new GPIO interface use the same GPIO building block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaf2d4eec7a13e558c75d7edea343b876909a5b33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On ADL, we actually use debug consent 2 for soc debug by DBC
Change-Id: Ie6fbf3cdcf5dcd1a11a895ea83f55157a2ac4eb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update SA table as per latest EDS (Doc no: 601458).
Add extra SKUs accordingly.
Signed-off-by: Rick Lee <rick.lee@intel.com>
Change-Id: Ia2bb9e54456dbea634c2b8e192f9fe813b9e6706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Update thermal setting from thermal team.
BUG=b:205648035
TEST=build and verified by thermal team.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If5082462b79c88ecf510f7a552381c792604366e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The cpu_relax method is defined for x86. This CL adds a no-op method so
that it can be used in common code.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcb4546ceb2894eeb37589d0282b7e076d7a4747
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set power limits for kano based on CPU SKUs.
BUG=b:205648035
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I25cf9be68f8981d8307b4c15ab9f65b59058fb19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch moves common thermal API between chipsets
with thermal device as PCI device and thermal device behind PMC
into common file (thermal_common.c).
Introduce CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV to let SoC
Kconfig to select as applicable for underlying chipset.
+------------------------------------------------------+--------------+
| Thermal Kconfig | SoC |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_PCI_DEV | SKL/KBL, CNL |
| | till ICL |
+------------------------------------------------------+--------------+
| CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC | TGL onwards |
| | ICL |
+------------------------------------------------------+--------------+
Either of these two Kconfig internally selects
CONFIG_SOC_INTEL_COMMON_BLOCK_THERMAL to use common thermal APIs.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I14df5145629ef03f358b98e824bca6a5b8ebdfc6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable DRIVERS_GENESYSLOGIC_GL9750 support for Gimble.
BUG=b:206014046
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ifc490e6e081b6a8534656417603d2916c3edcb05
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit e0844636ac (acpi: Move ACPI table
support out of arch/x86 (2/5)) moved the main acpi header file from
arch/x86/include/acpi/acpi.h to include/acpi/acpi.h, so change the
comment in here to point to the current location.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5fddd1cd5eefd83816b1c966b5c7edf53eb2486d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Cezanne already uses a define for this and it's better to define and use
constants instead of magic values.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifa4b3b3cdb161670128b284a3396fc5a85545608
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
CB:59479 introduced a blank default statement. This is treated as an
error or warning on some older toolchains. Add a break statement on
default case.
BUG=None
TEST=Build the Guybrush mainboard.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3d034cfebc8b8ae7d7024d41b4b2207cdeb083e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Disable PSE loading by default. If left enabled (current default),
the EHL coreboot will end up in endless restart loop, due to FSP
unable to locate PSE FW image and trigger global reset.
However disabling this flag (PchPseEnable) will cause the coreboot
to trigger a single reset due to CSE signal (HECI: CSE does not
meet required prerequisites). The reason behind this is that FSP
need to perform static disabling (power gate) to fully shut down
PSE HW, and to do this will need to global reset entire system
including CSE. Then PMC will power gate PSE from the start.
To avoid this behavior, the best way to disable PSE is to disable
via IFWI FIT softstrap (For specific detail can refer to Intel EHL
coreboot MR2 release notes). With this, PMC will power gate PSE
from the first cold boot and system will boot happily without
single reset behavior.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: Iccc0ab1c2e4ebb53013795933eb88262f70f456f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
It was already enabled on T520 and L520, but disabled on X220, T420 and
T420s.
On X220, it was disabled by commit 0793afe9 (mb/lenovo/x220: disable ME).
I can't reproduce those issues today on linux 4.4 and linux 5.13.
Also, it breaks the me_disable feature, we already have a Kconfig option
to hide MEI in case of errors, and it will be hidden on disabled,
recovery, firmware update paths anyway.
Change-Id: I8e6d067a9c728443d00df541ac7a9a878df58b6a
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The Prodrive Hermes mainboard has four i211 Ethernet NICs and an i210
Ethernet NIC, but their numbering isn't consistent with the PCIe root
port function numbers. With only a M.2 SSD plugged in, Linux uses the
following names:
PHY 0 ---> enp6s0
PHY 1 ---> enp4s0
PHY 2 ---> enp3s0
PHY 3 ---> enp1s0
PHY 4 ---> enp2s0
These names change after adding or removing PCIe devices in slots
connected to root ports that get enumerated before the NICs' root
ports, because the assignment of secondary bus numbers depends on
the enumeration order. Because of this, the "predictable" network
interface names are not at all predictable, which is awful.
To avoid this, describe the NICs using SMBIOS Type41 entries with the
correct instance numbers. With this patch, Linux uses these names:
PHY 0 ---> eno0
PHY 1 ---> eno1
PHY 2 ---> eno2
PHY 3 ---> eno3
PHY 4 ---> eno4
No matter what PCIe devices are present, these names don't change.
Change-Id: I7a527298f84172f9135006083ad7e748dcc27911
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58628
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select the EC option on boards with dGPUs to report GPU temperature and
fan data.
Tested on system76/oryp6. The GPU fan speed is reported in sensors when
the system is under load.
system76_acpi-acpi-0
Adapter: ACPI interface
CPU fan: 1985 RPM
GPU fan: 2348 RPM
CPU temp: +68.0°C
GPU temp: +0.0°C
Change-Id: Ieb45dc277c7eb11be1c50b9a9e3e20e3a88578b7
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Add a new config for boards with dGPUs to enable reporting fan duty and
temperature. The dGPU is not yet enabled on any boards, so it always
reports the temp as 0. However, the EC firmware does use the dGPU's fan
and so reports valid information for fan speed.
Change-Id: Iae1063ee6a082a77ed026178eb9471bbc2b2fadf
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57881
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add CMOS option to set IME mode. Default to "Disable" for CNL and TGL-H,
and "Enable" for TGL-U. Not set for KBL, which uses ME_CLEANER.
The HECI device must be enabled in devicetree for switching modes to
function correctly.
Change-Id: I3163dcb0a4af020c2cf6f94f2bb26380f17c253e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
When the cpu_cl_discovery is called, coreboot actually assigns a BAR
to cpu crashlog pci device. Hence, we don't need to assign a tmp BAR
for cpu crashlog pci device
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in depthcharge
Change-Id: Ib7e6772be51ec4f26ef31fed6cb2bddef8ffc6be
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
With cr50 fw 0.3.22 or older version, it needs to disable autonomous
GPIO power management and then can update cr50 fw successfully.
BUG=b:202246591
TEST=FW_NAME=redrix emerge-brya coreboot chromeos-bootimage.
Change-Id: Idc01ebb4d3ef990f24f18bef5424b7d6ba683d49
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
libcbfs has a workaround to avoid writing to ROM areas:
/* Hacky way to not load programs over read only media. The stages
* that would hit this path initialize themselves. */
if ((ENV_BOOTBLOCK || ENV_SEPARATE_VERSTAGE) &&
!CONFIG(NO_XIP_EARLY_STAGES) && CONFIG(BOOT_DEVICE_MEMORY_MAPPED)) {
This workaround is not triggered in QEMU, because
BOOT_DEVICE_MEMORY_MAPPED is only selected for SPI boot devices. This
results in confusing (to the VMM developer) writes to read-only
memory.
As far as I can tell, this issue is weird but harmless, because the
code does memcpy to ROM with source == destination. The concensus in
the mailing list thread [1] was that it's worthwhile to be fixed
regardless.
[1] https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/message/KDI6YQCPXSQF4NDUAAC7TIXQKSZ6T4X7/
Change-Id: I5cefbc31f917021236105f7dc969118d612ac399
Signed-off-by: Julian Stecklina <julian.stecklina@cyberus-technology.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The device is a PCIe Gen1 to SD 3.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9750S and the revision
is 01.
The patch disables ASPM L0s.
BUG=b:206014046
TEST=Verify GL9750 enters L1 by observing CLKREQ# de-asserts.
Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I6d60cef41baade7457a159d3ce2f8d2e6b66e71c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This file is using cpuid_result and cpuid(). I also removed the spinlock
header since it's not used. This is what was previously providing the
cpu.h header.
BUG=b:179699789
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc3daa64562c4a4d57b678f13726509b480ba050
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Introduce firmware-power-managed DSD ACPI property for TPM devices.
This property can be checked by the kernel TPM driver to override how
the TPM power states are managed. This is a tri-state flag, true,
false, or unset. So an enum used to keep the flag is unset by default.
When firmware-power-managed is true, the kernel driver will not send a
shutdown during s2idle/s0i3 suspend.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown is triggered on s0ix suspend on guybrush with patched
kernel
Change-Id: Ia48ead856fc0c6e637a2e07a5ecc58423f599c5b
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add option to initialize the TPM in PSP verstage during s0i3 resume.
This is needed if the TPM is reset in s0i3. FSDL is handling
restoring everything else, so only the minimum TPM initialization is done.
Move aoac and i2c init before psp_verstrage_s0i3_resume becasue i2c
needs to be ready before attempting to restore tpm.
BUG=b:200578885,b:197965075
TEST=Multiple cycles of S0i3 suspend resume. ~66ms of additional delay.
BRANCH=None
Change-Id: Ie511928da6a8b4be62621fd2c4c31a8d1e724d48
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The "internal audio connection" setting is actually about the front
panel audio. Rename functions and variables to reflect this.
Change-Id: I1be8f68ac3e8b91bc4983dc06daa37afb7bdf926
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin van Son <justin.van.son@prodrive-technologies.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Given EC CON and associated USB port objects, custom_pld or pld_group
information is retrieved from port and added to ACPI table as _PLD field
for typec connector.
BUG=b:202446737
TEST=emerge-brya coreboot & SSDT dump in Brya test device
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibc56ecd4e8954ffaace3acd9528a064b5fa2cf6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ADL-M has its own set of VBT files to pick during execution,
this will avoid any conflict with other ADL variants.
VBT files added at chrome-internal:4138272
BUG=None
TEST= Boot device on LP5/LP4, corresponding VBT file should be loaded.
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibbf3f11c9277f5dcb3e12f9020f54ec843444c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Add events for Chrome OS diagnostics in eventlog tool:
* ELOG_TYPE_CROS_DIAGNOSTICS(0xb6): diagnostics-related events
* ELOG_CROS_LAUNCH_DIAGNOSTICS(0x01): sub-type for diagnostics boot
These events are not added anywhere currently. They will be added in
another separate commit.
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: I1b67fdb46f64db33f581cfb5635103c9f5bbb302
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some weird things happen inside FSP and the routing is not correctly
applied, with PIN D being used but lacking a proper routing in ACPI.
To work around this issue generate _PRT for all 4 INT pins.
Change-Id: I5be6e4514f8c6a47bb887d9f9b95181c9f426a51
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Kconfig item ENABLE_TCSS_DISPLAY_DETECTION.
TEST=Build with the VBT provided in issue b:199490251. Check the dev screen in bios-stage.
BUG=b:199490251, b:206014054
Signed-off-by: Adam Liu <adam.liu@quanta.corp-partner.google.com>
Change-Id: I5f34be030a6d819a0e93a2d479c4ff41bb14cfe2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Added fw_config_probe method to distinguish different audio codecs to
facilitate the use of different topology files by the OS.
BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I0d5b95e89154b2cb6b371f24cc1b151c23ff642f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
ALC5682I-VS will use in next build.
BUG=b:194367025
TEST=none.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I34d736fe1c39860443dac07435a21ccd0ee2f21c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Acoustic noise mitigation for bugzzy and set slew rate to 1/8
which is calibrated value for the board.
BUG=b:207046230
BRANCH=dedede
TEST=build firmware to UPD and Acoustic noise test
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: Id249a143efb9bce70f48fb466fed42e766a10937
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add .enable method that will set the CSME state. The state is based on
the new CMOS option me_state, with values of 0 and 1. The method is very
stable when switching between different firmware platforms.
This method should not be used in combination with USE_ME_CLEANER.
State 1 will result in:
ME: Current Working State : 4
ME: Current Operation State : 1
ME: Current Operation Mode : 3
ME: Error Code : 2
State 0 will result in:
ME: Current Working State : 5
ME: Current Operation State : 1
ME: Current Operation Mode : 0
ME: Error Code : 0
Tested on:
KBL-R: i7-8550u
CML: i3-10110u, i7-10710u
TGL: i3-1110G4, i7-1165G7
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I374db3b7c0ded71cdc18f27970252fec7220cc20
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add EC support that supports different Q Events and EC memory.
Created from the ITE IT5570E and IT8987E datasheets, all using
data port 0x4e.
Tested with Ubuntu 20.04.3 and Windows 10 on:
* StarBook Mk V (TGL + IT5570E):
* ITE Firmware 1.00
* Merlin Firmware 1.00
* LabTop Mk IV (CML + IT8987E):
* ITE Firmware 1.04
* LabTop Mk III (KBL + IT8987E):
* ITE Firmware 3.12
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8023c26de23c874c84106fda96e64dcfa0c5ba32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58343
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Thermal configuration registers are now located behind PMC PWRMBASE
for Alder Lake Point PCH. Hence, ADL SoC to select
SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC to let thermal low threshold
is being set as per mainboard provided `pch_thermal_trip`.
Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.
BUG=b:193774296
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc. prior
to FSP-S shows that registers are now programmed based on
'pch_thermal_trip' and lock register BIT31 is set.
Change-Id: I0f972f47845c123f4f74fd75091c9703d54db796
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59271
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Thermal configuration has evolved over PCH generations where
latest PCH has provided an option to allow thermal configuration
using PMC PWRMBASE registers.
This patch adds an option for impacted SoC to select the Kconfig
for allowing thermal configuration using PMC PCH MMIO space.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp platform.
Change-Id: I0c6ae72610da39fc18ff252c440d006e83c570a0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59209
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove old code in favour of new format of firmware API.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iaf8f37a08c232b8754e57f022782f21284fa07dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch uses `clrsetbits32` helper function to set thermal
device Low Temp Threshold (LTT) value.
BUG=b:193774296
TEST=Able to build and boot hatch and adlrvp with this change.
Change-Id: I51fea7bd2146ea29ef476218c006f7350b32c006
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59310
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures IA common thermal block is now able to compile
under romstage with necessary compilation issues fixed.
BUG=b:193774296
Change-Id: I3279f55436977ab9a47e04455d8469e50b5c33c8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59391
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`struct device *dev` as part of the pch_get_ltt_value() argument is
being used hence, replace with `void`.
BUG=b:193774296
Change-Id: Iecdf6f6c3023f896a27e212d7c59b2030a3fd116
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59390
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the VccIn Aux Imon IccMax for ADL-M
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I21753f2e5e9867f22c05e087cbf1f1e097d28bca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
If a USB_MUX_EVENT happens while the AP is in S3 during powerdown
transtion (S0->S3->S5), this will cause the device to boot again after
it has finished sequencing down to S5. Since S3 is not POR for ChromeOS
devices anymore, change this event to wake from S3 and S0ix to just
S0ix.
BUG=b:206867635
TEST=emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Icdab40b6a845a34246d7da336f43e970f7908301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create an NVRAM counter in TPM 2.0 that survives owner clear and can be
read and written without authorization. This counter allows to seal data
with the TPM that can only be unsealed before the counter was
incremented. It will be used during Chrome OS rollback to securely carry
data across a TPM clear.
Signed-off-by: Miriam Polzer <mpolzer@google.com>
Change-Id: I511dba3b3461713ce20fb2bda9fced0fee6517e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
as doc #632048, there is a fix in MRC for this sighting but DdrMemoryDown need to be set to 1.
BUG=b:192478111
BRANCH=volteer
TEST=FW_NAME=chronicler emerge-volteer coreboot chromeos-bootimage
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: If7ead2d0bb2955a4f1b81d012ee2e2518b2a82e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59373
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial
probe during kernel boot and prevent privacy LED blink.
BUG=b:199823938
TEST=Build and boot redrix to OS. Verify entries in SSDT and monitor LED
during boot.
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I88ea1b87698c63e1bd69367ee857fba3f25c84ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The _DSC (Device State for Configuration) object evaluates to an integer
may be used to tell Linux the highest allowed D state for a device
during probe. The support for _DSC requires support from the kernel
bus type if the bus driver normally sets the device in D0 state for
probe.
The D states and thus also the allowed values for _DSC are listed below.
Number State Description
0 D0 Device fully powered on
1 D1
2 D2
3 D3hot
4 D3cold Off
More details can be found here https://lkml.org/lkml/2021/10/25/397
BUG=none
BRANCH=none
TEST=Add corresponding field in brya, boot and dump SSDT to check if
_DSC field is as per expectation.
Name (_ADR, Zero) // _ADR: Address
Name (_HID, "OVTI8856") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "Ov 8856 Camera") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Method (_DSC, 0, NotSerialized)
{
Return (0x04)
}
Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Change-Id: I5471f144918413a2982f86beaf3dbf7e4e66cc9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add separate gpio table for TPM i2c and interrupt. Remove TPM gpios from
early_gpio_table. This allows for initializing TPM gpios separately from
other gpios.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I51d087087b166ec3bb3762bc1150b34db5b22f2f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59083
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on Intel Kit#615686, USB3 only needs to disable TBT and DMA per
port. And if uses USB3 directly you need to set TcssAuxOri accordingly.
BUG=b:206716691,b:205235144
TEST=USB function work as expected at USB3 only sku.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I303d042d6c80194ff48130fe4e9c04b49ca13ee8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add SPD support to gimble for LPDDR4 memory part MT53E1G32D2NP-046 WT:B
and MT53E512M32D1NP-046 WT:B.
BUG=b:191574298
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Id3fc35605675b953bf993a29f35140f7721eedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59299
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After CB:57539 applied, it can support romstage GPIO table override.
We can move SSD PERST# de-assertion to romstage.
The reason for this is to give enough time after PERST#
deassertion so that the SSD has enough time to initialize before
the FSP scans the RPs for downstream devices.
BUG=b:199714453
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I242cb1517f564d9d135d523b1e7f95ac34d601f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Acoustic noise mitigation for redrix and set slew rate to 1/8
BUG=b:204009588
TEST=build and verified by power team
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I0fc0bb68c4de6fca60ee290eb46a77200d748ca8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Related to https://review.coreboot.org/c/coreboot/+/58555
commit-id: 35b7e0a2d82ac
In 58555, we added the SOC ID for Stoneyridge in amdfwtool
command line. But it raised building error because it then called
"set_efs_table" without setting SPI mode. So we skipped calling that.
But in set_efs_table, it has case for Stoneyridge. The boards also
need to have this setting. So we remove the skipping and give the
proper SPI mode in mainboard Kconfig.
Change-Id: I24499ff6daf7878b12b6044496f53379116c598f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Cyan's touchpad/touchscreen interrupts as SharedAndWake
rather than ExclusiveAndWake.
Test: build/boot Windows 10 on Relm, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad/touchscreen in use.
Change-Id: I09bc878318f9fa6252f65a42ad46109418805fa0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When fetching antirollback information for the kernel, it is not always
known ahead of time what the current size of the kernel secdata area
is. If the incorrect size is passed, the TPM will return back the
correct size, but at the cost of an extra transaction; when using cr50
over I2C, this can be as much as 20ms. Currently, the first attempt uses
the minimium size (aka version 0 or 0.2), and if another size is used
(which is the case for all modern cr50-based boards, version 1 or 1.0),
then a transaction is wasted on every boot.
Therefore, change the default size sent to the TPM to be the default one
used in the VB2 API instead of the minimum one.
BUG=b:201304784
TEST=verify TPM initialization time drops by ~20ms. Also the Kernel NV
Index is read correctly in the BIOS logs.
src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1007 return code 0
src/security/tpm/tss/tcg-2.0/tss.c:231 index 0x1008 return code 0
504:finished TPM initialization 99,953 (65,606)
Change-Id: I22d9c0079bb1175f24ff7317d116e79aa5ba08ed
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
As per the TPM spec, if offset and the size field of data add to a value
that is greater than the dataSize field of the NV Index referenced by
nvIndex, the TPM shall return an error (TPM_RC_NV_RANGE). Handle the TPM
error and map it to an appropriate vboot error.
BUG=None
TEST=Build and boot to OS in Guybrush.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8b403e2f33cc1368065cc21f73df1102695f73eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Correct GPE settings so touchpad can wake up DUT.
BUG=b:206526991
TEST=emerge-brya coreboot and builds without error
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I1978e9220ad7a275d351ad5eeff7036131926b24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:205315500
TEST=emerge-brya coreboot and test that DUT can boot to OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ib26797fa2d4d0b1a6eb28c5d79b9ac0a6054abd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reverts commit 1399442289.
Reason for revert:
Some Cr50 chips with old firmware version (x.y.22) don't support
long pulse interrupt command, requiring dynamic GPIO PM to be disabled
to intercept short pulse interrupt.
Due to this coreboot needs to expose SGPM, RGPM and EGPM ACPI methods
to support power gating of GPIO communities from the kernel when dynamic
GPIO PM is disabled.
BUG=b:204832081
BRANCH=None
Test= S0ix works with dynamic PM disabled.
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Change-Id: I2b5b00878062f8a499641d7a47db54ed078cd6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
SSD sometimes can't be detected in in warm/cold boot stress.
M.2 spec describes SSD_PERST# should be sequenced after power enable.
BUG=b:199967106
TEST=SSD was always discovered in warm/cold boot stress.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I74c21cd96cf1c4518c4ed7c0b3b39e915b6b1ff7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add VBTs for all hatch variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I3c62ce204e3272e778ba0a34f7a47a65d8125f53
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
TypeC AUX configuration is variant specific. So move into variant level.
BUG=b:205235144
TEST=No typeC port 0 AUX in felwinter.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I02bfea462cf4c6359fd8d5cca4368786ee03bc8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Make psp verstage initialization more granular be splitting
verstage_soc_init into separate functions. Specifically, create
soc init functions for espi, i2c spi, and aoac.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I489889a0dfd4016aa4f2b53a2c6a7a1ea4459e60
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Add VBTs for all octopus variants currently supported by
ChromeOS recovery images. For variants which use multiple
VBTs and select at runtime, ensure these are added directly
to CBFS.
Change-Id: I4b5c4268f9255d658f9762d94488db66e0677830
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Windows (10/11) freaks out and generates an interrupt storm
if two ACPI devices are enabled and share an interrupt, even
when only one device is actually present. To mitigate this,
mark Peppy's interrupts as Shared rather than the default
of Exclusive.
Test: build/boot Windows 10 on Peppy, observe normal CPU
usage in Task Manager for System Interrupts task when
touchpad in use.
Change-Id: Ida78ddec3105cef6581cdde78da2e2c97d983a0a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This board does not have a LPC or eSPI connection to the NC FPGA anymore
and therefore IO port 0x80 is not useable for POST codes anymore. Enable
the feature of sending the POST codes to the NC FPGA via PCI so that the
POST codes are visbile again in coreboot.
Change-Id: I9043e4ec9a2ad6b946e373bb3dce9da3d42d00d1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
So far POST codes were mapped on IO port 0x80 inside the NC FPGA which
was connected via the LPC bus to the host CPU. On recent x86 generations
the LPC bus was replaced with eSPI and not all Siemens boards have the
eSPI routed to the NC FPGA. In order to have POST codes visible on those
boards the display is accessible via PCI in addition.
This patch adds the feature of sending the POST codes to the NC FPGA via
a PCI mapped register.
Change-Id: Ie15686de49cface17830365d78fe7c54cce183a0
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
This patch adds cbfs_get_size() and cbfs_get_type() helper functions
(and _ro_ variations) to look up the size or type of a CBFS file without
loading it. Generally, use of these should be discouraged because that
tends to mean that the file needs to be looked up more than once, and
cbfs_alloc() or cbfs_type_load() are usually the more efficient
alternative... but sometimes they're unavoidable, so we might as well
offer them.
Also remove the <cbfs_private.h> header which had already become sort of
unnecessary with previous changes. cbfs_boot_lookup() is now exported in
<cbfs.h> for use in inlines, but should not be used directly by other
files (and is prefixed with an underscore to highlight that).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I8092d8f6e04bdfb4df6c626dc7d42b402fe0a8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Initialize SPM (System Power Management) in RAM stage.
This adds 55ms to the boot time.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I822417f7a679107760b202dd43fb79d1934940bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59342
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch adds support for loading SPM firmware from CBFS to SPM SRAM.
SPM needs its own firmware to enable SPM suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
TEST=program counter of SPM is correct value(0x250) after booting up
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia13e5a2ecf09561856b7e958128cd2f045c39f33
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59341
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSPM is "Secure System Power Manager" that provides power control in
secure domain. The initialization flow is to load SSPM firmware to
its SRAM space and then enable.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92eb501a1e48dd02d2f94ff392933261e6a42391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Setting of MSDC is defined by soc, so we move them to soc folder.
TEST=emerge-cherry coreboot; emerge-asurada coreboot
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84ad8a4cde120c97024870ebf750d44b36c2284d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
DCM (dynamic clock management) can dynamically slow down or gate clocks
during CPU or bus idle. Enable DCM settings on the MT8186 platform.
TEST=build pass and check register ok
BUG=b:202871018
Signed-off-by: Edward-JW Yang <edward-jw.yang@mediatek.corp-partner.google.com>
Change-Id: I82add5ae629d59f7d6773e26ac9cba9d54ab8caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch modifies the pch_get_ltt_value() function return type from
uint16_t to uint32_t to accommodate platforms with more than one thermal
threshold.
For example: Alder Lake PCH Trip Point = T2L | T1L | T0L
where T2L > T1L > T0L.
BUG=b:193774296
Change-Id: I5f46ccb457b9cfebf13a512eabb3fb0fab8adb39
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Update board type to 4 as per MRC team's input. This
fixes LP5 sagv point 3 being clipped from the expected
5200Mhz to 4800Mhz.
TEST=Boot to OS, verify frequency locked.
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I9472aec41537425c1ed648b949f484939ee9ff99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
In next phase build, the audio codec will change to ALC5682I-VS
BUG=b:205883511
TEST=emerge-brya coreboot chromeos-bootimage and check audio function
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5906ef9bb88da7fe450a986bf7dd1ee701227f95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This will enable preloading ramstage. By preloading the file into
cbfs_cache we reduce boot time.
BUG=b:179699789
TEST=Boot guybrush to OS and see 12ms reduction in boot time.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibe12de806449da25bc0033b02fcb97c3384eddc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Now that CBFS has this functionality built in, we no longer need to
manually code it.
payload_preload used to use the payload_preload_cache region to store
the raw payload contents. This region was placed outside the firmware
reserved region, so it was available for use by the OS. This was
possible because the payload isn't loaded again on S3 resume.
cbfs_preload only uses the cbfs_cache region. This region must be
reserved because it gets used on the S3 resume path. Unfortunately this
means that cbfs_cache must be increased to hold the payload. Cezanne is
the only platform currently using payload_preload, and the size of
cbfs_cache has already been adjusted.
In the future we could look into adding an option to cbfs_preload that
would allow it to use a different memory pool for the cache allocation.
BUG=b:179699789
TEST=Boot guybrush and verify preloading the payload was successful
CBFS DEBUG: get_preload_rdev(name='fallback/payload') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc521b238620ff52b8ba481cd3c10e5c4f1394bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
eGPIO is a scheme which allows special power island domain IOs to be
reused as regular chip GPIOs by muxing regular TLMM functions with
Island Domain functions. Allow the eGPIO to be configured via
gpio_configure API to be used as a TLMM gpio.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Change-Id: Ib2598a41ba3bb8a8a2acff8253b5bb78633f89f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Some eMMCs need 80+ms for CMD1 to complete. And the payload may need to
access eMMC in the very early stage (for example, depthcharge needs it
20ms after started) so we have to start initialization in coreboot.
TEST=boot kernel from eMMC ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I3bc06b1fc506b1d6f54f7f456117d22477a87e29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=boot kernel from eMMC and SDCard ok
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I0fa8712eb61685a305dc5dd49cc2e55f1f0eecd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The Corsola reference design has both eMMC and SD Card interfaces
so we have to configure both in RAM stage.
TEST=build pass
BUG=b:202871018
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I2f26a8a11edd29a80a7195e3a324151d66ecb293
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The _Static_assert without message string is only available
since C++17. Add the message to avoid build fail in the macro.
BUG=b:203145462
BRANCH=cherry
TEST=build pass and boot pass
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: Ib146ffafc21b9dbb9d383c9343a9ec1d7c478faf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59298
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
MT62F1G32D4DR-031 WT:B 1 (0001)
BUG=b:204284866
TEST=emerge-brya coreboot
Change-Id: I49745948ebdb25fd98e285defd75714f80271968
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
In CL:3248796 GPIO_5 was made the default for SD_AUX_RESET_L. No variant
is actually using GPIO_5 for SD_AUX_RESET_L. Making GPIO_69 the default
and only overriding to GPIO_70 for guybrush bid==1.
BUG=b:202992077
BRANCH=None
TEST=Build and boot guybrush, SD card works
Change-Id: I6546ad9961f6f7146aa3aefc35d39a2eb282a252
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
CPUCP is CPUSS Control Processor. It refers to the firmware for control
CPUSS active power management.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board
Change-Id: Idac22c8cb231658616999bc577bdf49f9aa7ae74
Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Redrix has 4 thermal sensors, so add the missing sensors settings.
BUG=b:200134784
TEST=build and verified by thermal team.
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Ia9c58129d439ade21e96896c5e593cd08a627603
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
As Hoglin variant was recently added, need to make sure that it uses
the same configs as piglin.
BUG=b:197366666
BRANCH=None
TEST=create hoglin image and make sure that it boots on CRD 2.0
Change-Id: I14497a205262ac1081c24631e4fd8d39bb804fce
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59273
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are currently two users of the SPI hardware, the LPC SPI DMA
controller, and the boot_device_rw device. We need to ensure exclusivity
to the SPI hardware otherwise the SPI DMA controller can be interrupted
and it will silently skip transferring some blocks.
Depending on the SPI speed, this change might add a small delay when
clearing the elog since a DMA transaction might be in flight. I'll
continue optimizing the boot flow to avoid the delay.
BUG=b:179699789
TEST=Hack up the code to interleave SPI transactions and verify this
patch fixes the silent data corruption.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5eee812a6979c8c0fb313dd2fbccc14b73d7d741
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This method will allow preloading the VGA_BIOS_FILE. By preloading the
file, into cbfs_cache we reduce boot time. In the future we can also add
support for loading the second VGA_BIOS_FILE and the DGPU VGA_BIOS_FILE.
BUG=b:179699789
TEST=Boot guybrush to OS and verify 12 ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icb54fe3a942e9507ff6f1173ba5620a8f4ce6549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This change makes it so the timers run after each boot state callback,
and after each boot state. This gives coop threads the opportunity to
run more frequently and predictably.
BUG=b:179699789
TEST=Boot guybrush to OS, see SPI transactions progress faster.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9508e7777d52fe934cc09d486abc0dab5cf7dad8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This reverts commit adb393bdd6.
This relands commit 6260bf712a.
Reason for revert:
The original CL did not handle some devices correctly.
With the fixes:
* commit 36721a4 (mb/google/brya: Add GPIO_IN_RW to all variants'
early GPIO tables)
* commit 3bfe46c (mb/google/guybrush: Add GPIO EC in RW to early
GPIO tables)
* commit 3a30cf9 (mb/google/guybrush: Build chromeos.c in verstage
This CL also fix the following platforms:
* Change to always trusted: cyan.
* Add to early GPIO table: dedede, eve, fizz, glados, hatch, octopus,
poppy, reef, volteer.
* Add to both Makefile and early GPIO table: zork.
For mb/intel:
* adlrvp: Add support for get_ec_is_trusted().
* glkrvp: Add support for get_ec_is_trusted() with always trusted.
* kblrvp: Add support for get_ec_is_trusted() with always trusted.
* kunimitsu: Add support for get_ec_is_trusted() and initialize it as
early GPIO.
* shadowmountain: Add support for get_ec_is_trusted() and initialize
it as early GPIO.
* tglrvp: Add support for get_ec_is_trusted() with always trusted.
For qemu-q35: Add support for get_ec_is_trusted() with always trusted.
We could attempt another land.
Change-Id: I66b8b99d6e6bf259b18573f9f6010f9254357bf9
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With latest hardware revision all clock outputs will be used on this
mainboard. For this reason set all clock source mappings to
'PCIE_CLK_FREE' to have a free running clock.
Change-Id: Ic3f6fb4e24128742ed72dade7a4555c39fb722ae
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59259
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
HECI #2 is not used for CSE communication. Therefore, it is not
necessary to set the parameter 'Heci2Enable' in devicetree.
Change-Id: I7012e4d877a464699727ca775af3f9965e0602e9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
VT-d needs to disabled for early silicons as it results in a
CPU hard hang.
BUG=b:197177091
Test=Boot brya to OS with no hang
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b9b76b6527d8b80777cb7588ce6b12282af7882
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
PCIE port 6 is empty as per schematics.
BUG=b:206047996
TEST=PCIE port 6 is disabled.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30fa897c9310c44545e3df670895639a5144e1de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
USB2 port 0 is empty as per schematics.
BUG=b:206047996
TEST=USB2 port 0 is disabled.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I45d467a80c23d82dc33dcbed176430a758eea403
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
For the stoneyridge, soc_name is not set in Makefile, so set_efs_table
is not called. Keep it unchanged.
Change-Id: I0e82188ce64733420a578446e22a077ef789be92
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
None of the *_DEVID defines was used in the code, so drop those. The SoC
code uses the PCI ID defines from include/device/pci_ids.h instead.
Since it might still be useful to have the PCI device IDs as a reference
in the SoC's pci_devs.h, add those as comments instead.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7c77d648dac57b15b56f631bd8b2494676c00a8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable RTD3 driver for PCIe-eMMC bridge, If the board version is less
than 1, do not enable RTD3 driver.
BUG=b:204469567
TEST=Boot into eMMC storage and perform suspend stress 100 cycle passed
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I5836d65cedfe3907af2c4c33de7a396c4bb8b727
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change to use MAX_DSAR_SET_COUNT which WLAN driver always expects 3
no matter what the revision is for EWRD.
It will pass the WLAN driver check then to retrieve the data properly.
BUG=b:204414616
TEST= tested on brya with DRTU tool to verify if SAR table is
read properly or not.
Change-Id: I18e7d5f658bbf42b7eeed3da330508f14b86c0f8
Signed-off-by: Matt Chen <matt.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Update PL1 minimum value from 3W to 12W as per the thermal design
discussed in this bug 203371203 comment #10.
BUG=b:203371203
BRANCH=None
TEST=Build and boot the gimble system
Change-Id: Id66cfb6f6dc0217bd4d83eae1d66ad867a1bdb46
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Create the vell variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:205908918
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_VELL
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: Ide8ba1c0dd9b5d9ad90556053abf2a597136a10c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add Kconfig option `SOC_INTEL_TIGERLAKE_S3` which will adjust
the ACPI to not offer D3Cold when using S3.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ieb1cc3d6a03cb452ff38ae393a993e881d9b5ff4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Software Connection Manager doesn't work with Linux 5.13 or later and
results in TBT ports timing out. Not advertising this results in
Firmware Connection Manager being used and TBT works correctly.
Linux patch:
c6da62a219
Tested on:
* StarBook Mk V
* System76 Oryx Pro 8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib947c3c9cd843e54d4664509c15336178c0bc99e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Add support for VMCH and VMC of MT6366.
TEST=measure voltage 3.3V for VMCH and VMC
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Id8d98b6d827abd4713ee5c216941a9621422c7eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. Enable and setup USB drivers.
2. Pull up to a weak resistor for USB3_HUB_RST_L and we reset
the hub via GPIO149.
TEST=boot kernel from USB ok
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ifcc11d51b0c1e495477957111e6021ef8275f629
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The 'corsola' reference design will include two implementations
with different BOM selections - 'krabby' and 'kingler'.
TEST=none
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Iaf9c6af1a395030937a9a5c00e95d7246ddcb6eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. Turn off L2C SRAM and reconfigure as L2 cache
Mediatek SoC uses part of the L2 cache as SRAM before DRAM is ready.
After DRAM is ready, we should invoke disable_l2c_sram to reconfigure
the L2C SRAM as L2 cache.
2. Configure DMA buffer in DRAM
Set DRAM DMA to be non-cacheable to load blob correctly.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If56d29cdd7d9dfaed05e129754aa1f887a581482
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Move mtk_soc_disable_l2c_sram and mtk_soc_after_dram to common folder
which are the same between MT8192, MT8195 and MT8186.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8f49214b932a8d28ed2ca0d764dc745fa8ad330d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Change help text to "dual IO read mode" to reduce noun confusion.
Suggestion from this comment:
https://review.coreboot.org/c/coreboot/+/58837/comment/40a98af1_dce6bb2b/
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I54b81cdeba3b693451f66e003fb470c9f8c19ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
CONFIG(SMP) was an invalid condition to use in cases where one
stage requires spinlocks and another one does not. The
stage not requiring spinlock still required <smp/spinlock.h>
to be implemented with no-op stubs.
This reverts commit 037ee4b556
soc/amd/picasso: Add dummy spinlock for psp_verstage
Change-Id: Iba52febdeee78294f916775ee9ce8a82d6203570
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add separate gpio table for early eSPI bus init. Remove espi GPIO from
early_gpio_table. This allows for initializing eSPI separately from
other GPIOs. Simplify verstage_mainboard_early_init.
BUG=b:200578885
BRANCH=None
TEST=Build and boot guybrush
Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change adds about 30 KiB to FSP-M. When not using the SPI DMA
controller, this change actually has a ~7 ms boot time penalty. When
we use the DMA engine, we end up with about a 5 ms decrease. Once we
switch to 100 MHz SPI this will help even more since we have effectively
eliminated the decompression time.
BUG=b:179699789
TEST=Boot nipperkin to OS and take boot time measurements
fspm.bin 0x2efc0 fsp 90953 LZMA (233472 decompressed)
fspm.bin 0x2cfc0 fsp 121156 LZ4 (233472 decompressed)
- FSP-M / no async -
| 508 - finished loading body | 177.019 | 179.384 Δ( 2.36, 0.16%) |
...
| 970 - loading FSP-M | 0.346 | 0.346 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 0.009 | 0.01 Δ( 0.00, 0.00%) |
| 18 - finished LZ4 decompress (ignore for x86) | 53.916 | 59.475 Δ( 5.56, 0.37%) |
- FSP-M / async -
| 508 - finished loading body | 177.185 | 179.689 Δ( 2.50, 0.18%) |
...
| 970 - loading FSP-M | 0.989 | 0.99 Δ( 0.00, 0.00%) |
| 17 - starting LZ4 decompress (ignore for x86) | 9.483 | 12.877 Δ( 3.39, 0.24%) |
| 18 - finished LZ4 decompress (ignore for x86) | 10.833 | 0.312 Δ(-10.52, -0.75%) |
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7d0363d27d98d4ed3afc6f802a13ff7986391921
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Show the DEBUG_FUNC option if COSOLE_OVERRIDE_LOGLEVEL is set, or it
will never be available for some mainboards.
This was missed in commit cf3dcd6d29
Change-Id: Id2ef287fb39989007f28fc6475209eda0a63c792
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Calling reboot_into_recovery with NULL context fails. Initializing ctx
early also fails because the cmos is not ready until after
verstage_soc_early_init. So just reboot and hope for the best.
BUG=None
TEST=Boot guybrush, suspend/resume guybrush
BRANCH=None
Change-Id: I7267a14ab048781b8998d3a6f4220de10e7df250
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This reverts commit ba6fdc892d.
Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The 64-bit compiler x86_64-linux-gnu-gcc-10 aborts the build with the format
warning below:
CC romstage/soc/intel/xeon_sp/memmap.o
src/soc/intel/xeon_sp/memmap.c: In function 'fill_postcar_frame':
src/soc/intel/xeon_sp/memmap.c:39:62: error: format '%lx' expects argument of type 'long unsigned int', but argument 4 has type 'size_t' {aka 'unsigned int'} [-Werror=format=]
39 | printk(BIOS_DEBUG, "cbmem base_ptr: 0x%lx, size: 0x%lx\n", cbmem_base, cbmem_size);
| ~~^ ~~~~~~~~~~
| | |
| long unsigned int size_t {aka unsigned int}
| %x
As `cbmem_size` is of type `size_t` use the appropriate length modifier
`z`.
Change-Id: I1ca77de1ce33ce1e97d7c8895c6e75424f0769f5
Found-by: gcc (Debian 11.2.0-10) 11.2.0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Lance Zhao
Do not place console output in low-level GPIO functions.
The caller of get_recovery_mode_switch() is in vboot_logic.c
that is linked in romstage. So presumably recovery mode
is broken and is not fixed with this commit either.
Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Add PEG60/10/62 IDs (0x464d/0x460d/0x463d) into device/pci_ids.h
2. Add these new IDs into pcie_device_ids[] in pcie.c
BUG=b:205668996
TEST=Build and check fsp log to confirm the settings are set properly.
Signed-off-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com>
Change-Id: Idc8a09b0579e1e6053ed2e35b7556a180a5f0088
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Add APU device apc driver and set up permissions.
APU has its own device apc for control access by domains.
For Domain 0, the access to the following slaves are restricted to
security read and write:
apusys_ao-2, apusys_ao-4, apusys_ao-5, apu_sctrl_reviser,
apu_iommu0_r1 apu_iommu0_r2, apu_iommu0_r3, apu_iommu0_r4
apu_iommu1_r1, apu_iommu1_r2, apu_iommu1_r3,apu_iommu1_r4
For VPU, D0/D5 are set as no protection, other domains are forbidden.
For other slaves, the D0 is no protection, other domains are forbidden.
BUG=b:203145462
BRANCH=cherry
TEST=boot cherry, check dump log and test permissions
Signed-off-by: Flora Fu <flora.fu@mediatek.com>
Change-Id: If92d3b02ac4966332315b85d68e0f48c6a9fce85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
FSP-S is normally memmapped and then decompressed. There are about 7 ms
between starting ramstage, and loading FSP-S. By preloading we can
ensure the fsps.bin is already in RAM by the time we need it. This
reduces boot time by about 7 ms.
BUG=b:
TEST=Boot nipperkin and see ~7ms reduction in boot time
| 10 - start of ramstage | 0.044 | 0.044 Δ( 0.00, 0.00%) |
| 30 - device enumeration | 1.899 | 2.073 Δ( 0.17, 0.01%) |
| 971 - loading FSP-S | 6.645 | 6.628 Δ( -0.02, -0.00%) |
| 15 - starting LZMA decompress (ignore for x86) | 0.016 | 0.01 Δ( -0.01, -0.00%) |
| 16 - finished LZMA decompress (ignore for x86) | 15.266 | 8.316 Δ( -6.95, -0.47%) |
| 954 - calling FspSiliconInit | 0.08 | 0.09 Δ( 0.01, 0.00%) |
CBFS DEBUG: _cbfs_alloc(name='fsps.bin', alloc=0xc9761e5c(0xc97a3f0c), force_ro=false, type=-1)
CBFS: Found 'fsps.bin' @0x1a1fc0 size 0x102cd in mcache @0xc97dd208
waiting for thread
took 1 us <-- fsps.bin was preloaded
CBFS DEBUG: get_preload_rdev(name='fsps.bin') preload successful
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5a728047b8ad92d70bba8485017579aa3df48d95
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This will enable reading FSP-S/M using the SPI DMA controller.
BUG=B:179699789
TEST=Build guybrush with SPI DMA enabled and verify alignment is set
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I282b9989d8e95c93603c6f69616a8f236a4e2e35
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or
less to production that will need to disable autonomous GPIO power
management and then can get H1 version by gsctool -a -f -M
BUG=b:201054849
TEST=USE="project_primus emerge-brya coreboot" and verify it builds
without error.
Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Low-level GPIOs should not depend on late cros_gpios that
should be guarded with CHROMEOS and implemented for the
purpose of ACPI \OIPG package generation.
Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable SaGv.
BUG=b:198235324
TEST=Boot into without issues.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: Id25d2797a91b05264b1a76fa8faec0533dd5ac78
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59120
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `dev` parameter of the `azalia_codecs_init()` function is not used.
Remove it, and update all call sites accordingly.
Change-Id: Idbe4a6ee5e81d5a7fd451fb83e0fe91bd0c09f0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59119
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: I83cf1a3a1a3854c9283ccac5e254357a32638dda
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59118
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the `codec_init()` function non-static so that it can be used in
other places. Rename it to `azalia_codec_init()` for consistency with
the other functions of the API.
Also, update the function's signature to make it more flexible. Remove
the unused `dev` parameter and allow callers to pass the verb table to
use. Update the original call site to preserve behavior.
Change-Id: I5343796242065b5fedc78cd95bcf010c9e2623dd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59117
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the `azalia_program_verb_table()` function in preparation to
deduplicate Azalia init code.
Change-Id: I22cfee41e001c9ecf4fbac37aadbd12f43ac8aaf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59116
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Handle the return value of `azalia_program_verb_table()` and print
different messages accordingly.
Change-Id: I99e9e1416217c5e67c529944736affb31f9c7d2f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59115
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: I982c1725d5affe95a20aa6713a246cd6b1ad270c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59114
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: Ib3b40e5788c6315cad02b670346997c9179e5fab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: Idc8d272d76a031c6835baf952eca03fc2e306525
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: I53d993ff74e7952c34fbe94d49d3ebf2489dd414
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the functionally-equivalent common Azalia code to get rid of
redundant code.
Change-Id: Icc435dd0c7cef1b458c877b5a64e6dba1d10524c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These southbridges support four external codecs, not three.
Change-Id: I3f352451d16dceefa0f3fabf413a0e57aa498df5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Make the `codecs_init()` function non-static so that it can be used in
other places. Rename it to `azalia_codecs_init()` to avoid name clashes
with static definitions in southbridge code (which will be removed in
subsequent commits).
Change-Id: I080a73102b0c4f9f8a283cd93bba9b3b23169be0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For consistency with other Intel southbridges, program PC BEEP verbs.
None of the boards in the tree using this southbridge provide PC BEEP
verbs, so this change makes no difference.
Change-Id: I94d24999af819cf3951510586fd4864d1ed3f2f1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use the `azalia_program_verb_table()` function in preparation to
deduplicate Azalia init code.
With this change, the "Azalia: verb loaded." message is now printed when
programming the verbs failed. This will be addressed once `codec_init()`
has been deduplicated.
Change-Id: I5d9e0f19429620166f2a6ef48ec7c963ee64b59c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
BUG=b:192415743
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Move SGX ACPI code to block/acpi. Also move the register definitions
there, since they are misplaced in intelblocks/msr.h and are used only
once anyways.
Change-Id: I089d0ee97c37df2be060b5996183201bfa9b49ca
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently all the power sequencing for FPMCU is done explicitly in
different stages of coreboot. This can all be done by adding ACPI power
resources for FPMCU and clean up the unused code. Here is the expected
power sequence:
PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL
Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL
Reboot : Shutdown -> 200 ms delay -> PowerUp
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to
unlock the system after the first login attempt. Ensure that the FP is
able to wakeup the system. Observed that the power resource is added
correctly in the FPMCU ACPI object
Name (_PR0, Package (0x01) // _PR0: Power Resources for D0
{
PR01
})
Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot
{
PR01
})
PowerResource (PR01, 0x00, 0x0000)
{
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x01)
}
Method (_ON, 0, Serialized) // _ON_: Power On
{
\_SB.CTXS (0x0B)
\_SB.STXS (0x20)
\_SB.STXS (0x0B)
}
Method (_OFF, 0, Serialized) // _OFF: Power Off
{
\_SB.CTXS (0x0B)
\_SB.CTXS (0x20)
}
}
Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Modify settings to enable CPU PCIE RP 1 according to schematics.
BUG=b:205504257
TEST=emerge-brya coreboot and can successfully boot with ssd and emmc.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
- Set MAX OC1 to USB2_C1
BUG=b:205676803
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
We need to put USB setting in mux order.
BUG=b:204230406
TEST=Type C mux configuration is correct.
Wrong:
added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
Correct:
added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add wifi sar for galtic/galtic360/galith360
Using convertible mode of SKU ID to load wifi table.
Each Project and SKU ID correspond as below
galtic (sku id:0x120000)
galith (sku id:0x130000)
gallop (sku id:0x150000)
galtic360 (sku id:0x260000)
galith360 (sku id:0x270000)
BUG=b:203741126
TEST=emerge-dedede coreboot chromeos-bootimage \
coreboot-private-files-baseboard-dedede
verify the SAR table is correct in each project
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
List of changes:
1. Create Module Type macros as per Memory Type
(i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation
issue due to renaming of existing macros due to scoping the Memory
Type.
2. Use dedicated Memory Type and Module type for `Form Factor`
and `TypeDetail` conversion using `get_spd_info()` function.
3. Create a new API (convert_form_factor_to_module_type()) for
`Form Factor` to 'Module type' conversion as per `Memory Type`.
4. Add new argument as `Memory Type` to
smbios_form_factor_to_spd_mod_type() so that it can internally
call convert_form_factor_to_module_type() for `Module Type`
conversion.
5. Update `test_smbios_form_factor_to_spd_mod_type()` to
accommodate different memory types.
6. Skip fixed module type to form factor conversion using DDR2 SPD4
specification (inside dimm_info_fill()).
Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx.
BUG=b:194659789
TEST=Refer to dmidecode -t 17 output as below:
Without this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Unknown
....
With this code change:
Handle 0x0012, DMI type 17, 40 bytes
Memory Device
Array Handle: 0x000A
Error Information Handle: Not Provided
Total Width: 16 bits
Data Width: 16 bits
Size: 2048 MB
Form Factor: Row Of Chips
....
Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
It's commented in <types.h> that it shall provide <commonlib/helpers.h>.
Fix for ARRAY_SIZE() in bulk, followup works will reduce the number
of other includes these files have.
Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
MAINBOARD_HAS_CHROMEOS always evaluates true for this board.
The commentary about get_write_protect_state() was wrong, it's
currently only called in ramstage.
Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Enable DPTF based thermal control functionality for tpch device
on brya device.
BUG=b:198582766
BRANCH=None
TEST=Build FW and test on brya0 board
Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Since the if block contains multiple statements, it uses curly braces
around them, so also add curly braces around the else block even though
it only contains one statement.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia8d6b45ec16916ff77078446414de259cffa1475
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59070
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We are currently counting how long it takes to print the waiting
message, in addition to the actual time we spent waiting. This results
in inflating the measurement by 1.7ms when the serial console is
enabled. This CL makes it so the print happens before the stopwatch
starts.
BUG=b:179699789
TEST=No longer see printk time taken into account on serial console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib48e37c1b2cb462d634141bf767673936aa2dd26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Currently, the MMCONF Kconfigs only support the Enhanced Configuration
Access mechanism (ECAM) method for accessing the PCI config address
space. Some platforms have a different way of mapping the PCI config
space to memory. This patch renames the following configs to
make it clear that these configs are ECAM-specific:
- NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT
- MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT
- MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS
- MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER
- MMCONF_LENGTH --> ECAM_MMCONF_LENGTH
Please refer to CB:57861 "Proposed coreboot Changes" for more
details.
BUG=b:181098581
BRANCH=None
TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max
Make sure Jenkins verifies that builds on other boards
Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Use bitwise or instead of additions to build bit masks with multiple
bits set.
TEST=Timeless build results in identical image on amd/mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42cc6686d8fa3f694a46ba4ca801a822ef1db1d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In both the Picasso PPR (rev 3.16) and the Cezanne PPR (rev 3.03) bit 16
of the misc I2C pad control registers is defined as BiasCrtEn, so rename
I2C_PAD_CTRL_BIOS_CRT_EN to I2C_PAD_CTRL_BIAS_CRT_EN.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If39ac17a433cb90c944fdde038cd246a995e193a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59028
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set RFI Spread Spectrum to 6% for Redrix as RF team request.
The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard
as default.
BUG=b:200886627
TEST=build
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is
copied to CSE_RW, so the sizes of these regions need to match.
BUG=b:189177538
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Reka Norman <rekanorman@google.com>
Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
For the Qualcomm PBL configuration of GPIO, we need to initial the
GPIOs for VDD33# and RST# at the beginning of coreboot. According to
the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#.
BUG=b:204637643
BRANCH=trogdor
TEST=verified the waveform of ps8640 at coreboot phase.
Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com>
Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns
and fall_time_ns values for each port are capured by a scope.
BUG=None
BRANCH=dedede
TEST=built and verified adjusted I2C speed < 400KHz
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add ELAN touchscreen support for magneto.
BUG=b:203122673
TEST=Build and verify that touchscreen works.
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update charger performance control table of DPTF for bugzzy.
Since the EC change chromium:197776876 modified maximum charging current
to reduce skin temperature, this change adjusts the charging performance
table with the modified value.
BUG=b:197776876
BRANCH=dedede
TEST=emerge-dedede coreboot
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
GNVS should not be used for values that are static at runtime. Thus,
use SSDT for the SGX fields.
Change-Id: Icf9f035e0c2b8617eef82fb043293bcb913e3012
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This drops VBOOT_NO_BOARD_SUPPORT.
There is little impact of always having recovery_mode_switch()
implemented in bootmode.c. A weak write_protect_state() is not
necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation.
Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS)
so the weak implementation would not be referenced.
Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
There is no platform in our tree that requires the PCI MMIO ops but
doesn't want the pci_s_* definitions. The only case where we include
the `pci_mmio_cfg.h` header but don't want the pci_s_* functions to
use MMIO is on older x86 platforms, so move the guard there.
Change-Id: Iaeed6ab43ad61b7c0e14572b12bf4ec06b6a26af
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Avoid indirect <vc/google/chromeos/chromeos.h> as the
files really only need <security/vboot/vboot_common.h>.
Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Technically, it's not depending on the hardware but on the software
(OS/payload), if the PM Timer is optional. OSes with ACPI >= 5.0A
support disabling of the PM Timer, when the respective FADT flag is
unset. Thus, drop this guard.
For platforms without hardware PM Timer (Apollo Lake, Gemini Lake) the
Kconfig `USE_PM_ACPI_TIMER` depends on `!NO_PM_ACPI_TIMER`.
As of this change, new platforms must either implement code for
disabling the hardware PM timer or select `NO_PM_ACPI_TIMER` if no such
is present.
Change-Id: I973ad418ba43cbd80b023abf94d3548edc53a561
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lance Zhao
In the non-XIP world, FSP is normally memmapped and then decompressed.
The AMD SPI DMA controller can actually read faster than mmap. So by
reading the contents into a buffer and then decompressing we reduce boot
time.
BUG=b:179699789
TEST=Boot guybrush and see 30ms reduction in boot time
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I28d7530ae9e50f743e3d6c86a5a29b1fa85cacb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This option will allow setting the FSP alignment in CBFS.
BUG=b:179699789
TEST=Boot with and without the option set and verify -a option was
passed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4533f6c9d56bea6520aa3aa87dd49f2144a23850
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We no longer need to do this since we relocate at runtime.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibef849d5b3f0290cb7b7c5ff18aabe002bf53344
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD platforms pass in the base address to cbfs tool:
fspm.bin-options: -b $(CONFIG_FSP_M_ADDR)
There is no technical reason not to allow FSP-M to be relocated when
!XIP. By allowing this, we no longer need to pass in the base address
into cbfstool when adding fspm.bin. This enables passing in the
`--alignment` argument to cbfs tool instead. cbfstool currently has a
check that prevents both `-b` and `-a` from being passed in.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I797fb319333c53ad0bbf7340924f7d07dfc7de30
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The follow up CLs will use CBFS_PRELOAD. The default CBFS_CACHE_SIZE was
derived by examining the `cbfstool print` output and summing the files
we intend to preload.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I208067e6ceec6ffb602a87bee3bf99a0a75c822d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Read fw_config value from VPD.
This new option can be used where chrome EC is not supported like
pre-silicon platform and fw_config can be updated by VPD tool in OS.
TEST= boot to OS and read fw_config from vpd
1. Boot to OS
2. Write "fw_config" in VPD
ex) vpd -i "RW_VPD" -s "fw_config"="1"
3. reboot and check fw_config value from coreboot log
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I4df7d5612e18957416a40ab854fa63c8b11b4216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Request fw_config values from various sources (as enabled via Kconfig)
until a valid value has been read.
With this change, Chrome EC CBI takes precedence over CBFS fw_config.
TEST=select both configs and check fallback behavior.
1. select both FW_CONFIG_SOURCE_CHROMEEC_CBI and FW_CONFIG_SOURCE_CBFS
2. check log for reading fw_config from CBI and CBFS
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I215c13a4fcb9dc3b94f73c770e704d4e353e9cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
elog init requires doing a lot of SPI transactions. This change makes it
clear how long we spend initializing elog.
BUG=b:179699789
TEST=Boot guybrush and see elog init timestamps
114:started elog init 3,029,116 (88)
115:finished elog init 3,071,281 (42,165)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia92372dd76535e06eb3b8a08b53e80ddb38b7a8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58957
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This gives us a knob that can be controlled via a .config to
enable/disable file preloading. I left the option disabled because
there is currently a race condition that can cause data corruption when
using the SPI DMA controller. The fix will actually introduce a
boot time regression because the preloads are happening at the same time
as the elog init. I want to keep preloading disabled for now until
I get all the sequencing worked out.
BUG=b:179699789
TEST=Boot guybrush and verify no preloading happens.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie839e54fa38b81a5d18715f190c0c92467bd9371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SPI speed override is not related to ChromeOS, thus the
location in chromeos.c was poor choice.
Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since all other defines for the number of certain things are at the top
of the file, move NUMBER_SMITYPES there as well to keep things
consistent.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idfb599531d6cc382ab258bd1eae89e7b35fa9e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
SCIMAPS is the total number of SCI to GEVENT mappings. configure_scimap
returns early when the scimap is greater or equal than SCIMAPS, so for
SMITYPE_ACDC_TIMER it returned early without doing what was expected
from it to do despite that being a valid value, so fix this off-by-one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibaf8c5618ddbf0b8d4cd612a7f1347d8562bbfcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Return 0 instead of -1 in case of error. Both values indicate an error
has happened. Adapt `cpu_bus_scan()` accordingly.
Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
EINT event mask register is used to mask EINT wakeup source.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel EINT upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I84946c2c74dd233419cb94f013a42c734363baf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The NOR-Flash can be configured on SPI0 or TDM-RX GPIOs so we have to
provide an init function in SoC for the mainboard to select right
configuration.
TEST=boot to romstage
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I285ec64ace8b72a48ef1d481d366bd67cb9b0337
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch sets the enable the external voltage rails since taeko
board have V1p05 and Vnn bypass rails.
BRANCH=None
BUG=b:204832954
TEST=FW_NAME=Check in FSP log and run PLT test
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Type C port2 uses EC mux port0 as per schematics.
BUG=b:204230406
TEST=No error message in depthahrge.
update_port_state: port C2: get_usb_pd_mux_info failed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Rewrite level type check and use unsigned types. In addition, also use
unsigned types in the `get_cpu_count()` function.
Change-Id: I63f236f0f94f9412ec03ae25781befe619cf7c1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reduce the visibility of the `get_threads_per_package()` function and
retype its return value to `unsigned int`.
Change-Id: Ie71730d9a89eb7c4bb82d09d140fbcec7a6fe5f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This can now be controlled with the `MMCONF_BUS_NUMBER` Kconfig option.
Change-Id: If0fdefc5b4339acc843443c551892b397ed39c2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Lance Zhao
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ic6e28add78f686fc9ab4556eddbedf7828fba9ef
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: Ia9a4b62c857f7362d67aee4f9de3bb2da1838394
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I2a57ea1c2f5b156afd0724829e5b1880246f351f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I617fea8a09049e9a87130640835ea6c3e2faec60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The `find_resource` function will never return null (will die instead).
In cases where the existing code already accounts for null pointers, it
is better to use `probe_resource` instead, which returns a null pointer
instead of dying.
Change-Id: I13c7ebeba2e5a896d46231b5e176e5470da97343
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Makes it so I can enable SPI debugging without modifying the source.
BUG=b:179699789
TEST=Add CONFIG_SOC_AMD_COMMON_BLOCK_SPI_DEBUG=y to my .config
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie3815e0398b5268874039196a625fc29dd3dc3d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reduces the number of selects required in the SOC_SPECIFIC_OPTIONS.
BUG=b:179699789
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7f1364fc269ea5ec17982bf750a164a3290adb0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This API will hide all the complexity of preloading a CBFS file. It
makes it so the callers simply specify the file to preload and CBFS
takes care of the rest. It will start a new thread to read the file into
the cbfs_cache. When the file is actually required (i.e., cbfs_load,
etc) it will wait for the preload thread to complete (if it hasn't
already) and perform verification/decompression using the preloaded
buffer. This design allows decompression/verification to happen in the
main BSP thread so that timestamps are correctly reflected.
BUG=b:179699789
TEST=Test with whole CL chain, verify VGA bios was preloaded and boot
time was reduced by 12ms.
Logs:
Preloading VGA ROM
CBFS DEBUG: _cbfs_preload(name='pci1002,1638.rom', force_ro=false)
CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0
spi_dma_readat_dma: start: dest: 0x021c0000, source: 0x51cc80, size: 55296
took 0 us to acquire mutex
start_spi_dma_transaction: dest: 0x021c0000, source: 0x51cc80, remaining: 55296
...
spi_dma_readat_dma: end: dest: 0x021c0000, source: 0x51cc80, remaining: 0
...
CBFS DEBUG: _cbfs_alloc(name='pci1002,1638.rom', alloc=0x00000000(0x00000000), force_ro=false, type=-1)
CBFS: Found 'pci1002,1638.rom' @0x20ac40 size 0xd800 in mcache @0xcb7dd0f0
waiting for thread
took 0 us
CBFS DEBUG: get_preload_rdev(name='pci1002,1638.rom', force_ro=false) preload successful
In CBFS, ROM address for PCI: 03:00.0 = 0x021c0000
PCI expansion ROM, signature 0xaa55, INIT size 0xd800, data ptr 0x01b0
PCI ROM image, vendor ID 1002, device ID 1638,
PCI ROM image, Class Code 030000, Code Type 00
Copying VGA ROM Image from 0x021c0000 to 0xc0000, 0xd800 bytes
$ cbmem
...
40:device configuration 5,399,404 (8,575)
65:Option ROM initialization 5,403,474 (4,070)
66:Option ROM copy done 5,403,488 (14)
...
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I879fc1316f97417a4b82483d353abdbd02b98a31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This cleans up the warning message:
WARNING: Prefer using '"%s...", __func__' to using 'thread_run', this function's name, in a string
BUG=b:179699789
TEST=boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I85bacb7b2d9ebec40b6b05edc2ecf0ca1fc8ceee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This makes it easier to grep for errors.
BUG=b:179699789
TEST=Boot guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7eecdfed6046b7d609069e7427f6883a4e9e521d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
All the mainboard variants of mc_ehl do not use the external switches
for the bypass rails. Disable the matching UPDs and all the low power
modes of the PMC.
Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to get a reliable real-time performance disable all P-States
for all mc_ehl based mainboard.
Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Disable all C-states other than C0/C1 for CPU and package.
Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
There are a bunch of devices in the devicetree that are disabled in
FSP-S and not used on this board. Having them around in the devicetree,
even if disabled, is not necessary and leads to a message in the log
(left over static devices...check your devicetree).
This commit cleans up devicetree.cb and removes all unused and disabled
devices.
Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will be used in cbfs.c which is used in all stages.
BUG=b:179699789
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0713ae766c0ac9e43de702690ad0ba961d636d18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
AMD platforms require the SPI contents to be 64 byte aligned in order to
use the SPI DMA controller.
BUG=b:179699789
TEST=Build guybrush and verify cbfs was invoked with -a 64
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I842c85288acd8f7ac99b127c94b1cf235e264ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
AMD platforms require the destination to be 64 byte aligned in order to
use the SPI DMA controller. This is enforced by the destination address
register because the first 6 bits are marked as reserved.
This change adds an option to the mem_pool so the alignment can be
configured.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8d77ffe4411f86c54450305320c9f52ab41a3075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56580
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently link_speed_capability is not specified within the DXIO
descriptors sent to FSP. This value specifies the maximum speed that
a PCIe device should train up to. The only device on Monkey Island that
is not currently running at full speed is the NVME but this may not
always be the case.
BUG=b:204791296
TEST=Boot to OS and check link speed with LSPCI to verify
NVME link speed goes from 2.5 GT/s to 5 GT/s
Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
All of these names came from public sources.
Signed-off-by: Martin Roth <martin@coreboot.org>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Introduce the `smbios_dev_info` devicetree keyword to specify the
instance ID and RefDes (Reference Designation) of onboard devices.
Example syntax:
device pci 1c.0 on # PCIe Port #1
device pci 00.0 on
smbios_dev_info 6
end
end
device pci 1c.1 on # PCIe Port #2
device pci 00.0 on
smbios_dev_info 42 "PCIe-PCI Time Machine"
end
end
The `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` Kconfig option enables using
this syntax to control the generated Type 41 entries. When this option
is enabled, Type 41 entries are only autogenerated for devices with a
defined instance ID. This avoids having to keep track of which instance
IDs have been used for every device class.
Using `smbios_dev_info` when `SMBIOS_TYPE41_PROVIDED_BY_DEVTREE` is not
enabled will result in a build-time error, as the syntax is meaningless
in this case. This is done with preprocessor guards around the Type 41
members in `struct device` and the code which uses the guarded members.
Although the preprocessor usage isn't particularly elegant, adjusting
the devicetree syntax and/or grammar depending on a Kconfig option is
probably even worse.
Change-Id: Iecca9ada6ee1000674cb5dd7afd5c309d8e1a64b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As a prevention of Row-Hammer attacks enable the FSP-M parameter
'RhPrevention'.
Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This configures GPIO GPP_G5 as an input pin for SD card detect.
Change-Id: I708eb112fa054f2f88857001c409fb62493b6206
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on
this mainboard and are not routed either, so remove them from the
devicetree completely. PCIe root port #7 (00:1c.6) is connected and
used. Add the missing settings for L1 substates and latency reporting to
disable these features for this port as well.
Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On mc_ehl2 there are currently four of the six PCIe clocks used to drive
PCIe devices. None of the used clock output is dedicated to a special
device. Therefore do not use a port mapping of the clocks to avoid a
stopping clock once a device is missing and the matching root port is
disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free
running clock.
In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the
value 0xFF to disable the CLKREQ-feature and unused clocks.
Change-Id: I81419887b7f463a937917b971465245c1cb46b94
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the
eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed
that the native function names don't have the EMMC_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This makes this header file consistent with the rest.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ice2872b4a24032d3a65777795943602cd2595de7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
