A looong time ago when cache_as_ram.S was built into romstage,
the stage was also linked twice. First at a fixed low address
and then again relocated at the final execute-in-place address.
Change-Id: Ic624feef6794f2c24e38459a45583d84fc07a484
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
When adding XIP stages on x86, the -P parameter was used to
pass a page size that covers the entire file to add. The same
can now be achieved with --pow2page and we no longer need to
define a static Konfig for the purpose.
TEST: Build asus/p2b and lenovo/x60 with "--pow2page -v -v" and
inspect the generated make.log files. The effective pagesize is
reduced from 64kB to 16kB for asus/p2b giving more freedom
for the stage placement inside CBFS. Pagesize remained at 64kB
for lenovo/x60.
Change-Id: I5891fa2c2bb2d44077f745619162b143d083a6d1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Picasso, Dali, and Pollock iGPU share the same PCI device ID, but need
different video BIOSes. This checks the vendor & device IDs along with
the revision and selects the correct video BIOS to use.
Also add the second VGA BIOS for Raven2-based SoCs and change all VGA
BIOS IDs to the format including the revision number.
Since SeaBIOS still expects the CBFS file name without the revision ID,
it won't find the VBIOS any more. As a temporary workaround add the
VBIOS for the silicon it will run on as VGA_BIOS_DGPU_*.
Change-Id: I8f48ecc3fbffddd21d1f830fbee26a09ac351e1c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://chromium-review.googlesource.com/2040455
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matt.papageorge@amd.corp-partner.google.com>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
• Based on FSP EAS v2.1 – Backward compatibility is retained.
• Add multi-phase silicon initialization to increase the modularity of the
FspSiliconInit() API.
• Add FspMultiPhaseSiInit() API
• FSP_INFO_HEADER changes
o Added FspMultiPhaseSiInitEntryOffset
• Add FSPS_ARCH_UPD
o Added EnableMultiPhaseSiliconInit, bootloaders designed for
FSP 2.0/2.1 can disable the FspMultiPhaseSiInit() API and
continue to use FspSiliconInit() without change.
FSP 2.2 Specification:
https://www.intel.com/content/www/us/en/intelligent-systems/intel-firmware-support-package/intel-fsp-overview.html
Change-Id: If7177a267f3a9b4cbb60a639f1c737b9a3341913
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41728
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If there is no installed audio daughter board on volteer then the
HDA driver in the kernel will crash on resume. In order to prevent
this disable the PCI device when AUDIO=NONE probe match is true.
BUG=b:147462631
TEST=boot on volteer and ensure that the PCI device at 0:1f.3 is gone
Change-Id: I4a436e1b76418030bf635427e490b54a713fdd33
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Zork family does not use OEM binary and so this change drops the
configs required for adding this binary.
Change-Id: Id38c67030e4055ab16934d1a900ee1cea5843b54
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This way drivers can wait for their devices to be enabled.
I also rewrote enable_aoac_devices to take advantage of
wait_for_aoac_enabled.
BUG=b:153001807
TEST=Trembyle builds
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8e653c857e164f90439e0028e08aa9608d4eca94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the OS sets the target device state to D3, we need to clear it so we
can reestablish register access.
BUG=b:153001807
TEST=Boot trembyle with I2C powered off and see it power back on.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If9bd1b7cfa7b8d074226c4dcdefc1a44cad8b940
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This functionality is needed in the PSP and I can't include all of
southbridge.c.
BUG=b:153001807
TEST=Made sure trembyle still compiles
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3a38c655588d7836e1bd033e958a505774de871e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42324
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The legacy UARTs are supposed to default to off according to the
documentation (PPR for AMD Family 17h Model 18h). But legacy UART Range_0
is enabled after reset. The PSP might be enabling it or the documentation
might be wrong.
Having it enabled causes problems though. We have ACPI nodes defining
MMIO UARTs, and the kernel also probes for legacy UARTs. This results in
two drivers accessing the same device, one via MMIO and one via IO. I
suspect this was the cause of the garbage serial output.
Before the change you would see the following in the console:
[ 0.741108] serial8250: ttyS3 at I/O 0x2e8 (irq = 3, base_baud = 115200) is a 16550A
After this change, we no longer see it.
BUG=b:152079780, b:157858890
TEST=Boot trembyle and make sure serial is still working.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9d837e449b961dbb55d1301d2107838e26b3f892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The purpose of pci_early_bridge_init() is to temporarily configure
PCIe rootport (or PCI bridge) on bus 0 to configure PCI device BARs
on the secondary bus. Currently used and tested only with UART_OXPCIE.
Since those BARs do not reset on stage changes, it is not necessary
to redo those steps for verstage or postcar. Note that the option
does not really work with many of the later platforms where PCIe
pins/links/lanes are configured late in FSP-M or similar blob.
Change-Id: I148f44c76c61edcfd8ab1c8c531cd2e6ca343130
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The start and end bus number in the MCFG ACPI table is inclusive.
Therefore, the number of buses decoded needs to be subtracted by
1.
BUG=b:158874061
Change-Id: Ic773bc1e0ccaa99af45d1a53919f6480887fa37e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42329
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enables the fourth thermal sensor for fan in DPTF for volteer
BRANCH=None
BUG=b:149722146
TEST= On volteer system check
`cat /sys/class/thermal/thermal_zone5/type` for TSR3
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Ie11496828133aa71f1017f759516e2e5d3dff2d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Currently, configuring and reviewing DPTF parameters is difficult
because DPTF tables and methods are defined in static ASL files, and are
littered with #ifdefs which both define parameters and influence
behavior (e.g., whether a method is included or not). This patch train
is an effort to bring DPTF support to our ACPI DSDT/SSDT generation
framework.
This first patch is very minimal, and includes only creation of the
DPTF device (in the DSDT).
BUG=b:143539650
TEST=compiles (later tests get more comprehensive).
Change-Id: I14df9f422c911677aeea25552ac1822a9462c58a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41883
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we plan to use VMX, enable CPU_INTEL_COMMON.
BUG=b:157388365
TEST=tested on Volteer
Signed-off-by: Alex Levin <levinale@chromium.org>
Change-Id: I5e7bdb4310947dd8a94ee554834a67ce94377ea5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Correct a message of "Error: Can't add stage_cache 57a9e101 to imd".
ramstage is 0xffc90 and adding FSP-S (0x50000) failed. Increase the
reserved region of SMRAM to accommodate both images.
BUG=b:158704095
TEST=Boot Mandolin and check console log
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I51595d80d4779e995ec2a26e395cf95d666a309e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42314
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Added device hid info to the MST and LSPCON devices.
BRANCH=None
BUG=b:156546414
TEST=Manual tested and able to see update on sysfs and ssdt table
Signed-off-by: Shiyu Sun <sshiyu@chromium.org>
Change-Id: Iaef6c08f241ea671d1487a8524162dbb438b8e98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Change-Id: Ib16d4f65707801b430f06892ab45ecfa7551593f
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
The Endeavour variant does not have a DisplayPort input so there's no
need to wait for it.
BUG=b:147830399
BRANCH=none
TEST=boot endeavour; check coreboot logs
Signed-off-by: Jeff Chase <jnchase@google.com>
Change-Id: I30c7c47f19a61ce66c6c923864d80870d2761859
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
ALIB function 1 needs to be called every time there is a change in
AC/DC state of the system. This change adds a wrapper method that can
be called by PNOT (method to notify system power state change) to
report to ALIB that system power state has changed i.e. AC <-> DC.
Additionally, this change drops the call to ALIB from _INI method
since the PWRS object might not be initialized correctly at that
point. Instead EC makes a call to PNOT when PWRS is initialized.
This wrapper also fixes the value of power state being passed into
ALIB. ALIB expects 0 = AC and 1 = DC. On the other hand, PWRS reports
1 as AC and 0 as DC. WAL1() takes care of inverting the PWRS state
before passing into ALIB.
BUG=b:157752693
TEST=Verified that WAL1() gets called on AC connect/disconnect.
Steps followed:
$ echo 1 > /sys/module/acpi/parameters/aml_debug_output
$ dmesg -w | grep ACPI
[ 76.306947] ACPI Debug: "EC: AC DISCONNECTED"
[ 76.307064] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 82.264946] ACPI Debug: "EC: GOT PD EVENT"
[ 82.539833] ACPI Debug: "EC: GOT PD EVENT"
[ 82.753721] ACPI Debug: "EC: GOT PD EVENT"
[ 82.843676] ACPI Debug: "EC: GOT PD EVENT"
[ 82.970596] ACPI Debug: "EC: AC CONNECTED"
[ 82.970659] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 83.047598] ACPI Debug: "EC: GOT PD EVENT"
[ 84.804733] ACPI Debug: "EC: GOT PD EVENT"
[ 86.317934] ACPI Debug: "EC: GOT PD EVENT"
[ 86.385920] ACPI Debug: "EC: GOT PD EVENT"
[ 86.515830] ACPI Debug: "EC: AC DISCONNECTED"
[ 86.515922] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x01"
[ 90.089062] ACPI Debug: "EC: GOT PD EVENT"
[ 90.357914] ACPI Debug: "EC: GOT PD EVENT"
[ 90.573812] ACPI Debug: "EC: GOT PD EVENT"
[ 90.662744] ACPI Debug: "EC: GOT PD EVENT"
[ 90.788706] ACPI Debug: "EC: AC CONNECTED"
[ 90.788835] ACPI Debug: "ALIB call: func 1 params 0x03 0x00 0x00"
[ 90.865675] ACPI Debug: "EC: GOT PD EVENT"
[ 92.621793] ACPI Debug: "EC: GOT PD EVENT"
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I1f2ade28ca35378ebf4647d8df3d2ea4d0b08096
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change calls \PNOT () method when AC power state is initialized
to allow platform code to take appropriate action.
BUG=b:157752693
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I089e9096f78728ddc5df2d8cb8f22f65b30b02dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This allows to remove references to CONFIG_DCACHE_RAM entries in
most cache_as_ram.S files. While Kconfig variable names appear
for every stage, linker symbol names will only appear in stages
they are valid in.
Also, linker scripts have LOG2CEIL which comes in handy to enforce
MTRR alignments.
Change-Id: I2fef3546d2bfea2d4d8f87aaf8376e5566fd6aaa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30872
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that Picasso uses its own memlayout.ld, always include id.ld in
arch/x86/memlayout.ld.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I04b59c2a273cad0a2e64dbc325c0b09fca254558
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42266
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that Picasso uses its own linker script, early_ram.ld from
arch/x86 is unused and hence is dropped as part of this change.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ida83d40d005ddab789628a1581389fc487b10d4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates memlayout.ld for Picasso to place all early
stages (bootblock, romstage, FSP-M, verstage) and data buffers (vboot
workbuf, APOB, preram-cbmem console, timestamp, early BSP stack) at
the bottom of DRAM starting at 32MiB. This uses static allocation for
most components by defining Kconfig variables for base and size. It
relies on the linker to complain if any of the assumptions are broken.
This also allows romstage to use linker symbols for
_early_reserved_dram and _eearly_reserved_dram to store information in
CBMEM about the early DRAM usage by coreboot before ramstage starts
execution. This allows ramstage to reserve this memory region in BIOS
tables so that S3 resume can reuse the same space without corrupting
OS memory.
BUG=b:155322763
TEST=Verified memory reported by coreboot:
Writing coreboot table at 0xcc656000
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000a0000-00000000000fffff: RESERVED
3. 0000000000100000-0000000001ffffff: RAM
4. 0000000002000000-000000000223ffff: RESERVED
5. 0000000002240000-00000000cc512fff: RAM
6. 00000000cc513000-00000000cc6bffff: CONFIGURATION TABLES
7. 00000000cc6c0000-00000000cc7c7fff: RAMSTAGE
8. 00000000cc7c8000-00000000cd7fffff: CONFIGURATION TABLES
9. 00000000cd800000-00000000cfffffff: RESERVED
10. 00000000f8000000-00000000fbffffff: RESERVED
11. 0000000100000000-000000042f33ffff: RAM
12. 000000042f340000-000000042fffffff: RESERVED
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I009e1ea71b5b5a8e65eba16911897b2586ccfdb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change adds a new CBMEM ID (CBMEM_ID_CB_EARLY_DRAM) that can be
used by platform code to stash details of early DRAM used by
coreboot.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I913c744fdce2f9c36afdc127b2668fccf57dde58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change copies src/arch/x86/memlayout.ld file to
src/soc/amd/picasso/ and sets MEMLAYOUT_LD_FILE config variable to
point to this newly added file. Unused elements from the memlayout.ld
file are dropped and path to early_dram.ld is updated to include the
one from src/arch/x86.
BUG=b:155322763
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I59bf5f93b712407ddcc9fb8a46167936c6c28a76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change defines a Kconfig variable MEMLAYOUT_LD_FILE which allows
SoC/mainboard to provide a linker file for the platform. x86 already
provides a default memlayout.ld under src/arch/x86. With this new
Kconfig variable, it is possible for the SoC/mainboard code for x86 to
provide a custom linker file as well.
Makefile.inc is updated for all architectures to use this new Kconfig
variable instead of assuming memlayout.ld files under a certain
path. All non-x86 boards used memlayout.ld under mainboard
directory. However, a lot of these boards were simply including the
memlayout from SoC. So, this change also updates these mainboards and
SoCs to define the Kconfig as required.
BUG=b:155322763
TEST=Verified that abuild with --timeless option results in the same
coreboot.rom image for all boards.
Change-Id: I6a7f96643ed0519c93967ea2c3bcd881a5d6a4d6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42292
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds memory parts used by variant voxel to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.
This variant is not yet supported by coreboot but DRAM IDs need to be
generated for it. In the coming days, variant voxel will be added to
coreboot.
BUG=b:157732528
Change-Id: I8780beec987deb8fed11bb8f84275dcba4768514
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
For Volteer mainboard, this patch set optimized values for PCH external
VR settings and ext rail voltage/current, to achieve better power
savings in sleep states.
v1p05 and vnn power rails can be used as an alternative source
by-passing vccin_aux during Sx. This by-pass feature, enables us to
shutdown vccin_aux rail which is higher voltage rail compared to v1p05
and vnn. These both rails were disabled by default in FSP. Changes in
this patch are:
1. v1p05 and vnn rails are enabled and enabled supported voltage types
in S0i1, S0i2, S0i3, S3, S4, S5 states. They were disabled by default.
2. Icc Max for v1p05 changed to 500 mA from default 100 mA.
3. vnn rail's voltage is changed to 5 V from default 4.2 V.
BUG=None
BRANCH=None
TEST="Build and boot volteer and check VR settings with Intel ITP-XDP
debugger and verify approx 250 mW power savings in Sx"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib46423872c956af9aaa92902fce552d5447237c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42223
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For Tiger Lake platforms, this patch set provides a way to override PCH
external VR settings and ext rail voltage/current through devicetree.
This enables setting of optimal settings for FIVRs for a particular PCH
type.
BUG=None
BRANCH=None
TEST=Build and boot volteer.
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ic55472d392f27d153656afbe8692be7e243bb374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41424
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The offset between registers has to be between different channels.
Change-Id: Ic6d959c31c78073a3ecbf7a17dfb73ac36340599
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
This port isn't packed on the board, so remove from
the devicetree.
BUG=b:154585046,b:156429564
BRANCH=none
TEST=none
Change-Id: Ib4aee337f67453adcebff7e93e25db7a838e3b2d
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42269
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reconfigures SPI speeds after FSP-S has run since
FSP-S is currently configuring the SPI frequency when it should
not. Until FSP-S behavior is fixed, this workaround needs to be
applied.
BUG=b:153506142
TEST=Verified that em100 works fine.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Id9b8330c6f82c7162ff91e8cc10160fdd8cfedab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Ie05f484cf4b346601e6128c95ff2b27ce59b995f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42188
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested with BUILD_TIMELESS=1, Intel DG43GT does not change.
Change-Id: Ifd5b8cd7644811a56afae82468c8eb0a7b6b7ff9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42157
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The picasso_ prefix on the fsp_pcie_descriptor and fsp_ddi_descriptor
structs isn't needed, since this code is picasso-specific, so drop it.
Change-Id: Ia6a0ddb411aa64becc3c23a876f2ea43cb68e028
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update DPTF_TSR2_SENSOR_ID to 2. Fixes the issue where TSR1 and
TSR2 have the same DPTF_TSR#_SENSOR_ID value causing them to
report the same temperature under /sys/class/thermal
and also swap TSR0 and TSR1 in DTRT to match physical sensor
in volteer schematics
BRANCH=None
BUG=b:149722146
TEST=On volteer system check TSR1 and TSR2 temperatures, should
report different values
`cat /sys/class/thermal/thermal_zone[3,4]/temp`
Also verify other TSRs using `cat /sys/class/thermal/thermal_zone*/temp`
and `ectool tempsinfo all ; ectool temps all`
Signed-off-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Change-Id: Idc5f35e4faf59b0ee726eb32a08eab4654fb342d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42232
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Combine the Ucode binaries for 3 revisions of CPU into one
CBFS module.
This should be moved to the AMD common code later.
BUG=b:153580119
TEST=mandolin
Change-Id: Ib08a65b93c045afc97952a809670c85831c0faf7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Selecting VBOOT_LID_SWITCH under BOARD_GOOGLE_BASEBOARD_HATCH creates a
requirement for VBOOT, and prevents building in the non-vboot/non-ChromeOS
case. As this symbol is already selected by CHROMEOS below, there's no need
for the baseboard (and only one of the two) to select it, so don't.
Change-Id: I060e82185997bce451648173dd97dd6a3d5d237f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Replace 'cse_bp'(cse boot partition) and 'ME' with 'cse_lite' in all log
messages in the cse_lite.c.
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I3fc677c9ec1962199c91cc310d7695dded4e0ba0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41972
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some cases could not be factored out while keeping reproducibility.
Also mark some potential bugs with a FIXME comment, since fixing them
while also keeping the binary unchanged is pretty much impossible.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Iafe62d952a146bf53a28a1a83b87a3ae31f46720
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42152
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ASSERT() macro depends on the line number, so changing the line it
appears in breaks reproducibility testing using BUILD_TIMELESS=1.
Work around this problem by placing the `pch_pcie_acpi_name` function,
which contains this macro, at the beginning of the file. This allows
refactoring the rest of the code without affecting the ASSERT() macro.
Change-Id: I2e0432ec9ae6c7d033fc7495afb3a71fe7e77729
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso doesn't really make use of the common mrc_cache driver because
of the PSP/ABL requirements for APOB NV data. The APOB NV data
gets consumed by PSP/ABLs before x86 comes out of reset. Hence, we cannot
really add any metadata to this saved data or use multiple slots as
done by the default MRC cache driver
(CACHE_MRC_SETTINGS). Additionally, FSP-M requires access to this APOB
NV data which coreboot needs to pass in from different locations
depending upon boot mode:
1. Non-S3 boot: PSP/ABLs store APOB NV data in DRAM at predetermined
location which is present in BIOS directory table.
2. S3 boot: PSP/ABLs do not store APOB NV data in DRAM.
Thus, coreboot needs to set FSP-M UPD NvsBufferPtr as the DRAM
location in non-S3 boot and the address of RW_MRC_CACHE on SPI flash
in case of S3 resume.
This change enables MRC cache support in Picasso in order to meet the
above requirements.
1. NvsBufferPtr is set based on boot mode.
2. APOB NV data is not stashed to CBMEM. Instead it is written right
away to SPI flash in romstage.
BUG=b:155990176
Change-Id: I8661a4cf2d34502967e936bf22a13f6f1b88e544
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change moves the check for NvsBufferPtr in S3 resume case to
happen just before FSP-M is called. This allows SoC/mainboard code to
set NvsBufferPtr if it doesn't use the default MRC cache driver.
BUG=b:155990176
Change-Id: Ia272573ad7117a0cb851f0bfe6a4c7989bc64cde
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This change sets FMDFILE for zork family so that coreboot builds pick
up the right flash layout.
BUG=b:155990176
Change-Id: Ia1673622ccd14a2ff7bde555ed33d5b51cf4272a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42106
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From `Documentation/coding_style.md`:
> This does not apply if only one branch of a conditional statement is a
> single statement; in the latter case use braces in both branches:
Change-Id: I5672949e587a9c0e4efa01521a659e4c224085d0
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Unify the file with the Cannon Lake version
`src/soc/intel/cannonlake/smmrelocate.c`. Now they are identical.
Change-Id: I8cae66038edb3966604c92597986839badd617c5
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Unify the file with the Cannon Lake version
`src/soc/intel/cannonlake/smmrelocate.c`.
Change-Id: Id4815836e93081b61f4c09b8b3ed81199d3ff409
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
Not strictly required for binaryPI boards, but do this for
consistency.
Change-Id: Id0bbbfb6f695c4bb920bc57a1e9362a23884efb3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Once we support building stages for different architectures,
such CONFIG(ARCH_xx) tests do not evaluate correctly anymore.
For x86 we define .id linking explicitly elsewhere.
Change-Id: I43f849465e985068cd0b8a1944213b7c26245b8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Setting the default values for GPIO community power management, causes
issues in detecting TPM interrupts. So to avoid that GPIO PM has to be
disabled in devicetree. But for S0ix it is needed. This patch implements
a workaround in ASL code to enable GPIO PM on S0ix entry and disable it
on S0ix exit.
This patch adds the following three platform specific methods.
1. MS0X to enable power management features for GPIO communities on
low power mode entry and disables it on exit.
2. MPTS to enable power management features for GPIO communities when
preparing to sleep.
3. MWAK to disable power management features for GPIO communities on
waking up.
BUG=b:153847814
TEST=Verify S0ix is working. GPIO PM configuration is upadated on low
power mode entry and exit.
Change-Id: I7225b78ab2ac5bf17f93230cd85cd21e836d807d
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41502
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds Hot-Plug and power management event handers(_L61 &
_L69) respectively for Thunderbolt in the GPE scope. The _L61 method
invokes sub-method HPEV to support Hot-Plug wake event from Thunderbolt
PCIe root ports. This method intercepts Presence Detect Changed
interrupt and make sure the L0s is disabled on empty slots. The _L69
method checks and clears root port's PME SCI status.
BUG=b:156435065
TEST=Verified multiple hot plug successfully with Lenovo dock.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I022cf4aa3f2ee459b9dc87849494e10755d995c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The ACP device sits behind a bridge. Despite the logs indicating
the bridge is likely hooked up, there's some unusual behavior of
writes not sticking. Aside from the speculation of what's causing
the issues the initialization of the device should occur at init()
because of these potential dependencies.
BUG=b:155882600
Change-Id: I8fa83d7d1d4f356c56971d4175a2ae6497a92fb8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42231
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Board devicetrees requests for drivers/pc80/tpm but that
was not included for the build. Note that there is actually
no on-board TPM, just an LPC header connector on these boards.
Change-Id: Ia959ae9072e3fc709b779b1fc778eb82e10c2ee3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
According to the comments of
https://review.coreboot.org/c/coreboot/+/41719
, which is about Microcode patch for amd/picasso.
Change the code with the same way.
The changes include:
1. combine the microcode_xxx.c and update_microcode.c
into one source.
2. Redefine the microcode updating function to eliminate
the parameter. Get the revision ID in the black box.
Reduce the depth of function calls.
3. Get the revision ID by bitwise calculation instead of
lookup table.
4. Reduce the confusing type casts.
5. Squash some lines.
We do not change the way it used to be. The code assume
only one microcode is integrated in CBFS. If needed in future,
41719 is the example of integrating multiple binaries.
And, 41719 depends on the definition in this patch.
Change-Id: I8b0da99db0d3189058f75e199f05492c4e6c5881
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This MSR is used for detecting if the micro code is applied
successfully.
Change-Id: I060eb1a31f3358341ac0d5b9105e710c351f2ce8
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42212
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting preferred_pm_profile under sb/ or soc/ overrides the
default determined from SYSTEM_TYPE_xx (or possibly
SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable.
With the overrides removed, AMD platforms will switch from
PM_UNSPECIFIED to PM_DESKTOP as their preferred profile.
Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide
board-specific mainboard_fill_fadt() should they need to change this.
As they already select SYSTEM_TYPE_LAPTOP, following boards
will change to PM_MOBILE:
google/kahlee
hp/pavilion_m6_1035dx
lenovo/g505s
Change-Id: I45c4a495a4bf3422adae9e22a6e436adef252e77
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The platform_cfg.h files under mainboard/ are a legacy configuration
mechanism used with AGESA family14 boards.
With this change following boards will have FADT preferred_pm_profile
changed from PM_UNSPECIFIED to PM_DESKTOP:
amd/inaqua
amd/south_station
amd/union_station
asrock/e350m1
Change-Id: Ic28761eb238dbbaf3e8f820a29ec64b89f12bf53
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Setting preferred_pm_profile under sb/ overrides the
default determined from SYSTEM_TYPE_xx (or possibly
SMBIOS_ENCLOSURE_TYPE with followup work). This is not desireable.
Boards need to either select a pre-defined SYSTEM_TYPE_xx or provide
board-specific mainboard_fill_fadt() should they need to change this.
As they already select SYSTEM_TYPE_LAPTOP, following boards
will maintain PM_MOBILE:
lenovo/t400
lenovo/x200
roda/rk9
Following will change to PM_DESKTOP:
aopen/dxplplusu
asus/p2b
emulation/qemu-i440fx
emulation/qemu-q35
Change-Id: I2986eb0a8abc94507e9797cc8b64611ae4bd888a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Use a local variable for the ResourceTemplate in the _CRS methods
instead of the RBUF object. When using RBUF, iasl complained that the
_CRS methods need to be serialized, since objects were created in there.
Since those are only used as local variables, just use local variables
for this.
TEST=iasl stops complaining about those methods not being serialized and
Linux still boots and there aren't any related ACPI errors or warnings.
Change-Id: Ic43fcaed5a8b19dbd5634c17f34a159803ba8577
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
- Move the GPIOs that are likely to be volteer-specific (mostly
peripherals) to reside in variants/volteer/gpio.c so that
variants don't have to override too many GPIO settings.
- Modify malefor's gpio.c to adjust for the changes to baseboard's
gpio.c.
- Remove unused GPP_C3 (USB4_SMB_SCL) and GPP_C4 (USB4_SMB_SCA)
settings.
- Remove unused GPP_D9, GPP_D10, GPP_D11, and GPP_D12 settings.
- Remove unused GPP_E8 (SLP_S0IX), COEX, WWAN, and SNDW related
settings for malefor.
- Remove unused GPP_R4 (HDA_RST_L) setting.
BUG=b:157597158
TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot
volteer SKU4 to kernel.
Change-Id: Ib2f384f539d55a3a8d4a7608336ef22aca3d8c4f
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Connect Topology Command(CNTP) is sent with default timeout value
(0x1388) along with FW CM. The CNTP is supposed to be skipped while
using SW CM. While transition from FW CM to SW CM, the default timeout
value could cause boot time delay up to ~10 seconds. Set this FSPS UPD
ITbtConnectTopologyTimeoutInMs to be 0 in order to avoid the 10 seconds
delay. Future FSP release will evaluate this ITbtConnectTopologyTimeoutInMs
value. While FSP finds this UPD value being 0, FSP will skip sending CNTP.
BUG=b:155893566
TEST=Built image with SW CM Thunderbolt firmware and verified no
outstanding delay time while using FSP v3197 during boot to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I47e3519fd818cb56e6abd16464d8370ffddabc5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42056
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update FSP headers for Tiger Lake platform generated based FSP
version 3197 to include below additional UPD:
FSPS:
ITbtConnectTopologyTimeoutInMs
Signed-off-by: John Zhao <john.zhao@intel.com>
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I06d605b156c1e6f90921c20e0b8fbbe4d64916ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42046
Reviewed-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With SoundWire and USB4 enabled some boards are running out of
memory with all of the ACPI devices and properties. Increase
the heap size to accommodate.
BUG=b:147462631
TEST=Successfully boot on volteer SKU5 board with SoundWire enabled,
before boot was failing with "Error! memalign: Out of memory"
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I0245bdfad93b381871514578e66640e7fe6fa5c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This patch adds correct PL2 baseline setting and PsysPL2 for different
SKUs. There is no way to identify the barral jack power rating, the
assumption is following that ships with the product:
1. i3/i5/i7: 90W BJ
2. Celeron/Pentium: 65W BJ
For Type-C adapter, we don't have Pcritcial (10ms) data, keeps the
original settings as 90% of adapter rating for PsyspL2/PL4 and PL2
as min(PL2, 0.9n) where n is adapter rating power.
BUG=b:143246320
TEST=Run with U62 and Celeron CPU and ensure the PL2 settings are correct
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: If7de614d58366158a566563990ee1ecc8c0110bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
This reverts commit 04506e2987.
Turned out that `dev->command` is only a `u8` and the way it's used
here is wrong: It is not supposed to reflect the state of the register
but only gathers (lower) bits to be enabled during allocation.
Change-Id: Iacd2b753939e8adcf5aedd4b9cf101638a324aa6
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42163
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Taken from Chrome OS update information. Looks like nami encompasses
many different devices, which would not fit in one line, so skip it.
Change-Id: I53405cba269cbfc25bd4618777b946500f173e7e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If16d8c4aef3dfd1dbeaf48d6855dd4c0ef328168
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: If7f3f06cd3524790b0ec96121ed0353c89eac595
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Commit 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
uses `pci_read_config8` to read the PCI command register, which does not
correspond with what has been stated in the commit message. Moreover, it
potentially breaks things, as the upper byte of the PCI command register
is now being cleared.
So, restore the original behaviour of the code, using 16-bit accesses.
Fixes: 5ac723e (nb/intel: Fix 16-bit read/write PCI_COMMAND register)
Change-Id: Id2c42ea8551a2fa2fa5c64e8fff8940d8304fbe0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For the sake of completeness, we should provide these operations.
Change-Id: Ia28af94ec86319c7380d8377f7e24e5cdf55dd9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42145
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The max98357a_platform_driver will turn on/off the speaker enable gpio
based on use, so configure it low to save power.
BUG=None
TEST=Built dedede and tested speaker playback working.
We are seeing a power saving of ~10mW.
Change-Id: I070679457b06cb82633c1197b893a5d89c8b2cf0
Signed-off-by: Usha P <usha.p@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Use x86_setup_mtrrs_with_detect_no_above_4gb() to only
solve the MTRR solution for memory up to 4GiB. This assumes
4GiB to TOM2 is marked as writeback in sys_cfg MSR.
BUG=b:155426691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib8358b614682f6a97278f3a60b5ada5e607965af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41898
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AGESA FSP-M implementation is now not updating MTRRs out from
under the caller. As such, remove the save/restore of MTRRs
from the FSP-M call.
BUG=b:155426691
Change-Id: I14f3b18dd373ce17957ef3857920e1c4e2901bbe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PSP does the memory training and setting up of MSRs for
TOP_MEM and TOM2. Set caching up for all the DRAM areas:
Enable WB caching for 1MiB->TOP_MEM, 4GiB->TOM2.
Enable WC caching fro 0->1MiB except 0xa0000->0xc0000.
BUG=b:155426691
Change-Id: I83916a220ea4016d4438dd4fb5be82dec5506f80
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Only Winbond parts seem to support making status register writes
volatile. So this flag should not be exposed in the generic interface.
Change-Id: Idadb65ffaff0dd7809b18c53086a466122b37c12
Signed-off-by: Daniel Gröber <dxld@darkboxed.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41746
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per JEDEC spec, manufacturer part name should be set to
blank (0x20). This change updates gen_spd.go to set bytes 329-348 as
0x20 and regenerates SPDs for TGL and JSL.
Change-Id: I6af18d89afd7264cec7e54b38e95df83d55aa058
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42023
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The orientation, etc. -switch properties are supposed to use the
connector device (underneath the MUX device) that belongs to the port
number in question. This patch finds the CONx device and uses that
to pass to the acpigen API.
BUG=b:154620502
TEST=on Volteer, dump SSDT and verify the *-switch properties point to
\_SB.PCI0.PNC.MUX.CON0 and CON1
Change-Id: Ie65c2d750f3d9f83285e0e4cc9642110c804bbad
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42045
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
A function pci_dev_disable_bus_master() is created. This function
can be used to disable Thunderbolt PCIe root ports, bridges and
devices for Vt-d based security platform at end of boot service.
BUG=None
TEST=Verified PCIe device bus master enable bit is cleared.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie92a15bf2c66fdc311098acb81019d4fb7f68313
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41042
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
All variants are overriding soc_common_config, so source it from
overridetree and remove entry from baseboard devicetree.
Only keeping chipset lockdown config in baseboard which will be
common across all the variants.
BUG=None
BRANCH=None
TEST=Checked code compilation and lockdown config is applied to all variants
Change-Id: I23714b721a6bb0bac785f046586790a98dc5b646
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Some of the boards do not select SYSTEM_TYPE_LAPTOP or _CONVERTIBLE
so their FADT preffered_pm_profile would change from PM_MOBILE without
the added overrides here.
Change-Id: I04b602b2c23fbd163fcd110a44ad25c6be07ab66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41920
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When MRC cached data update is performed, messages are written to
event log, which is flash based. For system that does not have flash
based event log, the messages are lost.
Added corresponding BIOS_DEBUG messages.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I1ef4794151fea7213c8317ddc898b0e37da280b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41981
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
BUG=none
BRANCH=none
TEST="BUILD for Volteer"
Signed-off-by: Venkata Krishna Nimmagadda <venkata.krishna.nimmagadda@intel.com>
Change-Id: Ib54b3f7da828ce8d232fcea0639077970638f610
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Venkata Krishna Nimmagadda <Venkata.krishna.nimmagadda@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This eliminates the differences in the first part of the file.
Change-Id: Ifb7d57da08e02664a28819e65bc8e9697ed38c4c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42009
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change allows treating the PMC as a 'hidden' PCI device on Jasper
Lake, so that the MMIO & I/O resources can be exposed as belonging to
this device, instead of the system agent and LPC/eSPI.
Change-Id: Ie07987c68388d03359c43f64a849dc6e3f94676e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
While working on psp_verstage, I noticed that this file had a number of
unnecessary includes. Remove them.
BUG=b:158124527
TEST=Build & boot psp_verstage on trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I32188e2dda39ece9dc98d0344824d997a2e80303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Currently, having libgfxinit try to enable VGA will result in a hang.
On the Asrock B85M Pro4, DDI E (VGA) was not being enabled in coreboot,
so it did not hang. However, this renders Linux's i915 driver unable to
use VGA at all. In absence of monitors with digital inputs, this is bad.
To work around this problem, mark DDI E as enabled, and comment out VGA
from gma-mainboard.ads for the time being. This allows one to use a VGA
monitor, even if it only works after Linux drivers have taken over.
Change-Id: Idd6a9e8515a1065ad3c6ddf136896fef9f0fa732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
The ASL code is copied from the Purism Librem 13v3, and is not needed,
as the standard fixed power button is used. It was removed for the
Pursim devices in commit 2d977b2dcb (mb/purism: remove duplicate ACPI
power button).
Change-Id: I18155ea672e7309b367ad4170f2f00f0b3e557db
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mimoja <coreboot@mimoja.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is copied from the Purism Librem 13v3, and is not needed, as the
standard fixed power button is used. It was removed for the Pursim
devices in commit 2d977b2dcb (mb/purism: remove duplicate ACPI power
button).
Change-Id: I8fe19b8fbcc11d859a75b3dc6b9bcc42c80d13f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rafael Send <flyingfishfinger@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards.
No idea, if this is correct for the two laptops. The Lenovo G505s also
incorrectly defines two power buttons.
[ 0.911423] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
[ 0.911434] ACPI: Power Button [PWRB]
[ 0.911493] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
[ 0.912326] ACPI: Power Button [PWRF]
If the generic power button device is needed, the POWER_BUTTON flag
should be set in FADT.
The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.
Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards
(SOUTHBRIDGE_AMD_PI_AVALON).
The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.
Change-Id: Ibeec73c15f2282f7ab0be88f96693bcb551b3e45
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change adds device_operations for UART MMIO devices that provides
following operations:
1. uart_acpi_name: Returns ACPI name of UART device. Generation of
UART device node is not yet moved to SSDT, but will be done in
follow-up CLs.
2. scan_bus: Uses scan_static_bus to scan devices added under the UART
devices. This allows mainboard to add devices under the UART MMIO
device.
Change-Id: I18abbe88952e7006668657eb1d0c177e53e95850
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
According to the Wilco EC spec the BTSC bit of PWSR is always cleared
when PWSR is read so that battery status change events are only
triggered one time. Testing of the Wilco EC has verified this behavior.
This changes the way in which the battery status change bit is used from
checking the bit state against the previous value to always issuing a
battery event when the BTSC bit is set. The other bits in PWSR indicate
state directly and do not behave like the BTSC bit.
BUG=b:157113138
TEST=Deploy on Drallion and verify that battery events are generated
BRANCH=drallion, sarien
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I8fbf2ee1158ddd790b04a20b1eb27a6cce4f5c81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add support for RT 1308 audio amplifier in TGLRVP.
We are using the i2c generic driver here to generate
the SSDT file. Datasheet:ALC-1308-CG-version-08.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp successfully. In kernel console
use the "aplay -l" command to check soundcard is listed.
Change-Id: I41d205a3ab87db85baf49e9e8a582c226ba5832d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This is a standard MSR. No reason for picasso to define its own.
BUG=b:147042464
TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idcfae356d35ff08ced4b7e5ccfc132a8492a6824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42087
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We don't use amd_setup_mtrrs, bsp_topmem or bsp_topmem2 in picasso.
BUG=b:147042464
TEST=Boot to OS on trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1941934975dfea4f189347811b003a33996c887a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable Cr50 update in recovery mode, so that we can at least still
update the process for most cases (that an update is pending in recovery
mode is not impossible but should be unlikely in the field).
Leave manual recovery unaffected so at least that would still work even
if Cr50 wedges in a weird way that it thinks it has an update on every
boot or something.
Setting the recovery_reason to VB2_RECOVERY_TRAIN_AND_REBOOT allows the
update to be applied.
BUG=b:154071064
BRANCH=none
TEST=builds
Thanks to Julius Werner for the suggested fix.
Change-Id: Iba341a750cce8334da4dcf6353ca8cd1268d170f
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This change adds memory parts used by variant wheelie to
mem_list_variant.txt and generates DRAM IDs allocated to these parts.
BUG=b:157862308
Change-Id: I53f6f5c832cd40068a6d4379ace849f6e8ad7a91
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41990
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that dedede is moved to using the auto-generated SPDs, we no
longer need the .spd.hex files in spd/ folder. Hence, this change
drops the files.
Change-Id: I026b3c61a2a88a7cd2c9842a26eb336324853add
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41882
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change switches dedede and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.
Change-Id: I6fadae0abcfb6e50d3cc502098ace9b668667a51
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41881
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GENERIC_SPD_BIN assumes that the SPDs are all placed in mainboard and
have .spd.hex as the suffix. Disable GENERIC_SPD_BIN for dedede as it
already provides its own rules for SPD inclusion. In follow up
changes, GENERIC_SPD_BIN can be re-enabled by updating gen_spd.go tool
to use similar suffixes and allowing different paths to be provided
for SPD by mainboard.
Change-Id: If10144e0b2bd67884af69f60e5117e388a3ae5da
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42054
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledoo and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Part: NT6AP256T32AV-J2
Waddledoo started assigning DRAM part IDs from 1. So, this change
fills in Nanya part as ID 0 (though it is currently unused).
Change-Id: I3879c4f3ad942eb349b52aad397333f576599bbd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds mem_list_variant.txt that contains the list of
memory parts used by wheelie and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Change-Id: If307bfb1d376e32af08af4f020f9e125f6a415dd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds mem_list_variant.txt that contains the list of
memory parts used by waddledee and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all dedede variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: MT53E512M32D2NP-046 WT:E
Byte# Current New Explanation
4 0x15 0x16 This part has only 1 die. Hence,
density per die is 16Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
9 0x40 0x00 Unused by MRC.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xFF as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Additionally, manufacturer name bytes are set to 0.
Part: NT6AP256T32AV-J2
Byte# Current New Explanation
4 0x14 0x15 This part has only 1 die. Hence,
density per die is 8Gb.
6 0x90 0x04 1 die in package and 2 channels per
die.
Manufacturer name bytes are set to 0.
Change-Id: I7a68a29ca3632e22f3960c9fc44acf3ce4f87c9c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds the following memory parts to LP4x global list and
generates SPDs using gen_spd.go for TGL and JSL:
1. MT53E512M32D2NP-046 WT:E
2. K4U6E3S4AA-MGCR
3. H9HCNNNCPMMLXR-NEE
4. K4UBE3D4AA-MGCR
BUG=b:157862308, b:157732528
Change-Id: Ib7538247d39dfe5faab277d646f87f09103d6969
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41989
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that volteer is moved to using the auto-generated SPDs, we no
longer need the spd/ folder under each variant. Hence, this change
drops the spd/ folders and the SPD files within them.
BUG=b:156126658
Change-Id: Icb36adeb11fd68a84df5b225db32fb8d840a530f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41619
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change switches volteer and family to using auto-generated SPDs
obtained using gen_spd.go and gen_part_id.go.
BUG=b:147321551,b:155423877
Change-Id: I9ed48f0b51714b072a0459d0b70b5417a49db54f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds mem_list_variant.txt that contains the list of
memory parts used by volteer and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
Part: K4UBE3D4AA-MGCL
Byte# Current New Explanation
6 0xB5 0xB4 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
Part: H9HCNNNBKMMLXR-NEE
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: H9HCNNNFAMMLXR-NEE
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
6 0xF9 0xB8 This device has 4 logical dies
instead of 8. Also, signal loading is
not used by MRC.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
20,21, 0x92,0x55, 0x12,0x29, As per datasheet, part supports CAS
22 0x00 0x15 latencies 6,10,16,22,26,32,36,40. So value
should be 0x12,0x29,0x15.
24 0x8C 0x96 taa is .468ns * CAS-40 which results
in byte 24 being 0x96 as per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x04C0.
123 0x00 0xE2 Fine offset for taa. Expected value
is 0xE2 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G32D2NP-046 WT:A
Byte# Current New Explanation
4 0x15 0x16 As per datasheet, density is 16Gb per
logical channel. So value should be 0x16.
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB5 0x94 This device has 2 logical dies. Also,
MRC does not use signal loading.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
12 0x0A 0x02 As per datasheet, this is 1rank and
16-bit wide channel. So, value should
be 0x02.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
29,30 0xC0,0x08 0xE0,0x0B As per datasheet, this corresponds to
380ns in MTB units which is 0x0BE0.
31,32 0x60,0x04 0xF0,0x05 As per datasheet, this corresponds to
190ns in MTB units which is 0x05F0.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I3998b2cd91020130bacf371fce9b0d307304acbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds mem_list_variant.txt that contains the list of
memory parts used by halvor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: H9HKNNNCRMBVAR-NEH
Byte# Current New Explanation
4 0x16 0x15 As per datasheet, density is 8Gb per
logical channel. So value should be 0x15.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels 2
dies. Hence, 0x94
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
29,30 0xE0,0x0B 0xC0,0x08 As per datasheet, this corresponds to
280ns in MTB units which is 0x08C0.
31,32 0xF0,0x05 0x60,0x04 As per datasheet, this corresponds to
140ns in MTB units which is 0x0460.
125 0xE1 0xE0 Fine offset for tckMin. tckMin is
calculated as (1/4267)*2 which comes
out to be 0.46871. Some datasheets
round this down to 0.468 and others
round it up to 0.469. JEDEC spec uses
0.468. As per that, this value comes
out to be 0xE0.
Part: MT53E1G64D4SQ-046 WT:A
Byte# Current New Explanation
5 0x21 0x29 As per datasheet, this part has 17row
address bits and 10column address
bits. This results in 0x29.
6 0xB9 0x94 Signal loading is not used by
MRC. Set bits 1:0 to 00. 2 channels,
2 dies. Hence, 0x94.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:147321551,b:155423877
Change-Id: I28b065a00380516d8686279a92ef68b9f17e2f65
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41616
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_list_variant.txt that contains the list of
memory parts used by malefor and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: I8b8bdc55314f538aff4dd1944a0b745357744d8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41615
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds mem_list_variant.txt that contains the list of
memory parts used by ripto and Makefile.inc generated by
gen_part_id.go using mem_list_variant.txt.
In the final change of the series, all volteer variants will be
switched from using the current SPDs to new auto-generated SPDs.
Differences in auto-generated SPD from current SPD are as follows:
Part: K4U6E3S4AA-MGCL
Byte# Current New Explanation
6 0x95 0x94 Signal loading is not used by
MRC. Bits 1:0 set to 0.
16 0x48 0x00 Signal loading is not used by
MRC. Set to 0x00.
19 0x0F 0xFF As per JEDEC spec, tckMax should be
100ns. So, value should be 0xff as
per datasheet.
21,22 0x55,0x00 0x54,0x05 As per datasheet, part supports CAS
latencies 20,24,28,32,36. So value
should be 0x54, 0x05.
24 0x8C 0x87 taa is .468ns * CAS-36 which results
in byte 24 being 0x87 as per datasheet.
123 0x00 0xE5 Fine offset for taa. Expected value
is 0xE5 as per datasheet.
124 0x7F 0x00 Fine offset for tckMax. Expected
value is 0x00 as per datasheet.
125 0xE1 0xE0 Fine offset for tckMin. As per
datasheet tckMin is 0.468ns. So, this
comes out to be 0xE0.
BUG=b:155239397,b:147321551
Change-Id: Ibb06443a5c7fd80915f66b806cdd7c3ae1275b05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41614
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that
can be used with JSL-based mainboards.
Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go
Mainboards can use the SPD files from SoC directly when creating
SPD binary to add to CBFS.
Change-Id: Ic52506b809c66b9f7cf25a100a959d85c67addf2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41876
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses gen_spd.go and global_lp4x_mem_parts.json.txt to
generate SPD files for currently known LP4x memory parts that can be
used with TGL-based mainboards.
Following files are added:
1. spd-*.hex: SPD files auto-generated by gen_spd.go
2. spd_manifest.generated.txt: Manifest file auto-generated by
gen_spd.go
Mainboards can use the SPD files from SoC directly when creating SPD
binary to add to CBFS.
BUG=b:147321551,b:155239397
Change-Id: Ic3935e4f6d106cbdf496fdfa28a0991e2d238fd9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Advertising SMI triggers in FADT is only valid if we exit with
SMI installed. There has been some experiments to delay SMM
installation to OS, yet there are new platforms that allow some
configuration access only to be done inside SMM.
Splitting static HAVE_SMI_HANDLER variable helps to manage cases
where SMM might be both installed and cleared prior to entering
payload.
Change-Id: Iad92c4a180524e15199633693446a087787ad3a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ifb4f99c11a72e75ec20b9faaf62aed5546de91fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41909
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If running on older (like before 2.4.0) version of QEMU there is
no SMI support, so never advertise SMI in FADT for the emulation.
Behaviour if ACPI daemon tries to raise SMI under these conditions
is unknown.
Change-Id: I170058793798648c6713de1530d89ec2ac53e39a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Ia61e50fb49719e9e18e81a27f355cdbd755a3f40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41906
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Change-Id: Iefa1e7d80367dbe380f69e768238b4124a45626f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We decided to store the FSG on eMMC instead of SPI flash, so we don't
need this region anymore. Getting rid of it allows us to put more space
into CBFS (to store hi-res bitmaps). Also grow VPD by some remaining
amount to keep the FMAP alignment reasonable.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: If73450b65718affae71b6ada70ded5c5f45cfb4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philip Chen <philipchen@google.com>
The existing define for SPI_FIFO_DEPTH looked a bit suspicious, but
turned out to be correct.
Change-Id: I91e65d922673f5c451a336ae013cb75f87a3fc98
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a helper function set_mmio_dev_ops() in chip.c which
is used for setting the dev->ops for MMIO devices based on the
comparison of MMIO address in device tree to the pre-defined base
addresses in iomap.h.
Call to i2c_acpi_name() is replaced with set_mmio_dev_ops and scope of
i2c_acpi_name is restricted to i2c.c since it is not required to be
exposed out of that file.
Change-Id: I31f96cfe8267b0df37012baeb7cfcaec9c2280f6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Drop functions that are not being used.
Change-Id: If406601f3bb7a98a621c1339b2f3413a43b8cc9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There have been changes to the way device properties are supported
in Linux[1] and Windows[2] which add flexibilty:
- non-standard UUIDs can be used instead of only ACPI_DP_UUID
- support for multiple different packages within the _DSD that
associate different properties with unique UUIDs.
To handle this I extracted the part that does the write of UUID and
properties to a separate function and defined a new PACKAGE type
which has the custom UUID as a name and can be used the same way that
child properties are today.
For example a PCIe root port for a USB4 port has a standard property
indicating the USB4 reference, and then two custom properties which
are defined for different attributes.
Example code:
/* Create property table */
acpi_dp *dsd = acpi_dp_new_table("_DSD");
acpi_dp_add_reference(dsd, "usb4-port", usb4_path);
/* Add package for hotplug */
acpi_dp *pkg = acpi_dp_new_table("6211e2c0-58a3-4af3-90e1-927a4e0c55a4");
acpi_dp_add_integer(pkg, "HotPlugSupportInD3", 1);
acpi_dp_add_package(dsd, pkg);
/* Add package for external port info */
pkg = acpi_dp_new_table("efcc06cc-73ac-4bc3-bff0-76143807c389");
acpi_dp_add_integer(pkg, "ExternalFacingPort", 1);
acpi_dp_add_package(dsd, pkg);
/* Write all properties */
acpi_dp_write(dsd);
Resulting ACPI:
Scope (\_SB.PCI0.TRP0)
{
Name (_DSD, Package ()
{
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package ()
{
Package () { "usb4-port", \_SB.PCI0.TDM0.RHUB.PRTA }
},
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package ()
{
Package () { "HotPlugSupportInD3", One }
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package ()
{
Package () { "ExternalFacingPort", One },
}
})
}
[1] https://patchwork.kernel.org/patch/10599675/
[2] https://docs.microsoft.com/en-us/windows-hardware/drivers/pci/dsd-for-pcie-root-ports
Change-Id: I75f47825bf4ffc5e9e92af2c45790d1b5945576e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create the voxel variant of the volteer reference board
BUG=b:157879197
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_VOXEL
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I8ba5412be211730db84675927c500238cb20ff3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
We previously confirmed [1] that bootblock will grow beyond current
8KiB size if console is enabled. Automatically change to 16KiB if user
enabled it in menuconfig.
[1] https://review.coreboot.org/c/coreboot/+/36775
Change-Id: Ic9988c77cf9677167a382aa4dc7dcfa2bc4cbe02
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41460
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If AMD_PUBKEY_FILE contains an absolute path the resulting path is
incorrect since it contains $(top).
BUG=b:147042464
TEST=Build trembyle with absolute and relative path.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib46b1799fad5588a18411f8c32541192d699cdd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40910
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add PCIe enumeration and resource assignment/allocation.
Xeon-SP processor family has split IIO design, where PCIe domain 0 is
split into multiple stacks. Each stack has its own resource ranges (eg.
IO resource, mem32 resource, mem64 resource). The stack itself is not
PCIe device, it does not have config space to be probed/programmed.
The stack is programmed by FSP. coreboot needs to take into account of
stack when doing PCIe enumeration and resource allocation.
Current coreboot PCIe resource allocator does not support the concept of
split IIO stack, thus entire support is done locally in this patch.
In near future, improvements will be done, first generalize for xeon-sp,
then generalize for coreboot PCIe device code.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: If461b1dc1f313d98b676dc9e91d08a1dbb9cb388
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
offsets for ACPI_PM are incorrectly configured for picasso SoC.
Especially incorrect ACPI_PM_TMR_BLK makes kernel to spend 10 sec for
trying to testing it on wrong address.
Fix them to correct offset with hack for GPE0_BLK.
BUG=b:147044624
TEST=build and boot on trembyle; PM Timer error is gone
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6adf71479c30f5b6751a21edc4bfa311ddbef5ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default HID was removed by a1c82c5ebe. We need to explicitly
specify it.
BUG=b:154756391
TEST=No longer see ERROR: _HID required message in console
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0083f98aea55ba262ac44b0018c9c1d2e12d9f8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If the device is missing the HID, the code would previously leave an
open scope and device on the stack.
BUG=b:154756391
TEST=Verify stack ACPI stack does not exceed limit on Trembyle.
Fixes: a1c82c5ebe ("drivers/generic/max98357a: Allow custom _HID from config")
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I798ed08ef0a0575def12937a66a7ce99f743e60d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These devices never show on the PCI domain.
Change-Id: I2d4d99c1e96c15dacb950aeb85b3e9a5d127c791
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: Ib0ffd9a332fa9590de63f8828d30daa710fe50db
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for google/link.
Change-Id: I5345ee22df7da92ee48c718f5bd748d7ea6155f2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Lower 20bits of TOLUD and TOLM registers include 19 reserved bits and
1 lock bit. If lock bit is set, then systemagent.asl would end up
reporting the base address of low MMIO incorrectly i.e. off by 1.
This change masks the lower 20 bits of TOLUD and TOM registers when
exposing it in the ACPI tables to ensure that the base address of low
MMIO region is reported correctly.
Change-Id: I1fb52a42e84130d973e0970024e263f443aa0b89
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41977
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change updates hostbridge.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for
google/beltino.
Change-Id: I0ba2da441c7b398cc7f84a7ef7a5d233b0365cbe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When no SMI is installed, FADT should not advertise a trigger
mechanism that does not respond.
Board does not support ACPI S4 or C-states or P-states.
Change-Id: If83efb72e076d404468259e312a5afac625f04af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Board does not have ChromeEC.
Change-Id: Id6ab2495d6e082fdcb71ec5162efde877d97ce22
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This file is not used.
BUG=b:154756391
TEST=Build trembyle and check that peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I721e295546aa75c9745a4836425b6e3e0067afaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Modify the FCH ACPI devices to query the PCI IRQ mapping registers for
their current IRQ numbers.
BUG=b:139429446, b:154756391
TEST=Boot trembyle and see that I2C and UART devices are finally
functional.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I8f2035f74240ead4089ff4d503dfbeb447cf8de4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch enables enables the CSE Lite SKU for all the
puff variant boards.
BUG=b:143229683
TEST=Build and boot puff with CSE Lite SKU.
Cq-Depend: chrome-internal:3046770
Change-Id: I0de6bca162b01870ca554ae97bc4a41cf66fef18
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch modified the puff fmd files to support CSE Lite SKU.
* Reduce the SI_ALL size to 3MiB since ME binary size is less
than 2.5MiB.
* Increase the FW_MAIN_A/B size to accommodate the ME_RW update
binary with CSE Lite SKU.
BUG=b:154561163
TEST=Build and boot puff with CSE Lite SKU.
Cq-Depend: chrome-internal:3046770
Change-Id: I4d39a1bdeabf48fc740da67539f48a9ff72c442c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41198
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These build on existing functions but use different object types
in order to provide functions for upcoming changes:
acpigen_write_return_op(): Return an operator.
acpigen_write_if_lequal_op_op(): Check if 2 operands are equal.
acpigen_get_package_op_element(): Read an element from a package
into an operator.
This one just provides the missing helper, the other 3 already exist:
acpigen_get_tx_gpio: Read TX gpio state.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I1141fd132d6f09cf482f74e95308947cba2c5846
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41985
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on schematic and gpio table of halvor, generate gpio setting and
overridetree.cb for halvor.
BUG=b:153680359
TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage
Verify that the image-halvor.bin is generated successfully.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: Ic6bd018551be58945742d1a6e7f7c5560f218e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The config option APL_SKIP_SET_POWER_LIMITS was accidentally left out
during the set_power_limits refactor (SHA 2adb50d32e). This patch
reinstates the config option which will cause APL boards to not set any
power limits.
TEST=util/abuild/abuild -p none -t siemens/mc_apl1 -a
Change-Id: Iec9f9f340d50a1212b6ef20c2c0e1b66385ae1b2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Call out the CSME-initiated bits from HPR_CAUSE0 register and
update the elog to include reset causes
Change-Id: I32ffb55ff2ad26ec4e7609c41fc65e021a327a14
Signed-off-by: derek.huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
H1 is stable after HW rework. Connect +3.3V_ALW_PCH with +3.3V_PRIM.
Therefore change I2C speed back to FAST.
BUG=b:154885320
TEST=Check H1 I2C speed is 375kHz by scope. And no error message in
cbmem and kernel log.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If58721039d90514a17f024e6b432f3a5226440e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Right now all FSP2.0 based IA platform doesn't need this driver anymore
hence removing to avoid debug and maintenance effort.
TEST=Verified booting from SATA on SPT/CNP/ICP/TGP PCH platforms.
Change-Id: Ied3832b26ba1fdd4c30fafe8149689a01d302c3e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41674
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The definition of processor_rev_id in struct microcode
is 16 bits. So we need to change the a series of parameters
passing to 16 bits.
Change-Id: Iacabee7e571bd37f3aca106d515d755969daf8f3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ripto board is still being used for testing so make sure it supports
the same audio config as volteer.
BUG=b:147462631
TEST=build ripto variant
Change-Id: Iabeb73307418dc16b12fa60ad26923cd9f6e1f3a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41896
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
For all of the audio devices in devicetree.cb add the probe matches
that will determine if the device should be enabled or not based on
the selected audio daughter board type.
AUDIO=MAX98357_ALC5682I_I2S: enable max98357 and alc5628, disable others
AUDIO=MAX98373_ALC5682I_I2S: enable max98373 and alc5682, disable others
AUDIO=MAX98373_ALC5682_SNDW: enable soundwire devices, disable others
BUG=b:147462631
TEST=test different device present in ACPI based on fw_config value:
> AUDIO=NONE
ectool cbi set 6 0x00000000 4 2
> AUDIO=MAX98357_ALC5682I_I2S
ectool cbi set 6 0x00000100 4 2
> AUDIO=MAX98373_ALC5682I_I2S
ectool cbi set 6 0x00000200 4 2
> AUDIO=MAX98373_ALC5682_SNDW
ectool cbi set 6 0x00000300 4 2
Change-Id: I5492e8cddcff3ba01023b0daef02be3508d347b0
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41216
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the current firmware configuration table for the volteer mainboard
and define some actions based on probe results for audio:
- When I2S options are selected disable the SoundWire GPIOs.
- When SoundWire is enabled disable the I2S GPIOs.
- When no audio is enabled disable all the GPIOs.
BUG=b:147462631
TEST=Test that GPIOs are configured as expected based on the current
value of the fw_config field in cbi.
Change-Id: I179f8b6436be83a2b37911777764bd26a0d404b7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41215
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Move all audio devices from baseboard to the volteer variant.
- Add max98373 devices and enable the driver
- Disable everything in FSP and let coreboot configure GPIOs.
BUG=b:147462631
TEST=this change makes all audio devices show up in ACPI, so this
was tested by ensuring that all audio devices are present in ACPI.
Change-Id: Ic654ea52a549053622603aa8c81fb37577d4e011
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change introduces a new top-level interface for interacting with a
bitmask providing firmware configuration information.
This is motivated by Chromebook mainboards that need to support multiple
different configurations at runtime with the same BIOS. In these
devices the Embedded Controller provides a bitmask that can be broken
down into different fields and each field can then be broken down into
different options.
The firmware configuration value could also be stored in CBFS and this
interface will look in CBFS first to allow the Embedded Controller value
to be overridden.
The firmware configuration interface is intended to easily integrate
into devicetree.cb and lead to less code duplication for new mainboards
that make use of this feature.
BUG=b:147462631
TEST=this provides a new interface that is tested in subsequent commits
Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's not a function that is the equivalent to
x86_setup_mtrrs_with_detect() but not solving for above 4GiB.
Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the
equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR
solver to not take into account memory above 4GiB.
BUG=b:155426691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41897
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that there is a generic solution in mtrr subsystem utilize
the API.
BUG=b:155426691,b:155322763
Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce concept of var_mtrr_context object for tracking and
assigning MTRR values. The algorithm is lifted from postcar_loader
code, but it's generalized for different type of users: setting
MSRs explicitly or deferring to a particular caller's desired
actions.
BUG=b:155426691,b:155322763
Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add RP configuration settings like Advanced Error Reporting(AER),
Latency Tolerence Reporting (LTR), Max Payload and Active State Power
Management (ASPM).
Tested on CFL platform
Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The porting of Asus P8Z77-M mainboard required changing certain Super
I/O configuration registers that were ignored in devicetree.cb because
they aren't listed as resources. Add the declaration so they can be
changed.
This change is nowhere near enough as the current structure is
insufficient to allow changing configuration registers in the 0xE?
range, which this board also needs.
TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when
inspected using superiotool -d.
Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: I76ec29210ecdde728ce55531d2b6657be87ce9da
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change updates gpio_op.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: I3ec442ad85f408135642a112873231ce7d39524e
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change updates pch_hda.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: I8e965560518decbfafabe9ac06066d28d59240d0
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change updates scs.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This change updates platform.asl to use ASL2.0 syntax. This
increases the readability of the ASL code.
TEST=Verified using --timeless option to abuild that the resulting
coreboot.rom is same as without the ASL2.0 syntax changes for wdoo.
Change-Id: Ie55bcd9ac2ca746c046ebe05140b2ac291fb0459
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release.
As CPX-SP FSP engineering is on-going (the processor Mass Production
is some time in this year). These header files will be adjusted when
changes are necessary with newer FSP release. This commit corresponds
to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65).
Also update soc/xeon_sp code file and Skylake-SP header file accordingly
to use FsptPort80RouteDisable instead of PcdPort80RouteDisable.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
