Commit c37b0e3 [soc/intel/skylake: Generate ACPI DMAR table]
only generates DMAR tables for boards using FSP 2.0, which
leaves out Skylake Chromebooks, which use FSP 1.1.
Correct this omission by adding the same functionality for
FSP 1.1 boards.
Test: build/boot on U-series Skylake Chromebook, observe
IOMMU fully functional with intel_iommu=on kernel parameter.
Change-Id: I68837f58aac357fa3f58979fe92d8993fae58640
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
FSP support two SATA modes as AHCI mode (0) and RAID mode (1), make it
more clear in header file.
Change-Id: I1edcadc0048df839da145260b60f9f7720d981fe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/30093
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CPU ratio will be fixed to non-turbo max value if CpuRatio UPD had been
set to zero.
BUG=N/A
TEST=Boot up into sarien system, cat /proc/cpuinfo and cpu frequency is
changing.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I3e82293c8b6027ddf9a528d0654fe46f233dcb82
Reviewed-on: https://review.coreboot.org/c/30216
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine if RAM must be reserved.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I3f55bf96ab2ec66cddbb54de03455a9bfd194682
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
commit msg copied from
commit id: 64c9f1584c
The GPIO drivers in Windows and Linux for the Icelake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
Change-Id: I94fafd8af13cf229f5c467de5179aed021465739
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Intel GMA ACPI opregion address needs to be set on S3 resume,
otherwise the Windows display driver fails to re-initialize correctly.
Fix by ensuring the address is set correctly regardless of display
init type used (GOP or VBIOS).
Test: build/boot on google/edgar, ensure internal display functional
following S3 resume under Windows 10.
Change-Id: I471c44e8ba4514e4a2ddf6739109b759145598ed
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Mirrors addition to Braswell SoC in commit d3d0f07.
Test: build/boot Windows 10 on Baytrail ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: Ia1fafa73325814fed30b2ac91290b682dd8eab04
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It seems they are not included anywhere, Jenkins?
Change-Id: I629cdeb337fce381c69bd1ba0520e524ccdd90dd
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/26756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The GPIO pin map for CNL-H does not match with the OS expected
pin numbers. This has been updated to match what is used by the
Linux kernel pinctrl driver and the pad base has been set for
the GPIO groups to match the sparse GPIO map used by the kernel.
I do not have CNL-H hardware to test this so it is verified against
the kernel driver at drivers/pinctrl/intel/pinctrl-cannonlake.c
Change-Id: Ife7d3090d654b0b88c6911befa08bf6abd4f2ff9
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30134
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO drivers in Windows and Linux for the Cannonlake CPU
have a sparse GPIO map and do not allocate pins contiguously.
Each GPIO group is allocated as 32 pads regardless of whether
the hardware actually has that many in the group.
It appears this originated with a bug in Windows/UEFI and was
carried over to Linux in order to work with existing firmware:
https://lore.kernel.org/patchwork/patch/855244/
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
BUG=b:120686247
TEST=tested with write protect GPIO on sarien board. Before this
change the ACPI pin number was 220 which did not correspond to the
pin number in Linux. After this change the ACPI number is 303,
which maps to the correct GPIO in Linux. Now the GPIO value reported
by the kernel changes when the WP pin is toggled in hardware.
Change-Id: I4f1a9e118d7e48f2445ccbb62a12a22e9a832c51
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The kernel GPIO driver only expects some GPIO communities to be exported
in the _CRS and it will not work correctly if the other communities are
exported.
CNL-LP: GPIO communities 0, 1, 4
CNL-H: GPIO communities 0, 1, 3, 4
Additionally one of the pin offset values was incorrect in GPIO
community 1 for CNL-LP. This doesn't have any specific failure mode but
it was found when auditing the GPIO code.
Details of the kernel expected map can be found in the linux kernel at
drivers/pinctrl/intel/pinctrl-cannonlake.c
BUG=b:120686247
TEST=check /sys/kernel/debug/pinctrl/INT34BB:00/pins to ensure that
pins >= 198 are not reading all zeros for the pin config registers.
Change-Id: Ie1a2f3b9f9f4b24a9fc57e468dee50e99753912f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Recently there has been a change to print ME version. But the stage at
which the version is printed causes the HECI device to remain in D0 state.
This in turn prevents the SoC from entering S0ix state.
This change moves printing ME version a little earlier so that the HECI
device is put into D0i3 state by FSP and the SoC can enter S0ix state
successfully.
BRANCH=octopus
BUG=b:120571529
TEST=Ensure that the ME version gets printed in BIOS logs. Ensure that
the device boots to ChromeOS. Ensure that the device enters S0ix
successfully(using suspend_stress_test -c 25).
Change-Id: I85bc45003a040c8347f929457792d78a9a077c6c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/30074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The input clock for the I2C controllers was set at 133MHz but should
really be 216MHz according to the kernel:
https://patchwork.kernel.org/patch/10408729/
"Intel Cannon Lake PCH has much higher 216 MHz input clock to LPSS I2C
than Sunrisepoint which uses 120 MHz. Preliminary information was that
both share the same clock rate but actual silicon implements elevated
rate for better support for 3.4 MHz high-speed I2C."
This change was tested on a sarien board where an I2C trackpad that was
measuring ~700MHz on I2C and is now measuring ~380MHz.
Change-Id: I792d1f013da5538a2b8157e2f99b754ca7b6bf70
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30061
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As part of the memory mapped BIOS region is covered by SRAM, check
that CBFS always fits the effectively mapped region of flash. This
is usually taken care of by reserving the SRAM range in the FMAP
(e.g. as BIOS_UNUSABLE), but can be missed.
Change-Id: If5a5b553ad4853723bf13349c809c4f6154aa5f2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/30055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use common code to tear down CAR.
Change-Id: I62a70ae35fe92808f180f2b5f21c5899a96c2c16
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch does the following:
- improve the style by removing tabs in front of jmp addresses
- Make the code for zeroing variable MTRR more readable (copied from
cpu/intel/car)
- Fetch PHYSMASK high from cpuid instead of Kconfig
Change-Id: I6ba67bb8b049c3f25b856f6ebb1399d275764f54
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This does the following:
- Reuse the cpu/intel/car/non-evict CAR setup and exit.
- Use postcar_frame functions to set up the postcar frame
Change-Id: I428832a2d7e46ce61a7f9bd498b609feb4518eb0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in
cpu/x86/smm.h
Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the ACPI device names for the USB ports to match what
is in the DSDT so USB ports can be defined in the SSDT.
Change-Id: Ibb323bbd324811fa3178b0cba3d7f0a315169486
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Increase the bootblock size to 48K to match skylake. With UART
enabled we are very near the 32K limit, and with upcoming changes
to add USB devices in devicetree for a cannonlake board it is over
the current 32K limit.
Change-Id: I155cb0a6af1746af6833fa9f35c2ea6fe0bc709f
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Define the constants that DPTF expects from the SOC in order to
use the common DPTF ACPI code. For cannonlake this indicates
the CPU device is called B0D4 and is at PCI address 00:04.0.
Change-Id: I43c2f8dd7281d3e9f791ab01478ee7823fd6b128
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29759
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method to convert from 1/10 Kelvin to Celsius. This
is useful for EC devices where the sensor temperature are
stored in Celsius instead of Kelvin.
Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support using the common ACPI code on more platforms
than just Apollo Lake the DPTF code needs to be told what the
PCI address is for the CPU thermal device.
Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Backlight control of internal panels likely won't work as configuration
for that seems absent in coreboot. Also, libgfxinit doesn't support any
MIPI/DSI connections, yet, and neither Gemini Lake.
TEST=Booted work-in-progress port kontron/mal10 with VGA text and
linear framebuffer modes. DP display came up.
Change-Id: I7b111f1cdac4d18f2fc3089f57aebf3ad1739e5d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support to print ME version if UART_DEBUG is
enabled. Check for UART_DEBUG is necessary because talking to ME to
get the firmware version adds ~0.6 seconds to boot time.
TEST=Verified on octopus that ME version printed is correct.
Change-Id: I41217371558da1af694a2705e005429155d62838
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/29989
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sync the FSP settings with what coreboot does. Why both FSP and coreboot
configure this redundantly stays a secret.
TEST=Set SERIRQ_CONTINUOUS on kontron/mal10. A CPLD connected to LPC
works correctly now, but was confused by the wrong settings before
because the FSP defaults allowed to disable the LPC clock.
Change-Id: Id1c7180f460678bf0f9458228591050dd628c052
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I01e4397b9a1c15eff4b856cbc697fa2b4bc9761f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: If482c64e7133cc6d82472d121ac138fc1b60a183
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: David Guckian
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Automatically generate \PPKG in SSDT.
Change-Id: I79d2eed9b89b420554ce10d1fc0f151b1872afe2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I93c11e89da34c5432c6ce0415998b47bad339763
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29889
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Ifb5a5c1255f9a922063293bf430e849909468eaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29888
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: I182585fd09e4ce848c860d00eb612e8f5fdde35e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29884
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Makes vboot measured boot mode available for all boards.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add missing files for Intel apollolake and
AMD stoneyridge as TPM driver target.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove the __SIMPLE_DEVICE__ define from files used only in romstage.
This is not required since romstage always defines __SIMPLE_DEVICE__.
Change-Id: I8db1b15c9186536c9b8a6b5d667fa5a11af1bad2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/29821
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RAM is reserved for Chromeos even when Chrome is not used.
Use CONFIG_CHROMEOS to determine is RAM must be reserved.
BUG=N/A
TEST=Intel BayTrail CRB
Change-Id: Ic1f5089227f802e2b2f62dc02fa0d1648c1855b5
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Make pch_early_iorange_init() function similar to
soc/intel/cannonlake/bootblock/pch.c while fixing below issue:
* COM1 not being enabled properly.
TEST=Able to get serial output from an 8250IO UART device at
the standard 0x3f8 base address.
Change-Id: I5ab02f46d27e667be3d9328d94b634ef04038d2f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/29835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Using 0 for PIRQ_PIC_IRQDISABLE might conflict with using IRQ0 as PIRQ.
Change PIRQ_PIC_IRQDISABLE value to 0x80, so value 0 is reserved for IRQ0.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I18706f12e7c2293e948eb10818393f0d1870f514
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29393
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The sizes of IO_BASE and ILB_BASE areas a incorrect.
Correct IO_BASE_SIZE and ILB_BASE_SIZE values.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I23c3fd608598c5ec2271d393168ac4bf406772b4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The resources of the local APIC are not reserved.
Use mmio_resource() to add local APIC resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ieb9de45098d507d59f1974eddb7a94cb18ef7903
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
ACPI and GPIO base are used by LPC controller, but not reserved.
Both bases are added to the LPC device resources.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I5248694b497c4965d79dd7c25ec97592dc0dddbc
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
PL4 is a preemptive CPU package peak power limit,it will never be exceeded.
Power is preemptively lowered before limit is reached.
This change provides option in devicetree and feeds FSP PowerLimit4 UPD for
power limit purpose.
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Change-Id: I64b5a029104a102e5741e8b37c7992f2693180e8
Reviewed-on: https://review.coreboot.org/c/29808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: I348eda57ab9dc0bd45f8dc9ab0e7c47c462102fe
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29788
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO and ACPI base sizes have defines, but they are not used.
Use GPIO_BASE_SIZE and ACPI_BASE_SIZE.
BUG=N/A
TEST=Intel BayTrail CRB
Change-Id: I3fe50effdb8236bc45d33a2345a773653df68d90
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Huang Jin <huang.jin@intel.com>
It's not implemented for Skylake, all combinations that try to enable it
either result in Kconfig or linker errors.
Move `config SKIP_FSP_CAR` into drivers/intel/fsp1_1 where it's
effective.
TEST=Built Intel/Kunimitsu (FSP1.1) and Intel/KBLRVP8 (FSP2.0) default
configs with and without this patch: binaries stay the same.
Change-Id: Iae0a2d2c7fd7a71ed24118564e6080c4789cda28
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/29533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The mentioned bits 14:8 are wrong as the functions always write
bits 15:8. What happens is visible in the written code. There is no need
for an extra comment.
Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a Kconfig switch to be able to set the CPU clock to the lowest
possible ratio. If enabled the CPU will consume as little power as
possible while providing the lowest performance.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to its need.
Change-Id: I4a59586da72d1915749110a36f565fe2aa69e073
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Provide a library function to set the CPU frequency to minimum
value. This will result in the lowest possible CPU clock with
the lowest possible power consumption. This can be useful in mobile
devices where the power dissipation is limited.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to it's need.
Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The timer interrupts don't appear when HPET is enabled. This
result in Linux reporting 'MP-BIOS bug: 8254 timer not connected
to IO-APIC'
Enabling CONFIG_DISABLE_HPET disables OS use of HPET.
Intel issue 4800413 (doc #5965535) reports Windows7/Ubuntu Installation
Hang or Slow Boot Issue.
BUG=Intel #4800413
TEST=Portwell PQ7-M107
Change-Id: Ie9a78dcc736eb057c040a0a303c812adb1f76f3c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This change makes the early IO decode setup mirror that of other
Intel SOCs and fixes issues with COM1 not being enabled properly.
Tested by successfully successfully receiving serial output from
an 8250IO UART device at the standard 0x3f8 base address.
Change-Id: I9bd894fea62b78b81e5c80b5e88a539ebddac2df
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
It defaults to y to avoid having to select it per mainboard. But that
makes a mess because it results in linker conflicts unless other UART
drivers disable it explicitly.
We try to be smarter about the default value for now. The real solu-
tion would be to hardcode it per mainboard. But who knows which boards
actually have it?
Change-Id: I7e755fe0e4f6d1c31ef2854603a5510c3cdc4967
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29571
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I9693f2a52529961e6b611b69e389f01f77f77d63
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/icelake/acpi/
Change-Id: Idec00c3b8a97cb5aa7b4000840aba914aea478c9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Braswell allready supported vmx, but offered no mechanism to unset it, nor
to set the lock bit required for Windows to recognize virtualization.
Enable this functionality by adding CPU_INTEL_COMMON config.
Test: build/boot Windows 10 on Braswell ChromeOS device, verify Windows shows
virtualization as enabled.
Change-Id: I0d39abaeb9eebcceb37dc791df6b06e521fe1992
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/29570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The common SPI controller driver in src/southbridge/intel/common does
match the SPI controller included in the PCH of Broadwell-DE SoC. Switch
to the usage of this driver and delete the dedicated one for the FSP
based Broadwell-DE implementation.
TEST: Boot mc_bdx1 with SPI driver active in romstage
Change-Id: I4fe8057ea1981e350659a5caa9912fb758110115
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/29633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Currently mode-aware DPTF depends on Tablet Mode Switch to load the
right table. This does not scale well with device types and configuration.
This change helps to decouple the mode-aware DPTF from Tablet Mode Switch.
This change allows ACPI to load the appropriate DPTF table based on the
profile number as detected by EC.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes(base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: Ibffe9c58f970aec37aa74a040170c4cf559bab33
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29249
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename EC_ENABLE_TABLET_EVENT config as EC_ENABLE_MULTIPLE_DPTF_PROFILES
since it aligns with the use-case.
BUG=b:118149364
BRANCH=None
TEST=Ensured that the expected DPTF table are loaded in different
modes (base attached/detached and clamshell/360-flipped) on Soraka and
Nautilus.
Change-Id: If147f1c79ceaaed00e17ec80ec6c912a8f7a8c2e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/29261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch makes static PIRQ->IRQ mapping, where IRQ10 is mapped
to PBRC and IRQ11 is mapped for PARC/PCRC/PDRC/PERC/PFRC/PGRC/PHRC.
Change-Id: I8722e34841fe53a4d425202b915ac7838af0d859
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29629
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since PIRQ->IRQ mapping registers PxRC are not available after FSP-S call
due to PCH requirement change from CNP PCH onwards, hence making static IRQ
mapping for pci_irqs.asl and pcie.asl
Also remove unused irqlinks.asl from soc/intel/cannonlake/acpi/
Change-Id: I35e2ed150a1db195fc9ce13897e65b23fc8b7ca1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove the SmbusEnable config option from devicetree and instead
use the state of the PCI device to determine if it should be
enabled or disabled.
Change-Id: Id362009e4c8e91699d1ca9bb3c2614e21cfc462a
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some embedded controllers expect to be sent a command when the OS
calls the ACPI \_PTS and \_WAK methods. For example see the code
in ec/google/wilco/acpi/platform.asl that tells the EC when the
methods have been executed by the OS.
Not all ECs may define these methods so this change requires also
setting a Kconfig option to enable it.
Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change disables HECI1 device at the end of boot sequence. It uses
the P2SB messaging to disable HECI1 device before hiding P2SB and
dropping privilege level.
BUG=b:119074978
BRANCH=None
TEST=Verified that HECI1 device is not visible in lspci on octopus.
Change-Id: Id6abfd0c71a466d0cf8f19ae9b91f1d3446e3d09
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add an option that will disable eSPI SMI when ACPI mode is enabled,
and re-enable eSPI SMI when ACPI mode is disabled. Additionally it
ensures eSPI SMI is disabled on the ACPI OS resume path.
This allows a mainboard to ensure that the Embedded Controller will
not be able to assert SMI at runtime when booted into an ACPI aware
operating system.
This was tested on a Sarien board with the Wilco EC to ensure that
the eSPI SMI enable bit is clear when booted into the OS, and remains
clear after resume.
Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kabylake RVP11 uses FSPT to support Intel security features like
bootguard verify boot and measured boot.
This patch add FSP CAR support for kabylake by programming tempraminit
parameters in fspcar.c and also add FSP_T_XIP default if FSP_CAR is
selected in order to relocate FSPT binary while adding it in CBFS so that
it can be executed in place.
BUG=None
TEST=Build and Boot to UEFI payload on kabylake RVP11 board and verified
for successful FSP CAR setup.
Change-Id: Id180ff9191d734c581ba7bf3879eaa730a799b52
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides an interface for apollolake to set TCC before
BIOS reset complete happens in romstage.
With this change, we can add code to update Tcc in devicetree.
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
soc_rtc_init() is executed in ramstage
The soc_rtc_init() needs to be executeed before FSP is called. Move the RTC
init from ramstage to romstage.
BUG=N/A
TEST=Intel CherryHill CRB
Change-Id: Ic19c768bf9d9aef7505fb9327e4eedf7212b0057
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/29397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PCH ISH enabled/disabled in FSP memory init UPD, it will be match the
setting in ISH device on/off in devicetree.cb.
BUG=N/A
TEST=Build and pass on whiskey lake rvp platform.
Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Required to compensate for Chrome OS' tree differences
Change-Id: I01fe80b55c69ff57da1c96a76bd1d9b5a2d4a9a8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Clone entirely from Cannonlake
commit id: 3487095304
List of changes on top off initial cannonlake clone
1. Replace "Cannonlake" with "Icelake"
2. Replace "cnl" with "icl"
3. Replace "cnp" with "icp"
4. Rename structrue based on Cannonlake with Icelake
5. Remove and clean below files
5.a. All NHLT blobs and related files.
5.b. remove cnl_memcfg_init.c file, will be added later.
5.c. Remove vr_config.c, this is WIP.
5.d. Clean up upd override in fsp_params.c,
will be added once FSP available.
5.e Remove CNL-H based GPIO configuartion.
Ice Lake specific changes will follow in subsequent patches.
Change-Id: I756fa7275c4190aebc0695f14484498aaf5662a5
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29162
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.
BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.
Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
- should not check VBOOT_STARTS_IN_BOOTBLOCK to set context flag
- implement vboot_platform_is_resuming on platforms missing it
- add ACPI_INTEL_HARDWARE_SLEEP_VALUES to two intel southbridges
[ originally https://review.coreboot.org/c/coreboot/+/28750 ]
BUG=b:114018226
TEST=compile coreboot
Change-Id: I1ef0bcdfd01746198f8140f49698b58065d820b9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/29060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This change adds new macros to GPIO common library helpers to allow
a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds
a helper macro to configure a pad for IRQ and wake.
Above macros are guarded using a newly added Kconfig option
SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only
by SoCs that have been validated to allow dual route of
GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that
have been validated to work with dual-routing of GPIs for IRQ and
wake.
BUG=b:117553222
Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates various PAD_CFG_GPI* macros to configure Tx as
Disabled in IO Standby state. This is done to ensure that the Tx
setting is same in IO Standby state as it was in active state i.e. Tx
disabled.
BUG=b:17553222
Change-Id: If462aee3884cc61a519fb358b84867c695ace251
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Also add a test case for that, a config taken from chromiumos with some
references to binaries dropped that aren't in our blobs repo (eg audio
firmware).
Change-Id: I411c0bacefd9345326f26db4909921dddba28237
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/29223
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch selects common HDA driver and adds audio controller device id
to enable audio on coffee lake platforms.
BUG= None
TEST= boot to yocto linux and windows os on CFL RVP11 & RVP8, verified audio
functionalities.
Change-Id: I4a60a4d7d8babcd0c14664a304ca81d47c668a6c
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29145
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In Skylake/Kabylake, if ACPI PM timer is disabled then TCO also gets
disabled & vice versa.
FSP default config for EnableTcoTimer is disabled, this caused ACPI PM
timer & TCO to be disabled by FSP even when config PmTimerDisable = 0.
Thus update FSPS UPD EnableTcoTimer in accordance to devicetree config
PmTimerDisable.
BUG=None
TEST= Build for Soraka with PmTimerDisable=0 & check if TCO caused
reboot after running shell command: cat >> /dev/watchdog0
Change-Id: Ia146761036c9dbaef3c02c9a7122ae3dcdef7bdd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/29108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
- CNL PCH-H has 12 GPIO groups which are grouped under 5 gpio communities.
- Add gpio pin definitions for CNP-H and related changes.
- Add gpio device name, host software ownership reg offset for CNP-H.
BUG: none
TEST: build and flash, boot to windows and yocto os on both CFL RVP8 &
RVP11 and verify power management, IO device functionalities
work fine.
Change-Id: I496ec059de125b97c646581bbd3b8bfe6ffa641e
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With https://github.com/IntelFsp/FSP/pull/4 merged, this allows using
Intel's FSP repo (that we mirror) to build a complete BIOS ifd region
with a simple coreboot build, automatically drawing in headers and
binaries.
This commit covers Apollolake, Coffeelake, Skylake, and Kabylake.
Skylake is using Kabylake's FSP since its own is FSP 1.1 and Kabylake's
also supports Skylake.
Another candidate (given 3rdparty/fsp's content) is Denverton NS, but
it requires changes to coreboot's FSP bindings to become compatible.
Cannonlake, Whiskeylake require an FSP release.
Change-Id: I8d838ca6555348ce877f54e95907e9fdf6b9f2e7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28593
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bounce buffers used to be used in those cases where the payload
might overlap coreboot.
Bounce buffers are a problem for rampayloads as they need malloc.
They are also an artifact of our x86 past before we had relocatable
ramstage; only x86, out of the 5 architectures we support, needs them;
currently they only seem to matter on the following chipsets:
src/northbridge/amd/amdfam10/Kconfig
src/northbridge/amd/lx/Kconfig
src/northbridge/via/vx900/Kconfig
src/soc/intel/fsp_baytrail/Kconfig
src/soc/intel/fsp_broadwell_de/Kconfig
The first three are obsolete or at least could be changed
to avoid the need to have bounce buffers.
The last two should change to no longer need them.
In any event they can be fixed or pegged to a release which supports
them.
For these five chipsets we change CONFIG_RAMBASE from 0x100000 (the
value needed in 1999 for the 32-bit Linux kernel, the original ramstage)
to 0xe00000 (14 Mib) which will put the non-relocatable x86
ramstage out of the way of any reasonable payload until we can
get rid of it for good.
14 MiB was chosen after some discussion, but it does fit well:
o Fits in the 16 MiB cacheable range coreboot sets up by default
o Most small payloads are well under 14 MiB (even kernels!)
o Most large payloads get loaded at 16 MiB (especially kernels!)
With this change in place coreboot correctly still loads a bzImage payload.
Werner reports that the 0xe00000 setting works on his broadwell systems.
Change-Id: I602feb32f35e8af1d0dc4ea9f25464872c9b824c
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/28647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove assert() and instead use if statement to check if
comm->groups is NULL.
Found-by: klockwork
BUG=None
TEST=Boot to OS
Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/28940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change sets PCIEXPWAK_DIS in PM1_EN register if WAKE# pin is not
enabled on the platform. This is required to prevent unnecessary wakes
if the WAKE# pin remains not connected on the platform. Function to
set PCIEXPWAK_DIS gets called in normal boot path (BS_PAYLOAD_LOAD) as
well as S3 resume path (BS_OS_RESUME).
BUG=b:117284700
TEST=Verified that no spurious wakes are observed on nocturne.
Change-Id: Iea93baffc9bb703c0ffedacafc6a9a9410c7ebfe
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch creates _PRT entires for each PCIE root port devices.
TEST=Able to see PCIE wake device in cat /proc/acpi/wake list
Change-Id: I183c89c92139e15e0bfc39620710dbdc6597b351
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Legacy PME are enabled by default in FSP-S UPD. This policy sets
PME Interrupt Enable (PIE) bit of RCTL register to trigger interrupt
generation when RSTS.PS state has changed (either due to 0->1 transition
or due to this bit being set with RSTS.PS already set). Due to this
interrupt generation, system wakes from sleep immediately it enters.
This patch overrides root port legacy pme upd policy from coreboot to
ensure no false SCI is triggerd when system is in S3/S0ix state.
BUG=b:113083354
BRANCH=none
TEST=Able to make S3 resume using wake on wifi connect/disconnect usecase
without any failure.
Change-Id: I779fac711eeeed65ea379fad1cc400052d8a00eb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fixes KW issue due to pointer being NULL and will be dereferenced
Change-Id: Iedb59daf5f448e31c0097873a086e4d08cd4a979
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28948
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.
Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.
BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.
Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:
1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.
2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.
3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.
4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.
Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.
BUG=b:112888584
Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch removes assert() and checks if the dev is NULL with "if"
condition only.
Found-by: klockwork
Change-Id: Icd2c8490c8bda14ecd752437d463a7110fe40aea
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28888
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move funtions callbacks used to override FSP upd values to
separate files. This serves as a base change for SoCs for which
FSP is still under development, and hence the FSP header files
are not available yet and in turn the UPDs cannot be referred.
These newer SoCs will implement empty callbacks. The code will
compile with basic header files which only include the architectural
FSP structures.
This allows plugging in these separate files for compilation in an
environment where FSP header files are available.
The fact is, FSP header files are not released externally until PRQ.
However the teams at intel and some partners have access to the development
version of these files. This code refactor helps to continue development
on the pre-PRQ silicons and submit related code to coreboot.org.
BUG=None
BRANCH=None
TEST=Build for cnlrvp
Change-Id: Iffadc57f6986e688aa1bbe4e5444d105386ad92e
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures I2C controllers are out of reset without any
assumptions.
BUG=b:116191230
BRANCH=none
TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT
at reset (by reading Bit 0-1 as 3)
Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Regarding the SDMs, IA32_MC0_STATUS register is at 0x401, and
IA32_MC0_CTL is at 0x400.
So replace MSR at (0x400+1) by IA32_MC0_STATUS and the one at
0x400 by IA32_MC0_CTL.
Change-Id: I3f53c80f39078bd0c47c25013657e1169fc6c4a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The function to fill out the FADT table exits early if the devicetree
config option to disable the legacy timer is set. This means it never
gets to the later check for s0ix config option and so the flag to
indicate that it supports low-power idle in S0 is not set.
Change-Id: Ia0416f21b6445f6feecb6f0301d48fdf2522b8a6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28755
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit
UPD, hence change the settings in coreboot side as well. The old options
in SiliconInit get deprecated, so leave the code as is will be
harmless. Make the changes limited to coffeelake itself.
Change-Id: If968de78117068668e4f0006c412442c50658ba9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28740
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the FSP silicon UPD entry can be updated base on device switch
in pci device tree, have both static config setting and device tree "on"
and "off" will be redundant.
BUG=N/A
TEST=Build and boot up fine with Whiskey Lake RVP platform.
Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/27766
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support to set eMMC tuning params from the device tree so that it
can be configured per board.
BUG=b:112718426,b:112690628
BRANCH=none
TEST=Build nocturne image and checked values passed in dev tree is set
by FSP.
Change-Id: Ic71934dce9a1c380a057e579ca3fda41983b9385
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/28274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
No support for SoC D-1 stepping is available.
According to Intel doc #332095-015 stepping C-0 has revision
id 0x21 and D-1 revision ID 0x35.
Also correct the RID_C_STEPPING_START value for C-0.
BUG=none
TEST=Built, Intel Cherry Hill Rev F.
Change-Id: I29268f797f68aa4e3b6203e098485e0bd4a44fc4
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/27471
Reviewed-by: Wim Vervoorn
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This included the microcode for some CPUID's found in
soc/intel/skylake/bootblock/report_platform.c (others are likely pre-release
SKU's)
The amount of FIT entries needed is currently 7 so setting
CPU_INTEL_NUM_FIT_ENTRIES is set to a safe 10 will be able to fit them all.
Change-Id: I3ba504a07b2697fe55ff8f28a934f761ae05a4ec
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to cannon lake PCH BIOS specification document #570374
target port id for interrupt and timer subsystem(ITSS) is C4 instead of C2.
BUG=None
TEST=None
Change-Id: I9f8783c682d2c4c4a86e1c9cf4b9c27a18fdf494
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Kin Wai Ng <nelsonaquik@gmail.com>
Remove const define for spd_smbus_address, the value can be updated
depends on platform configuration.
TEST=Build and Run on Whiskey Lake rvp platform.
Found-by: Converity Scan #1395725
Change-Id: Ib933ed872e9f85087bb3cd76a1f1e29cca75cd54
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28664
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP initializes the VT-d feature on Broadwell-DE and assigns an address
space to the MMIO range. coreboot's resource allocator needs to be aware
of this fixed resource as otherwise the address can be assigned to a
different PCI device. In this case addresses are overlapped and the VT-d
range is not accessible any more.
To deal with it the right way add a fixed MMIO resource to the resources
list if VT-d BAR is enabled.
TEST=Booted into Linux and checked coreboot log for resource assignment.
Change-Id: I626ac17420eadc0b49031e850f0f40b3b221a098
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The DMAR table generation depends on the VT-d feature which is
implemented in its own PCI device located in PCI:00:05.0 for
Broadwell-DE. Add a new PCI driver for this device and move
DMAR table generation to this device driver.
Change-Id: I103257c73f5e745e996a441a2535b885270bc204
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/28671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Use of device_t has been abandoned in ramstage.
Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add definition for PCH_GPIO_PIRQ_INVERT, which is needed
for google/buddy, a to-be-merged variant of google/auron.
Taken from Chromium commit 70ee99b [buddy: change trigger type of gpio53]
Change-Id: I21448160cee791710df51d06efa32cdfecf38c0f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/28611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid
Inter Flash Descriptor to exist. It does *not* identify platforms or boards
that are capable of running in descriptor mode if it's valid.
Refine the help text to make this clear.
Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply
declare that IFD is supported by the platform. Select this value everywhere
instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to
y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected.
Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to
the mainboard directory.
Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060
Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at>
Reviewed-on: https://review.coreboot.org/28371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, there is a trailing space in the log message below.
> Enabling VR PS2 mode: VNN VCC
So, put the space before the word.
Change-Id: Ic536d77aa910b1b98a3c2f35d595dee4251b1c18
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/28525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch adds the support for CmdTriStateDis FSP upd in skylake
soc structure so that we can define it in devicetree.CmdTriStateDis
needed to be set for the skylake/kabylake based boards where LPDDR3
design is without RTT for CMD/CTRL.We need to set this bit for those
designs for the margin to be proper.
BUG=b:111812662
TEST=Run memtester app and also webgl fishtank on
the LPDDR3 kabylake boards and also check the
margin data is proper in FSP.
Change-Id: Ida69e443aa6ea4b524bd3ea2dcf26f4e63010291
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/28424
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
this enables spi console for wedge100s with broadwell_de. the console
size is 64kb. enabling spi console in `board.fmd` enables code which
calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and
`udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE`
in fsp_broadwell_de's Kconfig to satisfy that.
Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8
Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com>
Reviewed-on: https://review.coreboot.org/28528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
