Now that __aligned is around, take advantage of it.
Change-Id: I93cdbe108d752088f34d3f5722dce5d9b90bcdc3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26022
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
barrier_wait_timeout() was not used anywhere in the code. The
remaining two functions, barrier_wait() and release_barrier(), are
not used anywhere but the mp code.
Change-Id: If09991f95306becc68b6008ae6448695fb4a2dca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/26021
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The existing logic to set up CsMux67 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
Commit cf1cb5b2d4 did the same
for CsMux45 but missed this one.
Change-Id: Ib97ca89535b8291397d42eca69e217c21a9dd937
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/25994
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation of having FIT payloads, which aren't converted to simple ELF,
rename the CBFS type payload to actually show the format the payload is
encoded in.
Another type CBFS_TYPE_FIT will be added to have two different payload
formats. For now this is only a cosmetic change.
Change-Id: I39ee590d063b3e90f6153fe655aa50e58d45e8b0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add device tree options to enable beeps when exceeding temperature,
voltage, and fan limits. As of this commit, setting voltage and fan
limits is not implemented.
Change-Id: I57ce622ee4498b75f00e678c2e6d72e499925bce
Signed-off-by: Vagiz Trakhanov <rakkin@autistici.org>
Reviewed-on: https://review.coreboot.org/22141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I6f6c4330ad88e013b24761a3aa1c29bc869da39d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: If2b9cbf130f963bc1bedef16b7951e9546054743
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Idb139d5cb2ac10f4051407137242ccee1a09b785
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: If9c122efbb7dbab7d834372da3c1c70463be7a77
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Idff2ec30f0b8c9a49f4369e231be92cbc8070dc0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Ia25c5097d4cfa979c18a855e656ad794c2f0260c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I839533a33aa54df4efed3f372c6f88e79b0b559b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I14c0db71ffa5faa8321c88c9c75c0c18a70910e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I5eb858df7b69a7177564c883b81177ffadc63691
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I6f3efd8c9be7f9fb83b373fbee311b06cde54181
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I82b73e1698d8d44e32ad9f21e575a7fce35baa1c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Ic25d1eb3c7f0ed5b65aa1cf9e16c39415b7cd3c7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add method to walk memory tables from OS point of view.
The tables don't change when modifiying bootmem entries and doesn't contain
bootmem specific tags.
Change-Id: Iee332a9821d12a7d9a684063b77b0502febd8d7d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a method to walk bootmem memory tables and call a function
for each memory range. The tables might not match with OS sight
of view.
Return true if the callback function returned false.
Required for FIT support in coreboot to find a usable RAM region.
Tested on Cavium SoC.
Change-Id: I0004e5ad5fe2289827f370f0d0f9979d3cbd3926
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce new bootmem tags to allow more fine grained control over buffer
allocation on various platforms. The new tags are:
BM_MEM_RAMSTAGE : Memory where any kind of boot firmware resides and that
should not be touched by bootmem (by example: stack,
TTB, program, ...).
BM_MEM_PAYLOAD : Memory where any kind of payload resides and that should
not be touched by bootmem.
Starting with this commit all bootmem methods will no longer see memory
that is used by coreboot as usable RAM.
Bootmem changes:
* Introduce a weak function to add platform specific memranges.
* Mark memory allocated by bootmem as BM_TAG_PAYLOAD.
* Assert on failures.
* Add _stack and _program as BM_MEM_RAMSTAGE.
ARMv7 and ARMv8 specific changes:
* Add _ttb and _postram_cbfs_cache as BM_MEM_RAMSTAGE.
ARMv7 specific changes:
* Add _ttb_subtables as BM_MEM_RAMSTAGE.
Change-Id: I0c983ce43616147c519a43edee3b61d54eadbb9a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Non-dts based systems can pass mclk to da7219 driver by
this property.
BUG=b:74570989
TEST=Enabled clock in kernel driver using the property
Change-Id: I2e10769e5b3c6b3aa30f340fe0e88c29b87430cb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ifdtool has relied on one of the fields within FCBA(read_freq) to
determine whether a platform supports IFD_VERSION_1 or
IFD_VERSION_2. However, newer platforms like GLK and CNL do not have
read_freq field in FCBA and so the value of these bits cannot be used
as an indicator to distinguish IFD versions. In the long run, we need
to re-write ifdtool to have a better mapping of SoC to IFD fields. But
until that is done, this change adds a list of platforms that we know
do not support read_freq field but still use IFD_VERSION_2. This
change also updates GLK and CNL to pass in platform parameter to
ifdtool.
BUG=b:79109029, b:69270831
Change-Id: I36c49f4dcb480ad53b0538ad12292fb94b0e3934
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the latest AGESA timestamp values were added, the descriptions
weren't added along with them. Because of this, the cbmem tool just
shows them as "<unknown>".
Bug=b:79153552
TEST=None
Change-Id: Iad7bcd53bc6136b74d4d933d1a290feac6a0de56
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26001
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit edf2f59b1d.
(google/kahlee: Resume on AC insertion)
The requirement to wake on AC insert is just to wake enough to charge,
not to wake the entire system.
BUG=b:77602394
TEST=None
Change-Id: I0ee709183b1605c1efc0fce673db512fac66adfa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26014
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
It's very confusing trying to find the google platform names, because
they seem all unsorted in Kconfig. They're actually sorted according
to the variant name, but previously, that was impossible to tell.
- Add a comment to the top of variants in Kconfig.name
- Inset each variant name. If you start a prompt with whitespace,
it gets ignored, so after trying various ways to indent, the arrow
was the option I thought looked the best.
It now looks like this:
*** Beltino ***
-> Mccloud (Acer Chromebox CXI)
-> Monroe (LG Chromebase 22CV241 & 22CB25S)
-> Panther (ASUS Chromebox CN60)
-> Tricky (Dell Chromebox 3010)
-> Zako (HP Chromebox G1)
Butterfly (HP Pavilion Chromebook 14)
Chell (HP Chromebook 13 G1)
Cheza
*** Cyan ***
Change-Id: I35cb16b040651cd1bd0c4aef98494368ef5ca512
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add raydium controller
- Update elan controller with reset and enable GPIOs.
- Enable 'probed' so Linux will check which controller is being used.
BUG=b:78929054
TEST=Both elan and raydium touchscreen controllers work
Change-Id: I3bd9912a4b1edc7bf1075cb649afa3eab5dca458
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25998
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix (assumed) regression with commit
ac63b41 vendorcode/amd/agesa: Fix variable length array declaration
The code used sizeof() on the struct where array length was
previously adjusted, but only f14 case was fixed accordingly.
Change-Id: Ib83660d5e102e13b4ffad19fb78f695ac4a871dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26036
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix a function prototype to support PCI on non x86.
The function itself does have the correct argument already.
Change-Id: I564fcfe9b85ed4f841a48fe17a3f5bf80e16560b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Definition of S_PSTATE only allowed PStateStruct[0], while it is
effectively used as a flexible array. Since sizeof(S_PSTATE) is
reduced here by sizeof(S_PSTATE_VALUES), we have to account for
that when calculating PStateLevelingSizeOfBytes.
In S_PSTATE context, PStateStruct[PStateMaxValue] is valid reference.
GCC 7.2.0 warns about an out of bounds array subscript.
```
CC libagesa/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.o
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c: In function 'PStateLevelingMain':
src/vendorcode/amd/agesa/f14/Proc/CPU/Feature/cpuPstateLeveling.c:524:65: error: array subscript is above array bounds [-Werror=array-bounds]
PStateBufferPtrTmp->PStateCoreStruct[0].PStateStruct[k].PStateEnable = 0;
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~
[1] https://gcc.gnu.org/onlinedocs/gcc/Zero-Length.html
Change-Id: If9598a951c6b882432689b677a956c44650c7083
Found-by: gcc (Debian 7.2.0-2) 7.2.0
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21297
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There might be certain requirement in user function where user
might not want to pass any timeout value, in those cases
run_ap_work() should consider infinity as timeout and perform
all APs initialization as per specification.
Set expire_us <= 0 to specify an infinite timeout.
BRANCH=none
BUG=b:74436746
TEST=run_ap_work() is running successfully with 0 expire_us.
Change-Id: Iacd67768c8a120f6a01baaa6817468f6b9a3b764
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25622
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In each stage keep GDT in the code region. This accommodates
platforms, such as glk, that are executing out of CAR. The
gdt is small and loading it is trivial so just do it unconditionally
instead of introducing another Kconfig.
BUG=b:78656686
Change-Id: I01ded6e9b358b23e04d92bef5263bfe8c2a5ec5a
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Now that VBOOT_STARTS_IN_BOOTBLOCK depends on C_ENVIRONMENT_BOOTBLOCK,
remove the complications in assembly_entry.S. There's no platform
utilizing romcc bootblock and needing to handle verified boot after
bootblock as well as not using verified boot. That combination makes
things very complicated. Clean up the complication as it's not a
combination that needs to be supported.
BUG=b:78656686
Change-Id: Ie2960790d60ccb8d5b75dab507fe70a6563b3d34
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25968
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
coreboot on skylake originally did ship with romcc bootblock and
verstage running after it. However, that configuration makes boot
flows very complicated. No platform in the current code base uses
this combination. Make VBOOT_STARTS_IN_BOOTBLOCK depend on
C_ENVIRONMENT_BOOTBLOCK.
BUG=b:78656686
Change-Id: Ia9446f209521f71c91b83d579b9e2d89744292bc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
The tablet event handler method TPET is defined as an extern, then
defined again in skylake, the only platform that supports it. In newer
versions of IASL, this generates an error, as the method is defined in
two places.
Remove the extern and the CondRefOf check. That's not needed if we
only set the EC_ENABLE_TABLET_EVENT define on platforms that have a
TPET handler.
Change-Id: I8bee069fc95637446593dfaaae1254e931421517
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
The _SB.DPTF.TPET ACPI code attached to EC_ENABLE_TABLET_EVENT doesn't
exist in the apollo lake code. Remove it from reef as part of the
cleanup to update to the new version of IASL.
This was in commit 4f803ac28f (mainboards/google/reef: Add support for
tablet mode switch.)
Change-Id: Ic10c418ddc708c1aed87ad4a9861f04d32445116
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25982
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set SPI Fast Read to 100MHz and Dual Read IO mode to speed up
the boot process by over a half second. Also, increase the Normal
Read speed to 33MHz as supported by the W25Q128FW.
BUG=b:70558952
TEST=Run cbmem -t to get boot times.
Change-Id: I616a96526ed90bb4ab0c9c6b78787799faa02633
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The sb_set_readspeed() was touching the wrong register and
the read speed settings are handled by sb_set_spi100(). Nothing
was using the function, so remove it.
Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Some touchscreens need to adhere to certain timings during the power
off sequence as well as during the power on sequence. Adding
reset_off_delay_ms, enable_off_delay_ms, and stop_off_delay_ms to
accommodate these devices.
BUG=b:78311818
BRANCH=None
TEST=./util/abuild/abuild -p none -t google/poppy -x -a
Change-Id: Idb4a5dbe56eee4749d2f2b514e92c28fb2c6078f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/25882
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's pretty well compressible which helps when space is tight.
The code encodes the assumption that the VBT is 8kb or less. Haven't
seen a larger one yet.
BUG=b:77971803,b:78541692
TEST=build, see that vbt.bin is compressed, boot, check log that the
reported VBT size is correct.
Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SPI chip in this board needs a custom OPMENU, otherwise flashrom
fails halfway during the write.
From the default OPMENU, Block Erase (0xd8) has been replaced by AAI
write (0xad) and Fast Read (0x0b) by Write Disable (0x04).
Change-Id: Ie18ee4e32511482dab747c9ffeac60d3994df320
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The X201 coreboot image is working well on the X201i. Besides, the
X201i seems to be almost identical to the X201 except for the CPU.
Change-Id: Iecc84faf78e7de34fb1add63c20904a5a28c5e9b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix regression after commit
7f5efd9 intel/bd82x6x: Use generated ACPI PIRQ
The call to inject generated PIRQ entry was not added when
the static entries as default_irq_route.asl file was removed
from boards using intel/nehalem southbridge.
Change-Id: I8097c1ab729d1eb91a6d547ef13948c1e21eca10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/25965
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matthias Gazzari <mail@qtux.eu>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes in pin usage between yorp and bip
- LTE_OFF_ODL pin moved from GPIO_161 to GPIO_66
- I2S0 interface is not used in bip. It was used in
yorp for DMIC Wake on Voice through Nuvoton EC.
Also fix both bip and yorp pin settings for
LTE_OFF_ODL (Enable LTE and add an internal pull up).
Internal pull up can be removed later when sub-board (which
will have an external pull up for this signal) is available.
BUG=b:77869623
BRANCH=none
TEST=Build coreboot for octopus.
Change-Id: I8907bd63a43c4bc51ca991c3ec7c1cae9e39e2d1
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move x86 specific pci_bus_default_ops into arch/x86 folder.
Fixes compilation on platforms that do neither have MMCONF_SUPPORT
nor NO_MMCONF_SUPPORT (for example: all non-x86) but select PCI.
Change-Id: I0991ab00c9a56b23cd012dd2b8b861f9737a9e9c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fixes a bug in the software_i2c (bitbang) framework where it
would previously not return an error when receiving a NACK on a write
transaction (deviating behavior from our hardware I2C drivers). It also
adds explicit error codes to be returned for the different kinds of
failure conditions so they are more useful for debugging when dumped.
Change-Id: Ie63bf35123d89dcd99a1f9c079d4cae6a33b0b09
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Frequency set to 19.2 MHz
TEST=build
Change-Id: I56e57156df8a74cf629f7ada86cf5a5fcd5ad3c4
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
At the time I ported coreboot to this board, the HDMI port of my board
was broken, so I couldn't test libgfxinit on HDMI.
Change-Id: Ibb8a4ef55bd97fd2d0baacdbc72863c0985d3d76
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/25820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Programming CxDRB should be cumulative as explained in "Intel ® 4
Series Chipset Family datasheet".
This does not seem to have any real impact but better do according to
the documentation and what vendor firmware does.
This also removes some dead code.
Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22911
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This training find the optimal write DQ delay and read DQS delay
settings. It does so on all lanes at the same time, like
vendor (training each lane individually has poor results).
The results are stored in the sysinfo struct and restored on next
boots and S3 resume.
This potentially increases stability as optimal settings are chosen
and is more necessary for DDR3 raminit where the write DQS delays are
leveled/variable due to the flyby topology.
TESTED on Intel DG43GT with (2G + 1G) on each channel, see that the
results are quite close to the safe original ones (that previous
worked fine) and tested with memtest86+.
Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove locking of PCI device 00:00.0 registers (nehalem/finalize.c)
and remove setting the zeroth bit of the MSR_LT_LOCK_MEMORY = 0x2e7 MSR
register (model_2065x/finalize.c) to fix a frozen boot and S3 resume issue
which became apparent with commit d533b16669.
More detailed, either setting the LSB of the 32 bit register at 0x98
of the PCI device 00:00.0 (in the intel_nehalem_finalize_smm function) or
setting the LSB of the the MSR register MSR_LT_LOCK_MEMORY = 0x2e7 (in the
intel_model_2065x_finalize_smm function) indepentenly causes a freeze
during bootup or a complete session loss on resuming from S3 as described
here: https://mail.coreboot.org/pipermail/coreboot/2018-April/086564.html
It seems like Nehalem CPUs do not have a MSR_LT_LOCK_MEMORY register.
Additionally, the "Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile
Processor Series, Datasheet Volume Two" indicates that registers of the
PCI device 00:00.0 cannot be locked manually. Instead, they can only be
locked by TXT, VT-d, CMD.LOCK.MEMCONFIG, ME_SM_LOCK or D_LCK.
Finally, the addresses and sizes of these registers were partially wrong.
Tested on Lenovo X201i with a Core i3 330M (no AES-NI, no VT-d and no TXT
support compared to the Core i5 and Core i7 processors of a X201).
Change-Id: I9d568d5c05807ebf7e131b3e5be8e5445476d61b
Signed-off-by: Matthias Gazzari <mail@qtux.eu>
Reviewed-on: https://review.coreboot.org/25914
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Introduce bootmem custom memory tags and use them instead of reusing
LB_MEM tags.
Use asserts in bootmem_add_range to verify parameters.
Tested with uImage payload on Cavium SoC.
Change-Id: I7be8fa792fc7933ca218ecd43d250d3a9c55caa6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
* Adapt to coreboot coding style.
* Use coreboot's endian conversion functions.
* Fix header and header guards.
* Get rid of unused functions.
* Add Kconfig to build it on ramstage.
* Replace size32 with ALIGN_UP and DIV_ROUND_UP.
* Add NULL pointer checks
* Convert constants to defines
Required for Cavium's BDK and uImage FIT support.
Change-Id: I6e6cd9f78fb402bd54d684097326d26eb78d552a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Required for general devicetree patching and FIT support.
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Ida75d4786eae38d84bfc71bf53573dafca8eda40
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Besides the FSP codepath, Sandy Bridge has two codepaths, one native
and one in the form of a binary. This allows the use of the binary.
This can be useful to find flaws in the native raminit.
The native raminit is still selected by default.
Change-Id: I2d71fb7bc5f7b0976157be146c0e4c39a3ed5602
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
After commit 2188f57a (src/device: Update LTR configuration scheme)
coreboot will hang when reading resources on the ASMedia SATA
controller, although there is already an ASPM config override. So use
the ASPM blacklist driver instead of setting the ASPM override in the
devicetree.
Change-Id: I807d9bd4deef8c1528dff96c7646240ef75e1953
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/25819
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I0b969a5109276d108e6140bad338c74786b967f3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I17675b004023453f137abd387cfacd308d9b98b5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I4b930a191130941c8349861cdd803a5be4219274
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23653
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I4c8acebb4a957a9600de15ea844f620a8909977b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Ibd01659f518b7a2b1aaf334fe5b16cfb936b68b7
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Icec2e5f722c1f15493e5861b47f64698250f5813
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: I585aa48b99f4ef63905cab5d6d1502bfed0e6e42
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Idcb8ff4081f2c45427aabb455a70fae1b46bcfc4
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: Ib3e708a7fa9f0a78dc704a502a2f01ee0fe209ae
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t`has been abandoned in ramstage.
Change-Id: I2cc938958097e416b85f6592cb8a4e645a3746ed
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use of `device_t` has been abandoned in ramstage.
Change-Id: If064a4027265e8fc2ea919d9742a554abf29b8db
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/23667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
CONFIG_ALT_CBFS_LOAD_PAYLOAD has long since been removed.
Clean up the remnants in braswell.
Change-Id: I88483a4c3a74ed0c7defacf872b1564c3ce7f909
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This configures GPP_A23 as a wake source for the trackpad. We also
need to set up GPP_A GPE0_DW0, thus evicting GPP_B. We don't have any
interesting signals in GPP_B, so we won't be missing it.
I don't have hardware with A23 wired up, so i just tested the wake
source using A19 which is essentially identical to A23.
BUG=b:78541883
TEST=verified we can trackpad can wake system from suspend
Change-Id: If800464c8b2319d758b1823850571919f85bdc6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/25850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Function gpio_output() is only setting the pin as an output, when in fact
it should also set the state (high/low) of the pin. Fix the procedure to
set the state of the pin.
BUG=b:78328773
TEST=None
Change-Id: I516192a0782a9bbb40124029f264a2711114c800
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, google_chromeec_pd_get_amode infinitely loops if a TCPC port
is connected to a device with alternate mode(s) and the call is made
for the mode with the index higher than 0 (e.g. Zinger).
Cros EC manages alternative modes entered in an array (amode[]). The
command is designed to accept a query for an particular index and a
particular SVID.
Zinger has a 'Google' mode. It's stored in amode[0]. When AP queries
first time for DisplayPort with index=0, EC says 'no' as expected.
AP sends the next query with index=1 but EC_CMD_PROTO_VERSION (0x00)
is sent instead because cmd_code is cleared by google_chromeec_command.
res.svid is supposed to be 0 when EC hits the last index + 1 but
res.svid is set to 2 by the EC_CMD_PROTO_VERSION handler because
EC_PROTO_VERSION is currently 2. So, the call succeeds and AP goes to
the next index and this repeats forever.
Any USB-C device with non-DisplayPort alternate mode can cause this
hang unless HDMI port is used.
This patch resets all the fields of chromeec_command in each iteration
in case google_chromeec_command changes them.
BUG=b:78630899
BRANCH=none
TEST=Verify Fizz boots without monitors on Zinger. Verify the svid
enumeration happens as expected.
Change-Id: I388ed4bdfac9176d8e690c429e99674ed267004f
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/25878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All ARM architecture boards are supposed to have a TTB region for their
page tables. ARM systems cannot use the data cache without enabling
paging, so it is imperative to do that as soon as possible. They will
also fault on unaligned accesses when not using the cache, which breaks
assumptions in CBFS code.
Unfortunately, we have some old boards in various stages of disrepair in
the tree that don't always follow these sorts of standard conventions.
It's not clear whether they actually boot anymore and if anyone still
has the respective hardware available to maintain them. I cannot really
fix and test them right now, but we should at least create a fake TTB
section for them so that common architecture code may make the correct
assumptions about which regions exist.
Change-Id: I51aa259fbb7a9c0ade72db905b1762c1c721f387
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
New API required by sdm845 DDR init/training protocol
TEST=build & run
Change-Id: I8442442c0588dd6fb5e461b399e48a761f7bbf29
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/25818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This creates a phaser variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:78572180
TEST=None
Change-Id: Ia03e8af91741f1f7aa3a42ac28688b8b6a708932
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/25877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Linux (4.16) assumes that the PIT interrupt is connected to the pin 0 of the
IOAPIC[0] and panics otherwise.
This might be a Linux bug. The MP Specification 1.4 does seem to mandate
sequential ordering for bus entries, but not for the I/O APICs.
Change-Id: Ibf823eb5b3a29e4590cba915069cdfe5f780edcd
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With only one entry for Write Protect gpio in the OIPG package, the sysfs
entry /sys/devices/platform/chromeos_acpi/GPIO.x is created as "GPIO"
instead of "GPIO.x". This was causing crossytem to return error for wpsw_cur.
BUG=b:78009842
Change-Id: Ica60f342420d95d09a45580f2f940443c03601de
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/25892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
scan-build from Clang 4.0.1-3 from Debian Sid/unstable warns about the
issue below.
```
CC ramstage/southbridge/amd/cimx/sb800/lpc.o
src/southbridge/amd/cimx/sb800/lpc.c:102:6: warning: Value stored to 'end' is never read
end = resource_end(res);
^ ~~~~~~~~~~~~~~~~~
1 warning generated.
```
The variable is only used in the commented out print statement. So,
remove the unused variable, and directly use the value directly in the
print statement.
Change-Id: I3f759f6361ffeb07980cb10e17930e11d738a6a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use acpigen method to return _STA instead of hardcoding unreadable
bytecode.
Change-Id: I290fb918675857e8ef798e3ab820bcfbdc6f5bdc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no physical LPC connector on apu3 mainboard. This board
contains only LPC debug test points with not all required pins exposed.
Change-Id: I83de16bb651846340788c6fa52c04b8e09e46a99
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Reviewed-on: https://review.coreboot.org/22630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This variable needs to be in byte so a division by 8 needs to happen.
This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD
decode and timing selection", but was probably not encountered because
such dimms are rather uncommon.
Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22991
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix regression after commit
0cc2ce4 arch/x86: Clean up CONFIG_SMP and MAX_CPUS test
In case PARALLEL_CPU_INIT=y BSP CPU no longer waited for APs to stop
before proceeding to next bootstates or device initialization.
Change-Id: Ie47e7896ed3d57d98a3ce6766e5c37b6dc22523b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/25874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, native VGA initialization takes 90 ms during resume. But, it
is not needed. So, skip it to save that time.
Note, it is assumed that ACPI aware operating systems ship the
appropriate drivers to initialize the graphics device. With Linux, if
the module/driver *i915* is not loaded, then the display will stay
black.
TEST=On Lenovo X60t with Debian and Linux 4.15.11-1~bpo9+1, suspend and
resume system and notice display is correctly initialized by the driver
i915 after resume. Notice the messages below.
```
PCI: 00:02.0 init ...
Skipping native VGA initialization when resuming from ACPI S3.
PCI: 00:02.0 init finished in 56 usecs
PCI: 00:02.1 init ...
```
Change-Id: I6cc9dde94c18671d077132daf648e8ba557e7887
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/25676
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This helps with meeting the line length limit.
Also, join some lines with the one above, as the line length is now met.
Change-Id: If457b3b592211aba1a3218501146b17abb5b799f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change configures a weak internal pull-up on ESPI_IO1 line for
octopus baseboard and variant bip. ESPI_IO1 is used as ALERT# line and
is expected to be open-drain. However, there is no external pull on
this line and so an internal pull-up is required to ensure proper eSPI
communication.
BUG=b:78497502
TEST=Verified that there is no eSPI communication failure between AP
and EC during boot-up and on suspend/resume.
Change-Id: Ic494aa7397b94bfd233ce10da8287660997b3377
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Add support and enalbe cache-as-ram paging for glk to work around
a cache-as-ram corruption issue. glk executes verstage, romstage,
and FSP-M directly out of cache-as-ram (just like apl). However,
the front end on glk is very agressive about pulling cache lines
into L1I for potential execution. When the snoops hit in the L1D
and the cache lines are dirty the processor writes the line back.
However, there is no backing store for the dirty lines to go. As
such when the line is pulled back in the value is all 0xff's,
corrupting cache-as-ram.
To fix the issue one needs to enable paging with NX (no execute)
permissions which prevents the above actions from happening because
the TLB will indicate that shouldn't be fetched into the instruction
cache since data will be marked no execute.
The generated page tables are added to cbfs and only added to the
COREBOOT cbfs as they are only consumed in the early cache-as-ram
stages.
The page tables generated with:
$ go run util/x86/x86_page_tables.go \
--iomap_file=src/soc/intel/apollolake/glk_page_map.txt \
--metadata_base_address=0xfef00000 \
--pdpt_output_c_file=src/soc/intel/apollolake/pdpt.c \
--pt_output_c_file=src/soc/intel/apollolake/pt.c
Merged address space:
00000000d0000000 -- 00000000fef00000 UC NX : 375 big 256 small
00000000fef00000 -- 00000000fef20000 WB NX : 0 big 32 small
00000000fef20000 -- 00000000fefc0000 WB : 0 big 160 small
00000000fefc0000 -- 00000000ff000000 WB NX : 0 big 64 small
00000000ff000000 -- 0000000100000000 WP : 8 big 0 small
Total Pages of page tables: 5
Pages linked using base address of 0xfef00000.
BUG=b:72728953
Change-Id: Icde9cc0bf5079bb5821f4e59eb61e939c13d7062
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.
This is preparation to have GPIO table/code also declare/program SCI/SMI.
BUG=b:72875858
TEST=Build grunt.
Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following things are specific characteristic of mc_apl1 board
variant:
- initialization for the eDP to LVDS converter
- enable decoding address range for COM 3
- legacy IRQ routing for PCI devices
- wait function for old legacy devices
- set coreboot ready LED
Change-Id: I5c853e6caae6cc880ead436f232cabddeee6d09a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25822
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To be selected by mainboard Kconfig if the board hosts an ASMedia chip
that spuriously advertises ASPM features.
Change-Id: I05f9789bc14db56d2ac085f4f14047d80c3aefb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25619
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove VBOOT_VBNV_CMOS from the mainboard. It is selected in the
stoneyridge Kconfig.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I30e517e06ab9d8f7d4a93bf82f12726756c44966
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add RW_NVRAM area to FMAP for VBOOT_VBNV_CMOS_BACKUP_TO_FLASH support.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: Id8c6f54634b94bf6ae3755a827e80d0862a42dd2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RISC-V doesn't set up page tables anymore, since commit b26759d703
("arch/riscv: Don't set up virtual memory").
Change-Id: Id1e759b63fb0bc88ab256994d3849d16814affa0
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The driver relies on I/O space access functions (inb, etc.), which are
only available on x86.
Rather than explicitly disallowing it on ARM, allow it only on x86.
TEST=Configure for RISC-V, and see that "Serial port on SuperIO" is not
available in the "Generic Drivers" menu anymore.
Change-Id: Ib8e8c402264afeba6dc098683c5464af6edb3ba3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This change uses the newly added vboot_can_enable_udc to decide if it
is okay to enable xDCI in vboot developer mode.
BUG=b:78577893
BRANCH=poppy
Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a function that will check the various requirements to
enable USB Device Controller (UDC):
- developer mode enabled
- GBB flag set or VBNV flag set
If VBOOT is not enabled, then default is to allow UDC enabling.
BUG=b:78577893
BRANCH=poppy
Change-Id: Id146ac1065f209865372aeb423f66ae734702954
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25847
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the SPI speed for Normal, Fast, AltIO, and TPM in bootblock.
This setup is needed when moving AGESA out of the bootblock. It sets the
SPI bus speed of the TPM access in verstage.
BUG=b:70558952
TEST=Boot with AGESA moved out of the bootblock.
Change-Id: Ida77d78eb1f290e46b57a46298400ed6c8015e2c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
It was decided to not add the buffers definitions, so the todo message
is obsolete. Replace it with minimum instructions about when a new buffer
will be needed.
It was also noticed a typo in one command. MBOX_BIOS_CMD_C3_DATA_INFO is
about S3 transition, so it should be called MBOX_BIOS_CMD_S3_DATA_INFO.
BUG=b:77940747
TEST=None.
Change-Id: I6143d7e85476061395962b95ad8864ac32a1d4a3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25740
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For broken devices that spuriously advertise ASPM, make it possible to
decide ASPM activation in the device driver.
Change-Id: I491aa32a3ec954be87a474478609f0f3971d0fdf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/25617
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The grunt touchpad interrupt can be used as a wake source. For grunt,
the touchpad interrupt uses GPIO5 which corresponds to GEVENT7.
BUG=b:77602771
TEST=In OS: # cat /proc/acpi/wakeup
=> D015 S3 *enabled i2c:i2c-ELAN0000:00
TEST=powerd_dbus_suspend, touching touchpad (> 1 sec) wakes from S3.
Change-Id: I510642108a1257f6601f18c77cf3107573427f39
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25827
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The grunt EC uses GPIO24 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO24 maps to GEVENT (GPE) 15.
The kahlee EC uses GPIO2 (EC_PCH_WAKE_L) to signal wake-up events to the AP.
On Stoney, GPIO2 maps to GEVENT (GPE) 8.
BUG=b:78461678
TEST=powerd_dbus_suspend, tap any key on keyboard wakes from S3.
TEST=sign in, EC: lidclose, EC: lidopen => system wakes from S3.
Change-Id: Ib1809740837e686992ff70b81933159a5dff7595
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On the kahlee variant, EC_SMI_ODL is connected to GPIO6, which uses
GEVENT 10 (GPE10). Fix this up, and also clean up the EC_*_GPI
definition format a bit to match the format in the baseboard/gpio.h.
BUG=b:78461678
TEST=build coreboot for kahlee
Change-Id: I9445efbc02559c2a7c90f67bcb0154b04b03a1aa
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that an idt is available in every stage utilize it for exception
processing to help catch and debug issues.
BUG=b:72728953
Change-Id: I69e7f938f36f2e522b787e311fd148bb8fd41247
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25764
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that assembly code isn't processing the idt gates there's
no need to ensure each vector entry is the same amount of code.
BUG=b:72728953
Change-Id: I2b248b26b9df36d6543163762c74622f79278961
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig IDT_IN_EVERY_STAGE to optionally specify having
the interrupt handling code available to all stages. In order
to do this the idt setup is moved to a C module. The vecX
entries are made global so that a table of references to all
the interrupt vector entry points can be used to dynamically
initialize the idt. The ramification for ramstage is that
exceptions are initialized later (lib/hardwaremain.c). Not
all stages initialize exceptions when this Kconfig variable
is selected, but bootblock for the C, stages using
assembly_entry.S, and of course ramstage do. Anything left
out just needs a call to exception_init() at the right
location.
BUG=b:72728953
Change-Id: I4146a040e5e43bed7ccc6cb0a7dc2271f1e7b7fa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The FU540 is the first RISC-V SoC with the necessary resources to run
Linux (an external memory interface, MMU, etc).
More information is available on SiFive's website:
https://www.sifive.com/products/hifive-unleashed/
Change-Id: Ic2a3c7b1dfa56b67cc0571969cc9cf67a770ae43
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
CSRs are XLEN bits wide (i.e. the same width as general purpose
registers), so size_t seems a little more correct than int.
This change doesn't affect functionality because MSTATUS_MPRV already
fits in 31 bits.
Change-Id: I003c1b88b4493681dc9b6178ac785be330203ef5
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
smi_sources is a file local array of constants.
Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
When employing PAGING_IN_CACHE_AS_RAM more areas need to be
mapped in at runtime. Therefore, paging_identity_map_addr() is
added to support adding identity mappings. Because there are a
fixed amount of pages in cache-as-ram paging only the existing
paging structures can be used. As such that's a limitation on
what regions and length one can map. Using util/x86/x86_page_tables.go
to generate page tables will always populate all the page directory
pages. Therefore, 2MiB mappings are easy to map in.
BUG=b:72728953
Change-Id: Ibe33aa12972ff678d2e9b80874529380b4ce9fd7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25718
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Siemens will provide further boards based on Apollo Lake. These differ
only slightly. To avoid copying the complete directory of the reference
board we simply create variants that only contain the differences, like
google/reef does.
To further the ability of multiple variant boards to share code provide
a place to land the split-up changes. This patch provides the tooling
by using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing.
The directory layout with a single variant mc_apl1 (which is also the
baseboard) looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/mc_apl1 - code
variants/mc_apl1/include/variant - headers
New boards would then be added under their board name within the
'variants' directory.
No split has been done with providing different logic yet. This is
purely an organizational change.
Change-Id: Ia3c1f45daee3b9690a448b82edbeec552ee05973
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
In some cases it may be useful to be able to bitbang a UART, such as
during early bring-up when a driver for the actual controller isn't
available yet. On some platforms we may even want to use this
permanently, such as on the SDM845 where the hardware UART controller
needs to have firmware loaded and is thus unavailable for most of the
bootblock.
This patch adds some helper code that makes it easy to implement this on
a platform, you just have to pass it a function to control the Tx pin
state and it will do the rest. It relies on the mono_time API and is
thus bound to microsecond timing granularity, but that seems to be
barely good enough for 115200 baud if the bit times are calculated
carefully.
Change-Id: If7dcecc7b8a95ec15f456efd2ec1f1e0dde239b4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/25812
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's going to be necessary to know the i/o hole size as well
the amount of memory configured in the sytsem. Therefore, add
two helper functions:
memory_in_system_in_mib()
iohole_in_mib()
Both return values in units of MiB.
BUG=b:72728953
Change-Id: I481ba517c37f769e76d9e12b3631f5f99b5427a9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25738
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Processors, such as glk, need to have paging enabled while
in cache-as-ram mode because the front end is agressive about
fetching lines into the L1I cache. If the line is dirty and in
the L1D then it writes it back to "memory". However, in this case
there is no backing store so the cache-as-ram data that was written
back transforms to all 0xff's when read back in causing corruption.
In order to mitigate the failure add x86 architecture support for
enabling paging while in cache-as-ram mode. A Kconfig variable,
NUM_CAR_PAGE_TABLE_PAGES, determines the number of pages to carve
out for page tables within the cache-as-ram region. Additionally,
the page directory pointer table is also carved out of cache-as-ram.
Both areas are allocated from the persist-across-stages region
of cache-as-ram so all stages utilizing cache-as-ram don't corrupt
the page tables.
The two paging-related areas are loaded by calling
paging_enable_for_car() with the names of cbfs files to load the
initial paging structures from.
BUG=b:72728953
Change-Id: I7ea6e3e7be94a0ef9fd3205ce848e539bfbdcb6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove Fch.h from being included in
src/vendorcode/amd/pi/00670F00/agesa_headers.h. It is not needed.
BUG=b:69220826
BRANCH=master
TEST=build Gardenia and Grunt systems.
Change-Id: Ifde58421d20c813ae5708b1d9c6ec76433051d33
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's broken for years and nobody noticed (%ei for %esi and stackerr for
.Lhlt). It would also leave CAR not zeroed out.
Change-Id: Ib1ca8e8e71ea8d1bf834c349fd6e2ca81538b6eb
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We need to ensure the cache as ram area is set to all zeroes so that
car_migrated works.
Despite a comment claims the previous value is a test pattern it's
actually not used for any testing. Drop the comment too.
Change-Id: I1c91acbca8a860c2ed9c691d08d18718604682d8
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch sets the NPK device off for octopus.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not
report "PCI: 00:00.2 not found, disabling it".
Change-Id: I3ac01f90cf946b019a6604a38dd1d6782f8d5759
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes our devicetree in sync with the FSP configuration.
Without this we see in boot logs "PCI: 00:00.2 not found,
disabling it". The reason being in FSP NPK device is disabled by
default. We can enable it by enabling the UPD parameter TraceHubEn.
If we enable it in FSP then the logs complain the NPK pcie device
is not seen.
BUG=b:76115112
TEST=Build for Octopus and check that the logs do not report
"PCI: 00:00.2 not found, disabling it".
Change-Id: I8fe3a36dac2eff2225dacb0e6e16500a5750261e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There's no good reason to use the more complicated name.
Change-Id: I515e2df3b87580ddd31d18fe63451a98e92ead61
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25700
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are redundant -- the actual APIC Ids and addresses are in the
devicetree.
Change-Id: I895563dd574a8f4631866ceec91a20cbc3b158e4
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/25800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This UART is used in the SiFive FU540 SoC, and will probably be used in
other SoCs in the future.
Change-Id: I915edf39666b7a5f9550e3b7e743e97fe3cacfd3
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/25768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Found-by: Coverity (CID 1387031: Memory - illegal accesses
(BUFFER_SIZE_WARNING)). Calling strncpy with a maximum size argument of
19 bytes on destination array "dimm->module_part_number" of size 19 bytes
might leave the destination string unterminated. Fix the size parameter.
BUG=b:76202696
TEST=Build and boot kahlee, using special debug code to see the output
strings, which was later removed.
Change-Id: I18fa5e9c73401575441b6810f1db80d11666368c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When GPIO tables were created, there was no study on which pins had to be
programmed ASAP and which could be programmed later. Execute such study and
move all non-critical gpios from reset to late.
BUG=b:76097508
TEST=Build and boot grunt to OS, test OS for lost functionality (WIFI, video
playback, track pad, keyboard).
Change-Id: Icbc9370050d619800026035caaac3e89536a460a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With the increase of dimm->module_part_number size from 19 to 21 (commit
35b273eea3) "include/memory_info.h: Change part number field from 19 bytes
to 21", this code is now advancing outside DDR3 SPD designated space. The
correct size is already defined as LPDDR3_SPD_PART_LEN, use it. Also make
sure to 0 terminate the string.
BUG=b:77943312
TEST=Build cyan.
Change-Id: Iba0ef4149acfc09b7672fce079df06bf1a01dff6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
DDR4 reserves 20 bytes for part number without termination. Therefor
coreboot buffer for part number has to be increased to 21 bytes, to
account termination.
BUG=b:77943312
TEST=Build kahlee.
Change-Id: I57aa8e06d907a1e6b11ce88f612a0d6c14b7c65b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add ENV_CACHE_AS_RAM to indicate to compilation units if cache-as-ram
is employed for that particular stage.
BUG=b:72728953
Change-Id: I06dfa7afe2d967229549090d5aa95455687b0bb9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
In commit d87e4b34 (stage_cache: Add rmodule params in metadata)
the cbmem stage cache was updatd to keep track of the arg from
struct prog in the metadata. However, external stage cache did
not get the same change. Fix that.
BUG=b:72728953
Change-Id: Ifdaaa255cac0f413856410ff61bfb411a9554a31
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Certain platforms need to pass different stack pointer values to
postcar depending on S3 resume or not. Add comments to ease the
reader in understanding the point. If different stack values weren't
needed the program was already cached in stage cache with the correct
value.
Change-Id: I7202c62e6202a14416cb49ad5348740174747c7d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Entry points from assembly to C need to have the stacks aligned
to 16 bytes with the newer compilers. This entry point was
missed. Correct it.
BUG=b:72728953
Change-Id: Idb29daf830c05fd5543c2194690364ce31b6a22c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Currently the idt setup and handling is only in ramstage. In
order to prepare having an exception handler in other stages
move the interrupt vector entry code to its own compilation
unit. vec0 and int_hand need to be global so c_start.S
references will resolve at link time.
BUG=b:72728953
Change-Id: I435b96d987d69fb41ea27a73e2dd634b5d6ee3d9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Current patch fixes problem with validation of ACPI in Linux kernel:
ACPI BIOS Error (bug): A valid RSDP was not found (20180313/tbxfroot-210)
1. function acpi_checksum() returns u8, so seems that is not good idea to
use write_le32().
2. at least RSDP (https://wiki.osdev.org/RSDP#Validating_the_RSDP) has
u8 checksum.
Change-Id: I1fb29ef4e58982aab0c54b1f715c5658d2a663d8
Signed-off-by: Oleksii Kurochko <oleksii.kurochko@gmail.com>
Reviewed-on: https://review.coreboot.org/25753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds keyboard backlight feature for Nami platform
BUG=b:78360907
BRANCH=none
TEST=keyboard backlight works when EC reports correct info.
Change-Id: I3fceb83e155032b6e9f1763c4e2a29e7521269d2
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/25782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove one *l* at the end.
Change-Id: Ife5af64b380dc5d31f22873f1639382d2bf9a5d9
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/25748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add paging_set_default_pat() which sets up the PAT MSR according
to util/x86/x86_page_tables.go. Using page attribute types require
a matching of the PAT values with the page table entries. This function
is just providing the default PAT MSR value to match against the
utility.
BUG=b:72728953
Change-Id: I7ed34a3565647ffc359ff102d3f6a59fbc93cc22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add the following functions for use outside of the paging module:
void paging_enable_pae_cr3(uintptr_t cr3);
void paging_enable_pae(void);
void paging_disable_pae(void);
The functions just enable and/or disable paging along with PAE.
Disassembly shows equivalent output for both versions.
BUG=b:72728953
Change-Id: I9665e7ec4795a5f52889791f73cf98a8f4def827
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
In preparation for bringing in paging early always provide the
paging pae module to all stages. Since we cull unused symbols this
is a no-op. Compilation testing will happen all the time since the module
currently doesn't compile without <arch/cpu.h> include. The current
file is completely guarded with ENV_RAMSTAGE because it's using
cpu_index() which is a ramstage-only construct.
BUG=b:72728953
Change-Id: Ib4310b8206e5247fa220b42203bcd18d522d51ea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25712
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
On a second look broadcom/cygnus and imgtec/pistachio appear to
support full duplex. Therefore, remove the use of spi_xfer_two_vectors().
For mediatek/mt8173 and qualcomm/ipq40xx, the driver is written in such
a way that it does not support full duplex. Remove the use of
spi_xfer_two_vectors() and explicitly error out when a full duplex
transaction is requested.
Change-Id: I8689bc9bb2b27563d25e9f165487d38881c0b059
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Aaron Durbin