The ARM configuration files have been changed that we need more settings to run
Coreboot on qemu-v7.
Also fixed the incorrect Makefile settings that caused armv7 to try building
with armv8 cache.
BRANCH=none
BUG=none
TEST=make menuconfig # select qemu-armv7
make # pass
qemu... # successfully boots to ramstage.
Original-Change-Id: I4040e86ad1ff6e8ebd07cfe387c3f5a0e8941800
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/186080
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@google.com>
(cherry picked from commit f2fab7383ee5352dab2d5f2b8a7d2d321d5944bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibe18a1a87f036df148393f8dfc6a6d92dba4ac5c
Reviewed-on: http://review.coreboot.org/7421
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This really is not critical but we might as well get it right.
Change-Id: Ifec1e8dc35d7f5bb89d9a7a877d82410c83a3288
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/7070
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
As currently many systems would be barely functional without ACPI,
always generate ACPI tables if supported.
Change-Id: I372dbd03101030c904dab153552a1291f3b63518
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4609
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This header has nothing to do with cache-as-ram. Therefore, 'car'
is the wrong term to use. It is about providing a prototype for
*romstage*.
Change-Id: Ibc5bc6f3c38e74d6337c12f246846853ceae4743
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6661
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When passing '-ffreestanding' the 'main' romstage.c may no longer
necessarily be considered the entry point.
From the C specification in 5.1.2.1 Freestanding environment;
"In a freestanding environment (in which C program execution may take
place without any benefit of an operating system), the name and type of
the function called at program startup are implementation-defined."
Clang complains about these being missing as Clang is somewhat more
strict about the spec than GNU/GCC is. An advantage here is that a
different entry-point type-signature shall now be warned about at
compile time.
Change-Id: I467001adabd47958c30c9a15e3248e42ed1151f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5872
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This patch cleans out a lot of unused variables in the
ARM Kconfig files and introduces CONFIG_RAMSTAGE_BASE
which is similar to CONFIG_RAMBASE on x86.
This gets rid of the hard coded assumption that on ARM
coreboot is always executed at the lowest DRAM address.
But in fact, this might not be true because we might want
coreboot to live at the end of RAM, or in SRAM
Change-Id: I03e992645f9eb730e39a521aa21f702959311f74
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/168645
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Tested-by: David Hendrix <dhendrix@chromium.org>
(cherry picked from commit 15b87892eb2d5e27759c49dc6c8c7e626f651d77)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6634
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The few remaining boards without CAR override this with
select ROMCC.
Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6172
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.
Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.
Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
RAMBASE, RAMTOP and XIP_ROM_SIZE are not used with ARCH_ARMV7.
Change-Id: I072ed022e3279ed23716fdf78d0db8952b3fdb32
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5627
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.
With this change it is possible to have other than debug console
on different UART port.
Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.
Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.
Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.
Removes:
CONSOLE_SERIAL_UART
HAVE_UART_IO_MAPPED
HAVE_UART_MEMORY_MAPPED
Renames:
CONSOLE_SERIAL8250 -> DRIVERS_UART_8250IO
CONSOLE_SERIAL8250MEM -> DRIVERS_UART_8250MEM
Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This probably belongs elsewhere, but I haven't found a nice place yet.
Change-Id: I9ca52db33905cf4ee229d7ff44012105915271a8
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Currently this is only a minimal stub to get console on qemu-armv7.
Change-Id: I3f20b7f944bc7d0e5ace9d22198d4c16a3839d2c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5162
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The replacement function confirms CBMEM TOC is wiped clean on power
cycles and resets. It also introduces compatibility interface to ease
up transition to DYNAMIC_CBMEM.
Change-Id: Ic5445c5bff4aff22a43821f3064f2df458b9f250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4668
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Now it boots up to message "Could not find payload".
Change-Id: I07ddca7046492f7e0dec15a8ea00c2870b09ee67
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4754
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Based on info from wiki.
Change-Id: Iebd799abe48550c4df55632b8177d845df7d9a7d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4706
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory
layout, remove it from current configurations.
Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b
Reviewed-on: https://gerrit.chromium.org/gerrit/61853
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4371
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
It's done in bootblock_simple.c just after returning from
the mainboard specific bootblock function.
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Change-Id: I96cab5e406132a9f7dc30d48ff99f524773a1a14
Reviewed-on: https://gerrit.chromium.org/gerrit/58473
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/4257
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Per our discussions with Gerd, qemu will now always do native graphics
on coreboot. The VGA BIOS capability is not needed and will no longer
be supported. Attempts to build without native graphics will result in
an error.
This code builds for both x86 emulation targets. I'm hitting an issue
testing that is unrelated to coreboot; if someone can test, that
would be helpful. Be sure to start qemu with -vga std.
We also add a test for the PCI BAR being zero and return silently if it
is.
Change-Id: I66188f61e1bac7ad93c989cc10f3e0b55140e148
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/4258
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Qemu makes the guest uuid (qemu -uuid $uuid) available
to the guest via fw_cfg. Other smbios fields can be
configured in qemu using the -smbios command line
switch (check the qemu manpage for details).
This patch adds coreboot support for this, so the
values provided by qemu will actually show up in the
smbios table.
Change-Id: Ifd9ae0d02749af4e7070a65eadbd1a9585a8a8e6
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4086
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Starting with release 1.7 qemu provides acpi tables via fw_cfg. Main
advantage is that new (virtual) hardware which needs acpi support
JustWorks[tm] without having to patch & update the firmware (seabios,
coreboot, ...) accordingly.
So if we find acpi tables in fw_cfg try loading them, otherwise fallback
to the builtin acpi tables.
Change-Id: I792232829b870ff6ed8414a3007e0af17f6c4223
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4040
Tested-by: build bot (Jenkins)
qemu 1.7+ provides a fw_cfg file named "etc/e820" with e820-like entries
for reservations and ram regions. Use it for ram detection if present,
otherwise fallback to the traditional cmos method.
Change-Id: Icac6c99d2a053e59dfdd28e48d1ceb3d56a61bdc
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4030
Tested-by: build bot (Jenkins)
Qemu can provide files using the firmware config interface.
This is used to pass config options, virtual machine config
info and option roms into the guest.
This patch adds support for reading the file index and loading
files from qemu.
Change-Id: I57d4a734527c4117239f355121cf1fb8a390ab0d
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/4029
Tested-by: build bot (Jenkins)
It is expected this will always be a casted get_top_of_ram() call
on x86, no reason to do that under chipset.
Change-Id: I3a49abe13ca44bf4ca1e26d1b3baf954bc5a29b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3972
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This reverts commit de1fe7f655.
While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.
Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.
This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.
Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Assume EARLY_CBMEM_INIT=y everywhere and remove option from Kconfig.
If romstage does not make the cbmem_initialize() call, features like
COLLECT_TIMESTAMPS and early CBMEM_CONSOLE will execute during
romstage, but that data will get lost as no CAR migration is
executed.
Change-Id: I5615645ed0f5fd78fbc372cf5c3da71a3134dd85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3917
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Without this coreboot may (depends on the amount of memory) place the
pci bars below 0xb0000000, then the linux kernel goes move them around
so they are inside the window declared in the acpi tables.
This breaks vesafb as the vga framebuffer gets moved after vgabios
initialization. It's also not exactly nice to expect the OS fix our
mess ;)
Change-Id: If6b50ea863958eea71b567ccb7a06c6a28076111
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3927
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.
Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Drop unused and commented out variable, and fix a comment while at it.
Change-Id: I1bd7d10aca949c8579433ea1c91264fd816a3fb4
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/3873
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The slightly hackish ioapic ressource reservation is needed for i440fx
emulation only, for q35 the ich9 southbridge driver handles this just
fine.
[ Side note: The i440fx chipset emulated by qemu is pimped up with alot
of stuff which never existed on real hardware, which leads
to tweaks like this one. ]
Change-Id: I06bf54cbc247ccf17aa9063fb7dee9def323c605
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3850
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
QEMU has a bunch of non-standard virtual devices on various I/O ports.
Allocate resources for them so the coreboot resource management knows
those ports are used.
Change-Id: I51a85967cf2dcd634b0c883210bb52c0c34c8283
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3851
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change all PCI configuration accesses to MMIO in qemu-q35
emulation
To enable MMIO style access, add (move) explicit PCI IO config write
in the bootblock. As there is no northbridge/x/x/bootblock.c
file, a mainboard/x/x/bootblock.c file is added for this purpose.
Change-Id: I979efb3d9b2f359a9ccbd1b4f6c05f83bab43007
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3599
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.
Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It might be that you want an early console in romstage before RAM is up, but
you can't or don't want to support the console all the way back in the
bootblock. By making the console in those two different environments
configurable seperately that becomes possible.
On the 5250 console output as early as the bootblock works, but on the 5420 it
only starts working in the ROM stage after clocks have been initialized.
Change-Id: I68ae3fcb4d828fa8a328a30001c23c81a4423bb8
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3671
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Not all ARM systems need "BL1", and the layout of BL* and bootblock may be
different (ex, Exynos 5250 may use a new BL1 with variable length checksum
header).
To support that better, define the real base address (and ROM offset) of boot
block, and then we can post-processing ROM image file by filling data / checksum
and any other information.
Change-Id: I0e3105e52500b6b457371ad33a9aa546acf28928
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3664
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When starting the Exynos5250 port, a lot of unneeded u-boot code
was imported. This is an attempt to get rid of a lot of unneeded
code before the port is used as a basis for further ARM ports.
There is a lot more that can be done, including cleaning up the
5250's Kconfig file.
Change-Id: I2d88676c436eea4b21bcb62f40018af9fabb3016
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3642
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
... and drop the wrapper on ARMv7
Change-Id: If3ffe953cee9e61d4dcbb38f4e5e2ca74b628ccc
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3639
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In ram stage, all code flow should be tied to the resource allocator.
Stuff that has to happen before everything else goes into the mainboard
enable function in mainboard.c. This patch empties the main() wrapper
around hardwaremain.c, allowing to get rid of this special case in the
ARM port.
Change-Id: Ide91a23f1043b64acf64471f180a2297f0f40d97
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3638
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In commit Rudolf Marek discovered, that it is not uniformly written. As
»ASL names are not case-sensitive and will be converted to upper case.« [2]
this change does not have any functional change.
The following command was used to create this patch.
$ git grep -l 'package()' src/mainboard | xargs sed -i 's,package(),Package(),'
[1] http://review.coreboot.org/#/c/3318/
[2] http://www.acpi.info/spec40a.htm
(18.2.1 ASL Names)
Change-Id: I1784dbc50936a1ef9d4376209a3c324ef1fb85cf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3516
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit was tested on qemu with and without CONFIG_DYNAMIC_CBMEM
by running cmbmem -c once booted. The qemu command that was used was:
qemu-system-i386 -bios ./build/coreboot.rom -serial stdio -hda ../virt/parabola.img
Note that using CONFIG_RELOCATABLE_RAMSTAGE make it fails like that:
Loading image.
CBFS: Decompressing stage fallback/coreboot_ram @ 0x3ffbefc0 (184400 bytes)
Loading module at 3ffbf000 with entry 3ffbf000. filesize: 0x18db8 memsize: 0x2c050
Processing 1703 relocs with adjust value of 0x3ffbe000
FATAL: Essential component is missing.
However without CONFIG_RELOCATABLE_RAMSTAGE set it boots fine.
Change-Id: I633a8c3832eee4e8bed244940fdc370b98dd26f0
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3504
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Add support for the new q35 chipset emulation
added in qemu 1.4.
Change-Id: Iabfaa1310dc7b54c9d224635addebdfafe1fbfaf
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3430
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
So the pci allocation code knows where memory is and doesn't
try map pci devices there. We also don't have to check for
overlaps between pci hole and memory then.
Change-Id: I5eaea0e4d21210719685860fa1f16ca7b2137cde
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3491
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Prepare tree for adding q35 support:
Move emulation/qemu-x86 to emulation/qemu-i440fx.
Rename some stuff to include 'i440fx'.
Change-Id: Ib8c58175c5734cfcda1b22404ef52c09d38f0462
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3429
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
First copy over from SeaBIOS git repo, then adapt for coreboot:
Disable cpu/pci hotplug bits. Disable dynamic pci window.
Both depend on stuff in the SSDT tables created by SeaBIOS.
Bits are left in, but deactivated via #if 0, so it's easier
to see the differences when diffing the coreboot tables with
the SeaBIOS tables.
Adapt dsdt DefinitionBlock.
Enable acpi table generation in acpi_tables.c.
With this patch linux boots successfully with ACPI enabled.
It's not bug-free though. Missing cpu detection leads to
funky messages like this one:
weird, boot CPU (#0) not listed by the BIOS.
and SMP most likely wouldn't work either.
Change-Id: Ic3803a6f1ef6d54c11cc4ca3844d3032a374ae6b
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3342
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Add boot cpu to the device tree. Figure the number of CPUs installed
(using the qemu firmware config interface) and add cpu devices for them,
so they show up in all generated BIOS tables correctly. This gets SMP
going.
Change-Id: I0e99f98942d8ca90150b27fc13c1c7e926a1a644
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Needed to make 'register "gpo" = ...' work.
While being at it add comments saying which device is which.
Change-Id: I911d5e4a7b6c7abf4ad73e863ab201e9e55ee0d4
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3346
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
qemu has a special device to pass configuration information
from qemu to the firmware. This patch adds initial support
the interface, namely some infrastructure, detection code and
a function to query the number of CPUs.
Change-Id: I43ff5f4fbf12334a91422aa38f514a82a1d5219e
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Do the setup for all PCI slots, not only the third.
Also remove the bogus message, as slot 3 may carry
any device, not only NICs.
This makes IRQ setup simliar to SeaBIOS.
SeaBIOS assignments (with patch for logging added,
and a bunch of pci devices for testing purposes):
PCI IRQ [piix]: bdf=00:01.3 pin=1 line=10
PCI IRQ [piix]: bdf=00:03.0 pin=1 line=11
PCI IRQ [piix]: bdf=00:04.0 pin=1 line=11
PCI IRQ [piix]: bdf=00:05.0 pin=1 line=10
PCI IRQ [piix]: bdf=00:06.0 pin=1 line=10
PCI IRQ [piix]: bdf=00:1d.0 pin=1 line=10
PCI IRQ [piix]: bdf=00:1d.1 pin=2 line=10
PCI IRQ [piix]: bdf=00:1d.2 pin=3 line=11
PCI IRQ [piix]: bdf=00:1d.7 pin=4 line=11
Coreboot assignments without this patch:
Assigning IRQ 11 to 0:3.0
Coreboot assignments with this patch:
Assigning IRQ 10 to 0:1.3
Assigning IRQ 11 to 0:3.0
Assigning IRQ 11 to 0:4.0
Assigning IRQ 10 to 0:5.0
Assigning IRQ 10 to 0:6.0
Assigning IRQ 10 to 0:1d.0
Assigning IRQ 10 to 0:1d.1
Assigning IRQ 11 to 0:1d.2
Assigning IRQ 11 to 0:1d.7
Change-Id: Ie96be39185f2f1cbde3c9fc50e29faff59c28493
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3334
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Extra care for the qemu vga should not be needed any more.
Since release 0.12 qemu loads the vgabios into the PCI ROM
bar, so everything works exactly like it does on real hardware.
Change-Id: I4b9bf1244cad437cbe5168600aeee52031456033
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3333
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since this parameter is not used anymore, drop it from
all calls to copy_and_run()
Change-Id: Ifba25aff4b448c1511e26313fe35007335aa7f7a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3213
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
it has been unused since 9 years or so, hence drop it.
Change-Id: I0706feb7b3f2ada8ecb92176a94f6a8df53eaaa1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3212
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This allows to drop some special cases in romstage.c
Change-Id: I53fdfcd1bb6ec21a5280afa07a40e3f0cba11c5d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2551
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's not used, and not needed.
Change-Id: Ifca92f3606ac58fc26e09676488c3add5d84ae79
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2548
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.
Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Similar to the discussion on the coreboot list [1]
Am Freitag, den 22.02.2013, 02:17 +0100 schrieb Peter Stuge:
[…]
> Function names should try to be descriptive. "enable_dev" is not very
> descriptive. I like "mainboard_enable" because it makes output such
> as
>
> printk("%s: foo", __func__);
>
> useful.
rename the function for the northbridge to `northbridge_enable`.
[1] http://www.coreboot.org/pipermail/coreboot/2013-February/074549.html
Change-Id: I262311ec511e394550330214621b8c37780c1d4e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To reduce the differences between these file name the enabling
device function in the directory `src/mainboard` uniformly
`mainboard_enable` [1].
Thanks to the awesome help of gnomon and BlastHardcheese in the
IRC channel #sed on <irc.freenode.net>. gnomon came up with the
following command to do the actual work.
$ cd src/mainboard
$ for f in */*/mainboard.c ; \
> do src="$(awk '/\.enable_dev = /{v=$NF; sub(/,$/,"",v); print v}' "$f")" ; \
> [[ -z $src ]] && continue ; \
> printf '%s\n' "g/${src}/s/${src}\([,(]\)/mainboard_enable\1/p" w | ed -s "$f" ; \
> done
`src/mainboard/digitallogic/msm586seg/mainboard.c` and
`src/mainboard/technologic/ts5300/mainboard.c` had to be adapted
manually as no comma was used separating the struct members.
And with the following statement, gnomon is even more likable!
My pleasure entirely. Good luck with coreboot; I'm a big fan of the project.
[1] http://www.coreboot.org/pipermail/coreboot/2013-February/074548.html
Change-Id: Ife9cd0c2d9cc1ed14afc6d40063450553f06a6c6
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2493
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If CONFIG_CONSOLE_SERIAL is set, and we can call the standard function
and get a non-zero uart address, then we create an lb table entry.
The code was mostly right, just needed a tweak.
Change-Id: I5b36c7b4e580a23319b7ba92cc8ad61592b1757a
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/2466
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
To simplify testing ARM implementation, we need a QEMU configuration for
ARM. The qemu-armv7 provides serial output, CBFS simulation, and full
boot path (bootblock, romstage, ramstage) to verify the boot loader
functionality.
To run with QEMU:
export QEMU_AUDIO_DRV=none
qemu-system-arm -M vexpress-a9 -m 1024M -nographic -kernel build/coreboot.rom
Verified to boot until ramstage loaded successfully by QEMU v1.0.50.
Change-Id: I1f23ffaf408199811a0756236821c7e0f2a85004
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2354
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Except for one board, the flags can be derived from CONFIG_MMX
and CONFIG_SSE.
Change-Id: I64a11135ee7ce8676f3422b2377069a3fa78e24d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2336
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch switches the Qemu target to use (pseudo) Cache As RAM
and enables some ACPI code. This allows to use the CBMEM console
and timestamp code with coreboot in Qemu. Right now, the ACPI code
is commented out because leaving it in breaks IDE.
Change-Id: Ie20f3ecc194004f354ae3437b9cf9175382cadf8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2113
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
intel_irq_routing_table is a local structure that should not be used
globally, because it might not be there on all mainboards.
Instead, the API has to be corrected to allow passing a PIRQ table in
where needed.
Change-Id: Icf08928b67727a366639b648bf6aac8e1a87e765
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Compose the name from Kconfig strings instead.
As the field is for debug print use only, a minor change in the output
should do no harm. The strings no longer include word "Mainboard".
Change-Id: Ifd24f408271eb5a5d1a08a317512ef00cb537ee2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1635
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Commit 188e3c2ff0 dropped mainboard
out of the static device tree. This left dev_root->chip_ops unset,
and mainboard_ops.enable_dev() was no longer called.
Change-Id: I6d447c8049a66041b8bb36ec9aac3e7e0d20a99b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1374
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
mainboard_config never worked right, at least not since we've had sconfig.
Hence, drop mainboard/<vendor>/<device>/chip.h and fix up the mainboards that
tried to use it anyways.
Change-Id: I7cd403ea188d8a9fd4c1ad15479fa88e02ab8e83
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1359
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There is no reason for this to be a top level directory.
Some stuff from lib/ should also be moved to drivers/
Change-Id: I3c2d2e127f7215eadead029cfc7442c22b26814a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/939
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
We used several names for that same value, and hardcoded the value
at some more places.
They're all LOCAL_APIC_ADDR now (except for lapic specific code
that still uses LAPIC_DEFAULT_BASE).
Change-Id: I1d4be73b1984f22b7e84681edfadf0588a7589b6
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/676
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
See discussion at
http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html
config->com1, devicetree.cb cleanup and init_uart8250() removal
will follow once this patch is comitted
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Updated to drop com1, com2.... from config structure and devicetree.cb
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, remove some less useful comments, some dead code / unused functions.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6108 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The following functions are moved to devices/device_util.c:
- ram_resource()
- tolm_test()
- find_pci_tolm()
There are only two tolm_test() / find_pci_tolm() which differ from the
defaults, one of them can easily be eliminated in a follow-up patch,
maybe even both, but for now keep it simple and only eliminate the majority.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
0xc0000-0xfffff, have coreboot qemu support enable the memory range at
startup.
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfigs from within the choice/endchoice block. This makes it possible to
define user visible board specific options. Moved all vendor names and PCI
ids to the vendors' Kconfigs. Now all options in each file depend on the same
symbol, so replaced all "depends on"s with a single "if". Sorted boards
(sort -d), cleaned whitespace.
This patch also introduces a dummy option BOARD_SPECIFIC_OPTIONS, which is
always "y" and never used. It it simply needed to have something to attach
the boards' "select" statements to.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5754 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
there is no free list.
Converting resource arrays to lists reduced the size of each device
struct from 1092 to 228 bytes.
Converting link arrays to lists reduced the size of each device struct
from 228 to 68 bytes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it centrally in console/console.h instead.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tell the BIOS how much RAM the virtual machine has available.
This patch fixes the detection.
Signed-off-by: Valdimir Serbinenko <phcoder@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is folded into mainboard/emulation/qemu-x86. Adapt code.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5376 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
makes include/console/console.h and console/console.c usable both in
__PRE_RAM__ and coreboot_ram stages.
While debugging this, I removed an indirection from the e7520 ram init code
(same as we did on a couple of other chipsets, removes some register pressure
from romcc)
Also, drop remainders of CONFIG_USE_INIT (except the one odd piece of dead code
in cache_as_ram.inc)
Then some ap_romstage.c fixes, at least the nvidia/l1_2pvv compiled for me with
CONFIG_AP_CODE_IN_CAR set in Kconfig which it did not before.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(since it's not assembly code, this was a dirty hack anyways)
Also run
awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines
mv $FILE.nonewlines $FILE
on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c
cut some holes into the source.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's not a real northbridge, so I just move it into the mainboard directory for
now (until we maybe have a qemu-q35 image some day?)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
better readability.
Also remove failover.c files in mainboards, as they're
not used anymore (and useless, too)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c like r5255 did for failover/fallback/normal
mainboards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- introduce BOARD_HAS_HARD_RESET and use it if a board provides
hard_reset in $(MAINBOARDDIR)/reset.c, instead of some chipset component
- move a couple of rules out of the mainboards' Makefiles into
src/arch/i386/Makefile.inc:
initobj-y += crt0.o
obj-y += mainboard.o
obj-$(CONFIG_GENERATE_MP_TABLE) += mptable.o
obj-$(CONFIG_GENERATE_PIRQ_TABLE) += irq_tables.o
obj-$(CONFIG_BOARD_HAS_HARD_RESET) += reset.o
- remove Makefile.incs that are empty (or comment-only) after these
changes, incl. Makefile.romccboard.inc (and references to it)
- Make include not fail if Makefile.inc doesn't exist.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5168 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
PS/2 keyboard API.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5152 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, delete duplicate romstage file in qemu-x86
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/i386/Makefile.inc
For that to work, I had to:
- Add a CONFIG_ROMCC variable
- Set that variable on all ROMCC boards
- conditionally choose romcc or gcc rule based on that variable
- remove those two rules from all the boards' Makefiles
- switch a couple of boards to HAVE_OPTION_TABLE, as they actually have.
Also remove the duplication of rules with the sole difference of if
they depend on option_table.h or not.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cache_as_ram_auto.c and auto.c are both called "romstage.c" now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5092 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of the equivalent copy in src/cpu/emulation/qemu-x86/northbridge.c.
Also, delete the copy.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- via/epia-cn is a romcc board, not a CAR board. (Thanks Kevin, for the report)
- Make emulation/qemu-x86, dell/s1850, via/epia-cn use Makefile.romccboard.inc
- New flag: BIG_BOOTBLOCK, which is always the inverse of tinybootblock
Suitable for Makefile.inc rules (foo-$(CONFIG_BIG_BOOTBLOCK) += ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Don't implicitly add __PRE_RAM__ in romcc.
Fixes intel/xe7501devkit
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Introduce the tiny bootblock infrastructure and use it on QEmu.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove all remaining warnings from qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
selected in sockets, and they aren't used yet.
Add a couple of variables to src/Kconfig for lack of a better place so that
their selects work.
Add select statements according to newconfig for some variables that were
defined but never selected in mainboard configs.
Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with the respective board.
Of course, the user can still override the size in menuconfig.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to build, but by default all the tables that are available are built.
Make PIRQ table build for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild-tested for the boards that are touched.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on QEMU.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and PIRQ tables were actually wrong, I cannot imagine they ever
worked properly.
- Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
hard-coded numbers.
- Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.
- Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
in the irq_tables.c file.
- Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
boards where they were set to 0 (in order to be overridden in
the respective targets/.../Config.lb).
This is mainly done to aid Patrick's scripts for kconfig conversion.
- Fix a number of comments in irq_tables.c files.
- Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
- tyan/s1846
- asus/a8v-e_se
- asus/m2v-mx_se
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
complete set of variables now, though they might still have
the wrong values.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.
Various calculations in {no,}failovercalculation.lb are adapted
accordingly.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)
After this commit, there is no way to build an image that is not using
CBFS anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
per discussion on the mailing list.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also enable building individual boards with kbuildall for
debugging.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.
Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).
Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.
Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.
Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.
Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.
Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.
Index: src/pc80/serial.c
make uart_init non-static.
Index: src/pc80/Config.lb
add initobject
Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
Index: src/arch/i386/init/car.S
generic i386 car code from v3.
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.
Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.
Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.
This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.
Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
as it's done everywhere else
- change the default config of abuild to not
provide ROM_IMAGE_SIZE values for the images
in a CBFS configuration
- change abuild's crosscompile autodetection to
not try to use "i386-elf-i386-elf-gcc" (which
is bogus)
Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS
The changes in util/abuild/abuild are trivial and
abuild tested.
As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested, incl. optionrom-in-cbfs for kontron, and compressed payloads
for both.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This also has the config tool changes in v2/util.
Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(trivial)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
working. Given all the limitations of PIRQ routing we keep it simple
and just set the IRQ directly. Most BIOSes are doing setup this way anyways,
since there are so many errors in PIRQ tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the
%04x.
- users pass in vendor and device id.
- users pass in a dest. If the dest is 0, the address of the ROM image in
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even
in the uncompressed case).
move qemu over to always using ROMFS
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested under abuild, causes no trouble.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
directories and use the global (v3) one in util/x86emu instead. It also fixes
the breakage introduced by 4000
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
mainboard_$VENDOR_$BOARD_config to mainboard_config.
Ron's part:
The config change that makes the naming change not break every build.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
lib/debug.c and use that one.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
targets/*/*/Makefile
targets/*/*/normal/Makefile
targets/*/*/fallback/Makefile
to use a common copy of romcc, and to leave this compiler untouched by
'make clean' in targets/*/*/fallback/ and targets/*/*/normal/ .
'make clean' in targets/*/*/ will clean romcc.
Thanks to Mats for the initial idea and implementation of a tool to do
this. This patch has almost the same behaviour as the original tool
without having to run the tool each time.
Tested for abuild-friendliness.
The patch saves ~10-12 seconds for every target using romcc. For a full
abuild run, this is ~20% time saved.
For the first 38 abuild targets, total build time is down to 13m24s
instead of 16m22s on my machine.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Mats Erik Andersson <mats.andersson@gisladisker.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
since it is still our most wide-spread codebase.
The patch is pretty trivial, and nobody except Torsten even looked at
it in a week, so....
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2880 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same format for all CHIP_NAME() entries in LinuxBIOS (Closes#20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and (hopefully) the correct canonical name of the vendor and board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to fail later than before.
dos2unix'ed the xe7501devkit files, that might have caused some problems
before.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2127 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. x86_setup_mtrr take address bit.
2. generic ht, pcix, pcie beidge...
3. scan bus and reset_bus
4. ht read ctrl to decide if the ht chain
is ready
5. Intel e7520 and e7525 support
6. new ich5r support
7. intel sb 6300 support.
yhlu patch
1. split x86_setup_mtrrs to fixed and var
2. if (resource->flags & IORESOURCE_FIXED ) return; in device.c pick_largest_resource
3. in_conherent.c K8_SCAN_PCI_BUS
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1982 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Creator: Yinghai Lu <yhlu@tyan.com>
write_pirq_routing_table for x86
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1979 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Move pci_set_method out of hardwaremain.c
- Re-add debugging name field but only include the CONFIG_CHIP_NAME is
enabled. All instances are now wrapped in CHIP_NAME
- Many minor cleanups so most ports build.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- mem.h and sizeram.h and all includes killed because the are no longer needed.
- linuxbios_table.c updated to directly look at the device tree for occupied memory areas.
- first very incomplete stab a converting the ppc code to work with the dynamic device tree
- Ignore resources before we have read them from devices, (if the device is disabled ignore it's resources).
- First stab at Pentium-M support
- add part/init_timer.h making init_timer conditional until there is a better way of handling it.
- Converted all of the x86 sizeram to northbridge set_resources functions.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Rename chip_config chip_operations throughout the tree
- Fix Config.lb on most of the Opteron Ports
- Fix the amd 8000 chipset support for setting the subsystem vendor and device ids
- Add detection of devices that are on the motherboard (i.e. In Config.lb)
- Baby step in getting the resource limit handling correct, Ignore fixed resources
- Only call enable_childrens_resources on devices we know will have children
For some busses like i2c it is non-sense and we don't want it.
- Set the resource limits for pnp devices resources.
- Improve the resource size detection for pnp devices.
- Added a configuration register to amd8111_ide.c so we can enable/disable individual ide channels
- Added a header file to hold the prototype of isa_dma_init
- Fixed most of the superio chips so the should work now, the via superio pci device is the exception.
- The code compiles and runs so it is time for me to go to bed.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
