The microcode for the Rangeley chip is supplied as .h files in the
Rangeley FSP POSTGOLD4 package.
When the rangeley microcode gets put into the blobs directory, this
can be reverted and the binary file put into the makefile.
Change-Id: I30e7436f26a247bc9431f249becfa5fe8c581be7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12335
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The eagleheights platform had 3 warnings:
The SIO device needs an _ADR object to specify the address in addition
to the operating region.
Not all the paths through the _OSC method returned a value. According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.
dsdt.aml 341: Device(SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 140: Method (_OSC, 4)
Warning 3115 - ^ Not all control paths return a value (_OSC)
dsdt.aml 140: Method (_OSC, 4)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _OSC)
- Remove Kconfig default disabling IASL warnings as errors.
Change-Id: Iab52f19b96468e142b06430d99ba1d9f367d126e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12522
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=chromeos-2015.07
BUG=none
TEST=verified on Oak rev3
Change-Id: Ied991f13b73e70b91cc267222f351b588df8df66
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4bc08ce28611d8b940642483c09614d2b8205c1f
Original-Change-Id: If78e154ff7f553f65aa44d370820cc8c7f829c96
Original-Signed-off-by: Biao Huang <biao.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297224
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12609
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The E38xx legacy uart fires IRQ4, not IRQ3.
PCI based IRQ A is switched from IRQ4 to IRQ3,
to get a working IRQ for the legacy uart.
Change-Id: Ibc8e824c92bf1b9a92594ddc5d8a06726c9f1744
Signed-off-by: Michael Tasche <michael.tasche@esd.eu>
Reviewed-on: https://review.coreboot.org/12622
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
- Move initialization of entry to later in main.
- Make boot_mode an unsigned char - no need to use int.
- Remove unnecessary variable filenames.
- Only get and try to boot fallback once.
Change-Id: I823092c60dd8c2de0a36ec7fdbba3e68f6b7567a
Test: compiled.
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12574
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The proper return value to signal an error from cbfs_prog_stage_load()
is -1, not 0.
Change-Id: Ie53b0359c7c036e3f809d1f941dab53f090b84ab
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This patch force AGESA to use basic SPI read mode.
Without it board hangs during spi configure if W25Q32 chip is used.
Change-Id: I3e17cd21702626be5061d2fc14adc0c22f167efb
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/12580
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of the SEABIOS_MALLOC_UPPERMEMORY option, use a saved SeaBIOS
.config file to do the same thing.
Change-Id: I29110a382b7770329ef938876426e571fbbbb339
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12569
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
BRANCH=none
BUG=none
TEST=Oak build pass
Change-Id: Ic2fd9b2ec0592d1f7195d72c60dab15961de0a9e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d0b00a779b87b0b625cc2bccd8f7470b79e6410
Original-Change-Id: Id9f17d64e9e30946817b86ec8cdfe67ea3dbc798
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292675
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
update dptf TSR1 & TSR2 critial points from 70 to 75
TSR1 & TSR2 are reach 68 degree that is close to 70 degree afer SVPT
test, change the point will avoid to trigger critial in our factory
run in test
BRANCH=none
BUG=none
TEST=build and boot chell DUT
Change-Id: Ie5b8b24d82e929a7bd254967b70b61fda2c8bd0a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf29fee19edf425010cc76af95b7a8e73a3d82bb
Original-Change-Id: Idb9dd77432cfd246c1c612e52c6f945352e265ca
Original-Signed-off-by: Wisley Chen <Wisley.Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313967
Original-Commit-Ready: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Chen Wisley <wisley.chen@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/12604
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
L2C will be released after DRAM is initialized. Move PRERAM_CBFS_CACHE
from SRAM_L2C to ensure that it can be switched correctly.
BRANCH=none
BUG=chrome-os-partner47952
TEST=none
Change-Id: I255a0116148777d384dda43682365a5e2375cb5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 19fcc170e57da514aee9e22289619729ddc2f792
Original-Change-Id: If3d9c1ef05dee0a10ee9151b63b8fd92cc9def51
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313888
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12602
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most devices do not use SPI before they initialize CBMEM. This change
initializes spi_flash in the CBMEM_INIT_HOOK to initialize the postram
cbfs cache so it is not overwritten when boot_device_init is called
later.
BUG=chromium:210230
BRANCH=none
TEST=confirm that the first cbfs access can occur before RAM initialized
and after on panther and jerry.
Change-Id: If3b6efc04082190e81c3773c0d3ce116bb12421f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ab242786a16eba7fb423694f6b266e27d7660ec
Original-Change-Id: I5f884b473e51e6813fdd726bba06b56baf3841b0
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/314311
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12601
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds GPIO mappings for PCH_BUZZER, AUDIO_DB_ID,
AUDIO_IRQ and BOOT_BEEP.
BUG=chrome-os-partner:47513
BRANCH=none
TEST=Built for kunimitsu but not verified on Fab 4.
Change-Id: I0172df3aa2a5c4bfc24422aa0bfb7e5f677d37c9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ba66bef6d402a1040f0f13bc828de400bc6371b7
Original-Change-Id: I1f2ed8fc283883a523a77e07de14ed90057b719b
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311806
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12600
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Disable the kepler device to save power and enable S0ix testing.
It has been disabled in the ME image and was not working anyway..
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Change-Id: I6640c7a09d418ba4b4de6f16138c124436dd8758
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6490769a32539cb6ef429717f021519c152a4a54
Original-Change-Id: If6e384dd2218c6a110747a489329a59fa6433c02
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313827
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12599
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
- Disable kepler device, it is removed and was not used on proto anyway.
- Enable GPP_D22 as GPO to control I2S2 buffer for bit-bang PDM.
- Disable HS400, this is breaking some devices on proto boards and
is being disabled to reduce risk for EVT build.
- Change Type-C USB2 port drive strength.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell proto
Change-Id: Icf31f08302c89b2e66735f7036df914c0a0b9e8c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d00abc12efa69a99e6b0272228f52fb29e6b9180
Original-Change-Id: I63bda0b06c7523df9af9aed9b82280133b01d010
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313825
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12598
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add the audio controller device to ACPI and define the _DSM handler
to return the address of the NHLT table, if it has been set in NVS.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I8dc186a8bb79407b69ef32fb224a7c0f85c05bc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6b73fba375f83f175d0b73e5e70a058a6c259e0d
Original-Change-Id: Ia9bedbae198e53fe415adc086a44b8b29b7f611d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313824
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12597
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This code is doing nothing and is not needed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados
Change-Id: I910d443f09a94de1ee0de03cda0577b8847b2de8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac09fdd7673e5fceb8bfaf1076a8a91e54fc31af
Original-Change-Id: Id989c82853d5a5d5b750def073d34c39816a48d5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313823
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12596
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add post codes for the various FSP phases and use them as appropriate
in FSP 1.0 and 1.1 implementations.
This will make it more consistent to debug FSP hangs and resets.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on glados and chell
Change-Id: I32f8dde80a0c6c117fe0fa48cdfe2f9a83b9dbdf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b616ff3c9d8b6d05c8bfe7f456f5c189e523547
Original-Change-Id: I081745dcc45b3e9e066ade2227e675801d6f669a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313822
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12595
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Adding print for full fsp revision which includes:
0:7 - Build number
8:15 - Revision
16:23 - Minor version
24:31 - Major version
BRANCH=NONE
BUG=chrome-os-partner:46050
TEST=Built for kunimitsu and tested fsp revision is printed properly.
Change-Id: If2739e7cccd97e4b39da503a9d61222cde03bc95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c49be46f8d2085a620abac74126de5c3b634e649
Original-Change-Id: I2223cce22fb3d39faa37902d415d5fdbe321add6
Original-Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310173
Original-Commit-Ready: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Tested-by: dhaval v sharma <dhaval.v.sharma@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12594
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update Memory ID for Proto board
Update detection of single/dual channel memory to use SPD Index (Memory ID)
Remove boardid.h as it is no longer needed
BUG=None
BRANCH=None
TEST=Build and Boot Lars (Proto)
Change-Id: I100b0fec4bf555c261e30140109cb0f36576130c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 24a4fddf4f1a4441fca8783cfa451e220ff986d8
Original-Change-Id: I636e881cb3fb9a0056edea2bc34a861a59b91c8f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313903
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12593
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updated Micron SPD data to correct values
BUG=none
BRANCH=none
TEST=Tested on FAB 4 with Micron Dimm
CQ-DEPEND=CL:312546
Change-Id: Iffe2917f083e4de7944c7f249cbf55bd199f6282
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 00234d81df38139312145c89cbf38d8ac3af5735
Original-Change-Id: Ifcc85cd1aae61e02b820cb25733dfb0680410107
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313003
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12592
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Changed index 3 to be an exception of the default Rcomp Value
BUG=None
BRANCH=None
TEST=Tested on FAB 4 SKU 1
Change-Id: I154c254835c4f6995183840cc241feeb9a448cdb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f08eba3cf623b5869a7bb03fb3b6ba084cdd1622
Original-Change-Id: I0fbcff2c3526c4ed7cf90088ca23b43774cb9f8f
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Freddy Paul <freddy.paul@intel.com>
Reviewed-on: https://review.coreboot.org/12591
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Updated Memory IDs and SKU IDs for FAB 4
Updated detection of single/dual channel memory to use SPD Index (Memory ID)
Added spd files for new dimms
Removed boardid.h as it is no longer needed
BUG=None
BRANCH=None
TEST=Tested on FAB4 SKU1 and SKU3
Change-Id: I60403c0e636ea28797d94cff9431af921631323e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ce39dc3b0b9448635f878ce8c1aea5b4743594c4
Original-Change-Id: I870b3dfa2c4f358defb9263e759de477bb32e620
Original-Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312546
Original-Commit-Ready: Freddy Paul <freddy.paul@intel.com>
Original-Tested-by: Freddy Paul <freddy.paul@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/12590
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently the CBFS mmap cannot be accessed at the beginning of romstage
because it waits until DRAM is initialized. This change first loads CBFS
into SRAM and then switches to using DRAM as the backing once it is
initialized.
BUG=chromium:210230
BRANCH=none
TEST=confirm that the cbfs can be access at the beginning and end of
romstage on different boards.
Change-Id: I9fdaef392349c27ba1c19d4cd07e8ee0ac92dddc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccaaba266386c7d5cc62de63bdca81a0cc7c4d83
Original-Change-Id: Idabfab99765b52069755e1d1aa61bbee39501796
Original-Signed-off-by: Mary Ruthven <mruthven@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312577
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12586
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We need mmu interfaces in these two stages for,
1. bootblock: to support mmu initialization in bootblock
2. romstage: to be able to add dram range to mmu table
BRANCH=none
BUG=none
TEST=build pass
Change-Id: I56dea5f958a48b875579f546ba17a5dd6eaf159c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cf72736bda2233f8e0bdd7a8ca3245f1d941ee86
Original-Change-Id: I1e27c0a0a878f7bc0ff8712bee640ec3fd8dbb8b
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292665
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12585
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The right thing to do is to hide them behind PLATFORM_USES_FSP1_1.
The only things that should depend on HAVE_FSP_BIN is the code
that actually adds the file to CBFS, and the path to the file in Kconfig.
Removing the HAVE_FSP_BIN check requires some default values
for two Kconfig variables.
Change-Id: I9b6c3ed0cdfb0e02421d7b98c488a66e39add947
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
verstage, romstage, and payload can be added through infrastructure now.
Change-Id: Ib9e612ae35fb8c0230175f5b8bca1b129f366f4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12549
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Not all the paths through the _OSC method returned a value. According
to the ACPI spec (5.0 & 6.0), bit 2 needs to be set for an unrecognized
GUID.
Fixes warnings for both platforms:
dsdt.aml 1143: Method(_OSC,4)
Warning 3115 - ^ Not all control paths return a value (_OSC)
dsdt.aml 1143: Method(_OSC,4)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _OSC)
Change-Id: Ibaf27c5244b1242b4fc1de474c371f54f930dcb6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12530
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We currently race in SMM init on Atom 230 (and potentially
other CPUs). At least on the 230, this leads to a hang on
RSM, likely because both hyperthreads mess around with
SMBASE and other SMM state variables in parallel without
coordination. The same behaviour occurs with Atom D5xx.
Change it so first APs are spun up and sent to sleep, then
BSP initializes SMM, then every CPU, one after another.
Only do this when SERIALIZE_SMM_INITIALIZATION is set.
Set the flag for Atom CPUs.
Change-Id: I1ae864e37546298ea222e81349c27cf774ed251f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/6311
Tested-by: build bot (Jenkins)
Tested-by: BSI firmware lab <coreboot-labor@bsi.bund.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Does native ram init for Intel Atom D5xx 8086:a000 northbridge
Tested on Intel D510MO mainboard, board boots linux kernel
- Works fully with both dimms populated (2x2GB), memtest passes 100%
- Almost boots with only one dimm in one of the slots
(suspect bad memory map with one dimm?)
- Reads garbage with only one dimm in other slot
Change-Id: Ibd22be2a959045e0a83aae2a3a0e877013f80711
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Existence of requested PCI device was not checked when enabling
IDE mode on the SP5100. Fix incorrect PCI device ID and check
for device existence before attempting setup.
Change-Id: I726c355571b5c67c9a13995be2352601c03ab1e4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12572
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Decision Feedback Equalization (DFE) is a form of dynamic
link training used to lower the overall error rate within
the coherent fabric. Enable it on all capable HT links.
Change-Id: I5e719984ddd723f9e375ff1a9d4fa1ef042cf3eb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12072
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The existing code did not properly detect various link attributes
on Family 10h/15h processors. With the addition of new HT3- and
IOMMU-specific code, proper detection has become critical to avoid
system deadlocks.
Fix and streamline link attribute detection.
Change-Id: If63dd97f070df4aab25a1e1a34df4b1112fff4b1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The existing code re-used the Family 10h XCS buffer setup on
Family 15h CPUs, which set incorrect values leading to random
system lockups.
Use the Family 15h XCS buffer setup shown in the BKDG.
Change-Id: Ie4bc8b3ea6b110bc507beda025de53d828118f55
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Minor change to be more explicit about the binary state
of the iolink detect variable.
Change-Id: Ifd8f5f1ab28588d100e9e4b1fb0ec2525ad2f552
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12069
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The secondary bus number set code incorrectly overwrote the link
buffer settings in F0x[F4,D4,B4,94]. Constrain the secondary
bus number set to the appropriate bits of the registers.
Change-Id: If70825449f298aa66f7f8b76dbd7367455a6deb1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12068
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Family 15h DRAM initialization did not set up the various
tristate enable codes in the MCT.
Add Family 15h tristate enable setup. This fixes multiple
DIMMs on a single channel.
Change-Id: I0278656e98461882d0a64519dfde54a6cf28ab0f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12060
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The Kconfig symbol CONFIG_HT3_SUPPORT is not implemented.
This mirrors commit c5163ed8 (AMD binaryPI: Drop HT3_SUPPORT)
Change-Id: I2682d3b620e2cee613c7421622a8c79db5ba3a86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12556
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Instead of having to remember to strip the quotes everywhere so that
string comparisons (of which there are a few) match up, do it right at
the beginning.
Fixes building the image with a .config where CONFIG_CBFS_PREFIX
contains quotes.
Change-Id: I4d63341cd9f0bc5e313883ef7b5ca6486190c124
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12578
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The symbol BAYTRAIL_SMM was never valid (there's no config statment
initializing the symbol), but it was being selected and used
in the code.
Now that SMM is supported in fsp_baytrail, the code it was trying
to switch can be removed, and just set up for SMM.
Change-Id: I0fd4865a951734e728500e7baf593ff7eb556f73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12553
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
There is no need to continue testing a DCT configuration after
data errors have already been detected; this just wastes time
during boot.
Change-Id: I979e27c32a3e0b101590fba0de3d7a25d6fc44d2
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This adds a new mainboard: Little Plains for Intel's atom c2000
It was based on Mohon Peak board with some minor changes
This board is not available as standalone product
It is a managment board for
Intel Ethernet Multi-host Controller FM10000 Series
The FSP package is available from Intel: https://www.intel.com/fsp
Change-Id: I28127a858106ed35d26e235f0c6393c20ed14350
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: https://review.coreboot.org/12503
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The CPU <--> CPU HT wiring on this board has only been validated
to 2.6GHz. While higher frequencies appear to function initially,
and in fact function when only one CPU package is installed, dual
CPU package systems will lock up after around 6 - 12 hours of uptime
due to presumed HT link errors at the higher (>= 2.8GHz) HT clocks.
If applications are not being used that stress the coherent fabric,
then the uptime before hang may be much longer. Users attempting
to overclock the HT links are advised to "burn in test" the HT links
by running memtester locked to a node with no local memory installed.
Change-Id: I8fae90c67aa0e8b103e9b8906dea50d1e92ea5a9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12064
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The BKDG recommends the use of an antiphase window detection
algorithm to ensure that the DQS data eye is properly centered.
TEST: Booted both with DIMMs known to move the data eye into the
prior clock phase and DIMMs known to keep the data eye in the
current clock phase.
Change-Id: I1d85fddd45197ca82dcaa46fe863e64589712d1f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12059
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
Reviewed-by: Martin Roth <martinroth@google.com>
As far as I can tell the Kconfig symbol DRIVERS_I2C_IDREG never actually
existed in the coreboot codebase. I didn't see anything that it might
have been a typo of.
Change-Id: Ib17de670e38e07ab4a4745143c42fa85da1754e1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12563
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
The odd rank of each DIMM could experience data corruption due to
incorrect DQS training. Fix the DQS training algorithm by executing
the relevant portions of the training algorithm on the odd ranks.
Change-Id: Ibc51f5052d5189e45b3d9aa98ca8febbfe13f178
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12058
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Also fix incorrect Trfc[0-3] value on Family 15h.
Change-Id: Iafc233984ae1d44fe6a1cb5b109d36397cbd991a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Hiding them requires #if CONFIG_HAVE_SMI_HANDLER instead of
if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER))
Change-Id: Ib874cd98e195ad7437d05be1696004b29bf97a66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12565
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The silicon in control of CC6 appears to contain minor bugs
and / or deviations from the BKDG; through trial and error
it was found that these issues can be worked around by reserving
the entire possible CC6 save region, regardless of currently
installed node count.
Change-Id: If31140651f25f9c524a824b2da552ce3690eae18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The missing brackets caused other registers, including the IO APIC
enable bit (EAN in OIC) to be overwritten. Bug introduced by
bde6d309 (x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer)
Change-Id: I1d5aa2af6d74405a1a125af6221ac0e635a6b693
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/12525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Add an empty Operating Region for the empty _REG method
- Move Named objects out of _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes these items:
dsdt.aml 1449: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1458: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I801a84468097687c91d6ee3f44cec06243355fac
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12531
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Change leading spaces to tabs.
Change-Id: Ief138f5f68198578ba9dddb8fbdabbd9a0185a21
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12546
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes IASL Warning and remark:
dsdt.aml 1451: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1460: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I4aa59468a89c4013146ab34004476a0968c60707
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12521
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Fixes early fault problem on Fam0Fh introduced in
Change I8e01a4ab68b463efe02c27f589e0b4b719532eb5,
commit 991f18475c.
Change-Id: Id215d2822b78917939c28f7a922a94e02e5d15bf
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: https://review.coreboot.org/12528
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably, the ATPX would not need a return value if Arg0 is anything
other than 0, so just return a zero.
- Serialize ATPX method to make IASL happy. This means that it can
only be used by one thread at a time.
Fixes these issues:
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 2581: Method (ATPX, 2, NotSerialized) {
Warning 3115 - ^ Not all control paths return a value (ATPX)
Change-Id: I14aeab0cebe4596e06a17cffc36cc01b953d7191
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12518
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Touchpad and Touchscreen _CRS methods do not return an interrupt
value if the I2c busses that the devices are on are not in PCI mode.
Previously they didn't return any value if they weren't in PCI mode.
This patch has them return an empty resource template.
Fixes these warnings:
dsdt.aml 2813: Method (_CRS)
Warning 3115 - ^ Not all control paths return a value (_CRS)
dsdt.aml 2813: Method (_CRS)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _CRS)
dsdt.aml 2832: Method (_CRS)
Warning 3115 - ^ Not all control paths return a value (_CRS)
dsdt.aml 2832: Method (_CRS)
Warning 3107 - ^ Reserved method must return a value
(Buffer required for _CRS)
Change-Id: I02a29e56a513ec34a98534fb4a8d51df3b70a522
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Affects these mainboards:
- lenovo/g505s
- google/parrot
- hp/pavilion_m6_1035dx
Fixes IASL notice for this specific instance:
dsdt.aml 1952: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
Change-Id: Id297cdea35d43f51887f798a9983629343c2313a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12513
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
Fixes IASL Warning:
dsdt.aml 1362: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Fixes IASL remark:
dsdt.aml 1353: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
Change-Id: Iff01613a6e3238469c1fcb8d74f5e98d18420aaf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12515
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fixes these remarks:
Object is not referenced (Name is within method [_CRS])
The ACPI compiler is trying to be helpful in letting us know
that we're not using various fields in the MCRS ResourceTemplate
when we define it inside of the _CRS method. Since we're not
intending to use those objects in the method, it shouldn't be an
issue, but the warning is annoying and can mask real issues.
Moving the creation of the MCRS object to outside of the CRS
method and referencing it from there solves this problem.
Change-Id: I54ab3ad9ed148fdd24e8615d83bc8ae668d1dbff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12514
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If any path in a method returns a value, IASL expects that all paths
within that method will return a value.
Presumably the MKHP method wouldn't get called unless there were a
pending event, but if no event is found, return a zero.
Fixes IASL warning:
dsdt.aml 1785: Method (MHKP, 0, NotSerialized)
Warning 3115 - ^ Not all control paths return a value (MHKP)
This was the only IASL warning in most lenovo mainboards.
Change-Id: Id93dcc4a74bd4c18b78f1dde821e7ba0f3444da3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12517
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The SIO device needs to provide an _ADR object with the IO
address as well as the address in the OperationRegion.
ACPI provides two different Resource Descriptor Macros to describe the
I/O areas required for a device. The FixedIO macro is only valid for
10-bit IO addresses. Use the IO macro instead.
Thank you to recent IASL that allows for addition in the ASL file. :)
Fixes these warnings:
dsdt.aml 2276: Device (SIO) {
Warning 3141 - ^ Missing dependency
(Device object requires a _HID or _ADR in same scope)
dsdt.aml 2390: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
dsdt.aml 2394: FixedIO (0xa00, 0x34)
Warning 3060 - ^ Maximum 10-bit ISA address (0x3FF)
Lumpy now compiles its ASL tables with no warnings. Re-enable
Warnings as errors.
Change-Id: Id26e234eadaa3b966e8f769cb9f9fb7ea64fc9e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12520
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
FSP 1.0 has a fixed-size temporary cache size and address and the entire
cache is migrated in the FSP FspInitEntry() function.
Previous code expected the symbol _car_data_start to be the same as
CONFIG_DCACHE_RAM_BASE and _car_data_end to be the same as
_preram_cbmem_console.
FSP 1.0 is the only one that migrates _preram_cbmem_console.
Others leave that where it is and extract the early console data in
cbmemc_reinit(). Special handling is needed to handle that.
Commit dd6fa93d broke both assumptions and so broke the timestamp table
and console.
The fix is to use CONFIG_DCACHE_RAM_BASE when calculating the offset and
to use _preram_cbmem_console instead of _car_data_end for the console
check.
Change-Id: I6db109269b3537f7cb1300357c483ff2a745ffa7
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Add an empty Operating Region for the empty _REG method
- Serialize _CRS Method
- Remove Kconfig default disabling IASL warnings as errors
dsdt.aml 1445: Method (_CRS, 0)
Remark 2120 - ^ Control Method should be made Serialized
(due to creation of named objects within)
dsdt.aml 1454: Method (_REG, 2)
Warning 3079 - ^ _REG has no corresponding Operation Region
Change-Id: I2b64609c929af62c2b699762206e5baf58fbdb8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12523
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If the timestamp table gets corrupted (separate issue), the
timestamp_sync_cache_to_cbmem() function may add a large number of bogus
timestamp entries.
This causes a flood of "ERROR: Timestamp table full". With logs going
to a serial console, this renders the system essentially unbootable.
There really isn't a need to log that more than once, so log it when the
last slot in the timestamp table is filled.
Change-Id: I05d131183afceca31f4dac91c5edc95cfb1e443f
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12506
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Drop the last remnant of vanished CONFIG_MARK_GRAPHICS_MEM_WRCOMB.
Could not build test google/cyan and intel/strago due to lack of UEFI
headers, OMG.
Change-Id: I0b9eac5c040d24bab2b85e9b63042b6aaa9879d9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The function delay in uart8250mem.c is not enough for hudson. I guess
there are some problems in lapic_timer(). I uploaded a patch to gerrit
to show the way to enable UART feature.
http://review.coreboot.org/#/c/12343/4
Currently the HUDSON_UART is unchecked by default. Select HUDSON_UART to
enable this feature.
The UART is test at BIOS stage.
Since it is not a standart UART device, the windows internal UART driver
doesnt support it. I guess we need a driver to use it on windows.
Change-Id: I4cec833cc2ff8069c82886837f7cbd4483ff11bb
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11749
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The coherent fabric on all Family 10h/15h devices supports
isochronous mode, which is required for IOMMU operation.
Add initial support for isochronous operation.
Change-Id: Idd7c9b94a65f856b0059e1d45f8719d9475771b6
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12042
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of having to have an ifeq() all across the code base,
use $(target-objcopy). And correct target-objcopy to a value
that objcopy actually understands.
Change-Id: Id5dea6420bee02a044dc488b5086d109e806d605
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/11090
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Based on i945. Tested on Intel D510MO mainboard,
board boots to UART console with this code.
Change-Id: I1d92a1aa6d6d767bda8379807dc26b50b9de75c9
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/10073
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
It works as an ICH7 on Intel D510MO mainboard
Change-Id: Ib8c76c001dffee8f93e3d6aa3156d4413b2e842a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/12431
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Certain workloads may evict too many lines of other cores from the
L3 cache if configured as one monolithic shared cache region.
Forcibly partition L3 cache to improve performance.
Change-Id: Ie4e28dd886aaa1c586b0919c5fe87ef1696f47e9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12036
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The existing code generated an invalid NUMA table
that was rejected by Linux, leading to poor resource
allocation. This was due to system MMIO resources
being inserted into the table when the table should
only contain DRAM resources.
Do not include system MMIO resources (i.e. resources
with an index less than 0x10) in the NUMA table.
Change-Id: I99c200382b52a99687daf266a84873d9ae2df025
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12035
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
fsp-based platforms have this ID, so give it a name.
Change-Id: Idce4dbb60b7b3581e18046e66183a7c91b17abd7
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12485
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There were several symbols that were inside the 'if HAVE_FSP_BIN' that
don't really depend on having the FSP binary. In theory, we should be
able to build a coreboot rom and add the FSP binary later. This doesn't
always work in practice, but this is a step in that direction.
This also fixes a Kconfig warning for Rangeley.
Change-Id: I327d8fe5231d7de25f2a74b8a193deb47e4c5ee1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12461
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We've actually got more warnings now than when I first tested IASL
warnings as errors. Because of this, I'm adding it with the option
to have it disabled, in hopes that things won't get any worse as we
work on fixing the IASL warnings that are currently in the codebase.
- Enable IASL warnings as errors
- Disable warnings as errors in mainboards that currently have warnings.
- Print a really obnoxious message on those platforms when they build.
***** WARNING: IASL warnings as errors is disabled! *****
***** Please fix the ASL for this platform. *****
Change-Id: If0da0ac709bd8c0e8e2dbd3a498fe6ecb5500a81
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/10663
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
coreboot's binary policy forbids to store include files required to build
the host binaries in the blobs directory. Hence remove the infrastructure
to do so.
Change-Id: I66d57f84cbc392bbfc1f951d13424742d2cff978
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
util.h uses ENV_* and hence needs to have rules.h
This is required for successful compilation of strago.
Change-Id: I0df35e90e2010aac43ef0a4d900f20c842d3bcb5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12495
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Stability issues have arisen on multiple Family 15h systems
when configuration restoration is enabled. In all cases these
stability issues resolved by allowing the RAM to go through a
full training cycle.
Change-Id: I017e0dd5120110124d5b5d5276befef6f7740614
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12034
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set default values for the hex and int kconfig symbols so they don't
come up as undefined.
Change-Id: Ib51272f35baa32fe5f3dc369c7f554c77bc2add1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12499
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set default values for the hex and int kconfig symbols so they don't
come up as undefined.
Change-Id: If104cbf7d84719a63fb80aa955efa8baa3953d09
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12498
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add help and a comment about the serial IO port selection to give the
user better feedback when a port index is selected.
Change-Id: I4c1614be51aee0286308fbc5c24554e218120bf7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12487
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
hexdump currently rounds up length to a multiple of 16.
So, hexdump(ptr, 12) prints 16 hex digits, including 4 garbage bytes.
That isn't desirable and is easy to fix.
Change-Id: I86415fa9bc6cdc84b111e5e1968e39f570f294d9
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The E3800 with ordering code FH8065301487717 is stepping D0, value 0x11.
Add that so the debug log shows 'D0' instead of '??'.
Also, add the C0 stepping decode to fsp_baytrail.
Change-Id: Ibec764fcf5d3f448e38831786a071f5ab6066d67
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Looking at the coreboot console logs there are sometimes trailing
whitespaces in the output, for example, if writing `Done` was not
possible.
Adapt the code, that spaces are only added when needed.
Change-Id: Ia0af493ab62b6fab24e8a2629cf5fd67329e0af7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/12357
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Put dependecies on CHROMEOS's selection of the Kconfig symbols
TPM_INIT_FAILURE_IS_FATAL and SKIP_TPM_STARTUP_ON_NORMAL_BOOT to match
the dependencies on those symbols where they are defined in
src/drivers/pc80/tpm/Kconfig
The file that uses these only gets built in if CONFIG_LPC_TPM is
selected selected.
The warnings were:
warning: (CHROMEOS) selects TPM_INIT_FAILURE_IS_FATAL which has unmet
direct dependencies (PC80_SYSTEM && LPC_TPM)
warning: (CHROMEOS) selects SKIP_TPM_STARTUP_ON_NORMAL_BOOT which has
unmet direct dependencies (PC80_SYSTEM && LPC_TPM)
Change-Id: I7af00c79050bf511758bf29e3d57f6ff34d2a296
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12497
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Certain older Opteron processors use a higher (+1.2V) northbridge
voltage. The existing code assumed the use of +1.1V northbridge
voltages and threw an alert when the older Opterons were installed.
Update the permissible NB voltage range to include both the 1.1V
and 1.2V Opteron processors.
Change-Id: I35c90f37d180f59c53d0d2bf3ff0eaf985b26da3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The BKDG is not correct regarding HT Freq write ordering;
indicate this in a comment to avoid confusion.
Change-Id: I37db191c144c81aba5d4a1e6291db5669a35a31a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12030
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The revision detection code for AMD Family 10h/15h was modified
to use a 64-bit value instead of 32-bit in order to accomodate
additional processor revisions. The FIDVID code was not updated
at that point, leading to incorrect revision use during FIDVID.
Change-Id: I7a881a94d62ed455415f9dfc887fd698ac919429
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12026
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Never defined by the server.
Change-Id: If22727cf3953c2931d107146fb99b5997f8a13d5
Original-Reviewed-by: Eric Anholt <eric@anholt.net>
Original-Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ide861733d721a21b77862076bf7ad70c7ee6a472
Original-Reviewed-by: Adam Jackson <ajax@redhat.com>
Original-Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12492
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All modern Opteron processors support the HT probe filter,
which helps to increase coherent fabric performance by
reducing the number of HT transactions per cache probe.
AMD recommends that the probe filter be enabled on all
systems with more than two nodes, and it does not hurt
to enable it on systems with 2 nodes.
Change-Id: I00a27a828260be8685ae622cfa5a4995add95a8e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12021
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Since this code is not currently being built by coreboot, it
failed compilation.
Change-Id: Ib8a0e1ebc76b7dca3dd785b09398b73abad46366
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/12466
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move the #ifdef chain to set the stage name to rules.h.
Change-Id: I577ddf2de4ef249a1a4ce627bb55608731a9f5ed
Signed-off-by: Ben Gardner <gardner.ben@gmail.com>
Reviewed-on: http://review.coreboot.org/12479
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This makes the same changes to the LPDDR3 configuration that
were made for Samsung modules:
- Enable ODT function
- Change DS to 40 from 34.3
BUG=chrome-os-partner:47416
BRANCH=firmware-veyron-6588.B
TEST=Boot on mickey elpida board
Change-Id: If8c729188803dd854dbbe80539fb228636b5eb9f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b3eb8bc31b9727b67a6b53b4370315010d9d6379
Original-Change-Id: I2d54d3087ecd3536469866f30e4eb2d8b1acd5c1
Original-Signed-off-by: jiazi Yang <Tomato_Yang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311153
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311855
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12484
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch implements Memory Margin Analysis feature in coreboot.
Few things to note
(1) the feature is enabled by setting CONFIG_MMA=y in the config file
(2) coreboot reads mma_test_metadata.bin from cbfs during romstage and
gets the name of MMA test name and test config name. Then coreboot finds
these files in CBFS.
If found, coreboot passes location and size of these files to FSP via
UPD params. Sets MrcFastBoot to 0 so that MRC happens and then MMA test
would be executed during memory init.
(3) FSP passes MMA results data in HOB and coreboot saves it in cbmem
(4) when system boots to OS after test is executed cbmem tool is used
to grab the MMA results data.
BRANCH=none
BUG=chrome-os-partner:43731
TEST=Build and Boot kunimitsu (FAB3) and executed MMA tests
Not tested on Glados
CQ-DEPEND=CL:299476,CL:299475,CL:299474,CL:299473,CL:299509,CL:299508,CL:299507,CL:*230478,CL:*230479
Change-Id: I0b4524abcf57db4d2440a06a79b5a0f4b60fa0ea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4aba9b728c263b9d5da5746ede3807927c9cc2a7
Original-Change-Id: Ie2728154b49eac8695f707127334b12e345398dc
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/299476
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: http://review.coreboot.org/12481
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are no longer needed.
Test: Booted minnowmax.
Change-Id: Ie77040f3506464c614760bd4d30280c8113373bd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12468
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The Bolton FCH needs different firmware files than the Hudson FCH.
A small patch to vendorcode is probably needed to make the XHCI controller work.
XHCI_DEVID in pci_devs.h is probably wrong for Hudson.
Change-Id: Ib81c0881979edcde717217dc89d8af415520d7e5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/9623
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing code did not set the northbridge throttle
values on Family 15h, leading to sporadic and random
deadlocks in the crossbar per AMD notes.
Properly set the northbridge throttle values on Family 15h.
Change-Id: I6304b63708c65fedb9c2d46b8c862b7f0adf1102
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12025
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Clear the precomputed checksums in hwinfo as they
will be updated in manufacturing process.
Change-Id: I952ca8f1ca32831c4b296de633c0d58da111ccba
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/12475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is the initial version of README.
AMD provides stable Bettong code in github. Add the link and bug fixed
list to README.
Change-Id: Ie8b761096fd1850afb9363ebb761aa4992b47643
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11737
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
1. Use write_pci_int_table to write registers 0xC00/0xC01.
2. Add GPIO, I2C and UART interrupt according
"BKDG for AMD Family 15h Models 60h-6Fh Processors",
50742 Rev 3.01 - July 17, 2015
3. The interrupt valudes are moved from bettong/mptable.c.
All devices work in Windows 10.
Change-Id: Iad13bc02c84a5dfc7c24356436ac560f593304d7
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/11746
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
These platforms needed to be adjusted to fix various Kconfig warnings.
Both platforms needed MAINBOARD_HAS_NATIVE_VGA_INIT because they're setting
MAINBOARD_DO_NATIVE_VGA_INIT.
veyron_emile needed a few symbols that depend on CHROMEOS to be moved
into a new config CHROMEOS section. This matches the other CHROMEOS
platforms.
veyron_danger needed to select MAINBOARD_HAS_CHROMEOS before the
CHROMEOS symbol was set.
Change-Id: I8c7f594ba572a02513a68095c16314006fb4e379
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12462
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
EC_SOFTWARE_SYNC depends on CHROMEOS, so move it into the CHROMEOS section.
This fixes the kconfig warning:
warning: (CHROMEOS && BOARD_SPECIFIC_OPTIONS ...) selects
EC_SOFTWARE_SYNC which has unmet direct dependencies
(MAINBOARD_HAS_CHROMEOS && CHROMEOS && VBOOT_VERIFY_FIRMWARE)
Change-Id: I459f48fd18c7568c4584df7d4aefa69dec3e4907
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12460
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Found while doing code review.
Use a function to toggle IO reset signal.
Change-Id: I4cb0885ed9be763fbc4069e4d015a36a7183c823
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11916
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are few drawbacks reading VPD from SPI flash in user land, including
"lack of firmware level authority" and "slow reading speed".
Since for many platforms we are already reading VPD in firmware (for
example MAC and serial number), caching the VPD data in CBMEM should
will speed up and simplify user land VPD processing without adding
performance cost.
A new CBMEM ID is added: CBMEM_ID_VPD, referring to a structure containing
raw Google VPD 2.0 structure and can be found by the new LB_TAG_VPD in
Coreboot tables.
BRANCH=smaug
BUG=chrome-os-partner:39945
TEST=emerge-smaug coreboot chromeos-bootimage # and boots successfully.
[pg: lots of changes to make it work with what happened in upstream
since 2013]
Change-Id: If8629ac002d52abed7b480d3d06298665613edbf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 117a9e88912860a22d250ff0e53a7d40237ddd45
Original-Change-Id: Ic79f424a6e3edfb6c5d168b9661d61a56fab295f
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/285031
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12453
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The EDID parsing code continued to update _some_ fields of the output
edid but not others if "did_detailed_timing" was already set. It also
then went on to print out this halfway mix of modes each time, despite
the fact that it didn't really update everything.
Let's fix that. We'll reduce code changes by using a temporary copy of
data in detailed_block() and then we'll copy it back if we decide we
should update.
BRANCH=none
BUG=chrome-os-partner:46998
TEST=No more bogus printouts
Change-Id: Idbfa233e0997244c22ef21c892c4473a91621821
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4d69999cdd7ce3cd2c9332ab3f22ea8eb4b6f2e9
Original-Change-Id: Ia72cac7fda2772f26477e43237678fa30feca584
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309541
Original-Reviewed-on: https://chromium-review.googlesource.com/309609
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12444
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The hardcoded clock value for 640x480 was 25.175 MHz. That's a valid
clock to use, but is quite hard to make a non-jittery clock from PLLs.
It's much easier to make 25.200 MHz, so let's do that.
The difference between the two modes is 59.9 Hz vs. 60 Hz and it seems
better to make a non-jittery 60 Hz rather than a very jittery 59.9 Hz.
BRANCH=none
BUG=chrome-os-partner:46256
TEST=Insignia monitor works, so do others
Change-Id: I8aa124d04a90f5dcf9cfa923ed3b693fbb4a06d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e32ce13462101dc60cfed60b6948b7597e93525a
Original-Change-Id: Ia9804afe8011a915e4bec306e863d34ad7e27be5
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309540
Original-Reviewed-by: Stphane Marchesin <marcheu@chromium.org>
Original-(cherry picked from commit 7f32c9f460991e5e3b947117d6ae4080e630a532)
Original-Reviewed-on: https://chromium-review.googlesource.com/309576
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12443
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The set to say that a standard timing was supported was not properly in
the "if" test. That meant that even when standard timings weren't
supported, we thought that they were. That had the side effect of never
using the detailed mode.
BRANCH=none
BUG=chrome-os-partner:46998
TEST=Adafruit panel works now
Change-Id: Ide3ed6c5682840f808d854755dac58e9057e6bda
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c99d3ee8d163fc6be207c5a7df2a7aecd7af7849
Original-Change-Id: Ib67735219fd28516857d9b63f1ba156573f1bea3
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309521
Original-(cherry picked from commit 4e4c2816e2239299bc02e3a57fb18056db62b56c)
Original-Reviewed-on: https://chromium-review.googlesource.com/309552
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12442
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The detailed_cvt_descriptor() function takes a parameter "out" for no
good reason. Remove it.
BRANCH=none
BUG=chrome-os-partner:46998
TEST=Build and boot
Change-Id: I1042dba9ddf2b4b543bd07615013088be5055950
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c3474c9b1f9fb73f44d64d3a0592f92339da2df
Original-Change-Id: I4d695a6dba6606d2132578ce0ab4cb612c83d0f4
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309598
Original-(cherry picked from commit 39122e242e808d71a4e274e8a23e9a63f4984388)
Original-Reviewed-on: https://chromium-review.googlesource.com/309496
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12441
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing HyperTransport register configuration values were incorrect
in many spots. Apply the correct values from the BKDG on Family 10h and
Family 15h processors.
Change-Id: I009b6f478340e2dbfcda2b4534473d4397f9ecef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12022
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
We have had the "APIC: 00 missing read_resources" messages
for many years. It's obviously not an error, and also doesn't
cause boot failures. Therefore, remove the message.
Change-Id: I7f99c5950a3457df04e7ef6edb456b70dba9680c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12471
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The existing code for the Lenovo T400 works without changes on the
Lenovo R400. Same HDA verbs are provided by Lenovo BIOS on both
laptops.
Change-Id: I1dadddd7250ab80a4c40c2435865d72e3e5d99c9
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: http://review.coreboot.org/8393
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
only enable pcie gpp clocks when the corresponding clkreq pin is asserted
Change-Id: I7822d011bb94867d470c0194e6b652833c395cb2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12353
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
disable unconnected FCH clock outputs to save some power
Change-Id: Ib3efebb8656392d58d762c23827168017d273de8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12082
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The Intel cave creek chipset needs to have port 80 routing configured
before any post codes can be sent to port 80h. Sending post codes out
before the routing is done will hang the system.
This patch allows us to disable the first couple of post codes that go
out before the routing can be configured.
The Kconfig symbol is selected by the cave creek chipset (fsp_i89xx).
Change-Id: I9bf41669ec32744f87a1ed2de011d31c72ea38da
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12422
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: York Yang <york.yang@intel.com>
HAS_PRECBMEM_TIMESTAMP_REGION was dependent on COLLECT_TIMESTAMPS,
but should be allowed to be selected independently. My thought is that
the code may only be used when collecting timestamps, the HAS prefix
signifies that this is a platform configuration option.
This fix could also be done by adding 'if COLLECT_TIMESTAMPS' everywhere
that 'select HAS_PRECBMEM_TIMESTAMP_REGION' is used
Change-Id: Iaf4895475c38a855a048dc9b82d4c97e5e3f4e5c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Alignment of Intel Firmware Support Package 1.0 Rangeley
header and source files to the revision: POSTGOLD4
Detail changelog can be found at http://www.intel.com/fsp
FSP release date September 24, 2015
Change-Id: If1a6f95aed3e9a60af9af8cf9cd466a560ef0fe2
Signed-off-by: Marcin Wojciechowski <marcin.wojciechowski@intel.com>
Reviewed-on: http://review.coreboot.org/12418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This fixes Family 15h multiple package support; the previous code
hung in CAR setup and romstage when more than one CPU package was
installed for a variety of loosely related reasons.
TEST: Booted ASUS KGPE-D16 with two Opteron 6328 processors
and several different RDIMM configurations.
Change-Id: I171197c90f72d3496a385465937b7666cbf7e308
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12020
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Merlin Falcon's FCH has GPIO, UART and I2C. All of them are controlled
by registers mapped at MMIO space.
This ASL code is used for Windows drivers.
TEST:
1. Boot Windows 8 or Windows 10.
2. Install AMD Catalyst driver.
3. AMD FPIO, UART and I2C can be found in device manager.
4. I2C passed Multi Interface Test Tool (MITT) test.
Change-Id: I7ffe3fe0046d9a078cc38176c29a8e334646a5a3
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11750
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
On one particular TV the TV was holding SDA low when it came up. It
would release the SDA when the SCL went low the first time.
Unfortunately the HDMI i2c port wouldn't transmit until the SDA was
released.
Let's detect this case and insert a bogus clock pulse to try to get the
other side to release SDA.
It's unclear why the kernel doesn't have this problem.
BRANCH=none
BUG=chrome-os-partner:46256
TEST=Insignia TV works now
Change-Id: Ic9d27eb69bdc9c5fb11a68258e0c755cdc8b79d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 356ee7503f04e741a41be37ad573b588067b7114
Original-Change-Id: I4b6361877e0576cc4ea2f643f073f1aab660e434
Original-Signed-off-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/309258
Original-Reviewed-by: Agnes Cheng <agnescheng@google.com>
Original-Commit-Queue: Agnes Cheng <agnescheng@google.com>
Original-Trybot-Ready: Agnes Cheng <agnescheng@google.com>
Original-Tested-by: Agnes Cheng <agnescheng@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/309546
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12451
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.
BUG=none
BRANCH=none
TEST=emerge-lars coreboot
Change-Id: I2b65f6a37783ecdbdbc32ebe613243e042c865e9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ec5b629f920984564f12f2c09458ed300d031f69
Original-Change-Id: I9bd2b3595ae833fa5d07d97a7cda4a29041be837
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311890
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/12449
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use the keyboard backlight to provide indication that the system is
booting. This is useful for determining that a system is in S0 and
is running BIOS code.
BUG=chrome-os-partner:47435
BRANCH=none
TEST=boot on chell and see keyboard backlight come on early
Change-Id: I43e699bcc2f34998d3d6ce33ce72c7b04b55c146
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a3a0147b6de681365a9c995175076d5f397016fb
Original-Change-Id: I2441c28431e71b13b70e6533e175d29ccfd8d7e9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12448
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The GPIO for USBA_1_ILIM_SEL_L should be low to enable 2A charging
from the Type-A port.
BUG=chrome-os-partner:47172
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I1bbcdd467684e7c1372c8ca862d498fb6cbb966c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c8a8fbed6d0fd7aea0a41db2bde104fe7a05cabe
Original-Change-Id: I3b18cbb204cfa19e50f34ea9533018e286342513
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312451
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12447
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.
BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built for chell.
Change-Id: I5843f13be43a6ec143600585a5a0c47563e533dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ddd5860dc0cfee68ec2f77f4931665740bede08c
Original-Change-Id: Ife0e2fb11373dd129e20b914b45cd5b56c3493f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312321
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
For the rails controllable by the host processor through
gpios turn them off in the sleep paths. The result is that
S3 and S5 will turn off those rails.
BUG=chrome-os-partner:47228
BRANCH=None
TEST=Built and booted glados. Suspended and resumed.
Change-Id: I6d45683b64ca5f7c3c47e11f95951bd2d9abf31e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ed432e2b5535da6f872a53b76886d983f00b4e8e
Original-Change-Id: I94d7e0b00bf7e7da8dc59f299e41b72e8fcb64f4
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312320
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12445
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
By calling cbmem_recovery() with `0`, we rewrote the cbmem table even
on the resume path. By that, we lost the OS' resume vector and ended up
loading the payload.
Change-Id: Ic24a12d4143d6924321b1d01f07a467c58c4e9ea
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/12420
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix regression introduced by:
3660c0fc65
"northbridge/intel/sandybridge: Enable PEG clock-gating on demand"
Issue observed:
GNU/Linux kernel crashes in earlyinit on systems without PEG devices.
The crash occurs on every boot in different functions.
There's no problem on systems with PEG enabled.
Test system:
* Lenovo T530
* Intel Core i5-3320M CPU
* Fedora GNU/Linux 4.1
* PEG disabled in devicetree
Problem description:
Tests shows that modifing PEG chicken bit or device enable bits
after setting BIOS_RESET_CPL causes random crashes in GNU/Linux.
Problem solution:
Disable PEG devices before setting BIOS_RESET_CPL.
Final testing results:
No more random kernel crashes.
Change-Id: I4a967c2d00d7d1e4426cf5abdd5f616c21557da7
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/12112
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Issue observed:
Coreboot stops at: "Not enough MTRRs available!"
Test system:
* Gigabyte GA-B75M-D3H
* Intel Pentium CPU G2130
* ATI Radeon HD4780
Problem description:
In case the IGD does not claim VGA decode, the code path taken results
in an integer overflow as uma_memory_base isn't initialized.
The MTRR assignment will fail, because of invalid memory regions.
Problem solution:
Properly initialize uma_memory_base to prevent possible integer overflow.
Final testing results:
The system boots again with IGD not claiming VGA decode.
Change-Id: I025be23b1defb6155469a3eee66569e49a695e7f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: http://review.coreboot.org/11918
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Issue observed:
Intel raminit works in about 50% of all test-cases on lenovo x220.
Problem solution:
Prefer a smaller valid value over the measured one for
initial timB timings.
Final testing result:
Tests on x220 shows that the issue was resolved.
The test system booted successfully ten times in a row.
Tests on Gigabyte GA-B75M-D3H revealed no regressions.
Test system:
* Intel Pentium CPU G2130
* Gigabyte GA-B75M-D3H
* DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ"
Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11248
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This patch removes the old arm64/stage_entry.S code that was too
specific to the Tegra SoC boot flow, and replaces it with code that
hides the peculiarities of switching to a different CPU/arch in ramstage
in the Tegra SoC directories.
BRANCH=None
BUG=None
TEST=Built Ryu and Smaug. !!!UNTESTED!!!
Change-Id: Ib3a0448b30ac9c7132581464573efd5e86e03698
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12078
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch expands the existing ENV_<stage> macros in <rules.h> with a
set of ENV_<arch> macros which can be used to detect which architecture
the current compilation unit is built for. These are more consistent
than compiler-defined macros (like '#ifdef __arm__') and will make it
easier to write small, architecture-dependent differences in common code
(where we currently often use IS_ENABLED(CONFIG_ARCH_...), which is
technically incorrect in a world where every stage can run on a
different architecture, and merely kinda happened to work out for now).
Also remove a vestigal <arch/rules.h> from ARM64 which was no longer
used, and genericise ARM subarchitecture Makefiles a little to make
things like __COREBOOT_ARM_ARCH__ available from all file types
(including .ld).
BUG=None
TEST=Compiled Falco, Blaze, Jerry and Smaug.
Change-Id: Id51aeb290b5c215c653e42a51919d0838e28621f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12433
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Without BOOTBLOCK_CONSOLE any call to die() fails due to die() symbol
not being defined at link time. die() is not is dependent on the
console backend, and can function without it (the prink gets no-oped).
Change-Id: I6cecafb576c3b1e901f3927c777f6282174fb259
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/12356
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The microcode for Bay Trail that's in the blobs repo is for the
M and D chip variants only. The fsp_baytrail directory is for
Bay Trail I chip variants, and will not boot if the M/D microcode
is used. The microcode for the I variant is supplied as part
of the Bay Trail FSP package.
Change-Id: I5493deb1626dc3cf037053e13e092f5a1143a13a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12334
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing arm64 architecture code has been developed for the Tegra132
and Tegra210 SoCs, which only start their ARM64 cores in ramstage. It
interweaves the stage entry point with code that initializes a CPU (and
should not be run again if that CPU already ran a previous stage). It
also still contains some vestiges of SMP/secmon support (such as setting
up stacks in the BSS instead of using the stage-peristent one from
memlayout).
This patch splits those functions apart and makes the code layout
similar to how things work on ARM32. The default stage_entry() symbol is
a no-op wrapper that just calls main() for the current stage, for the
normal case where a stage ran on the same core as the last one. It can
be overridden by SoC code to support special cases like Tegra.
The CPU initialization code is split out into armv8/cpu.S (similar to
what arm_init_caches() does for ARM32) and called by the default
bootblock entry code. SoCs where a CPU starts up in a later stage can
call the same code from a stage_entry() override instead.
The Tegra132 and Tegra210 code is not touched by this patch to make it
easier to review and validate. A follow-up patch will bring those SoCs
in line with the model.
BRANCH=None
BUG=None
TEST=Booted Oak with a single mmu_init()/mmu_enable(). Built Ryu and
Smaug.
Change-Id: I28302a6ace47e8ab7a736e089f64922cef1a2f93
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/12077
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The existing MCT support code did not perform any of the requisite
configuration to support registered or x4 DIMMs. Add the needed
configuration per the BKDG for Family 15h.
Change-Id: I9ee0bb7346aa35f564fe535cdd337ec7f6148f2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12019
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Sufficient support has been added to allow booting with registered
DIMMs on the KGPE-D16 in certain slots. ECC support needs additional
work; the ECC data lanes appear to cause boot failures in some slots.
Change-Id: Ieaf4cbf351908e5a89760be49a6667dc55dbc575
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12017
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Load microcode to APs when performing baytrail_init_cpus. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.
Change-Id: I7b7c0f43da0d149048ae5a8fd547828f42de04fd
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/12095
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Load microcode to BSP in bootblock so later on the FSP TempRamInit call
can be success. The updated fsp1_0 driver calls TempRamInit API with a
dummy microcode, so FSP will not handle the microcode load. If BSP is
not loaded a microcode before calling TempRamInit API, the call will
fail with the error No Valid Microcode Was Found.
Change-Id: I1fbe68e14e5a24d8f2da70603cd2f03675b9ca81
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/11896
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Pass in dummy microcode when calling FSP TempRamInit API. FSP will not
do the microcode load and leave the work to coreboot.
Ensure that BSP has been loaded a microcode before calling TempRamInit
API, otherwise FSP will return error that No Valid Microcode Was Found.
Change has been verified on fsp_baytrail and will be applied to rangeley.
Change-Id: I8247c0503c8eb3d1c8eaa059632fb3a11c9daae9
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/11895
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Load microcode to APs when performing model_406dx_init. The updated
fsp1_0 driver calls TempRamInit API with a dummy microcode, so FSP
will not handle the microcode load.
Change-Id: Ib75f860a34c84bf13c0c6c31ebed13e5787f365e
Signed-off-by: David Guckian <david.guckian@intel.com>
Reviewed-on: http://review.coreboot.org/12436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Load microcode to BSP in bootblock so later on the FSP TempRamInit call
will return with success. The updated fsp1_0 driver calls TempRamInit
API with dummy microcode, so FSP will not handle the microcode load. If
BSP is not loaded with microcode before calling TempRamInit API, the
call will fail with error No Valid Microcode Was Found.
Change-Id: I9c55acaf3353a759bb0119f0a5402a704ffb2c4a
Signed-off-by: David Guckian <david.guckian@intel.com>
Reviewed-on: http://review.coreboot.org/12367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
The current code did not define the number of DIMM slots on the
mainboard, which lead to incorrect configuration values and
occassional training failure.
Add preliminary support for DIMM slot count configuration.
Change-Id: I488511d6262ffa8207c442d133314aed0f75acfb
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12016
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
On some multi-socket AMD platforms there are too many cores for all
APs to start up without stack collisions with either each other or
the BSP. On such platforms a larger amount of CAR memory is also
available.
Allow the maximum DCACHE size to be increased via a mainboard-
specific Kconfig flag.
Change-Id: I72ae8f7abeb9a83b57505469922818f9ec5bdf3f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12015
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
CAR space on certain platforms is nearly full. This prevents the
addition of necessary RAM initialization features such as x4 DIMM
support. As the DIMM SPD cache uses a sizeable amount of CAR RAM,
reducing it would free up a significant amount of CAR RAM.
DDR3-based AMD platforms only support up to 3 physical DIMMs on
each channel (6 per node). Reduce the maximum number of DIMMs
on a node from 8 to 6 accordingly.
Change-Id: I38def86da76fc622785318c825670209b2ac9017
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12107
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
On the ASUS KGPE-D16 it was noted that the pin straps did not properly
configure the lane director hardware, causing link training failure
on NIC B. Forcing coreboot to always reconfigure the lane director
on startup resolves this problem.
Change-Id: I5b78cef84960e0f42cc3e0406a7031d12d21f3ad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12014
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In the course of adding full Family 15h MCT support some Family
15h specific settings were inadvertently applied to Family 10h
processors.
Only apply Family15h specific settings to Family 15h processors.
Change-Id: I5dcb333d3a5a49318fe7bddd4c386642205c343e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12013
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
When both DCTs of a node are in use the DRAM clocks should be skewed
with respect to one another in order to reduce cross-channel interference.
Set the clock skew bit according to the BKDG recommendations.
Change-Id: Ibcce54fc53b79beba2f790994bcf87cc0354213a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12011
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The existing code did not set Rtt timing parameters when registered
DIMMs were used with Family 15h processors. Set the Rtt values
according to the BKDG recommendations.
Change-Id: I80cd7f8aec12951611d802f33e5e167a41dd532e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
AMD Opteron processors contain a very fragile phy phase detection circuit.
Additionally, the algorithm given in the BKDG does not function as intended;
this was verified both on real hardware via execution trace and on paper
with values read back from multiple CPUs and DIMMs.
As a result, the phy training algorithm given in the BKDG has been
replaced with a phy training algorithm developed at Raptor Engineering.
This particular patch is the first part of that algorithm; the code
is updated in future patches but this should exist in the historical
record in case something breaks down in the later sections of code.
Change-Id: Ic7a19d24954f47c922126e3da7be1f7e85f7396f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12007
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
AMD's automatic phy phase detection hardware is very fragile and often
produces incorrect results. Attempt to recover from obvious phase
locking errors by retrying phy training on the failing link.
Change-Id: Ia2c3022534c9ad44714eef6e118869f054bd9f6b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The existing MCT code did not properly set up the On Die Termination
(ODT) or timing values for registered DIMMs. Use the BKDG recommended
values when registered DIMMs are installed.
Change-Id: Ia9ee770d9f9c22e18c12e38b5bb4a7bae0a99062
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12005
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
There were numerous issues surrounding AMD ECC initialization on
Family 15h processors due to the incomplete derivation from Family
10h MCT code. Bring the Family 15h ECC initialization and supporting
setup code in line with the BKDG recommendations.
Change-Id: I7f009b655f8500aeb22981f7020f1db74cdd6925
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12003
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The existing ECC initialization algorithm contained several bugs on both
Family 10h and Family 15h processors, including activation of ECC scrub
before DRAM setup was completed, in violation of both BKDG and errata
recommendations.
Change-Id: I09a8ea83024186b7ece7d78a4bef1201ab34ff8a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12002
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Since there are no longer any newisys mainboards, remove the directory
and Kconfig files. This removes the Kconfig warning:
mainboard/newisys/Kconfig:3:warning: config symbol defined without type
Change-Id: Icb2e782173166a26fa261f6cfb81b665a846931e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/12423
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kernel needs to set Audio IRQ as wake capable.
BUG=chrome-os-partner:47450
BRANCH=NONE
TEST=System wakes up from S0ix by pressing headset buttons.
Change-Id: I0f89d05b4c5449e5e3277dde938d941e4ad8cbea
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 65bf434f7c7e1662211f9c8bf61eeb4f41bdc675
Original-Change-Id: I7b5b564023044b4458eb0976488018b3226f4c70
Original-Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311793
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12414
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In 2014 or so the RTC code was changed to assume the ALTCENTRY
register (0x32) as always being utilized for creating an rtc_time.
However, one needs to ensure it's set at least once otherwise
the year field in rtc_time is not sane.
In practice this doesn't matter unless somone wants to use the
full year value. cmos_init() should do the same thing in the
rtc fail case, but the machine I had never had that set correctly.
BUG=chrome-os-partner:47388
BRANCH=None
TEST=Booted glados w/ 0xff ALTCENTRY value. New value is 0x20.
Change-Id: I028f801c5d717a0018ed00df82c25b466d64670c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d5be5bc697bef60a264ddc7f67755aa96088d36
Original-Change-Id: I6e12a30c9e08d8c1002e4cef0f143f0f88009e92
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12411
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The elog format stores the year of the event in bcd format.
Semi-recently rtc_get() started returning the full year,
e.g. 2015. However, bin2bcd takes a uint8_t as a parameter.
Converting a full year (2015 or 0x7df) to a uint8_t results
in passing bad values (223 or 0xdf) to bin2bcd. In other words
the input value of bin2bcd needs to be a number between 0 and 99.
Therefore fix that mistake.
BUG=chrome-os-partner:47388
BRANCH=None
TEST=Events show up with correct year in eventlog now.
Change-Id: I9209cb9175c0b4925337e2e5d4fea8316b30022a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 95a86013234dc999c988291f636e2db3803cc24a
Original-Change-Id: I12734bc3a423ba9d739658b8edc402b8d445f22e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12410
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
1. This is required the BLOB change Ie86bb0cf
AMD Merlin Falcon: Update to CarrizoPI 1.1.0.1 (Binary PI 1.5)
2. This is tested on Bettong Alfa(DDR3) and Beta(DDR4). Both of the
boards can boot to Windows 10. PCIe slots, USB and NIC work.
Change-Id: I6cf3e333899f1eb2c00ca84c96deadeea0e23b07
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11752
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The SB700 silicon is somewhat buggy; if the links come up in an
incorrect state after POR the silicon cannot automatically recover.
If a disk fails to come online, reset the associated link and try
disk detection again.
Change-Id: I29051af5eca5d31b6aecc261e9a48028380eccb3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11999
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing prefetcher configuration was incorrect; use the correct
values from the AMD Family 10h and Family 15h BKDGs as appropriate.
Change-Id: I287ffa6345e1f4d232d4b2ea4251650ada3fda92
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/12417
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The existing code enabled ECC before clearing memory. As the
AMD CPUs will generate MCEs on any invalid check bits, this
resulted in random lockups during memory training due to the
uniniailized check bits.
Initialize ECC check bits before enabling ECC hardware.
Change-Id: I992e7040520570893ba6a213138dd57bfa14733b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11996
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In AHCI mode SeaBIOS randomly fails to detect disks (AHCI timeouts),
with the probability of a failure increasing with the number of disks
connected to the controller. Resetting the SATA controller appears to
show the true state of the underlying hardware, allowing the drive
detection code to attempt link renegotiation as needed.
Change-Id: Ib1f7c5f830a0cdba41cb6f5b05d759adee5ce369
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11998
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
SeaBIOS AHCI drive detection randomly fails for drives present
on the secondary channel of each AHCI SATA BAR. Forcing native
drive detection in AHCI mode resolves this issue.
Change-Id: I34eb1d5d3f2f8aefb749a4eeb911c1373d184938
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11997
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Certain DIMMs, for example DIMMs on which the EEPROM has been modified
by the end user, may not contain a valid SPD checksum. While this is
not a normal condition, it may be useful to allow a checksum override
while memory timing parameters are being altered, e.g. in the course
of overclocking or underclocking, or when recovering from a bad SPD
write.
This is an advanced level feature primarily useful for debugging
and development.
Change-Id: Ia743a13348d0a6e5e4dfffa04ed9582e0f7f3dad
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11987
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if devices actually use
no-msi.
Change-Id: I5eab28956b7a3fbc7c10447e99d6c11dbe6a1d14
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12363
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The plugged devices on PCIe should use IOAPIC2 instead of standard
IOAPIC1. The entries in IOAPIC2 count from the end of IOAPIC1.
The unchanged code worked because the OS uses MSI instead APIC.
To test that, boot linux with parameter pci=nomsi and see if the devices
like NIC work well as they do without the booting parameter.
run 'cat /proc/interrupts' to see if the devices actually use
no-msi.
Change-Id: Id6d35224312aeb6e3a175ec9990e0bb34bad67e7
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/12362
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The AMD Register Programming Reference states that the user should
have the option to disable Active Link Power Management for two
reasons. First, some drives may not function correctly with the
ALPM implementation of the SP5100, and second there are some
situations where low latency access is more important than the
power savings created by using ALPM.
Allow the user to disable ALPM if desired.
Change-Id: I88055cbb4df4d7ba811cef7056c0a6ca2612fcb0
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11993
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Under specific circumstances, for instance in low power or fanless
machines, it may be useful to cap the maximum P-state of the CPU.
Allow the maximum CPU P-state to be set via an NVRAM option.
Change-Id: Ifdbb1ad11a856f855c59702ae0ee99e95b08520e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11985
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
o. Make some gpio changes base on Emile spec.
o. Init sdmmc function.
o. Revert cpu freq reducing in recovery mode since Emile
have more effective thermal than Mickey.
o. Revert the changes of lpddr3-samsung-2GB config.
BUG=chrome-os-partner:46658
TEST=build and boot on Emile
BRANCH=veyron
Change-Id: Ibdc2ce511c8e215c202e2067d79f4c60cdfca738
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 39e5436c8aa3353af77f62e548f48d19dc722999
Original-Change-Id: Ib2c78c9b5e3ac6620ab1772879a7ea0f7007f96e
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307651
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12396
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch enables GPP_B5 as ACPI_SCI for wake.
It also defines touchpad wake device in ACPI with GPE0_DW0_05 for _PRW.
BUG=chrome-os-partner:43491
BRANCH=none
TEST=Build for kunimitsu. Tested wake from touchpad on a reworked kunimitsu board.
Change-Id: I4347be8f7a4552c6b583f0797fab64045aa9792e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8c21f3b5df21d96937975dc20ee5e2f83fb3d75e
Original-Change-Id: I76e69bdba81ec22ae67c7cff3a807cea8c54a5b3
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311007
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/12395
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is a copy of mickey and renamed.
CQ-DEPEND=CL:306967
BUG=chrome-os-partner:46658
TEST=build coreboot
BRANCH=veyron
Change-Id: I9e1232f3f1334ec747a5beb52f214635a7ab08ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 9316a9ec27d5799e290add1e5818f4449b680fde
Original-Change-Id: I906de7bbc8b8e110e0774c14ec636a327230b325
Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/307620
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/12394
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When enabling CONFIG_SEPARATE_VERSTAGE the functions in chromeos.c need
to be put into verstage.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=enable SEPARATE_VERSTAGE and build for chell
Change-Id: Ic58a6e383806a7a64b9af760e194fddf15c645f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 403f0707074802371237beecf1941034c1612f10
Original-Change-Id: Ib1154869974337b53a64efa5892a83ecd81973b8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/310928
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12393
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to wake from trackpad and wifi we cannot enable Deep S3.
BUG=chrome-os-partner:46289
BRANCH=none
TEST=wake from trackpad on chell
Change-Id: Ieb2210d5d15b5f5d744a686c743df11e5d72558f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbc74e13b754249869144df84ab2bb9b7e77119a
Original-Change-Id: I84265197fb964e0594a4672a40fd3e2362e29ae1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311306
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12392
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds the SPD for SK-Hynix H9CCNNNCLTMLAR memory to be
used in the EVT build.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: I45d0840e43ed81d8286b005f0a99b014b7f0cf28
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1e917440141c586cb370147f9c5b782d6e77ea10
Original-Change-Id: I02f1349f38d83f4a09887adf81384b5a8f475dd0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311214
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12391
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The family variable was not being set yet for skylake, add this
to the current boards.
BUG=chromium:551715
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Icf175e4ce89cb47b9eabce1399eb3ef29e7a607f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e379402f38634eb0204e03b616111fff9515cec
Original-Change-Id: Ia31fb04b5c22defc71a0c02d9fa1eff93ccbc49d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311213
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12390
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The net names are offset by 1. My board is not stable enough
to really test all of these yet...
BUG=chrome-os-partner:46289
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: I65e17323f2819eca130c1bf0ccbc3ea0ec2f383f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 327194dcfcb3a5c9f431b1a2e26c230cb2b2a48b
Original-Change-Id: I50e9ea091bb6e6a1da3a9434ae0fbf3f652fa354
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/311113
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12389
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds CC6 power save support to the AMD Family 15h
support code. As CC6 is a complex power saving state that
relies heavily on CPU, northbridge, and southbridge cooperation,
this patch alters significant amounts of code throughout the
tree simultaneously.
Allowing the CPU to enter CC6 allows the second level of turbo
boost to be reached, and also provides significant power savings
when the system is idle due to the complete core shutdown.
Change-Id: I44ce157cda97fb85f3e8f3d7262d4712b5410670
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/11979
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
A wrong function name made an #ifdef'd code path not compile. Fix that,
and also use IS_ENABLED() to make sure that such issues won't come up
again there.
Change-Id: Iccb98842dde498cce32cd86a770e22a506ad4cc2
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/12296
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is an attempt at better compatibility with driver matching etc.
Change-Id: I26eccbe17a31ba2042d0fe1bb424d9f380c0a82e
Signed-off-by: Urja Rannikko <urjaman@gmail.com>
Reviewed-on: http://review.coreboot.org/12351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Martin Roth