While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.
Apply errata 531 only to revisions listed in Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I removed the gpio asserts - I think those are not used here.
The pcie 1x slot works, the x1 card I have does not work in 16x slot, but in orig bios I cannot see it any slot, so it is kind of better.
The classic PCI slot works fine too. However it seems SATA has some issues.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Trying to keep it simple: Two sizes are expected equal so use same %x for both.
Cast to unsigned int to make sure it fits.
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
notices. Getting it into the tree so people can get to it.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5717 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://www.gigabyte.cn/products/product-page.aspx?pid=3118#ov
the simple config is
AM2+DDR2+SB700+RS780, the superIO is IT8718F
The patch has been tested with SeaBIOS + SUSE11.2
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
detected by the existence of dev3. Some other RS780 mainboard has
the same function. The patch added the function to make these boards work
smoothly.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Details of the hardware configuration can be found at
http://www.gigabyte.com/products/product-page.aspx?pid=3478
Brief configuration is:
1. CPU:Support for AM3 processors: AMD PhenomTM II processor/ AMD Athlon™ II processor
2. North Bridge: AMD 785G
3. South Bridge: AMD SB710
4: Super IO : ITE8718F
The mainboard has two bios flashchip. Coreboot ROM should be flashed into the
M_BIOS (which means main bios).
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kind. Move it to drivers and make the necessary adaptions. Also drop empty
drivers/generic/generic and start cleaning up Makefiles in drivers/
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5710 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5707 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
After lots of testing, the SuperIO LDN 7, register 0xEF is the key to the
problem. This patch adds a function which stops dual bios mainboards from
rebooting, when called.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Drop lots of dead code from the various cache_as_ram.inc files.
- Use some descriptive macros instead of magic numbers for MTRR MSRs
- drop unused duplicate descriptors from romstage GDT
- slightly reformatting code and comments
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5696 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pretty much 1:1 the same file (despite an include and a typo) so drop one
instance of it. We only have one prologue.inc for the romstage code now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The bit 15 seems to be a new feature when CPU started to have more than 4
cores.
Zheng
Yes, this was add for revD.
Marc Jones
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
board porter: printk should always be available in CAR mode.
Also drop CONFIG_USE_INIT, it's only been selected on one ASROCK board
but it's not been used there. Very odd.
There is one usage of CONFIG_USE_INIT which was always off in
src/cpu/intel/car/cache_as_ram.inc and we have to figure out what to do with
those few lines.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5682 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Revert until someone with the boards refactors it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix up converted mainboards that still used early_mtrr_init()
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5678 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
that causes CAR to hang, provide more debugging output wrt memory size,
and correct the numbering on the ram init sequence.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5677 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- make SMM relocation debugging Kconfig accessible
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5676 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also clean up gx2def.h and geode_post_code.h a little.
abuild tested and boot tested on a Wyse S50.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Part of converting GX2 to use CAR.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5670 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Justification:
- dbm690t isn't actively developed (no new warnings will be introduced)
- having this board fail clutters the mailing list
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
change the behavior, since it is disabled by default.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix the ctrl_devport_conf_clear to clear the enable bit.
A simplification:
Dynamically enable ck804s that are found instead of relying on #defines.
Removing an Opteron changes the number of ck804s that are present.
Simple changes to make it easier to compare the factory BIOS with Coreboot when
using SerialICE for boards with the Nvidia ck804 chipset:
If the mask is zero, don't read the value, just write the new value over it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5652 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
reading that information from the device tree.
Use this function on kontron/986lcd-m
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5638 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5635 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This resolves problems with terminated DRAM modules.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Roland G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
there is no free list.
Converting resource arrays to lists reduced the size of each device
struct from 1092 to 228 bytes.
Converting link arrays to lists reduced the size of each device struct
from 228 to 68 bytes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
However on these platforms we were causing a resource conflict by
letting the resource allocator start allocations at 0x400.
Change the constraints to start at 0x1000 so we avoid allocating over
LPT ports (0x778-0x77f), PCI (0xcf8-0xcff) and some other fixed
resources that might live down there (smbus base, acpi base,...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5622 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
range as detailed on p104 of the cs5536 Device Data Book.
Extended to 0x1000. Same change for cs5535.
Signed-off by: Edwin Beasant edwin_beasant@virtensys.com
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Especially most _smbus functions misuse port 0x80 writes for delays.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
108 src/arch/i386/include/arch/acpi.h:402:5: warning: "CONFIG_HAVE_ACPI_SLIC" is not defined
1 src/mainboard/getac/p470/mainboard.c:83: warning: assignment discards qualifiers from pointer target type
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, drop some dead code at the very end where some segment registers
get set up and are immediately overwritten by pops.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
segment registers before restoring register values. This was breaking
the Geode VSA, and probably would have hurt other option roms as well.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5612 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Using YABEL isn't supported for the VSA, so don't allow a choice.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5608 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
src/northbridge/amd/amdk8/amdk8_acpi.c
src/southbridge/amd/amd8132/amd8132_bridge.c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
http://www.coreboot.org/pipermail/coreboot/2010-June/058668.html
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Print fewer characters for pointers to make the output more concise.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5602 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
based on Kontron 986LCD-M
changed superIO chip to w83627ehg, dropping MIDI
dropped second superIO at 4e
changed superIO-addr from 2e to 4e
adjusted irq_tables.c and devicetree.cb
dropped setup of 3xGBit-Ethernet
adjusted IRQ-map (using values from mainboard/intel/d945gclf)
disabled parts about HD-audio (missing on that board)
Signed-off-by: Bernhard M. Wiedemann <corebootbmw@lsmod.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5599 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This still requires someone to adjust the #includes in the
model_XXX_init.c files but with a script we're getting closer
to automate the update of 3rd party files.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
No new microcode files included.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and replace them by their counterparts from Intel's
opensource microcode file.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To apply this patch you need to
cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot is direct. This patch does it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cs5536.c:chipsetinit() is called during northbridge pci_domain_enable()
which happens before scan_bus() so the device tree does not have PCI
vendor/device ids yet. Let's use dev_find_slot() for now. This works
only as long as the CS5536 has PCI device id 0xf in all mainboards,
and a better solution is needed in case that ever changes!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Nathan Williams <nathan@traverse.com.au>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In the bootblock, 4MB of ROM are mapped instead of the
default 1MB
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot later. Current ASL compilers check for validity
and complain about the dummy values.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_10xxx/fidvid.c:758:
warning: 'fid_max' may be used uninitialized in this function
Quoting Marc:
It [fid_max] should be initialized to 0. The !nb_cof_vid_update would mean that
the fidmax shouldn't change so the value isn't important, but 0 would be the
safest if there is another hole in the logic and CPUs are not matched.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5577 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This board is similar to the AMD Norwich mainboard.
Signed-off-by: Nathan Williams <nathan@traverse.com.au>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Move the 'USE CMOS' question from the top level to the
General Setup section of Kconfig.
Signed-off-by: Joe Korty <joe.Korty@ccur.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5564 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5563 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
also the GCC generated code and it looks all right. Please test on some
multicore CPU.
I added the "memory" clobber to read_cr0 / write_cr0 function as it is in Linux
Kernel. Seems that if this is missing, GCC is too smart and messes the order
of reads/writes to CR0 (not tested if really a problem here, but be safe for
future users of this function ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5562 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
legacy software to recognize it as IDE and boot from it. I think
this should be the default for two Tyan boards (k8s aka s2882 and s2881).
Rename the directory to sil prefix to match the Linux kernel naming.
(And I think it was a SiliconSystems wish to be named sil ;)
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This fixes serial console on GIGABYTE GA-6BXE.
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5555 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* fix some potential compiler issues with newer gccs
* add some more comments
* make 32bit accesses for feature test functions
* make some objects drivers because they contain a pci_driver struct.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5552 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The values are overwritten on the fly but without the patch iasl will refuse to
compile the code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5550 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
northbridge/amd/amdht/ht_wrapper.c
northbridge/amd/amdfam10/raminit_amdmct.c
cpu/amd/model_10xxx/fidvid.c
pc80/mc146818rtc_early.c
They are now included by the fam10 chipset code that requires them.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with Geode LX , adds gpl2 headers plus some white space fixes.
This is build and boot tested.(of course vsa loading is stil not fixed,it now
runs forever with :"Oops, exception 13 while executing option
rom")
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5544 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
some register values from C.
This theoretically fixes non-vga option roms, but it also allows to use
the same assembler code for option roms and vsm.
It will also make using the bootsplash without yabel a lot easier.
Factor out and improve BDA setup, do some rom segment setup for those
option roms that need it.
Don't call the coreboot exception handler if an exception occurs in real
mode. It's only partly usable, but mainly the Kontron 986LCD-M (and other
i945GM boards) choke on an exception #6 (invalid opcode). This particular
issue is not introduced by the changes in this patch but has been around
for quite a while at least.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5543 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
common one is enough. Trivial
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5540 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c files in mainboards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it centrally in console/console.h instead.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
build rule is needed as for console.o
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5529 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
romstage.c.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5527 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in device trees. Adapt sconfig as necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tell the BIOS how much RAM the virtual machine has available.
This patch fixes the detection.
Signed-off-by: Valdimir Serbinenko <phcoder@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
files using prototypes is the way to go I think. It would make our life a lot
easier should we ever decide to move (some mainboards) over to not #include
all those .c files in romstage.c anymore.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5518 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same preprocessor check
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Anders Jenbo <anders@jenbo.dk>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5508 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5501 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
correct ram clock to the vga bios or there be dragons.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5500 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
geode lx and amd opteron don't use this yet.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5499 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(which could at some time hold global post code definitions, too)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5498 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
were not treated separately until now. Fix it. Hope self ack is OK,
compiled tested locally.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5497 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5495 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to option based (similar what Uwe did) and also it uses GFXUMA to handle the
high_tables_start offset from memory top.
To satisfy the CMOS option users (Hi, libv! ;) I added also a possibility to do
that through CMOS.
Fixed printks to match the new style.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We changed almost associated code when we ported but overlooked some.
Some legacy of SB600 are also fixed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of devices/oprom/x86.c.
We have some tests on hardware. Moving RAMBASE to
1MB needs to wait a bit until C7 cache_as_ram.inc
has been adapted to cache that area or things will
become incredibly slow (1.5s boot time instead of 0.5)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
independent of strapping, making larger flashes work. We cannot walk anything
else than PCI bus 0 because HT is not setup yet.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Allows to drop quite a bunch of nasty code
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the gx2+5536 issue is still open, and it reveils a serious problem with the
code that was hidden under a bunch of warnings until now.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
between having VSA functionality in the code, and adding a VSA image to the
ROM.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
nothing to do with SMP)
- move src/arch/i386/smp/mpspec.c to src/arch/i386/boot/mpspec.c (where
acpi, pirq and coreboot table generation lives)
- modify src/arch/i386/boot/Makefile.inc,
src/arch/i386/lib/Makefile.inc
and src/arch/i386/smp/Makefile.inc accordingly
- src/arch/i386/smp is now empty. drop it.
- drop src/arch/i386/init/car.S (unused)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5460 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
only. Keeping them as #warnings will not likely that they're fixed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's currently its able to run coreboot + seabios + sgabios.
The following hardware works;
P3
i440BX northbridge
82371 southbridge
IDE normal disks + CF
The following hardware doesn't work:
4x NIC 21143-PD
2x PCMCIA PCI1225PDV
Signed-off-by: Marc Bertens <mbertens@xs4all.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- More explicit rules for obj/%.c->obj/%.o builds
- Hide printf even with verbose make
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5456 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
proper libgcc handling, which we introduced by revision r4679, which was
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5455 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
modifying the variable for their own purposes)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5454 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the build tree.
Allow separate build tree for utils
Use separate build tree for utils in abuild
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Which is not (always) the case.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5441 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
was mainboard specific and unused there already.
some more minor warning fixes.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5433 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Neither does quadcore.h (anymore)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5429 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this patch also slightly changes it so we have a single cache_as_ram.inc which
requires no "help" from cache_as_ram_post.c and cache_as_ram_disable.c (or
worse, a lot of cruft hacked right into romstage.c like on tyan s2735)
Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new
simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mention it explicitly.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5420 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
where applicable.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5419 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
into the cached area. Back to 469ms until coreboot_ram is actually
running on epia-cn
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5417 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
not a 6ex board, but using the same CAR code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5414 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
currently unused. Just keep it in sync, we might need it some day.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5413 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
single several pages long asm statement
Could use some renumbering of post codes, but that's good for another time.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5412 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/arch/i386/Makefile.inc to the respective CPU directories.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5411 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Necessary for romstraps
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- set them to span the last 64k, instead of the last 128k
by default
- fixes via CAR for tiny bootblock
- enabled tiny bootblock for via/vt8454c
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5409 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fix mbi length detection, this will remove what looked like an endless loop
during vga init in some cases.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
does not work as it is, but it's the only compile test case for i855pm). It's
the only board left using an ICH4 that does not use CAR. Change that.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Xavi Drudis Ferran