More will follow so better move them where they are used. Also remove
defaults and add dependencies to not clutter .config files up that
don't have any of these options selected.
Change-Id: I3a255c821cc26aeb66e4fd6adf7142d7e856f5ac
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For general use of this driver it is necessary to move some parameters
from init_fan_ctrl() to init_temp_mon(). This shift does not lead to any
functional change.
Change-Id: I6b8f770c768f3dacf96087eb0194cc99f0d11e17
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was either SAGE or AMD AES who implemented these for
binaryPI, and it is not part of the documented AGESA API.
My conclusions of these are:
AmdGetValue() returns values from build-time configuration,
these may not reflect the actual run-time configuration as
there are OEM customization hooks to implement overrides.
AmdSetValue() in __PRE_RAM__ will fail, as configuration
data is const. Also AmdSetValue() in ramstage may fail, if
said configuration data has already been evaluated.
Semamtics of these calls are unusable unless one also has
access to PI source to make exact decision on when they
can be called. Remove these now that stoneyridge does not
actually require them.
Change-Id: I3379a75ce3b9448c17ef00eb16d3193c296626cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the USBDEBUG_DONGLE_BEAGLEBONE_BLACK option that does the same as
USBDEBUG_DONGLE_STD and update the description of USBDEBUG_DONGLE_STD that it
also should be selected for the BeagleBone Black.
Change-Id: I3093a6d2c39e7b5e81785028e436109090d9e6dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/21486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make the spelling of *romstage* consistent without a space. Choose this
version, as *ramstage* is also spelled without a space, since commit
a7d924412a (timestamps: You can never have enough of them!).
Fixes: 0db924d74c (cbmem: print timestamp names)
Change-Id: I1b1c10393f0afb9a20ac916ff9dc140a51c716cd
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
IMGU and CIO2 devices do support the hardware managed cache
coherency and hence removing the CCA object which was
reporting that cache coherency is not supported.
BUG=none
BRANCH=none
TEST=Build and boot soraka. Dump ACPI tables and verify that
CCA object is not present.
Change-Id: I14b0a92eafe193e9004d2dad0957a3fe8d05d313
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.
BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.
Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In current versions of spike, the config string is not available
anymore, because RISC-V is moving toward OpenFirmware-derived device
trees (either in FDT or text format). Using query_config_string leads to
a crash in these versions of spike.
With this commit and If0bea4bf52d ("riscv: Update register address"),
coreboot reaches the romstage again, on spike.
Change-Id: Ib1e6565145f0b2252deb1f4658221a4f816e2af4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is easier to read than the raw shift amount that's extracted from
load/store instructions.
Change-Id: Ia16ab9fbaf55345b654ea65e65267ed900eb29e1
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
We need support two touchpad for Robo project,
so adding Synaptices touchpad to coral.
BUG=b:63134907
TEST=Compiled, verified by ODM
Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50
Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the cache-as-ram teardown to use invd instead of wbinvd.
Save the return and recover the call's return address in
chipset_teardown_car.
CAR teardown had been modified to use wbinvd to send CAR contents
to DRAM backing prior to teardown. This allowed CAR variables,
stack, and local variables to be preserved while running the
AMD_DISABLE_STACK macro.
Using the wbinvd instruction has the side effect of sending all
dirty cache contents to DRAM and not only our CAR data. This
would likely cause corruption, e.g. during S3 resume.
Stoney Ridge now uses a postcar stage and this is no longer a
requirement.
BUG=b:64768556
Change-Id: I8e6bcb3947f508b1db1a42fd0714bba70074837a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20967
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Insert a postcar stage for Stoney Ridge and move romstage's CAR
teardown there.
The AMD cache-as-ram teardown procedure currently uses a wbinvd
instruction to send CAR contents to DRAM backing. This allows
preserving stack contents and CAR globals after the teardown
happens, but likely results in memory corruption during S3 resume.
Due to the current base of the DCACHE region, reverting to an
invd instruction will break the detection mechanism for CAR
migrated variables. Using postcar avoids this problem.
The current behavior of AGESA is to set up all cores' MTRRs during
the AmdInitPost() entry point. This implementation takes control
back and causes postcar's _start to clear all settings and set
attributes only for the BIOS flash device, TSEG, and enough space
below cbmem_top to load and run ramstage.
BUG=b:64768556
Change-Id: I1045446655b81b806d75903d75288ab17b5e77d1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relocate the call to AGESA in preparation for implementing postcar.
This change should have no net effect as long as the ordering is
maintained and AmdInitEnv stays later than CAR teardown.
BUG=b:66196801
Change-Id: I0e4a5fd979b06cf50907c62d51e55db63c5e00c5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Now that soc/amd supports EARLY_CBMEM_INIT, put the HEAP into cbmem,
allowing better control of its cacheability in subsequent patches.
This relocates the heap initialization from the common directory into
a romstage cbmem hook. The conversion relies on cbmem_add() first
searching cbmem for the ID before adding a new entry.
Change-Id: I9ff35eefb2a68879ff44c6e29f58635831b19848
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make GetHeapBase a static function. Change the type of return value to
a void pointer and remove the unused StdHeader argument. This should be
innocuous and will allow a subsequent patch to be simpler.
Change-Id: Id4a024d000a514ea9a44f9dfc2caffae9ff01789
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21593
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add an extra include file to northbridge.c for completeness. cpu/msr.h
is already included in cpu/amd/mtrr.h which allows the file to build
properly.
Remove include files that are no longer required for the file.
Change-Id: I3e5ab39fd0640d2983fc5b7b202fb65d42c5ce3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add necessary features to allow mp_init_with_smm() to install and
relocate an SMM handler.
SMM region functions are added to easily identify the SMM attributes.
Adjust the neighboring cbmem_top() rounding downward to better reflect
the default TSEG size. Add relocation attributes to be set by each
core a relocation handler.
Modify the definition of smi_southbridge_handler() to match TSEG
prototype.
BUG=b:62103112
Change-Id: I4dc03ed27d0d109ab919a4f0861de9c7420d03ce
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21501
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add a #define for TSEG as well as some register field definitions.
Change-Id: Iad702bbdb459a09f9fef60d8280bb2684e365f4b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21500
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Create an SMM_AMD64_SAVE_STATE_OFFSET #define similar to others in the
same file.
Change-Id: I0a051066b142cccae3d2c7df33be11994bafaae0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change the Stoney Ridge SOC to a more modern method for setting up
the multiple cores.
Add a new cpu.c file for most of the processor initiliazation. Build
mp_ops with the necessary callbacks. Note also that this patch removes
cpu_bus_scan. Rather than manually find CPUs and add them to the
devicetree, allow this to be done automatically in the generic
mp_init.c file.
SMM information is left blank in mp_ops to avoid having mp_init.c
install a handler at this time. A later patch will add TSEG SMM
capabilities for the APU.
This patch also contains a hack to mask the behavior of AGESA which
configures the MTRRs and Tom2ForceMemTypeWB coming out of AmdInitPost.
The hack immediately changes all WB variable MTRRs, on the BSP, to UC
so that all writes to memory space will make it to the DRAM.
BUG=b:66200075
Change-Id: Ie54295cb00c6835947456e8818a289b7eb260914
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Call into commmon SGX code to configure core PRMRR and follow
other SGX init seqeuence.
- Enable SOC_INTEL_COMMON_BLOCK_SGX for both GLK
- Enable SOC_INTEL_COMMON_BLOCK_CPU_MPINIT for GLK, as MP init needs
to be completed before calling into fsp-s for SGX.
Change-Id: I9331cf5b2cbc86431e2749b84a55f77f7f3c5960
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Refactor the GPIO functions to use GPIO numbers. This is more consistent
with other GPIO code in coreboot.
BUG=b:66462235
BRANCH=none
TEST=Build and boot Kahlee
Change-Id: I6d6af7f6a0ed9ba1230342e1ca024535c4f34d47
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It shares the same northbridge, cpu, romstage with asus/p2b-ls, which is
already on EARLY_CBMEM_INIT as of commit e14d7de.
Change-Id: I8e7c468f0363a5cb9885020bc116e5ae3480ec17
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Boot tested on p2b-ds. Migrate p2b-d as well because they share
the same mainboard romstage.
Change-Id: I3e4b98cc6191d557325fc5da97744902996673af
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is required to transmit button information from EC to kernel.
BUG=b:65980005
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I3cd524aec47ca988d6044cb089e7aa7636e64ab2
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Reviewed-on: https://review.coreboot.org/21633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
src/lib/loaders was removed in commit 899d13d0df ("cbfs: new API and
better program loading").
Change-Id: Ic7a9f5d83c5f9445bf24970e0c8cc645dd1944ff
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I triggered a bug, when I try to debug riscv code by spike.
This bug is caused by an instruction exception[csrwi 0x320,7].
This is operate for mcounteren. This address is error. 0x306
is right. scounteren is not need to be set, because S-mode
code controls it.
Change-Id: If0bea4bf52d8ad2fb2598724d6feb59dc1b3084a
Signed-off-by: wxjstz<wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
It makes no sense for Das U-Boot which uses the same setting.
Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/21611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Use reserved_ram_resource to help ensure the UMA memory is typed
as WB.
BUG=b:65856868
TEST=Inspect MTRRs and compare with UMA memory
Change-Id: Ifa54d9b1c206d2ee6dc4b8f90b445a6820ceb8fd
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21606
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EXT_CONF_SUPPORT symbol doesn't exist for the Stoney Ridge SoC.
Clean up northbridge.c by removing the check for the config value set.
Remove the CPU initialization code that clears the EnableCf8ExtCfg
bit. The location where it was set was removed in
c1d72942 Disable PCI_CFG_EXT_IO
BUG=b:66202622
Change-Id: Ic58c47fc5f568d17f5027c96d4152b0e5b3e1d14
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21497
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Delete the obselete Kconfig symbols regarding the memory hole. Integrate
the hole check into domain_set_resources(). The hardware configuration
is done by AGESA, so only discover the setting and adjust the mmio_basek
accordingly.
BUG=b:66202887
TEST=Check settings with HDT
Change-Id: Id15a88897e29bff28ab7c498dc4d3818834f08b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
A regression is hidden in commit 7eb0157fca
(device/dram/ddr2.c: Decoding byte[12] bit7 as self refresh flag ), which
breaks the build procedure when CONFIG_DEBUG_RAM_SETUP is set.
Maybe it had better implement "printram" and the like as inline
functions instead of macros.
Change-Id: If956435bd0c39b1f3e722c2cfc48d2d0f35abc9b
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/21673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of duplicating the code across multiple mainboards, provide a
helper function to read boardid from Chrome EC.
Change-Id: I2008de7032bc880e90b2c3c385b2a67bfb8724cc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
New AGESA support files will be used for binaryPI
platforms as well. Furthermore, some of those should
move from split nb/ sb/ directories to soc/, so move
support files for the API under drivers/.
Change-Id: I549788091de91f61de8b9adc223d52ffb5732235
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Except for family15, all AGESA boards have moved
away from AGESA_LEGACY_WRAPPER, thus they all
have POSTCAR_STAGE now.
AGESA family15 boards remain at AGESA_LEGACY=y, but
those boards have per-board romstage.c files and
are not touched here.
Change-Id: If750766cc7a9ecca4641a8f14e1ab15e9abb7ff5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move all boards that have moved away from AGESA_LEGACY_WRAPPER
or BINARYPI_LEGACY_WRAPPER to use POSTCAR_STAGE.
We use POSTCAR_STAGE as a conditional in CAR teardown to tell
our MTRR setup is prepared such that invalidation without
writeback is a valid operation.
Change-Id: I3f4e2170054bdb84c72d2f7c956f8d51a6d7f0ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This file mostly mimics Porting.h and should be removed.
For now, move it and use it consistently with incorrect form
as #include "cbtypes.h".
Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression of IDS debugging after commit
1210026 AGESA buildsystem: Reduce include path exposure
Mainboard directory was removed from libagesa includes
path here, and this resulted with fam15tn and fam16kb using
a template OptionsIds.h file under vendorcode/ instead.
Add mainboard directory back to include path of libagesa
and remove those (empty) template files.
Change-Id: Iee4341a527b4c152269565cac85e52db44503ea6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's already implemented like this with binaryPI API header.
That implementation is essentially the same with 'const' qualifier
just being ignored in the build process for PI blob.
For open-source AGESA build, work around -Werror=discarded-qualifier
using a simple but ugly cast.
Change-Id: Ib84eb9aa40f1f4442f7aeaa8c15f6f1cbc6ca295
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Copy-paste, was not really used at all.
Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17
is insufficient to use.
Using VPD to control could prevent H/W change.
BUG=b:65339688
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I55ab741354797e022dd945da9c8499ee5e041316
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
variant_board_sku() callback exists to allow some of the variants to
report the sku id differently based on board implementation. However,
there are cases where there are multiple ways to encode the sku id, but
the original way should be used as a fallback. As such expose a helper
function, sku_strapping_value(), such that there isn't code duplication
for the common fallback case.
BUG=b:65339688
Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update I2C5 bus parameters to obtain clock frequency <400kHz.
BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.
Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The x220 and x230 do have BDC detection, but it's broken.
Disable BDC detection on those two boards, and add a comment
why it doesn't work.
The issue has been reported and tested on Lenovo X220.
Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/21587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Dump PMH7 revision and ID for diagnostic purposes.
Tested on Lenovo T430: PMH7: ID 05 Revision 12
Change-Id: I60d15a8f740aeb974a79b27507e974a730cec174
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
SPD decoding problems are no longer a good method for detecting if i2c
byte read failed, since the return value of i2c_block_read is checked.
Change-Id: I230aa22964c452cf28a9370c927b82c57e39cc62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
We can't use $(CC) in case it's set to Clang.
TEST=Built one target with Ada sources before and after this change and
verified that the same compiler commands are emitted.
Change-Id: I9b8ea35352d74b364f09fc12d8d981ca42f8b7c8
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We don't output special ADAFLAGS in xcompile but its CFLAGS are
compatible with and necessary for Ada too. So use the latter and
make sure we use them for libgnat too.
Fixes i386 builds with x86_64 toolchain.
TEST=Gave libgfxinit a shot on lenovo/t420.
Change-Id: I0d13f182acfaa9bd1b608edd8a508c4ceedef3b3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The original options were named and described under the false assumption
that the chipset lockdown would only be executed during S3 resume. Fix
that.
Change-Id: I435a3b63dd294aa766b1eccf1aa80a7c47e55c95
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/21327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
For all valid SPD values the same decoded tRR was returned.
Change-Id: Iec43f8c7460dfcf68f7c92dfdf333b004f368b65
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Found-by: Coverity Scan #1381369, #1381370, 1381371, 1381372, 1381373
Reviewed-on: https://review.coreboot.org/21642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch implements soc override function to calculate reserve memory
size (PRMRR, TraceHub, PTT etc). System memory should reserve those
memory ranges.
BRANCH=none
BUG=b:63974384
TEST=Ensures DRAM based resource allocation has taken care
of intel soc reserved ranges.
Change-Id: I19583f7d18ca11c3a58eb61c927e5c3c3b65d2ec
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21540
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch uses BIOS EBDA area to store relevent details
like cbmem top during romstage after MRC init is done.
Also provide provision to use the same EBDA data across
various stages without reexecuting memory map algorithm.
BRANCH=none
BUG=b:63974384
TEST=Ensures HW based memmap algorithm is executing once in romstage
and store required data into EBDA for other stage to avoid redundant
calculation and get cbmem_top start from EBDA area.
Change-Id: Ib1a674efa5ab3a4fc076fc93236edd911d28b398
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides new APIs to write into EBDA area
and read from EBDA area based on user input structure.
Change-Id: I26d5c0ba82c842f0b734a8e0f03abf148737c5c4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch provides a kconfig option as EARLY_EBDA_INIT to
ensures user can make use of EBDA library even during early
boot stages like romstage, postcar.
Change-Id: I603800a531f56b6ebd460d5951c35a645fbfe492
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With reset default of the clockgen on this board the SATA clock which
needs to be 100MHz depends on FSB BSEL straps.
This explains why SATA was originally tested to be working but fails
with CPUs operating at different FSB.
This change sets a bit in the clockgen configuration which fixes the
SATA clock.
TESTED on with a 1333MHz FSB CPU.
Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
This patch adds the support for Kabylake Celeron base SKU
with PCH ID 0x9d50.
BRANCH=none
BUG=b:65709679
TEST=Ensure coreboot could recognize the Kabylake Celeron base
SKU and boot into OS.
Change-Id: I9c6f7bf643e0dbeb132fb677fcff461244101a55
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Wu <david_wu@quantatw.com>
Reviewed-by: T.H. Lin <T.H_Lin@quantatw.com>
Unlike Chromebooks, Purism laptops are only sold under one vendor name,
so MAINBOARD_VENDOR only needs to be set in src/mainboard/purism/Kconfig.
Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21591
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants
Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/banon (Acer Chromebook 15 CB3-531) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new banon variant
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Gardenia (with Stoney Processor) has a single memory channel, not two.
This corrects DMI type 17 reporting and the memory clear functions.
Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21602
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once w83627hf_set_clksel_48() is unified into
winbond/common/early_init.c by /c/21331 (Unify w*_set_clksel_48()),
this file is no longer needed and can be dropped.
Build tested on select affected mainboards.
Change-Id: I6a5e27fdd48c6e002c3a39dc92fef77e85aea209
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It is already using winbond_enable_serial(). Once
w83697hf_set_clksel_48() is unified into winbond/common/early_init.c,
this file is no longer needed and can be dropped.
Change-Id: I7424233b5d70e143721038493f194760f07346a1
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This function is identical throughout all Winbond superios in
the tree, so move it into superio/winbond/common/early_init.c,
renamed from early_serial.c because it now does more than just
early serial.
Change all affected mainboards to use the unified function.
Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
IRQ 9 is used for different purpose on this mainboard so move SCI away
to IRQ 10.
Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The System Control Interrupt is routed per default to IRQ 9. Some
mainboards use IRQ 9 for different purpose. Therefore it is necessary to
make the SCI configurable on Apollo Lake.
Change-Id: Ib4a7ce7d68a6f1f16f27d0902d83dc8774e785b1
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable LTR for Root port 0, where wifi card is connected.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are a lot errors reported by AER driver for root port 0.
The erors are being caused by an unsupported request from the
device to the upstream port. Enabling LTR on the root port stops
these errors, it is because LTR is enabled on the device side but
not on the root port and hence root port was logging the LTR messages
from the device as unsupported.
The PCIe base spec (v3.1a) section 6.18 also states that:
LTR support is discovered and enabled through reporting and control
registers described in Chapter 7. Software must not enable LTR in an
Endpoint unless the Root Complex and all intermediate Switches indicate
support for LTR. Note that it is not required that all Endpoints support
LTR to permit enabling LTR in those Endpoints that do support it. When
enabling the LTR mechanism in a hierarchy, devices closest to the
Root Port must be enabled first.
If an LTR Message is received at a Downstream Port that does not
support LTR or if LTR is not enabled, the Message must be treated
as an Unsupported Request. FSP has a UPD for enabling/disabling
LTR on root port, use the same for configuring LTR on PCIe root ports.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: Ica97faa78fcd991dad63ae54d2ada82194b4202a
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In coreboot commit bcd0bdabed (soc/intel/cannonlake: add rtc failure
checking), the function soc_get_rtc_failed was supposed to be moved,
but the old function was not removed, causing a build error.
BUG=b:63054105
Change-Id: I31c1966af413df3f5a5492a5dd891a6eb26a1fc4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It's helpful to use the common vbnv_reset() function to
initialize the vbnv contents when backing store failures occur.
Therefore, allow that to happen.
BUG=b:63054105
Change-Id: I990639e8c163469733fdab0d3c72e064acc9f8d8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to early_pch_common.c and
add a helper function to determine if failure occurred.
BUG=b:63054105
Change-Id: I710d99551cfb6455244f66b47fcbecc790ae770f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I368c31b9935c0fa9e8a1be416435dd76f44ec1ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ic4bf99dc3a26fbc3bd508e484963b9298ef1b24b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I1d90cc557225ddbba1787bf95eae0de623af487e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I88bf9bdba8c1f3a11bc8301869e3da9f033ec381
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21554
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred. In addition actually
provide soc_get_rtc_failed() which properly indicates to the common
code that RTC failure did occur in the cmos_init() path.
BUG=b:63054105
Change-Id: I9dcb9377c758b226ee7bcc572caf11b7b2095425
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: Ia0a38f00d2a5c7270e24bdd35ecab7fbba1016d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to prepare for checking RTC failure in the early boot
paths move the rtc failure calculation to pmutil.c and add a helper
function to determine if failure occurred.
BUG=b:63054105
Change-Id: I1b02028a1830ff9b28b23da7a4a1fd343f329f0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add vbnv_init() which is responsible for doing any vbnv initialization
and reading the vbnv contents. Having this function allows for
putting vbnv backing store specific support in the main vboot logic
path.
BUG=b:63054105
Change-Id: Id8f0344e5de5338417ae2e353ae473d6909c860a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21550
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of having each potential caller deal with the differences
of cmos_init() and init_vbnv_cmos() when VBOOT is enabled put the
correct logic within the callee, cmos_init(), for handling the
vbnv in CMOS. The internal __cmos_init() routine returns when the
CMOS area was cleared.
BUG=b:63054105
Change-Id: Ia124bcd61d3ac03e899a4ecf3645fc4b7a558f03
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21549
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Linux Pstore area must not be cleared on a reboot. Set the option
to not clear the memory in AGESA.
BUG=b:64193190
BRANCH=none
TEST=Memory clear isn't called in AGESA.
Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21596
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee has a single memory channel, not two. This corrects DMI type 17
reporting and the memory clear functions.
BUG=b:65403853, b:64193190
BRANCH=none
TEST=AGESA DMI reports the correct number of DIMMs.
Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch outputs decoding errors with BIOS_WARNING instead of
depending on CONFIG_DEBUG_RAM_SETUP.
Returns SPD_STATUS_INVALID on invalid settings for tRR, bcd and tCK
and doesn't try to create a valid setting if an invalid setting is
detected.
Change-Id: Iee434d1fa1a9d911cc3683b88b260881ed6434ea
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This simplifies computing dram timings a lot.
This removes computation of rank size based on columns, rows,
banks,... and uses the information in SPD byte 31. The result of this
is that dimms with multiple asymmetric ranks are not supported
anymore. These however are very rare and most likely never tested on
this platform.
This also uses i2c block read instead of byte read to speed up the
raminit. The result is less time is being spend reading SPDs.
It still keeps smbus read byte as a backup if i2c block read were to
fail.
Change-Id: I97c93939d11807752797785dd88c70b43a236ee3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add PMC pci driver on top of PMC common code, also include pmc init code
reference from skylake.
Change-Id: I95895a3e26cdebd98a4e54720bd4730542707d7e
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The ACPI spec requires devices with children to have an HID,
and Windows enforces this strictly. Without the SIO device
having an HID, Windows will not detect the attached PS2 keyboard
and trackpad. Therefore, add the proper HID.
TEST: boot Windows on google/stout, observe PS2 keyboard and
trackpad detected and functional.
Change-Id: I61d7341c15483f8e1fe0e485a25591ceb92eaae1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ToString() requires the input buffer data to be null-terminated,
but the data returned by the EC is not, leading Windows to fail
to report any battery data at all. Correct this by concatenating
a null terminator (0x00) to the end of the buffer data before
inputting to ToString() where needed
TEST: boot Windows on google/stout, observe battery data
reported correctly.
Change-Id: I974afcd6ff1c617301d0897d6bd1fe14200aa3b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
EC ACPI code is calculating the drain rate, but does not store it
in the battery status package before returning it. Correct this
omission, and set the drain rate to a preset minimum if calculated
value is less. Taken from vendor firmware ACPI dump.
Change-Id: I52837d5879112ab3103976bda28906fac8f880ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
me_cleaner now allows setting a bit in the PCH straps - AltMeDisable
tells the ME to stop execution after BUP - disabling the 30 minute
watchdog - but also "breaking" the ME. The ME reports opmode = 2.
This means the ME will not respond when we wait for an acknowledgement
about the DRAM being ready. The current code waits 5 seconds for a
response, that in this case, never comes.
If the ME is reporting opmode 2, don't delay or wait for a response
from the ME.
Tested on my X220, this patch fixed the five seconds before the payload
executed. Verified using the timestamp patch.
Change-Id: Ifdda6b2dbb8ae3a650be6d5df6c60475a3fa74aa
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to clang, main has no prototype for bcom/winnetp680
so add it into corresponding raminit.h
Change-Id: I8a55267901986757a4fa88ee13460ffbed3eeadc
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.
BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.
Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set keyboard backlight to 75% on boot, except when resuming
from S3. This enables the backlight at a reasonable level
prior to the OS driver taking over, providing early proof-of-life
and enhanced usability in grub etc.
Uses same method as other google boards with a keyboard backlight
(chell, link, samus). 75% value determined based on user feedback.
TEST: boot google/lulu,gandof boards, observe keyboard backlight
enabled in pre-OS environment.
Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/reks (Lenovo Chromebook N22/N42) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new reks variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-reks-7287.133.B,
commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
variants other than cyan
Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data
Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Bit 7 is set on all options so only the default option in the switch
statement is returned.
Change-Id: I6a698ec9c15a2611a34c5965edf93638553775f0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Add EC entries into chromeos.fmd file.
BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in
coreboot does not match intel flash map generated from fit.
Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UNCORE PRMRR BASE and MASK MSRs are not common, so move to
SOC specific header file and rename the #define to start with MSR_*
Change-Id: I799c43f0b7a9eec5b3b69ab0f5100935c7f3f170
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use soc_get_uncore_prmmr_base_and_mask() API to get PRMRR base and mask.
Change-Id: I2fd96607c4f5fed97e38087b60d47d6daacc7646
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21246
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To remove chip.h dependency from SGX common code
- Create API soc_fill_sgx_param() and use it in sgx.c
- Implement same API for skylake/kabylake
- define sgx_param structure
Also include intelblocks/sgx.h instead of soc/msr.h
Change-Id: I358f0817bec5dd6cd147a645675b5688969a04e0
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There are old legacy onboard devices which are too slow for a coreboot
boot with log level BIOS_ERR. In this case coreboot is so fast that these
devices do not have enough time to become visible on the PCI bus and
this in turn leads to missing resource allocation for this devices. The
most generic way to work around this problem on existing hardware is to
introduce a delay right before the PCI enumeration starts. The needed
delay time depends on the hardware and will therefore be get from
hwinfo.
Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Add a function to retrieve the elapsed time since boot. For that purpose
use the base time in the timestamp table among with the current
timestamp at call time of the function. So more precise the returned
time is the elapsed time since the timestamp was initialized scaled
in microseconds. This was chosen to get a reliable value even on
platforms where the TSC might not be reset on software reset or warm
start.
Change-Id: Ib93ad89078645c0ebe256048cb48f9622c90451f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There's no reason to mutate the struct device when determining
the ACPI name for a device. Adjust the function pointer
signature and the respective implementations to use const
struct device.
Change-Id: If5e1f4de36a53646616581b01f47c4e86822c42e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was originally designed such that if usbdebug_init() was called
before cbmem_initialize(), it would fetch the already-initialized
state from CBMEM. This changed when cbmem_find() behaviour changed
to require cbmem_initialize() to be called first. As a result,
ramstage had to reinitialize all of the EHCI controller and USB
endpoints on entry. This was slow, specially with AMD hardware
where one can scan USB ports to probe for the debug dongle.
For postcar and ramstage, move usbdebug entry such that it is
triggered from CBMEM_INIT_HOOK instead of console_init().
Side-effect of this is usbdebug console shows 'coreboot-xxx ...
starting...' line only for romstage.
Initialisation for usbdebug is never done in postcar. If you have
USBDEBUG_IN_ROMSTAGE=n, postcar will not have console output on
usb either.
While at it, fix also some other __PRE_RAM__ cases to ENV_ROMSTAGE
and alike.
Change-Id: If8ab973321a801abc5529f3ff68c5dccae9512ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All thse Option.*Install.h files are about configuring
what eventually is referenced in the final libagesa
build. It's self-contained so isolate these together
with PlatformInstall.h to hide them from rest of
the build.
Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
One liner that fixes a warning with clang
Change-Id: I4d7dfaa5fcf0e95acd650e4c129e0899b5d68f09
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There were two copies of the same definitions in the file.
Change-Id: Iafb10476f32505f6b4ad7b5ba6fa5de2c4648836
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
To avoid error with symbol redefinition (using clang):
src/drivers/intel/fsp1_0/fsp_util.c:111:22: error: invalid symbol redefinition
".global find_fsp\n\t"
Rename the asm global symbol to find_fsp_bypass_prologue and fix jmp.
Change-Id: I84c152f9a580fdfc40e9f6e998d2d6484b7f47df
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/21353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fine tune usb 2.0 strength for port 4 to pass eye diagram.
BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.
Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Stoney Ridge APU can never be used in a multi-node system. Reduce
the feature set to a single node.
Remove the static variables for each D18Fn device and replace the routines
with coreboot config read and write functions.
Strip down domain_set_resources() to consider only a single node. A
follow-on patch will further simplify this.
Change-Id: I1982b3fbf8dbb44ca75112c57afa59a2b4e4cf5a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove the check for the southbridge link from Stoney Ridge. The APU
is an SoC which can never be installed in a multi-node system. It is
pointless to detect and remember the sblink value, which is set by
hardware and comes up 0. The BKDG marks this as a reserved field vs.
documentation for multi-node-capable Family 15h devices.
Because there is only one option for SB link now, relocate the register
write done by set_vga_enable_reg() and remove the function.
Change-Id: Ie4ce6b5aa847a184534224db302437ff8d37c14b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Delete the check for sibling cores and the programming of CPUID HTT
and CmpLegacy back-door bits. The code has no effect on modern
Family 15h APUs. The bits being modified come up set out of reset.
Change-Id: Ida76863d84109b49ce6b12c71bad5b44331a2ff9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the step of setting PSP BAR3 from cpu_dev_ops .init. The
BAR is configured in romstage by AmdInitPost().
Change-Id: I7e77fad3abdcb6482f1b9d849e5922a426dff5f5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make the default for SMM_TSEG_SIZE depend on SMM_TSEG in addition to
HAVE_SMI_HANDLER.
Change the value returned by cbmem_top() to carve out a range to be
used by TSEG. The SMM Mask register has a granularity of 128KB but
align the value to 16MB to keep down the number of variable MTRRs
required.
Change-Id: I54ffc10108862b7d022fbbd92bf97525b349df27
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use fixed resources for LPSS uart devices for debugging purpose.
BUG=NONE
BRANCH=NONE
TEST=Boot up with coreboot rom, without this changes, serial log will
stop print anything during PCI resourcre setup as MMIO address of UART
will be re-assigned.
Change-Id: Ib773e01d5f5358f13297400075d6920793200b88
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These two boards have been boot tested with EARLY_CBMEM_INIT
and is good to go.
Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21351
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Implement cbmem_top() required for cbmem support in romstage.
Boot tested on asus/p2b-ls. Boards to move to this setup in
followup patches.
Change-Id: I432f145a5343c1bb5f2b0de3b6b88f57124d1bd9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20977
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
EC needs to have command to set SKU ID from APU to support
specific feature (ex: keyboard backlight) for variant board.
BUG=b:65359225
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8cd3b8f646d4134d6bfff2869f6df2d9c615c157
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new parameter to hwilib called LegacyDelay. It will be used to
define a delay time to wait for legacy devices if coreboot is too fast
for old and slow onboard devices.
Change-Id: Id0386fdea0ecfb3c1ff6ec1c456071246529950a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/21517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a timestamp before and after waiting for the ME to acknowledge the
DRAM being ready.
This allows easier debugging during use of me_cleaner and/or alternate
ME images.
Change-Id: Ie228e12a75d373b4f406b3595e1fb1aab41aa5df
Signed-off-by: Nathaniel Roach <nroach44@gmail.com>
Reviewed-on: https://review.coreboot.org/21465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch fixes the build issue by replacing UART_DEBUG_BASE_ADDRESS
macro with UART_BASE_0_ADDR macro to configure LPSS UART base adress
for ACPI debug prints.
TEST= Build and boot soraka and fetch the ASL debug prints.
Change-Id: Ib31174701c56c88829ae0e725b546b66ea1ed16d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21513
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Basic ACPI support for CNL on top of common ACPI, which will establish
a root of FADT table, fill MADT entry, create gnvs field, record wake
status and convert device names into DSDT dev definitions.
Change-Id: Ibc16d2afdd3cb9bad2ecb85cf320c88504409707
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21076
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch makes coreboot set VBSD_EC_EFS flag if CONFIG_VBOOT_EC_EFS
is set. Depthcharge/Vboot uses this flag to determine whether it can
update EC when it's already running a RW copy.
BUG=b:65028930
BRANCH=none
TEST=Verify soft sync runs successfully on Fizz.
Change-Id: Ic51ddd4819262162a8d8519461c4ace57ee01cb5
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21489
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This board uses the reset defaults for DxxIP and DxxIR.
The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family"
mistakenly says in the D31IP register that all function have INTB as
default. This is however not true as documented in the reset default
value.
This fixes the DSDT such that the SMBus device gets a route for the
INT C interrupt it uses.
Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21442
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED: NGI works on VGA with adapter on DVI-I port
Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This makes the VGA output on the DVI-I connector usable.
This reuses vendor settings.
Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For boards with cimx/sb800, mainboards defined only empty
stubs. Reset functionality is handled as BiosCallout.
For amd/inagua, the defined function was actually initial
GPIO programming.
For cimx/sb700, function had prototypes but no callers.
For cimx/sb900, everything was commented out already.
Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Because cpu/intel/car/romstage.c assumes a 8KiB stack size
when setting up stack guards, and all Slot 1 compatible
CPUs have enough L1 cache available for the increase.
Adjust DCACHE_RAM_BASE to match.
Boot tested on asus/p2b-ls and asus/p3b-f using a 1400MHz
Tualeron. The latter actually requires this patch to boot
successfully.
Change-Id: I5b440e7be4f3149378db88872872012c92049c20
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Make all CAR-related calculations refer to CONFIG_DCACHE_RAM_BASE
and CONFIG_DCACHE_RAM_SIZE for consistency.
Do not set %ebp before and switch directly to stack returned by
romstage_main().
Remove an unneeded 4-byte gap in CAR stack.
The caching strategy for flash XIP area should be WRPROT.
Clarify the various comments in the file on the logic.
Together they lay the groundwork for bringing EARLY_CBMEM_INIT to
intel/slot_1 boards.
Change-Id: Ibb6cf6a2adbe3a1f28bf2903d852ddc19e09b484
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21503
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove CAR testing code currently blocked out by #if. Newer CAR code
don't even do it anymore.
Change-Id: I2d53b4e7a244824c7aa2c0f597ed91e17f6cc668
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21502
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove Hyperthreading related code that was missing setup of SIPI
vector and did not work.
Change-Id: I27e329a7b667ce4405fe07a637edbc6b5be22f2d
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/21375
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add support for detecting WWAN.
* Allows to turn off power to WWAN if no card is installed.
Add the following devicetree values:
* has_wwan_detection
Set to one to indicate that the following register are sane.
* wwan_gpio_num
SB GPIO num to read.
* wwan_gpio_lvl
SB GPIO level for card to be present (usually zero).
Don't enable WWAN power if no card is detected.
As there are no devicetree values yet, the new code doesn't have any effect.
Change-Id: Ie53275b384c85df8adf71fe79b3d54211c868756
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Add support for BDC detection, based on the schematics for each board.
Support for boards without schematics needs further testing.
Needs test on all boards.
Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Move rtc init code into common area and update the implementation for
apollolake to avoid build break.
Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The RO_VPD region is required for ChromeOS.
BUG=b:65408869
TEST=Build and check coreboot.rom with fmap_decode.
Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
With AMD_INIT_ENV and AMD_INIT_S3LATERESTORE moved
from romstage to ramstage, heapamanager in romstage
is no longer needed.
Change-Id: Iea8ad3ddb245c83dd290436ac9d4ecac9350b88c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CONFIG_MAINBOARD_VENDOR is customizable by OEM for Chrome OS
devices. However, VBOOT_FWID_MODEL indicates the firmware vendor and
hence if CHROMEOS is selected, then VBOOT_FWID_MODEL should always
prefix "Google_" instead of CONFIG_MAINBOARD_VENDOR.
BUG=b:65493192
Change-Id: I0a2280bfd6d535586bc14d9a3c4a8198287f08bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig.
- Remove 2nd set of variables that are duplicates of the first set.
- Delete duplicate set of Prerequisites
Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21451
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Adapted from Chromium commit 9756af8.
Add SOC helper to identify BSW SoC stepping. Will be used to
override USB2 phy setting based on stepping in subsequent commit.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With FSP 1.1, all FSP blobs are forward-compatible with newer FSP 1.1
header files, so adjust the header revision check to ensure that the
FSP blob isn't newer than the header, rather than an exact version match.
This resolves a version mismatch issue with Braswell ChromeOS devices,
which ship with FSP blobs newer than the publicly-released blob (1.1.2.0),
but older than the current Braswell FSP 1.1 header (1.1.7.0).
TEST: build/boot google/cyan and edgar boards, observe no adverse
effects from using current FSP header (1.1.7.0) with the factory-
shipped FSP blobs (1.1.4.0/1.1.4.2).
Change-Id: I8934675a2deed260886a83fa34512904c40af8e1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the common acpi code.ACPI code is very similar
accross different intel chipsets.This patch is an effort to
move those code in common place so that it can be shared accross
different intel platforms instead of duplicating for each platform.
We are removing the common acpi files in src/soc/intel/common.
This removes the acpi.c file which was previously in
src/soc/common/acpi. The config for common acpi is
SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's
Kconfig file in order to use the common ACPI code. This patch also
includes the changes in APL platform to use the common ACPI block.
TEST= Tested the patch as below:
1.Builds and system boots up with the patch.
2.Check all the ACPI tables are present in
/sys/firmware/acpi/tables
3.Check SCI's are properly working as we are
modifying the function to override madt.
4.Extract acpi tables like DSDT,APIC, FACP, FACS
and decompile the by iasl and compare with good
known tables.
5.Execute the extracted tables in aciexec to check
acpi methods are working properly.
Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
APL internal UARTs are not used on this mainboard.
Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
There is one on-board PCI device where bus master has to be enabled in
PCI configuration space. As there is no need for a complete PCI driver
for this device just set the bus master bit in mainboard_final().
Change-Id: I45202937eba11da3bea14fef6ebed70599804335
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/21405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Boards with CBMEM_TOP_BACKUP=y can also use POSTCAR_STAGE
for MTRR setup after adding this file in the build.
Change-Id: I5f9a673ff59ccfbba16308d27f653f5cf3b49017
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Postcar failed when loading from stage_cache, if
romstage did not pass same pcf->stack on normal
and resume paths.
Change-Id: I853afb1fbdb942fd671d89950911c850c96e3af3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The change allows to update rmodule parameters after
it has been loaded from stage cache.
Change-Id: Ib825ffe245d447ad3a8246f7dbd52c6e34103a0c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch implements soc function to get previous sleep state
using chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix the warnings of klocwork scan.
e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159"
Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Vendorcode expects some DRAM controller registers to
be writable, but they are actually locked after soft
resets if C6 states are enabled.
Without the workaround, raminit fails on soft resets.
Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's too critical to ignore when sending the message on
SMBus fails, so allow for a fair amount of retries.
Failure here causes watchdog to do hard reset later.
Move it out of mainboard.c as we need to call this
early in romstage while we are debugging.
Change-Id: I1006b079269d6dd44de630db7a5694124af2f974
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression caused by commit
9e94dbf ACPI: Get S3 resume state from romstage_handoff
Boards with EARLY_CBMEM_INIT are required to provide
romstage_handoff structure to signal S3 resume path.
Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Fix regression caused by commit:
714709f AMD fam10 ACPI: Use common fixed sleepstates.asl
Adding common sleepstates.asl got lost in rebase process.
Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change list adds imon and vmon slot numbers as params for
Maxim 98927 driver. These values are looked up in the kernel driver
to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I21d72ba91af83782587f11018b2d1d1c8d4f676c
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There was already a uart.c added to bootblock. Remove the
duplicate addition.
Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kyösti Mälkki