Commit graph

7289 commits

Author SHA1 Message Date
Sean Rhodes
e633d37000 soc/intel/cometlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I579f85e84e0aba7f192ff81a6725d65b7f79ff75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74517
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 12:27:39 +00:00
Julius Werner
6e303aa89b cbfs: Allow controlling decompression of unverified files
This patch adds a new Kconfig that controls whether CBFS APIs for
unverified areas will allow file decompression when CBFS verification is
enabled. This should be disallowed by default because it exposes the
attack surface of all supported decompression algorithms. Make
allowances for one legacy use case with CONFIG_SOC_INTEL_CSE_LITE_
COMPRESS_ME_RW that should become obsolete with VBOOT_CBFS_INTEGRATION.

Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ieae420f51cbc01dae2ab265414219cc9c288087b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75457
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-06-19 12:27:15 +00:00
Mario Scheithauer
3f1e034835 soc/intel/apollolake: Switch to snake case for SataPwrOptimizeDisable
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPwrOptimizeDisable'.

Change-Id: I35b36f60d2f00bfad307dff7bd131c20ebccf60b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75859
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:10:32 +00:00
Mario Scheithauer
c7beb4f317 soc/intel/apollolake: Switch to snake case for DisableSataSalpSupport
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.

Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:10:19 +00:00
Mario Scheithauer
53ad07a1ec soc/intel/apollolake: Switch to snake case for PmicVdd2Voltage
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicVdd2Voltage'.

Change-Id: I179b8f5b56c5bfe7f6fc3148e4c95954c0755ffd
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75857
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:10:05 +00:00
Mario Scheithauer
8c822189bd soc/intel/apollolake: Switch to snake case for ModPhyVoltageBump
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'ModPhyVoltageBump'.

Change-Id: Ic1e743e23bdfc45588411c584eecb839cc552faf
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75856
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:09:47 +00:00
Mario Scheithauer
16d1eb68d2 soc/intel/apollolake: Switch to snake case for ModPhyIfValue
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'ModPhyIfValue'.

Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:09:36 +00:00
Mario Scheithauer
feafddba8e soc/intel/apollolake: Switch to snake case for DisableComplianceMode
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableComplianceMode'.

Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-19 11:09:19 +00:00
Mario Scheithauer
1bbdd0ad01 soc/intel/apollolake: Switch to snake case for PmicPmcIpcCtrl
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicPmcIpcCtrl'.

Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:09:08 +00:00
Mario Scheithauer
67fa483235 soc/intel/apollolake: Switch to snake case for SataPortsHotPlug
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsHotPlug'.

Change-Id: I8fc8b30ac2c182ffaf2dee37e0116e27071b6a2c
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75852
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 11:09:03 +00:00
Mario Scheithauer
54fda51e0c soc/intel/apollolake: Fix FSP SATA speed limit configuraion
With commit f165bbdcf0 ("soc/intel/apollolake: Make SATA speed limit
configurable") came the expansion to adjust the SATA speed.
Unfortunately, APL FSP-S sets only the default value, so Gen 3, and
ignores the passing parameter value. Since the corresponding register
entry can only be changed once, the setting must be made on coreboot
side before FSP-S is called. This patch fixes the SATA speed
configuration for Apollo Lake CPUs.

Link to Intel Pentium and Celeron N- and J- series datasheet volume 2:
https://web.archive.org/web/20230614130311/https://www.intel.com/content/www/us/en/content-details/334818/intel-pentium-and-celeron-processor-n-and-j-series-datasheet-volume-2.html

BUG=none
TEST=Boot into Linux and check SATA configuration via dmesg

ahci 0000:00:12.0: AHCI 0001.0301 32 slots 1 ports 3 Gbps 0x1 impl SATA
mode
ata1: SATA max UDMA/133 abar m2048@0x9872a000 port 0x9872a100 irq 126
ata1: SATA link up 3.0 Gbps (SStatus 123 SControl 300)

Change-Id: I6f55f40941fa618e7de13a5cefe9e17ae34c5c99
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75820
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-19 08:46:45 +00:00
Eric Lai
884a70b379 soc/intel/meteorlake: Update tcss_usb3 alias
TCSS and TBT use the same lane on schematic. Update the port start
from 0 to match the Intel schematic. You can better follow the it
without convert the port number.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-17 02:37:47 +00:00
Ronak Kanabar
8e38a67bac soc/intel/meteorlake: select UDK_202302_BINDING Kconfig
MTL FSP uses 202302 Edk2. select UDK_202302_BINDING Kconfig for MTL SoC.

BUG=b:261689642
TEST= Build and boot to Google/rex.

Change-Id: I9167e3b08a2a1fa2f4cc6ca11cb8308dc56fd940
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75728
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16 18:50:17 +00:00
Pratikkumar Prajapati
42f7dc7493 soc/intel/common: Add configs for TME exclusion range and new key gen
Add following config options.

1. TME_GENERATE_NEW_KEY_ON_WARM_BOOT
   Program Intel TME to generate a new key for each warm boot. TME
   always generates a new key on each cold boot. With this option
   enabled TME generates a new key even in warm boot. Without this
   option TME reuses the key for warm boot.

2. TME_EXCLUDE_CBMEM_ENCRYPTION
   This option allows to exclude the CBMEM region from being encrypted
   by Intel TME. When TME is enabled it encrypts whole DRAM. TME
   provides option to carve out a region of physical memory to get
   excluded from encryption. With this config enabled, CBMEM region
   does not get encrypted by TME. If TME is not programmed to generate
   a new key in warm boot, exclusion range does not need be programmed
   due to the fact that TME uses same key in warm boot if
   TME_GENERATE_NEW_KEY_ON_WARM_BOOT is not set. But if TME is
   programmed to generate a new key in warm boot, contents of the CBMEM
   get encrypted with a new key in each warm boot case hence, that leads
   to loss of CBMEM data from previous warm boot. So enabling this
   config allows CBMEM region to get excluded from being encrypted and
   can be accessible irrespective of the type of the platform reset.

Bug=b:276120526
TEST=Able to build rex

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: Id5008fee07b97faadc7dd585f445295425173782
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75625
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-16 14:14:25 +00:00
Subrata Banik
82226f6e5c soc/intel/meteorlake: Disable ACPI PM timer using IOE.PMC
This patch disables the ACPI PM timer which is necessary for XTAL OSC
shutdown. Also, disabling ACPI PM timer switches off TCO.

BUG=b:274744845
TEST=Able to boot and verify S0ix is working even with EC reset and
cold boot scenarios.

w/o this cl:
> iotools mmio_read32 0xfe4018fc
  0x0

w/ this cl:
> iotools mmio_read32 0xfe4018fc
  0x2

Change-Id: Ibb6e145f67dba7270e0a322ef414bf1cb09c5eda
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-16 08:04:06 +00:00
Eric Lai
b15946d72c soc/intel: Add max memory speed into dimm info
Add MaximumMemoryClockSpeed if FSP have it, otherwise pass 0.

TEST=check dmidecode dump the max speed.
Handle 0x000C, DMI type 17, 40 bytes
Memory Device
        Array Handle: 0x000A
        Error Information Handle: Not Provided
        Total Width: 64 bits
        Data Width: 64 bits
        Size: 16 GB
        Form Factor: SODIMM
        Set: None
        Locator: Channel-0-DIMM-0
        Bank Locator: BANK 0
        Type: DDR5
        Type Detail: Unknown Synchronous
        Speed: 5600 MT/s
        Manufacturer: Micron
        Serial Number: 3f064d84
        Asset Tag: Channel-0-DIMM-0-AssetTag
        Part Number: MTC8C1084S1SC56BG1
        Rank: 1
        Configured Memory Speed: 5200 MT/s
        Minimum Voltage: 1.1 V
        Maximum Voltage: 1.1 V
        Configured Voltage: 1.1 V

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I854474bce8d6ed02f47f6dce8585b3ddfae73f80
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75810
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15 15:08:12 +00:00
Michał Żygowski
3d51e83347 soc/intel/*/include/soc/pmc.h: Add missing periodic SMI rate bits
Based on:

- Apollo Lake datasheet Vol. 3 Revision 005:
  https://cdrdv2.intel.com/v1/dl/getContent/334819
- 7th Generation Intel Processor Families I/O for U/Y Platforms
  Datasheet Vol.2 August 2017:
  https://cdrdv2.intel.com/v1/dl/getContent/334659
- edk2-platforms source for Whitley and Purley platforms (Xeon SP)

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ic600d39d49135808dd1f571c9eff3cdb98682796
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15 14:14:05 +00:00
Michał Żygowski
c68456ee4b soc/intel/apollolake: Select PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Select
PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to indicate the register
difference.

Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If182e1285ad6bd3f7c54760440010c50f57f7013
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72072
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15 13:58:44 +00:00
Michał Żygowski
0d28b978e5 intel/cmn/smm: Introduce PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B
Certain chipsets/SoCs like Apollo Lake use GEN_PMCON_B for periodic SMI
rate selection unlike other chipsets which use GEN_PMCON_A. Introduce new Kconfig option PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B to
indicate the register difference.

Based on Apollo Lake datasheet Vol. 3 Revision 005:
https://cdrdv2.intel.com/v1/dl/getContent/334819

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I11241836ecc9066d323977b030686567c87ed256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-15 13:57:29 +00:00
Subrata Banik
f27a41f207 soc/intel/cmn/cse: Read ISH FW version if avilable in CSE partition
This patch reduces the redundant config check to understand if an ISH FW
partition is available and to fetch the ISH FW version.

The goal is to fetch the ISH FW version if the ISH FW belongs to the CSE
firmware partition table.

Change-Id: I689a71377e7aea0fa3bc1835f355708c33c2caea
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75811
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15 07:39:38 +00:00
Dinesh Gehlot
225d9c1af4 soc/intel/cmd/blk/cse: Hook get CSE RW version into .final
This patch calls get CSE RW version function from .final hook if
the platform has required config (`SOC_INTEL_CSE_LITE_SKU`) selected.

BUG=b:280722061
TEST=Able to build and boot google/rex.

> cbmem -c | grep "CSE RW Firmware Version:"
[DEBUG]  CSE RW Firmware Version: 18.0.0.1682

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ifdb82c180b64fbb4575932427be54f544e1c98d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75749
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-15 07:39:11 +00:00
Subrata Banik
3c06f1e522 soc/intel/cmn/cse: Always save CSE RW version to CBMEM
This patch renames `cse_store_rw_fw_version` function that store
currently running CSE RW FW version inside CBMEM.

Additionally, perform the CSE RW FW storing operation unconditionally.

TEST=Able to build and boot google/marasov.

Change-Id: Iba85807b7d9e6f067b5b628c6fa062fab5c485e0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15 07:38:59 +00:00
Subrata Banik
272ce9a579 {driver, mb, soc}: Rename Intel CSE FPT config to ISH FW version config
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config
to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config
is clear.

Any platform would like to fetch the currently running ISH firmware
version should select this configuration.

TEST=Able to build and boot google/marasov.

Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-15 07:38:47 +00:00
Michał Żygowski
2fffb5df88 soc/intel/alderlake/vr_config.c: Fix GT domain TDC current
Alder Lake-S 2+0 SKUs and 35W SKUs have 20A GT TDC, all other Alder
Lake-S SKUs have GT TDC of 22A.

Based on the default settings of ADL-S FSP.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ie6851d322fc9354d019a76503c3d35b5e6eca48b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-06-14 21:16:15 +00:00
Jeff Li
575eb73951 soc/intel/xeon_sp: Fix HEST table length
"current" points to the start of HEST table, so "next - current" already
includes the size of its header, no need for increment here. This issue
was found on SPR-SP platform. The length of HEST table is now correct
with this patch.

Change-Id: I6ff1e8e24612b7356772d582ff9a7e53863419db
Signed-off-by: Jeff Li <lijinfeng01@inspur.com>
Signed-off-by: Ziang Wang <ziang.wang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75738
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-06-14 09:53:57 +00:00
Pratikkumar Prajapati
ea66c9899b soc/intel/common: Make get_ramtop_addr non static
Make get_ramtop_addr not static to allow other code to use it.

Bug=b:276120526
TEST=Able to build rex

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I8ef8a65b93645f25ca5e887342b18679d65e74b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-07 22:00:47 +00:00
Pratikkumar Prajapati
e4893d6b80 soc/intel/common/crashlog: Add support for IOE die
Intel Meteor Lake SOC has a separate I/O Expander (IOE) die.
SRAM from this IOE die contains crashlog records for the IPs
of the IOE die.

This patch adds functions with empty implementation using
__weak attribute for IOE die related crashlog, changes common
data structures while maintaining backwards compatibility,
and support for filling IOE crashlog records, guarded by
SOC_INTEL_IOE_DIE_SUPPORT config and makes cl_get_pmc_sram_data
function as weak because it needs SOC specific implementation.

Bug=b:262501347
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog

Change-Id: Id90cf0095258c4f7003e4c5f2564bb763e687b75
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75475
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-06 17:34:53 +00:00
Naresh Solanki
82390fad49 soc/intel/xeon_sp/spr: Add RMT config
This commit adds a configuration option to enable RMT in the coreboot
build for the Intel Xeon SP SPR platform.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: I9b9276116c22cfbbec132d7a1b0026a52a51398a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-06-06 12:20:32 +00:00
Kapil Porwal
fbe044235b soc/intel/meteorlake: Fill PCI SSID parameters
Set SSID UPD to program DID as SSID for all the on board PCIe devices
if SSID is not being overridden by CONFIG option or device tree.

BUG=b:263846223
TEST=Verify that SSID for all PCI devices is same as their respective
DIDs.

Output of lspci in the OS:
00:00.0 0600: 8086:7d02 (rev 01)
        Subsystem: 8086:7d02
00:02.0 0300: 8086:7d45 (prog-if 00 [VGA controller])
        Subsystem: 8086:7d45
00:04.0 1180: 8086:7d03 (rev 01)
        Subsystem: 8086:7d03
00:05.0 0480: 8086:7d19 (rev 01)
        Subsystem: 8086:7d19
00:06.0 0604: 8086:7e4d (rev 01) (prog-if 00 [Normal decode])
        Subsystem: 8086:7e4d
        Capabilities: [98] Subsystem: 8086:7e4d
00:07.0 0604: 8086:7ec4 (prog-if 00 [Normal decode])
        Subsystem: 8086:7ec4
        Capabilities: [90] Subsystem: 8086:7ec4
00:07.2 0604: 8086:7ec6 (prog-if 00 [Normal decode])
        Subsystem: 8086:7ec6
        Capabilities: [90] Subsystem: 8086:7ec6
00:0a.0 1180: 8086:7d0d (rev 01)
        Subsystem: 8086:7d0d
00:0d.0 0c03: 8086:7ec0 (prog-if 30 [XHCI])
        Subsystem: 8086:7ec0
00:0d.2 0c03: 8086:7ec2 (prog-if 40)
        Subsystem: 8086:7ec2
00:0d.3 0c03: 8086:7ec3 (prog-if 40)
        Subsystem: 8086:7ec3
00:14.0 0c03: 8086:7e7d (rev 01) (prog-if 30 [XHCI])
        Subsystem: 8086:7e7d
00:14.2 0500: 8086:7e7f (rev 01)
        Subsystem: 8086:7e7f
00:14.3 0280: 8086:7e40 (rev 01)
        Subsystem: 8086:0094
00:15.0 0c80: 8086:7e78 (rev 01)
        Subsystem: 8086:7e78
00:15.1 0c80: 8086:7e79 (rev 01)
        Subsystem: 8086:7e79
00:15.3 0c80: 8086:7e7b (rev 01)
        Subsystem: 8086:7e7b
00:16.0 0780: 8086:7e70 (rev 01)
        Subsystem: 8086:7e70
00:19.0 0c80: 8086:7e50 (rev 01)
        Subsystem: 8086:7e50
00:19.1 0c80: 8086:7e51 (rev 01)
        Subsystem: 8086:7e51
00:1c.0 0604: 8086:7e3e (rev 01) (prog-if 00 [Normal decode])
        Subsystem: 8086:7e3e
        Capabilities: [98] Subsystem: 8086:7e3e
00:1e.0 0780: 8086:7e25 (rev 01)
        Subsystem: 8086:7e25
00:1e.3 0c80: 8086:7e30 (rev 01)
        Subsystem: 8086:7e30
00:1f.0 0601: 8086:7e04 (rev 01)
        Subsystem: 8086:7e04
00:1f.3 0401: 8086:7e28 (rev 01)
00:1f.5 0c80: 8086:7e23 (rev 01)
        Subsystem: 8086:7e23

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I364c2052984b6f562bffe8f5ad7035c8b659d369
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-06 12:15:58 +00:00
Hsuan Ting Chen
3c2cdb6e57 lib: Support localized text of memory_training_desc in ux_locales.c
To support the localized text, we need to get the locale id by vboot
APIs and read raw string content file: preram_locales located at either
RO or RW.

The preram_locales file follows the format:
  [string_name_1] [\x00]
  [locale_id_1] [\x00] [localized_string_1] [\x00]
  [locale_id_2] [\x00] [localized_string_2] ...
  [string_name_2] [\x00] ...

This code will search for the correct localized string that its string
name is `memory_training_desc` and its locale ID matches the ID vb2api
returns. If no valid string found, we will try to display in English
(locale ID 0).

BUG=b:264666392
BRANCH=brya
TEST=emerge-brya coreboot chromeos-bmpblk chromeos-bootimage

Change-Id: I7e3c8d103c938a11b397c32c9228e44e31c3f01d
Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-06-04 19:00:18 +00:00
Subrata Banik
53d7e708e5 soc/intel/meteorlake: Apply PCIe RP mask based on SoC type
This patch ensures to update the FSP-M UPDs related to PCIe RP mask
properly as per the SoC type.

For example: PCIe RPs belong to the SoC/IOE die for MTL-U/P whereelse
PCIe RPs are from PCH die in case of MTL-S.

BUG=b:276697173
TEST=Able to build and boot google/rex.

Change-Id: Ice81553274682476bb4c927061b1196dc142836d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75608
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-06-04 18:20:25 +00:00
Subrata Banik
807d3330d4 soc/intel/meteorlake: Introduce different SoC flavors of Meteor Lake
This patch introduces the different SoC flavors of Intel Meteor Lake as:
* MTL-U
* MTL-P
* MTL-S

MTL-U and MTL-P are PCH less designs, while MTL-S is with PCH die.
The task for mainboard is to specify the correct SoC type rather than
selecting the MTL SoC by default.

This change is necessary to support the different SoC flavors of Intel
Meteor Lake.

BUG=b:276697173
TEST=Able to build and boot google/rex.

Change-Id: I27404bbbd0b489412953118e140f6f39b6e43426
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04 18:19:08 +00:00
Ronak Kanabar
b807a1d035 soc/intel/meteorlake: Hook up UPD PchHdaSdiEnable
Hook the PchHdaSdiEnable UPD so that mainboard can change the
settings via devicetree. PchHdaSdiEnable UPD enable HDA SDI lanes.

BUG=b:273962021
TEST=Verified the settings on google/rex using debug FSP logs.

Change-Id: I43f1e59d28fc07218f8e25266f8ce3bdcf3f6e5c
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75529
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-06-04 18:18:49 +00:00
Mario Scheithauer
7e5b28feb6 soc/intel/apollolake: Switch to snake case for SataPortsEnable
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.

Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-02 17:58:46 +00:00
Sean Rhodes
21e61847c4 soc/intel/jasperlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iadbce3124a88cf5be0aebde4a76ec6fd4b670216
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-06-01 19:00:03 +00:00
Mario Scheithauer
c8dc2c1204 soc/intel/apollolake: Make hard drive type for SATA ports configurable
Intel's APL FSP offers the possibility to select the connected hard
drive type to SATA ports. One has the option to choose between HDD ('0'
- default) and SSD ('1').

This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.

Change-Id: I52c3566fb3c959ada6be33f0546ac331f4867d10
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-06-01 15:42:30 +00:00
Mario Scheithauer
f165bbdcf0 soc/intel/apollolake: Make SATA speed limit configurable
In cases where there are limitations on the mainboard it can be
necessary to limit the used SATA speed even though both, the SATA
controller and disk drive support a higher speed rate. The FSP parameter
'SpeedLimit' allows to set the speed limit.

It should be noted that Gen 3 equals the default value '0'. This means
that inside FSP the same code is executed.

This patch provides a chip config so that this FSP parameter can be
set as needed in the devicetree on mainboard level.

Change-Id: I9c3eda0649546e3a40eb24a015b7c6efd8f90e0f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75364
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01 15:41:22 +00:00
Pratikkumar Prajapati
385f4bb965 soc/intel/common/crashlog: Check cbmem pointer before copying records
Check existence of crashlog records in CBMEM before copying them
to BERT, otherwise it can lead to NULL pointer access.

Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.

Change-Id: I4288011866283a3a5fb8ec9e10cd51b794052b4e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75528
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01 13:14:39 +00:00
Pratikkumar Prajapati
5f3b6545f4 soc/intel/common/crashlog: Check for invalid record
Do not copy the crashlog record if the record is 0xdeadbeef

Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.

Change-Id: I0edbf6902685a882876d525e63c5b602c1590ea1
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-06-01 13:14:15 +00:00
Pratikkumar Prajapati
d4330e7dfb soc/intel/common/crashlog: Fix checking PMC record size
Check pmc_record_size variable for collecting PMC records,
instead of cpu_record_size variable.

Bug=None
TEST=Able to build. With Meteor Lake SOC related patch, able to
capture and decode crashlog.

Change-Id: I4c35ba2bcf757231aa2872802eb82d4d50742cd9
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75526
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01 13:13:51 +00:00
Nico Huber
ae81497cb6 device/pci: Limit default domain memory window
When the default pci_domain_read_resources() is used,
keep 32-bit memory resources below the limit given by
CONFIG_DOMAIN_RESOURCE_32BIT_LIMIT. This serves as a
workaround for missing/wrong reservations of chipset
resources.

This will help to get more stable results from our own
allocator, but is far from a complete solution. Indvi-
dual platform ASL code also needs to be considered, so
the OS won't assign conflicting resources.

Most platforms have reserved space between 0xfe000000
and the 4G barrier. So use that as a global default.
In case of `soc/intel/common/`, use 0xe0000000 because
this is what is advertised in ACPI and there are traces
of resources below 0xfe000000 that are unknown to core-
boot's C code (PCH_PRESERVED_BASE?).

Tested on QEMU/Q35 and Siemens/Chili w/ and w/o top-
down allocation. Fixes EHCI w/ top-down in QEMU.

Change-Id: Iae0d888eebd0ec11a9d6f12975ae24dc32a80d8c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75102
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-06-01 13:11:33 +00:00
Naresh Solanki
c7338085fe soc/intel/xeon_sp: Enable build for IO Margining
This commit enables the build for IO Margining, ensuring that ASPM is
disabled and certain FSP knobs are adjusted in coreboot as below

1. Enable DFXEnable
2. Disable PcieGlobalAspm
3. Disable KtiLinkL1En & KtiLinkL0pEn

Since the FSP UPD does not provide all the necessary knobs for IO
Margining, the following settings need to be applied during the FSP
build process:

1. Enable PcdBiosDfxKnobEnabled
2. Disable PchDmiAspm
3. Enable SataTestMode
4. Enable WmphyMargining
5. Disable IioErrorEn

TEST=Build for IBM sbp1 board.

Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Change-Id: Ie306d12943adb76411d55358548b5cb2eb3a95be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75415
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-28 20:11:25 +00:00
Sumeet R Pawnikar
83b36f8276 soc/intel/common: Support power limits update for variants
Add support to update power limit values for variants.
Until now, each SoC implements this themselves.
To avoid code duplication, add this to common code.

BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
      for 15W SKU on Rex board.
     Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
      (57000, 57000) PL4 (W) (114)

Change-Id: I414715f211d816bbfad03a673ca96dd5df94caeb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-26 18:04:30 +00:00
Bora Guvendik
9f15dee56d soc/intel/meteorlake: Hook up SaGvFreq, SaGvGear upds
Hook the SaGvFreq, SaGvGear upds so that mainboard can change the
settings via devicetree. Meteor Lake supports 4 SaGv work points and it
can dynamically scale the work point based on memory bandwidth
utilization. Dynamic gearing technology allows the Memory Controller to
run at 1:1, 1:2 or 1:4 ratio of DRAM speed. The gear ratio is the ratio
of DRAM speed to Memory Controller Clock.

BUG=b:282164577
TEST=Verified the settings on google/rex using debug FSP logs.

Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I37169880af4019675374594e90735b5d7d0873b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75290
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26 17:57:12 +00:00
Jeremy Compostella
246b943056 soc/intel/mtl/acpi/xhci: Add clock gating support
Implement PS0 and PS3 methods to support xHCI clock gating in S0ix
suspend and resume.

BUG=b:283989367
TEST=S0iX test passed

Change-Id: Ia5b72b81fd1c0d0b7b90f8d9cbf6ef4aa9da9743
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25 21:19:53 +00:00
Pratikkumar Prajapati
20ce90154e soc/intel/meteorlake: Enable Key Locker
BUG=b:276988831
Platform=Rex
Test= inteltool -k
============= Dumping INTEL Key Locker status =============
Key Locker supported : YES
AESKL instructions enabled : YES
===========================================================

Also,
No S0ix issue seen, no impact on power just with this coreboot patch, no stability issue seen.

Boot time delta (using cbmem -t):

Without this CL:
963:returning from FspMultiPhaseSiInit 1,299,043 (98,480)

With this CL:
963:returning from FspMultiPhaseSiInit 1,324,659 (121,995)

Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Change-Id: I9919f44623972d7bbae4a9b886e1da4ac7879c98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71120
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25 15:18:12 +00:00
Subrata Banik
a193308fab soc/intel/meteorlake: Set SaGv work points as enum macro
This patch adds an enum macro to define the different SaGv work points.
The enum macro is named `sagv_wp_bitmap` and it has three values:

The goal is to choose the optimal SaGv work point for the target
platform after considering the two inputs as power consumption and performance. The first group is for workloads that require high performance, even if it means consuming more power. The second group
is for workloads that can tolerate lower performance, in order to save
power.

SAGV_POINTS_0_1: The highest power consumption, but also the highest
                 performance.
SAGV_POINTS_0_1_2: A lower power consumption than work point
                   SAGV_POINTS_0_1, but also a lower performance.
SAGV_POINTS_0_1_2_3: The lowest power consumption, but also the lowest
                     performance.

Set SaGv work points after reviewing the power and performance impact
with SaGv set to 1 (Enabled) and various considering various work points
between 0-3 being enabled.

BUG=b:267879107
TEST=Able to build google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4af0038f2799a458d1b006270068341f65d36609
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75362
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-25 05:04:06 +00:00
Marx Wang
00d9107e02 soc/intel/meteorlake: Add CPU PortID for GPIO Community
Add CPU PortID for GPIO communities in order to calculate
IOM Aux Bias data correctly.

BUG=b:283044004
TEST=able to detect external display

Signed-off-by: Marx Wang <marx.wang@intel.com>
Change-Id: I79f27fb0b6bde0a4ce2466eaf707166a952fad81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-24 11:41:56 +00:00
Mario Scheithauer
f5a48989b4 soc/intel/elkhartlake: Make PCIe root port max payload size configurable
The data payload size of PCIe root ports can be set to either 128
(default) or 256 bytes. A bigger payload size can improve PCIe data
throughput on the given port. FSP-S provides a parameter to configure
this value.

This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.

Change-Id: I5798a72adaa8089dda0b4bc12266b5a235ed4aa3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24 11:25:24 +00:00
Johnny Lin
3435f81ab7 soc/intel/xeon_sp: move and rename set_cmos_mrc_cold_boot_flag
1. Rename set_cmos_mrc_cold_boot_flag() to soc_set_mrc_cold_boot_flag
   in case a certain platform may not support this via CMOS data, and
   the function could in turn calls mainboard defined method in the
   future. Move the code into soc_util.c.

2. Remove redundant static get_system_memory_map() from cpx/romstage.c
   and call the soc_util.c one.

Change-Id: Ib7d9bed9092814658f4a0b1d6dcf3c7d79178048
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23 20:22:33 +00:00
Jeremy Soller
14d69d03b7 soc/intel/common: Add RPP-S PCI IDs
Add PCI IDs to support Raptor Point PCH.

Ref: Intel 700 Series PCH Datasheet, Volume 1 (#743835, rev 2)
Change-Id: Iee410ed3179260b08d45f50e8126fb815c686324
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73437
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-23 20:21:39 +00:00
Sean Rhodes
bfe2cd402d soc/intel/common: Add an error for missing ramtop CMOS entry
Show an error if an option table is used, and the ramtop entry is not
defined on a platform that uses it.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie48f0766b29be8e1fb0c1f71c4b2ce6ed20e6207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-22 12:42:54 +00:00
Subrata Banik
9405541b1a soc/intel/meteorlake: Add .final to check FSP reset pending request
This patch adds an API to check FSP reset pending requests. This
information is useful to understand if FSP would like boot firmware to
issue any reset to complete the silicon initialization.

As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.

BUG=b:282266168
TEST=Able to build and boot google/rex and able to detect FSP reset
pending request.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibf7c996f09affa099c9124773fe2d581f370d1a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-21 14:53:21 +00:00
Felix Singer
531023285e soc/intel/quark: Drop support
As announced in the 4.20 release notes, support for the Intel Quark SoC
is moved to the 4.20 branch and dropped from master.

Change-Id: I8a1ca7a2092aaeaea9c72eac5a8dd8f7d72e8f09
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-20 16:27:14 +00:00
Sean Rhodes
4265d5265d soc/intel/common: Correct the check for ramtop length
The `ramtop_table` is 10 bytes long, so adjust the check to
account for this.

Also, adjust the wording to make it clear what is required to fix it,
should the error be shown.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If2898c4bb22abb1779035aadc08f32898e9a096b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19 17:40:39 +00:00
Chia-Ling Hou
141d0dfafb soc/intel/jasperlake: Add PsysPmax config
Enable PSYS capability. PSYS is required to safeguard the system
stability if no charger IC.

BUG=b:281479111
TEST=emerge-dedede coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS

Change-Id: Ibe54acaf80700252558b82f194b9536b6117b84e
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75196
Reviewed-by: Reka Norman <rekanorman@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19 10:16:36 +00:00
Won Chung
ede5564b3e soc/intel/meteorlake: Add igd device
Add igd device name in soc_acpi_name(), and src/drivers/gfx/generic
can generate device in GFX0 scope in SSDT.

BUG=b:277629750
TEST=emerge-rex coreboot then check SSDT on DUT

Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Id7a136b5234cf5c0f60ecf253ee78c123f1f573b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-19 10:13:58 +00:00
Subrata Banik
3553a16003 soc/intel: Extend fsp_get_pch_reset_status() to all FSP APIs
This patch drops the assert check around
`FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN` config to ensure
`fsp_get_pch_reset_status()` can be used by all other FSP APIs to know
the status of the pending reset.

As per recent debug it has been found that, FSP is accumulating all
platform resets and executing a single reset from FSP Notify Phase.
As coreboot skipped calling into the FSP Notify APIs hence, it might
have missed the scope to issue the platform reset.

Going forward coreboot needs to implement the corresponding logic to be
able to identify any pending platform reset request and execute to
complete the silicon initialization flow.

BUG=b:282266168
TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2c9e37fadc27eab820a3121e47e09529de34d10e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75309
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-19 08:23:42 +00:00
Nico Huber
6a07db21b1 console: Add format-checking __printf() to die()
Code changes are necessary because `-Wformat` warns about empty
format strings by default.

Change-Id: Ic8021b70f4cd4875b06f196f88b84940c9a79fe0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75147
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17 11:23:59 +00:00
Nico Huber
feba51ba17 soc/intel/xeon_sp/spr: Fix format specifier for __LINE__ (%d)
Change-Id: I1384a02fa2931002ddd629acef0a4368435cfeb5
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-17 11:22:41 +00:00
Sean Rhodes
579e03a13e soc/intel/common: Don't hardcode ramtop offset
The `ramtop` can be obtained from the `option.h`, so remove the
hardcoded value. Keep the check for the value being byte aligned.

Change-Id: I5327b5d4e78b715a85072e5d9a62cf8fd2ae92c0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74511
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-17 09:23:26 +00:00
Subrata Banik
0cf2674087 soc/intel/alderlake: Handle FSP logo params
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.

TEST=Able to see splash screen while booting google/marasov
with BMP_LOGO config enable.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I421da2b4dadb892f17a859ce0ec586a2880469eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75294
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17 07:55:54 +00:00
Subrata Banik
e4f0df7dab soc/intel/meteorlake: Handle FSP logo params
This patch overrides FSP-S UPD `LogoPtr/LogoSize` with a valid
logo.bmp file if `BMP_LOGO` config is enabled.

TEST=Able to see splash screen while booting Intel Meteor Lake RVP
with BMP_LOGO config enable.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaba187456dd4dfb2f69d3532e83a3850f31783ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75198
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-17 07:55:47 +00:00
Kyösti Mälkki
8febc91b30 soc/intel/xeon_sp: Drop dummy FADT entry
Specifying types without addresses for PM1B events is
not useful.

Change-Id: I839208eaecf689a32484b9154647fc66633e5eef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-16 06:58:57 +00:00
Felix Held
f0a8b042c9 acpi/Kconfig: move \_SB scope out of ACPI_CPU_STRING
In ACPI 1.0 the processor objects were inside the \_PR scope, but since
ACPI 2.0 the \_SB scope can be used for that. Outside of coreboot some
firmwares still used the \_PR scope for a while for legacy ACPI 1.0 OS
compatibility, but apart from that the \_PR scope is deprecated.
coreboot already uses the \_SB scope for the processor devices
everywhere, so move the \_SB scope out of the ACPI_CPU_STRING to the
format string inside the 3 snprintf statements that use the
ACPI_CPU_STRING.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I76f18594a3a623b437a163c270547d3e9618c31a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-13 18:34:44 +00:00
Arthur Heymans
851236704e soc/intel/apl: Remove set but unused variable
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I62b7390c2de244cce169550e9b1fa41af738525d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75037
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-12 16:37:33 +00:00
Sridhar Siricilla
e9f4e56435 soc/intel/common: Define enum types for MKHI group IDs and ME SKUs
The patch defines enum type for MKHI group IDs and ME SKU types instead
of macros.

TEST=Build code for Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I102e802938a6a664a43a362d90a26755cff8f316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-05-12 09:22:23 +00:00
Sean Rhodes
bc602b856d soc/intel/common: Remove superfluous cmos_offset from ramtop
Having `_cmos_offset` in a CMOS offset is superfluous; remove it
so the CMOS entry is just `ramtop`.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibc1e7d78d2e3ae04330d19e64c3437ff07060ea8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-12 08:34:44 +00:00
Sean Rhodes
3b56cffa8a soc/intel/apollolake: Only use 8 bits for afterg3
In GEN_PMCON1 (Offset 1020h), Bit 0 is the "After G3 Enable" (ag3e)
(source Intel document #569262). Only use 8 bits, in the same way as
most other Intel SOCs do, for pmc_soc_set_afterg3_en.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idb290d1480b03cb3425edc6ff29b9c78a6545df1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74955
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11 16:54:13 +00:00
Dinesh Gehlot
8c53e6a053 soc/intel/cmn/blk.cse: Fix check condition in store_cse_rw_fw_version()
The return value of cse_get_bp_info() is an enum integer, where zero
means success and non-zero means failure. The function
store_cse_rw_fw_version() calls the function cse_get_bp_info() and
validates the return value as a boolean causing prematurely returns of
the parent API even if cse_get_bp_info() is successful.

This patch corrects this logical error by returning only if
cse_get_bp_info() fails.

TEST=Build and boot google/nivviks and verify that the ISH version info
command is only being sent during cold boot.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ice278e5ac69ff2f2c9f1936b76d71ae9deb6f855
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74998
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-11 16:50:35 +00:00
Sean Rhodes
88ade91073 soc/intel/common: Fix long delay when ME is disabled
If the ME is disabled with the `me_state` CMOS setting, boot
times are approximately 5 seconds longer:
    942:before sending EOP to ME    1,240,773 (5,599)
    943:after sending EOP to ME     6,263,951 (5,023,177)
    Total Time: 6,167,443

This is because the current code only checks if the ME is
disabled for CSE LITE SKUs. With this patch, boot times are
approximately 5 seconds quicker:
    Total Time: 1,143,932

Tested on `starbook/adl` and `starbook/tgl`.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I182f30d4fbf43955747c6a7a0b284a43f9c5e4ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-11 14:54:54 +00:00
Ravi Sarawadi
31e0aeb747 soc/intel/meteorlake: Increase pcie snoop/non-snoop latency
This fixes an issue where pcie was not power gating and blocked
S0ix entry. Overwrite pcie max non-snoop and snoop latency tolerance
values to 15.73ms as stated in doc #729123 - MTL External Design
Specification.

BUG=none
TEST=Boot google/rex, print/check values.

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com>
Change-Id: I9dfb9edbac95d28d50653777466ea172be64f612
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68308
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-11 08:18:39 +00:00
Kyösti Mälkki
85556ac1dc soc/intel: Clean up some includes
Change-Id: Ibb680bb8f94fb8a2812f420ac38f15684b5c0b4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10 21:27:29 +00:00
Kyösti Mälkki
5cd548b773 sb,soc/amd,intel: Sync FADT entries visually
Change-Id: I20a66dce1612ab4394c26f9b0943dac14bcdcfc4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-10 21:26:55 +00:00
Bora Guvendik
396201c1ef soc/intel/cmn/pcie: Allow SoC to overwrite snoop/non-snoop latency
The Intel SoC Meteor Lake requires a higher pcie max non-snoop and
snoop latency tolerance. Add config to let SoC overwrite the common
code settings if needed.

BUG=none
TEST=Boot google/rex and print/check if able to overwrite values.

Change-Id: Ic2b9a158d219e6c6e7f6e7f0ae0f093c1183b402
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-10 13:07:17 +00:00
Mario Scheithauer
15e7499cdd soc/intel/elkhartlake: Make hard drive type for SATA ports configurable
Intel's EHL FSP offers the possibility to select the connected hard
drive type to SATA ports. One has the option to choose between HDD ('0'
- default) and SSD ('1').

This patch provides a chip config so that this FSP parameter can be set
as needed in the devicetree on mainboard level.

Change-Id: Idb03aff5b6c5df592b47e2f4abe4fe58ac7151ba
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74946
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-10 13:06:12 +00:00
Kyösti Mälkki
83faa5d804 mb/google,intel: Use common ChromeEC code for lid shutdown
Change-Id: I4d34e5c094440dad4a6ab9adc67d3da6b71ac2bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74514
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-09 18:08:45 +00:00
Kyösti Mälkki
e599d43633 sb,soc/amd,intel: Apply minor FADT fixes
Change-Id: I27a610255e5680be1b507d45c6695cf9419ee052
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-05-09 15:35:37 +00:00
Kyösti Mälkki
9641c0e102 soc/intel/xeon_sp/spr: Drop spurious FADT fields
Assigning duty_offset while duty_width==0 has no purpose.

Under intel/common/block, previous assignment for fadt->gpe0_blk
resolves GPE0_STS(0) from xeon_sp/ebg/.../soc_pm.h and also assigns
value matching pmbase + 0x60.

Change-Id: Iaf688d9471ac527ac20307cf16216abdab731a06
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74827
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-09 15:34:23 +00:00
Tarun Tuli
33c666587a soc/intel/early_graphics: support to allow early graphics GPIO config
For early Sign of Life to work, we may need certain pin configurations
very early in boot (e.g. HDMI).  This may happen before romstage GPIOs
are configured, and bootblock is not suitable for field upgrading
existing devices.  Add a separate GPIO table that can be configured
when early graphics is invoked.

BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds and SoL functions on HDMI enabled variants

Change-Id: I7b3ce96a4166451e72aa70b3086eff3fb8b082b7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-08 13:13:34 +00:00
Subrata Banik
deebd9466f soc/intel/meteorlake: Apply large cbmem buffer size for FSP debug
This patch ensures that the PRERAM_CBMEM_CONSOLE_SIZE and
CONSOLE_CBMEM_BUFFER_SIZE hold a larger cbmem buffer size to contain
the entire FSP debug serial log.

The existing implementation was not appropriate, where the larger cbmem
size was even applicable for serial AP firmware (w/o FSP debug) image
as well.

This change is necessary to ensure that the FSP debug serial log is
always available, even in cases where the cbmem buffer size is
limited.

BUG=b:280481298
TEST=Able to build and boot google/rex with non-FSP serial AP image
and with FSP serial AP image. Able to see the AP log completely inside
the cbmem.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib35780fd558c8b6d9aa2e17241131ea4a58c2b9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-05-08 12:51:58 +00:00
Subrata Banik
792ce81973 soc/intel: Do CSE sync in romstage, unless ramstage chooses otherwise
This patch makes CSE sync in romstage default enabled unless ramstage
config (SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) chooses to override it.

TEST=Able to build google/marasov with this change where CSE sync is
performed early inside romstage.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-06 05:36:44 +00:00
Maximilian Brune
27900ea9f8 src/soc/intel: Document meaning of variables
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: Iaf88f34cedd09e2461bb05050392e178ec84d5d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05 12:36:29 +00:00
Felix Singer
51d8b25984 soc/intel/spr: Fix copy paste issue in error messages
The commit a0b199c6b4 ("soc/intel/xeon_sp/spr: Add soc
set_cmos_mrc_cold_boot_flag") introduced a copy-paste issue in two error
messages. The error messages should mention the Intel platform SPR
instead of CPX. Fix that.

Change-Id: I4de61ec2cf9fbd98263a7a7a588938d548148656
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74956
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-05 00:12:07 +00:00
Joey Peng
ea2a38be32 soc/intel/alderlake: Disable C1E on RPL CPUs
Since disabling C1E could improve acoustic noise for RPL, add judgement
in SOC code to disable C1E on RPL CPUs and enabling it on ADL CPUs .

BUG=b:278654939
TEST:emerge-brya coreboot

Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic2d2d5d6075de25141c1d08ec18838731c63a342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-05-02 19:03:38 +00:00
Subrata Banik
65b64b3f03 soc/intel/alderlake: Select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config
At present the problem has only been reported with Alder Lake and
Raptor Lake FSP where MultiPhaseSiInit API is unable to return any ERROR
status. Hence, this patch ensures to select applicable W/A config to
read FSP return status from the FSP Reset HOB.

BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.

Without this patch:

  IshInit() Start
  IshDisable() Start
  IshPerformGlobalReset()
  ....
  ....
  FSP returning control to Bootloader with reset required return
       status 40000003
  FspMultiPhaseSiInit Index-1 returned 0 <-- after control returns
       into coreboot, the `status` from the FSP API is reset to `0`
       instead 0x40000003. Hence, coreboot avoid hitting the reset.

With this patch:

  IshInit() Start
  IshDisable() Start
  IshPerformGlobalReset()
  ....
  ....
  FSP returning control to Bootloader with reset required return
       status 40000003
  FSP: handling reset type 40000003 <-- coreboot is able to understand
                                        the reset request in proper.
  GLOBAL RESET!
  global_reset() called!
  HECI: Global Reset(Type:1) Command

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I18a918cca7e19e03ed6020c55c86c64a94212963
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74785
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02 10:51:33 +00:00
Subrata Banik
da7d00ef21 soc/intel/common: Introduce API to get the FSP Reset Status
This patch creates a function to read the FSP API Reset Status. This
function relies on the FSP Scheduled Reset HOB which holds the reset
type (warm/cold/shutdown) information along with any platform specific
reset need (like global reset).

Ideally FSP API should be able to return the status (both success and
error code) upon exiting the FSP API but unfortunately there are some
scenarios in ADL/RPL FSP where MultiPhaseSiInit API is unable to return
any ERROR status. Hence, this function provides an additional hook to
read the FSP reset status by reading the dedicated HOB without relying
on the FSP API exit status code.

Additionally, create FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN config option
to handle broken FSP API return status issue.

Any SoC platform that selects the `FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN`
config will call into this newly added API to get the FSP return status
from MultiPhaseSiInit.

BUG=b:278665768
TEST=Able to select FSP_MULTIPHASE_SI_INIT_RETURN_BROKEN for ADL/RPL SoC
code and call into this API to know the return status from
MultiPhaseSiInit FSP API.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ief5d79736cc11a0a31ca2889128285795f8b5aae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-02 10:51:01 +00:00
Matt DeVillier
71fee41ef5 soc/intel/adl: Unhide PMC, IOM ACPI devices from OS
These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.

TEST=build google/banshee, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.

Change-Id: Idbbaee29bffb49059d8450abd09e0c3f7b490fae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74850
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01 14:47:10 +00:00
Matt DeVillier
3d85d6b292 soc/intel/tgl: Unhide PMC, IOM ACPI devices from OS
These were hidden because no Windows drivers existed, but now that
they do, the ACPI devices need to be visible in order for the
drivers to properly attach.

TEST=build google/drobit, boot Windows, verify Windows drivers
correctly attach to PCM/IOM devices.

Change-Id: I1520a71e318674baa234fc6a2126d1d17933d983
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-05-01 14:47:04 +00:00
Anil Kumar
afb926ab0a soc/intel/cmn/cse: Decouple ME_RW compression from CSE RW Sync
The change 'commit Iac37aaa5ede5e1cd ("Add Kconfigs to indicate
when CSE FW sync is performed")' adds support to choose CSE FW update
to be performed in ROMSTAGE or RAMSTAGE. The patch also introduced a
dependency on ME_RW firmware compression.

This patch removes the dependency between CSE FW sync in RAMSTAGE and
ME_RW firmware compression as these two are not related and should be
decoupled to support CSE FW sync in RAMSTAGE without the requirement
to compress ME_FW.

Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I5ca4e4a993e4c4cc98b8829cbefff00b28e31549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74796
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
2023-05-01 14:42:53 +00:00
Kyösti Mälkki
02a1901091 sb,soc/amd,intel: Drop include <cpu/x86/smm.h>
I forgot to remove these in commit 0fe36db154eb ("ACPI: Make FADT
entries for SMI architectural").

Change-Id: Ib1bc1dad6053ddb0454d4510917fd2bcf0901f35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74811
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29 01:21:23 +00:00
Kyösti Mälkki
240baa31e8 ACPI: Make FADT entries for RTC/CMOS architectural
For AMD, replace name RTC_ALT_CENTURY with RTC_CLK_ALTCENTURY
that points to same offset. Since the century field inside
RTC falls within the NVRAM space, and could interfere with
OPTION_TABLE, it is now guarded with config USE_PC_CMOS_ALTCENTURY.

There were no reference for the use of offset 0x48 for century.

Change-Id: I965a83dc8daaa02ad0935bdde5ca50110adb014a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74601
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-29 01:20:54 +00:00
Christian Walter
bf0b87d813 soc/intel/common/block/pmc: Sort Kconfig in alphabetical order
Change-Id: I7392ede4226a940896c805fc0b0bc0dd615a964c
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74810
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-28 13:38:59 +00:00
Hsuan Ting Chen
26a9555073 vga: Change the arguments of vga_write_text to support extended ASCII
VGA defined the extended ASCII set based on CP437, but the function
vga_write_text() accepts a signed char array.

This will cause unnecessary confusion that if we want to print u with
umlaut (code=129 in CP437), we need to explicitly cast it to -127 in
signed char.

Since we still want to leverage the built-in string utilities
which only accepts const char*, we still need to cast it to signed char
while processing, and cast it back to unsigned once we write into the
frame buffer.

BRANCH=brya
BUG=b:264666392
TEST=emerge-brya coreboot chromeos-bootimage

Signed-off-by: Hsuan Ting Chen <roccochen@chromium.org>
Change-Id: If555bbc05f40ce3f02339c0468afff6dda8b7ded
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-28 09:39:06 +00:00
Kyösti Mälkki
121d3d57ad ACPI: Make FADT entries for SMI architectural
Change-Id: I80aa71b813ab8e50801a66556d45ff66804ad349
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74600
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-27 03:13:33 +00:00
Ashish Kumar Mishra
2ee716227e intel/mtl: Add get_cse_ver_from_cbfs function
This patch implements helper function get_cse_ver_from_cbfs() to
retrieve the CSE Lite version from CBFE RW's metadata and calls
the helper function from cse_check_update_status()

TEST=Verified CSE Lite version in coreboot boot log

Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: Ie1bf186adfc3f87826a7ce9b0167a6bbe6767299
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74755
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
2023-04-26 17:23:32 +00:00
Arthur Heymans
cbc5d3f34b soc/intel: Don't report _S1 state when unsupported
Since skylake Intel hardware does not support this sleep state. Trying
to enter S1 by having the OS enter sleep results in a system hang on at
least Alder lake (prodrive/atlas).

CONFIG_SOC_INTEL_COMMON_BLOCK_PMC is a good proxy whether devices
support 'skylake style' PMC PCI device for ACPI registers.

Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: Ic9e19410696240755e8714db53a0525284f3a2da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-26 15:41:03 +00:00
Kyösti Mälkki
8eac12fa7d soc/intel/common: Use ACPI_COMMON_MADT_IOAPIC
For the first IOAPIC, use the common MADT generator with
default IRQ overrides.

Change-Id: Ie6e3eae1728a9a94205ec59557d4af1655191166
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 11:06:10 +00:00
Kyösti Mälkki
6437409b76 soc/intel/baytrail,braswell: Use COMMON_MADT_IOAPIC
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: I3a61a0ceb0e6e4a09570beef6d0170354eb498ac
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 11:03:40 +00:00
Kyösti Mälkki
81dc352032 intel/bd82x6x,broadwell,lynxpoint: Use ACPI_COMMON_MADT_IOAPIC
Change IRQ #0 to GSI #2 override to positive edge trigger from
the bus ISA default (positive edge).

Change-Id: Iab3d38da9610ede1d338440b4a8ec0f1537c17e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 11:03:13 +00:00
Kyösti Mälkki
10bdee1327 ACPI: Add COMMON_ACPI_MADT_IOAPIC and CUSTOM_ACPI_MADT
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.

Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.

Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 11:02:18 +00:00
Kyösti Mälkki
e742b68f1a arch/x86/ioapic: Promote ioapic_get_sci_pin()
Platform needs to implement this to provide information about SCI IRQ
pin and polarity, to be used for filling in ACPI FADT and MADT entries.

Change-Id: Icea7e9ca4abf3997c01617d2f78f25036d85a52f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 10:53:16 +00:00
Kyösti Mälkki
ae1b2d49cf soc/intel: Introduce ioapic_get_sci_pin()
According to ACPI Release 6.5 systems supporting PIC (i8259)
interrupt mechanism need to report IRQ vector for the SCI_INT
field. In PIC mode only IRQ0..15 are allowed hardware vectors.

This change should cover section 5.2.9 to not pass SCI_INT
larger than IRQ15. Section 5.2.15.5 needs follow-up work.

Care should be taken that ioapic_get_sci_pin() is called
after platform code has potentially changed the routing
from the default.

It appears touched all platforms except siemens/mc_aplX
currently program SCI as IRQ9.

Change-Id: I723c207f1dcbba5e6fc0452fe1dbd087fad290ee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-26 10:52:21 +00:00
Sumeet R Pawnikar
dbf132cc1e soc/intel/meteoerlake: set power limits dynamically
Set power limit values dynamically based on Meteor Lake
CPU TDP and PCI ID of SKU.

BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values for 15W SKU on Rex board

Change-Id: I20c9bc21dfa79696b07c460dbcedb4fa51838bdb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-22 16:24:41 +00:00
Subrata Banik
044fc9f671 soc/intel/cmn/cse: Make cse_get_fpt_partition_info() function static
The patch makes `cse_get_fpt_partition_info()` AP local/static as all
the references to this function are in local to the cse_lite.c file.

BUG=b:273661726
TEST=Able to build and boot google/marasov with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie50453946c8abe55c29e9001263f0264a73c8fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74388
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-22 05:38:35 +00:00
Subrata Banik
9bb2690609 soc/intel/alderlake: Implement soc_is_ish_partition_enabled override
This patch implements `soc_is_ish_partition_enabled()` override to
uniquely identify the SKU type between UFS and non-UFS to conclude
if ISH partition is enabled and need to retrieve the ISH version from
CSE FPT by sending HECI command.

TEST=Able to uniquely identify the UFS and non-UFS SKUs while booting
to google/marasov.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7771aebb988f11d9d1b2824aa28e6f294fd67c25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74532
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-22 05:37:57 +00:00
Subrata Banik
3879334ca0 mb/google/rex: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.

With these settings we have observed a boot time reduction of about
100ms on google/rex.

TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.

Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-22 05:37:18 +00:00
Sean Rhodes
e24d9d6b45 soc/intel/meteorlake: Don't offer D3Cold when it's disabled
Use D3COLD_SUPPORT Kconfig option to adjust the maximum supported sleep
state in ACPI.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifa55a19727e6adb6864158c2c323d08a0c22b996
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-21 21:30:36 +00:00
Subrata Banik
b1b7c532b0 soc/intel/cmn/cse: Store ISH firmware version into CBMEM
The patch stores the ISH in the CBMEM table. It verifies CSE has been
updated by comparing previous and current CSE versions. If it has, the
patch updates the previous CSE version with the current CSE version. It
then updates the CBMEM table with the current ISH version.

BUG=b:273661726
TEST=The current and old CSE and ISH versions are verified on the
google/nissa during cold and warm reboots.

Additionally, version updates are verified by a debug patch that
purposely updated the stored cse version.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: Ie5c5faf926c75b05d189fb1118020fff024fc3e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21 17:22:20 +00:00
Subrata Banik
fc313d655f {commonlib, soc/intel/cmn/cse}: Store CSE firmware version into CBMEM
The patch implements an API that stores the CSE firmware version in the
CBMEM table. The API will be called from RAMSTAGE based on boot state
machine BS_PRE_DEVICE/BS_ON_EXIT

Additionally, renamed ramstage_cse_fw_sync() to ramstage_cse_misc_ops()
in order to add more CSE related operations at ramstage.

This patch also adds a configuration option,
'SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION', which enables the storage
of firmware version information in CBMEM memory. This information can be
used to identify the firmware version that is currently installed on the
system. The option depends on the `DRIVERS_INTEL_ISH` config and
platform should be flexible enough to opt out from enabling this
feature.

The cost of sending HECI command to read the CSE FPT is significant
(~200ms) hence, the idea is to read the CSE RW version on every cold
reset (to cover the CSE update scenarios) and store into CBMEM to
avoid the cost of resending the HECI command in all consecutive warm
boots.

Later boot stages can just read the CBMEM ID to retrieve the ISH
version if required.

Finally, ensure this feature is platform specific hence, getting
enabled for the platform that would like to store the ISH version into
the CBMEM and parse to perform some additional work.

BUG=b:273661726
TEST=Able to build and boot google/marasov.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I923049d2f1f589f87e1a29e1ac94af7f5fccc2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-21 17:22:00 +00:00
zhaojohn
0cca0176d5 soc/intel/meteorlake: Add VPU into the DMAR SATC table
This change adds the VPU into the DMAR SATC table in order to support
the VPU IO virtualization.

BUG=None
TEST=Enabled the VPU, booted to kernel and verified that DMAR SATC table
includeded the VPU entry.

Change-Id: I6d4af7c9844e33483a1e616eaee061a90d0be6fc
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-21 15:23:49 +00:00
Subrata Banik
5ff0118a58 soc/intel/(adl, cmn, mtl): Refactor cse_fw_sync() function
This patch refactors cse_fw_sync() function to include timestamp
associated with the CSE sync operation.This effort will ensure the
SoC code just makes a call into the cse_fw_sync() without bothering
about adding timestamp entries.

TEST=Able to build and boot google/marasov.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib5e8fc2b8c3b605103f7b1238df5a8405e363f83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21 15:23:13 +00:00
Subrata Banik
db7b35a9c9 soc/intel/cmn/cse: Refactor ramstage_cse_fw_sync() function
This patch refactors sleep type check inside ramstage_cse_fw_sync()
to avoid additional logic while performing cse_fw_sync() operation.

TEST=Able to build and boot google/marasov.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7c7a91c81d51dbf6742e12c58a24b9f52fff5630
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
2023-04-21 15:22:51 +00:00
Kyösti Mälkki
91c8c39eb8 soc/intel/braswell: Replace <build.h> with <version.h>
To use generated build.h one should have had a pre-requisite in the
Makefile. Reference coreboot_build_date from lib/version.c instead.

Change-Id: Icd6fa2ddf8aa584b0f51ba130592f227bbdad975
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21 15:12:25 +00:00
Kyösti Mälkki
67c48a3677 ACPI: Obsolete FADT p_lvl2_lat and p_lvl3_lat fields
After the obsoletion of Processor() it is necessary to provide
_CST package to define P_LVLx IO addresses for C2/C3 transitions.
The latency values from _CST will always replace those in FADT.

Change-Id: I3230be719659fe9cdf9ed6ae73bc91b05093ab97
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-21 09:38:26 +00:00
Cliff Huang
8fbdefc37f soc/intel/common/block/pcie/rtd3: Fix source clock check condition for PM method
srcclk_pin is 0-based and '0' is a valid clock source number. If
srcclk_pin is set to -1, then the clock will not be disabled in D3.
Therefore, clock source gating method should not be generated.

BUG=b:271003060
BRANCH=firmware-brya-14505.B
TEST=Boot to OS and check that rtd3 ACPI entries are generated as
expected. For those PCI devices with RTD3 driver whose srcclk_pin to
0, the RTD3 entries should not be missing due to check error.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia831b8fd17572cc35765bd226d1db470f12ddd41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73889
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-20 22:13:33 +00:00
Subrata Banik
ad42d9c22b soc/intel/meteorlake: Send CSE EOP Async CMD early
This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.

Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample which causes idle delay while waiting
for EOP response.

The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd. This patch helps to create
ample duration between CSE EOP command being sent and response being
captured.

TEST=Able to boot google/rex sku to ChromeOS and observed ~100ms of
boot time savings (across warm and cold reset scenarios)

Change-Id: I91ed38edbd5a31d61d4888e1466169a3494d635a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-20 22:04:30 +00:00
Sean Rhodes
2dcb2e28b6 soc/intel/meteorlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is currently unused.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I08930ef84438140a13df74900570b126088bd1cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74478
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:44:53 +00:00
Sean Rhodes
6bb11a3e6c soc/intel/alderlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is currently unused.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2590e8dec0a308e0dc3d467cb3dd2bb97e877492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74477
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:44:21 +00:00
Sean Rhodes
2980e317e3 soc/intel/tigerlake: Replace TcssD3ColdDisable with D3COLD_SUPPORT
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:43:29 +00:00
Sean Rhodes
648ff9268f soc/intel/common/rtd3: Use D3COLD_SUPPORT to set max sleep state
Use D3COLD_SUPPORT Kconfig option to set the maximum support sleep
state. Report `4` in `_S0W` only when D3COLD_SUPPORT is enabled, as
if it is not, it will break S3 exit.

When D3COLD_SUPPORT is not enabled, return `3` (D3Hot).

This fixed S3 exit on both TGL and ADL. Tested on StarBook
Mk V and Mk VI.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I578d4933b6144aec79fe0b2eb168338ef82c0b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74406
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-20 20:43:02 +00:00
Sean Rhodes
5f0cda7e91 soc/intel/tigerlake: Replace SOC_INTEL_TIGERLAKE_S3 with D3COLD_SUPPORT
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.

Remove it, and instead use D3COLD_SUPPORT so it's clear what the
option is doing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:42:41 +00:00
Sean Rhodes
aa8c6a22e5 device: Move D3COLD_SUPPORT symbol
Move D3COLD_SUPPORT to device, so it can be used by multiple
SOCs.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie92736458ab95374c51346107665dc0fd1e653a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74404
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-20 20:42:18 +00:00
Subrata Banik
03ff5db8b8 soc/intel/meteorlake: Drop FSP CPU feature programming for ChromeOS
The Intel FSP used on ChromeOS platform has dropped the
`CpuFeaturesPei.ffs` module to opt for coreboot running this
additional feature programming on BSP and APs.

TEST=Able to build and boot google/rex without any boot regression.
Please refer to the boot time and SPI flash savings after dropping
the FSP feature programming:

Boot time savings=10ms
SPI Flash size savings=34KB

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iaed0a009813098610190b2a3a985b0748c0d51de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-20 08:31:50 +00:00
Sean Rhodes
1d41f909f3 soc/intel/alderlake: Rename SOC_INTEL_ALDERLAKE_S3 to D3COLD_SUPPORT
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.

Rename it to D3COLD_SUPPORT to make it clear what it's doing.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2023-04-19 13:25:29 +00:00
Kyösti Mälkki
d521b967c4 cpu,soc/intel: Separate single SSDT CPU entry
Change-Id: Ic75e8907de9730c6fdb06dbe799a7644fa90f904
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-17 08:13:38 +00:00
Matt DeVillier
e30d204d38 soc/intel/jasperlake: Hook up GMA ACPI brightness controls
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.

Tested by adding gfx register on google/magpie. Backlight controls
work on Windows 10 and Linux 6.1.

Change-Id: Iaa9872cd590c3b1298667cc80354ed3efd91c6c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-16 14:06:57 +00:00
Subrata Banik
7f66adbc71 soc/intel/cmn/cse: Move API to get FW partition info into cse_lite.c
The patch moves API that gets the CSE FW partition information into
CSE Lite specific file aka cse_lite.c because the consumer of this API
is the cse_lite specific ChromeOS devices hence, it's meaningful to
move the cse lite specific implementation inside cse_lite.c file.

BUG=b:273661726
TEST=Able to build and boot google/marasov with this code change.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I49ffaec467f6fb24327de3b2882e37bf31eeb7cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74382
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 15:54:17 +00:00
Lean Sheng Tan
dc08548ea8 soc/intel/tigerlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I3b68d13aa414e69c0a80122021e6755352db32fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73738
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 14:36:46 +00:00
Lean Sheng Tan
ce68d68e00 soc/intel/alderlake: Enable early caching of RAMTOP region
Enable early caching of the TOM region to optimize the boot time by
selecting `SOC_INTEL_COMMON_BASECODE_RAMTOP` config.

Purpose of this feature is to cache the TOM (with a fixed size of
16MB) for all consecutive boots even before calling into the FSP.
Otherwise, this range remains un-cached until postcar boot stage
updates the MTRR programming. FSP-M and late romstage uses this
uncached TOM range for various purposes (like relocating services
between SPI mapped cached memory to DRAM based uncache memory) hence
having the ability to cache this range beforehand would help to
optimize the boot time (more than 50ms as applicable).

TEST=Able to build and boot Starlab ADL laptop to OS.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Iba554af4ff0896e133d20860ff72dd1a10ebd1e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73736
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-15 14:36:29 +00:00
Musse Abdullahi
ab496bf177 soc/intel/meteorlake: Add B0 stepping CPU ID
This patch adds CPU ID for B0 stepping (aka ES2).
DOC=#723567
TEST=Able to boot on B0 rvp and get correct CPU Name in coreboot log.

Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Change-Id: I8b939ccc8b05e3648c55f8f2a0a391cb08f04184
Signed-off-by: Musse Abdullahi <musse.abdullahi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74300
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 12:10:08 +00:00
Kyösti Mälkki
71fd3becf0 soc/intel/baytrail: Make acpi_madt_irq_overrides() static
Change-Id: Id362e023358054df2c4511fd108c313da868306d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74325
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-15 05:14:37 +00:00
Kyösti Mälkki
69a13964ea sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPIC
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.

Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.

For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.

Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-15 05:14:14 +00:00
Elyes Haouas
9ac50e1575 cpu,soc/intel: Use acpigen_write_processor_device()
Use acpigen_write_processor_device() instead of deprecated
acpigen_write_processor().

Change-Id: I1448e0a8845b3a1beee0a3ed744358944faf66d8
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72488
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 17:33:25 +00:00
Lean Sheng Tan
d33cbf1803 soc/intel/xeon_sp/spr: Remove stale call to xeonsp_init_cpu_config
This fixes the Jenkins build error when building INTEL_ARCHERCITY_CRB
that was caused by the API change in commit 36e6f9bc04. This patch removes the
broken API function and also adds package_id log print same as previous
commit mentioned above.

Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I89e14b40186007ab0290b24cd6bd58015be376b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74436
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-14 15:23:47 +00:00
Subrata Banik
ae0c84f987 soc/intel/cannonlake: Allow SoC to choose CAR mode (eNEM/NEM)
This patch avoids cannonlake base config to select eNEM for CAR by
default. Rather allow other SoC config to choose the applicable CAR
mode between eNEM and NEM.

CML and WHL select eNEM whereas CFL decided to use NEM for CAR setup.

Here is some background about why CFL SoC platform decided to choose
NEM over eNEM:

It was found that some coffeelake CPUs like Intel i3 9100E fail to enter
CAR mode because some MSR used by NEM enhanced are lacking. According to
the Intel SDM CPUID.EAX=07h.ECX=0 reg EBX[12 or 15] should indicate the
presence of IA32_PAR_ASSOC and CPUID.EAX=10h.ECX[1 or 2] reg ECX[2]
should indicate IA32_L3_QOS_CFG and IA32_L2_QOS_CFG respectively but
even on a Intel coffeelake CPU that works with the NEM_ENHANCED these
CPUID bits are all 0 so there is no way of knowing whether NEM_ENHANCED
will work at runtime. Instead just always use regular NEM.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibeaa4d53279ff9cbcd0b2ac5f2ad71925872355b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 14:45:12 +00:00
Arthur Heymans
36e6f9bc04 soc/intel/xeon_sp: Don't sort struct device cpus for numa
Currently the xeon_sp code reassigns struct devices apic_id so that srat
entries can be added in a certain order.

This is not a good idea as it breaks thread local storage which contains
a pointer to its struct device cpu.

This moves the sorting of the lapic_ids to the srat table generation
and adds the numa node id in each core init entry. Now it is done in
parallel too as a bonus.

Change-Id: I372bcea1932d28e9bf712cc712f19a76fe3199b1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68912
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14 10:50:44 +00:00
Kapil Porwal
4e498e169e soc/intel/meteorlake: Replace assert with error message
Avoid asserts related to CNVi UPDs which are not boot critical.
Instead, add error messages which are more helpful in identifying
the issue.

BUG=none
TEST=Boot to the OS on google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I49a988b7eda009456d438ba7be0d2918826e1c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74370
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-14 09:46:16 +00:00
Kyösti Mälkki
c77b607138 soc/intel/common: Fix acpigen use for processor Device
Change-Id: Ib4e21732ac31076a1a97a774e03c8466d17c5f29
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-14 08:33:18 +00:00
Dinesh Gehlot
f963febd29 soc/intel/cmd/block: Implement an API to get firmware partition details
This patch retrieves details of a specified firmware partition table.
The information retrieved includes the current firmware version and
other information about the firmware partition. The patch communicates
with the ME using the HECI command to acquire this information.

BUG=b:273661726
Test=Verified the changes for ISH partition on nissa board.

Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I0582010bbb836bd4734f843a8c74dee49d203fd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-04-13 17:40:17 +00:00
Kapil Porwal
78cc76d204 soc/intel/meteorlake: Hook up UPD CnviWifiCore
Hook the newly created/exposed CnviWifiCore UPD up as a chip driver.
Enable this option by default to maintain the existing behavior.

BUG=b:270985197
TEST=Verified by enabling/disabling the UPD on google/rex

Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I5b4662c2a064f7c9074797c8a2541dcf1dd686fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74306
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13 13:32:27 +00:00
Sridhar Siricilla
02b39efca4 soc/intel/common: Update cpu_apic_info_type struct
The patch updates total cpu count variable and total P-core count in
cpu_apic_info_type structure to `unsigned short int` to address more
cores.

TEST=Verify the build on Rex

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I46239cc7ad9870e7134955af56b9f6625be2b002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-13 13:31:58 +00:00
Johnny Lin
514930c2af soc/intel/xeon_sp: Fix very small total memory when CXL is enabled
Processor attached memory should not use reserved_ram_from_to and
treat the calculation of gi_mem_size size as 64MB.

By default SOC_INTEL_HAS_CXL is enabled for Sapphire Rapids platforms,
this should fix small total memory issue. Before the fix running
command 'free -g -h' under Linux shows the total memory is only 1.4Gi,
after the fix it's showing the expected total memory size 15Gi.

Tested=On AC without attaching CXL memory, the total memory size is
the same as de-selecting SOC_INTEL_HAS_CXL.
On OCP Crater Lake with CXL memory attached, CXL memory can be recognized
in NUMA node 1:
numactl -H
available: 2 nodes (0-1)
node 0 cpus: 0 1 2 3 4 5 6 .. 59
node 0 size: 95854 MB
node 0 free: 93860 MB
node 1 cpus:
node 1 size: 63488 MB
node 1 free: 63488 MB
node distances:
node   0   1
  0:  10  14
  1:  14  10

Change-Id: I38e9d138fd284620ac616a65f444e943f1774869
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74296
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-13 07:56:23 +00:00
Michael Niewöhner
a231e71cf1 Revert "soc/intel/rtd3: Hook up supported states to Kconfig"
This reverts commit dbb97c3243.

Reason for revert: dependency for revert CB:73903

Change-Id: Ibc81483239a13f456d20631725641b7219af4ef8
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:20:19 +00:00
Michael Niewöhner
076f86125f Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"
This reverts commit 6bfca1b689.

Reason for revert: dependency for revert CB:73903

Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:19:56 +00:00
Michael Niewöhner
7c722ce179 Revert "soc/intel/{tgl,adl}: Replace _S3 with D3COLD_SUPPORT symbol"
This reverts commit fd4ad29f18.

Reason for revert: dependency for revert CB:73903

Change-Id: I5ed5e3e267032d62d65aef7fb246a075dccc9cf6
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12 15:19:49 +00:00
Patrick Rudolph
76c27c8032 soc/intel/xeon_sp: Drop Kconfig MAX_SOCKET_UPD
The Kconfig is only used in common code to gather the build time
maximum socket number FSP support. The same information is available
in FSP header as MAX_SOCKET, thus use the FSP as truth of source.

Currently MAX_SOCKET is 4.

Change-Id: I10282c79dbf5d612c37b7e45b900af105bb83c36
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74339
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-12 14:51:40 +00:00
Kyösti Mälkki
2e9f0d3b6a ACPI: Add helper for MADT LAPICs
This avoids some code duplication related to X2APIC mode.

Change-Id: I592c69e0f52687924fe41189b082c86913999136
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11 19:58:17 +00:00
Kyösti Mälkki
9ac1fb729f ACPI: Add helper for MADT LAPIC NMIs
This avoids some code duplication related to X2APIC mode.

Change-Id: I2cb8676efc1aba1b154fd04c49e53b2530239b4c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2023-04-11 19:57:58 +00:00
Michał Żygowski
56621e1e57 soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration
space from coreboot on Alder Lake systems.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11 16:35:06 +00:00
Michał Żygowski
16c7626077 soc/intel/alderlake: Hook up P2SB PCI ops
P2SB device is being hidden from coreboot by FSP-S. This breaks the
resource allocator which does not report P2SB BAR via intel common
block P2SB driver. Hook up the common block P2SB driver ops to
soc_enable function so that the resources will be reported. The P2SB
device must be set as hidden in the devicetree.

This fixes the silent resource allocation conflicts on machines with
devices having big BARs which accidentally overlapped P2SB BAR.

TEST=Boot MSI PRO Z690-A with multiple PCIe devices/dGPUs with big
BARs and see resource conflicts no longer occur.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7c59441268676a8aab075abbc036e651b9426057
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-11 16:34:48 +00:00
Patrick Rudolph
d708884d50 soc/intel/xeon_sp/acpi: Fix _OSC method
Fix a couple of bugs in the _OSC method for handling
"PCI Host Bridge Device" on Xeon-SP.

- Drop the Sleep. The code doesn't write to hardware at all, so
  there's no need to sleep here.
- Make sure that the number of DWORD passed in Arg2 is at least 3.
  The existing check was useless as it would not create the
  DWordField, but then use it anyways.
- Add check for CXL 2 device method calls which provide a 5 DWORD
  long buffer to prevent buffer overflows when invoking the
  "PCI Host Bridge Device" method.

Test:
Boot on Archer City and confirm that no ACPI errors are reported
for _OSC.

Change-Id: Ide598e386c30ced24e4f96c37f2b4a609ac33441
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-04-11 16:28:03 +00:00
Michał Żygowski
daf834a705 soc/intel/alderlake/iomap: Fix the PCR BAR size on ADL-S
According to ADL PCH BIOS specification (DOC# 630603) ADL-S PCH
uses a fixed SBREG_BAR of 256MiB starting at 0xe0000000.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ied59a6dad8fb065dc3aeb6281bd32074aaa5e3b8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11 16:24:25 +00:00
Arthur Heymans
8b8400a889 drivers/fsp2_0/mp_service_ppi: Use struct device to fill in buffer
Now the CPU topology is filled in struct device during mp_init.

Change-Id: I7322b43f5b95dda5fbe81e7427f5269c9d6f8755
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11 16:02:09 +00:00
Subrata Banik
cda48b297c soc/intel/{adl, cmn}: Send CSE EOP Async CMD early
This patch sends the CSE EOP command asynchronous implementation early
as part of `soc_init_pre_device`.

Without this patch the duration between asynchronous CSE EOP send and
receive commands is not ample whichcauses idle delay while waiting
for EOP response.

The goal of the CSE async implementation is to avoid idle delay while
capturing the response from CSE EOP cmd.

This patch helps to create ample duration between CSE EOP command
being sent and response being captured.

TEST=Able to boot google/marasov EVT sku to ChromeOS and observed
~30ms of boot time savings (across warm and cold reset scenarios).

Without this patch:

  963:returning from FspMultiPhaseSiInit          907,326 (97,293)
  ...
  ...
  115:finished elog init                          967,343 (2,581)
  942:before sending EOP to ME                    967,821 (478)
  … 
  16:finished LZMA decompress (ignore for x86)    1,017,937 (12,135)
  943:after sending EOP to ME                     1,067,799 (49,861)
  …
  …
  1101:jumping to kernel                          1,144,587 (13,734)

  Total Time: 1,144,549

With this patch:
  963:returning from FspMultiPhaseSiInit          918,291 (97,320)
  942:before sending EOP to ME                    918,522 (230)
  ...
  ...
  16:finished LZMA decompress (ignore for x86)    1,029,476 (12,483)
  943:after sending EOP to ME                     1,033,456 (3,980)
  ...
  ...
  1101:jumping to kernel                          1,111,410 (14,007)

  Total Time: 1,111,375

Change-Id: Idaf45ef28747bebc02347f0faa77cc858a4a8ef1
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-11 11:37:38 +00:00
Sridhar Siricilla
7301cfac60 soc/intel/common: Order the different types of cores based on APIC IDs
Currently coreboot presents the BSP core first, then efficient cores and
Performance cores as indicated below:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3

```
Existing code presents mix of different cores to OS and causes CPU load
balancing and power/performance impact. So, the patch fixes this
disorder by ordering the Performance cores first, compute die efficient
cores next, and finally SOC efficient cores if they are present. This
is done to run the media applications in a power efficient manner,
please refer the ChromeOS patches for details:
https://chromium-review.googlesource.com/c/chromiumos/platform2/+/3963893

BUG=b:262886449
TEST=Verified the code on Rex system

After the fix:

```
/sys/devices/system/cpu/cpu0/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu1/topology/thread_siblings_list:0-1
/sys/devices/system/cpu/cpu2/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu3/topology/thread_siblings_list:2-3
/sys/devices/system/cpu/cpu4/topology/thread_siblings_list:4
/sys/devices/system/cpu/cpu5/topology/thread_siblings_list:5
/sys/devices/system/cpu/cpu6/topology/thread_siblings_list:6
/sys/devices/system/cpu/cpu7/topology/thread_siblings_list:7
```

Change-Id: I21487a5eb0439ea0cb5976787d1769ee94777469
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2023-04-07 09:59:52 +00:00
Jeremy Compostella
c49efa365e mb/google/brya: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.

With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.

BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
     End-Of-Post after PCI initialization and EOP message received at
     `BS_PAYLOAD_BOOT'.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-07 04:50:59 +00:00
Jeremy Compostella
1d79188dc5 soc/intel/cmn/cse: Handle EOP completion asynchronously
coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
   `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
   `SOC_INTEL_CSE_SEND_EOP_LATE' is selected

Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.

This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.

This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.

   |    #     | Late EOP | Async EOP |
   |----------+----------+-----------|
   |    1     | 1020.052 |   971.272 |
   |    2     | 1015.911 |   971.821 |
   |    3     | 1038.415 |  1021.841 |
   |    4     | 1020.657 |   993.751 |
   |    5     | 1065.128 |  1020.951 |
   |    6     | 1037.859 |  1023.326 |
   |    7     | 1042.010 |   984.412 |
   |----------+----------+-----------|
   | Mean     |  1034.29 |    998.20 |
   | Variance |   4.76 % |    5.21 % |

The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.

We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.

   |        # | Late EOP | Async EOP |
   |----------+----------+-----------|
   |        0 | 1067.719 |  1050.106 |
   |        1 | 1058.263 |  1056.836 |
   |        2 | 1064.091 |  1056.709 |
   |        3 | 1068.614 |  1055.042 |
   |        4 | 1065.749 |  1056.732 |
   |        5 | 1069.838 |  1057.846 |
   |        6 | 1066.897 |  1053.548 |
   |        7 | 1060.850 |  1051.911 |
   |----------+----------+-----------|
   |     Mean |  1065.25 |   1054.84 |

The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.

CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
   requested to wait for the command completion before loading the OS or
   second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
   command and can perform other operations in the meantime as long as
   they do not involve HECI commands.

On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post.  FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.

If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.

According to commit 387ec919d9 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.

This patch also introduces a new code logic to detect if CSE is in the
right state to handle the EOP command. Otherwise, it uses the
prescribed method to make the CSE function disable. The typical
scenario is the ChromeOS recovery boot where CSE stays in RO partition
and therefore EOP command should be avoided.

    [DEBUG]  BS: BS_PAYLOAD_LOAD exit times (exec / console): 0 / 14 ms
    [INFO ]  HECI: coreboot in recovery mode; found CSE in expected
             SOFT TEMP DISABLE state, skipping EOP
    [INFO ]  Disabling Heci using PMC IPC
    [WARN ]  HECI: CSE device 16.0 is hidden
    [WARN ]  HECI: CSE device 16.1 is disabled
    [WARN ]  HECI: CSE device 16.2 is disabled
    [WARN ]  HECI: CSE device 16.3 is disabled
    [WARN ]  HECI: CSE device 16.4 is disabled
    [WARN ]  HECI: CSE device 16.5 is disabled

BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
     End-Of-Post sent soon after FSP-s and EOP message receive at
     `BS_PAYLOAD_BOOT'.  Verify robustness by injecting a
     `GET_BOOT_STATE' HECI command with or without `heci_reset'. The
     implementation always successfully completed the EOP before
     moving to the payload. As expected, the boot time benefit of the
     asynchronous solution was under some injection scenario
     undermined by this unexpected HECI command.

Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I01a56bfe3f6c37ffb5e51a527d9fe74785441c5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-07 04:50:47 +00:00
Subrata Banik
1d13fba3c3 soc/intel/meteorlake: Perform feature control lock
This function calls into `set_feature_ctrl_lock()` to lock
IA32_FEATURE_CONTROL MSRfeature control.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie9a03ee6786144dae6fd3a18bcc53cb62919dd42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06 19:35:48 +00:00
Subrata Banik
ad6073c8b0 soc/intel/meteorlake: Enable VMX using coreboot CPU feature program
This function calls into `set_feature_ctrl_vmx_arg()`
to enable VMX for virtualization if not done by FSP (based on
DROP_CPU_FEATURE_PROGRAM_IN_FSP config is enabled) in MeteorLake
SoC based platform.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7e49c15fd4f78a3e633855fea550720f0a685062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06 19:35:02 +00:00
Subrata Banik
d8fc4fa4e6 soc/intel/meteorlake: Set AES-NI Lock
This function performs locking of the AES-NI enablement state.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I16f1c14d8a0ca927a34c295cb95311bd4972d691
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06 19:34:09 +00:00
Subrata Banik
6e911eebc5 soc/intel/meteorlake: Disable 3-strike error
This patch calls into API to disable 3-strike error on
Meteor Lake SoC based platform.

TEST=Able to build and boot google/rex to ChromeOS.
Dumping MSR 0x1A4 shows BIT11 aka 3-strike error is disabled

```
  localhost ~ # iotools rdmsr 0 0x1a4
  0x0000000000000900
```

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5c33a1fa2d7e27ec8ffdea876edbb86adc3b45b9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06 19:33:37 +00:00
Subrata Banik
fa85b0f37c soc/intel/meteorlake: Allow to drop redundant CPU feature programming
This patch introduces a new config named
`DROP_CPU_FEATURE_PROGRAM_IN_FSP` to avoid FSP running basic CPU
feature programming on BSP and on APs using the "CpuFeaturesPei.efi"
module.

Most of this feature programming is getting performed today in scope
of coreboot doing MP Init. Running this redundant programming in
scope of FSP (when `USE_FSP_FEATURE_PROGRAM_ON_APS` config is enabled)
results in CPU exception (for example: attempting to reprogram CPU
feature lock MSR is causing CPU exception).

SoC users should select this config after dropping "CpuFeaturesPei.ffs"
module from FSP-S Firmware Volume (FV). Upon selection, coreboot runs
those additional feature programming on BSP and APs.

This feature is by default enabled, in case of "coreboot running MP
init" aka `MP_SERVICES_PPI_V2_NOOP` config is selected.

At present, this option does not do anything unless any platform
eventually decides to drop FSP feature programming module and choose
coreboot CPU feature programming over it.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3be5329390401024d7ec9eed85a5afc35ab1b776
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-06 19:33:12 +00:00
Subrata Banik
39b7665abe soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
In Intel designs, internal processor errors, such as a processor
instruction retirement watchdog timeout (also known as a 3-strike
timeout) will cause a CATERR assertion and can only be recovered from by
a system reset.

This patch prevents the Three Strike Counter from incrementing (as per
Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging.

TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-06 19:32:28 +00:00
Patrick Rudolph
ccbe9a5435 soc/intel/xeon_sp/spr: Drop devicetree setting X2apic
Drop devicetree setting X2apic as the same functionality is already
exposed in Kconfig.

To activate X2apic select X2APIC_ONLY or X2APIC_RUNTIME in
the "APIC operation mode".

Note: Your OS must have support for X2APIC. If you are using less
      than 256 CPU cores select XAPIC_ONLY here.

Test:
- Booted to OS in X2APIC mode when X2APIC_ONLY or X2APIC_RUNTIME
  was selected.
- Booted to OS in XAPIC mode when XAPIC_ONLY was selected.

Change-Id: I65152b0696a45b62a5629fd95801187354c7a93b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-06 07:08:49 +00:00
Patrick Rudolph
ae90fc0bb6 soc/intel/xeon_sp/spr: Default to X2APIC support
When more than 255 CPU cores are present on a board
the X2APIC must be used.

Select DEFAULT_X2APIC_RUNTIME to support X2APIC by
default when a mainboard enables it in the devicetree.

Change-Id: I3e84cfbd2a7f05b142dc4d782764edce81646c8a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74184
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-06 06:53:43 +00:00
Patrick Rudolph
6e6832d898 soc/intel/xeon_sp/spr: Fix ACPI errors on multi socket systems
Inject ACPI code for all generated ASL templates.
This fixes ACPI errors shown in linux when not all sockets
are currently plugged in or some have been disabled.

Test:
Boot Archer City with CONFIG_MAX_SOCKET=4

Change-Id: I9562a37a92c6140a5623db3c8fb5972e6a90aaa4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74183
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
2023-04-05 19:23:03 +00:00
Cliff Huang
69564f3de5 soc/intel/common/block/pcie/rtd3: Add root port mutex support
When 'use_rp_mutex' (default = 0) is set in the device tree, a root
port mutex will be added. This mutex is used in _ON and _OFF method,
where the GPIO reset and/or enable GPIO value is changed. The
companion driver, such as WWAN driver, needs to acquire this root
port mutex when accessing the same GPIO pins. Using this common mutex
prevents those invoked methods from being called from different thread
while one is not completed.

An example is that WWAN driver calling _RST method to reset the device
and does remove/rescan for the device while the pm runtime work might
call RTD3 _OFF.

For those root port without additional driver, this mutex is not needed.

BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated and _ON and _OFF should use this
mutex.

Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ibc077528692b2d7076132384fb7bd441be502511
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
2023-04-05 12:45:24 +00:00
Nick Vaccaro
417fc15d8a Revert "soc/intel/cmn/cse: Handle EOP completion asynchronously"
This reverts commit e7a1204f26.

This initial change was causing a boot failure when transitioning into
recovery mode.

BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.

Change-Id: Ibebb20a000a239c344af1c96b8d376352b9c774e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74207
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-05 03:56:10 +00:00
Nick Vaccaro
78d0e807a9 Revert "mb/google/brya: Enable asynchronous End-Of-Post"
This reverts commit 11f2f88a27.

Revert initial change as it was causing a boot failure when
transitioning into recovery mode.

BUG=b:276927816
TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas
SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into
recovery mode.

Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-05 03:55:32 +00:00
Bora Guvendik
34c37bb1c5 soc/intel/meteorlake: Inject CSE TS into CBMEM timestamp table
Get boot performance timestamps from CSE and inject them into CBMEM
timestamp table.

990:CSME ROM started execution                        0
944:CSE sent 'Boot Stall Done' to PMC                 47,000
945:CSE started to handle ICC configuration           225,000 (178,000)
946:CSE sent 'Host BIOS Prep Done' to PMC             225,000 (0)
947:CSE received 'CPU Reset Done Ack sent' from PMC   516,000 (291,000)
991:Die Management Unit (DMU) load completed          587,000 (71,000)
  0:1st timestamp                                     597,427 (10,427)

BUG=b:259366109
TEST=Able to see TS elapse prior to IA reset on Rex

Change-Id: I548cdc057bf9aa0c0f0730d175eaee5eda3af571
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73713
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04 08:08:35 +00:00
Bora Guvendik
94050499ca soc/intel/alderlake: Add support for CSE timestamp data versions
CSE performance data timestamps are different for version 1
Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch
moves the current ADL/RPL timestamp definitions to a separate
header file. It marks current structure as version 1.

BUG=b:259366109
TEST=Boot to OS, check ADL/RPL pre-cpu timestamps.

Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04 08:07:56 +00:00
Jeremy Compostella
0973c32c5d soc/intel/alderlake: Fix RPL-U 15W and RPL-P 28W TDC current values
The Intel Power and Performance (PnP) team requested to update the
following:
- TDC settings for RPL-U 15W variant should be 22A.
- TDC settings for RPL-P 28W variant should be 33A.

BUG=b:275694022
BRANCH=firmware-brya-14505.B
TEST=PnP validated performance impact with these settings on both
     RPL-U 15W and RPL-P 28W

Change-Id: I1141414785a990b975e32ebc03e490b83082aab7
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74046
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03 13:24:40 +00:00
Sridhar Siricilla
f8ac3dda02 soc/intel/common: Order the CPUs based on their APIC IDs
The patch  defines acpi_set_cpu_apicid_order() which orders the APIC IDs
based on APIC IDs of Performance cores and Efficient cores, calculates
the total core count and total Performance cores count,  populates the
information in the cpu_apicid_order_info struct.
The helper function useful to present the Performance and Efficient
cores in order to OS through MADT table and _CPC object.

TEST=Verify the build for Gimble (Alder Lake board)

Change-Id: I8ab6053ffd036185d74d5469fbdf36d48e0021ce
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72131
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02 10:53:46 +00:00
Subrata Banik
450699d1c8 soc/intel/meteorlake: Set Power Performance Platform Override
According to document 640858 MTL EDS Vol2, bit 18 (PWR_PERF_PLATFRM_OVR) of MSR_POWER_CTL must be set.

This patch is backported from
`commit 117770d324 ("soc/intel/
alderlake: Enable Energy/Performance Bias control")`.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic83225b619c49db0b49b521a83a2f1dc1ad69be8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74155
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02 10:07:21 +00:00
Subrata Banik
d0d7f47104 soc/intel/meteorlake: Add EPP override support
This updates energy performance preference value to all logical CPUs
when the corresponding chip config is true.

This patch is backported from
`commit 0bb2225718 ("soc/intel/alderlake: Add EPP override
support")`.

BUG=b:266522659
TEST=Able to build and boot google/rex.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8172276159fe3987dae36ec30ebceb76dd0ef326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74154
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-02 10:07:12 +00:00
Patrick Rudolph
f7f7b3bbf6 soc/intel/alderlake: Add ADL-P 4+4 with 28W TDP
Add the 28W TDP version of the ADL-P with MCHID 0x4629.

Verified that all 28W SoCs have the same PL1/PL2 defined
in Intel document #655258 "12th Generation Intel Core
Processors Datasheet, Volume 1 of 2".

Fixes the error seen in coreboot log:
[ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration

Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-02 06:27:50 +00:00
Jonathan Zhang
d80e6f2eca soc/intel/xeon_sp/spr: Add ACPI support for Sapphire Rapids
Add ACPI support for Sapphire Rapids. Passes FWTS ACPI tests.
The code was written from scratch because there are Xeon-SP specific
implementation especially Integrated Input/Output (IIO).

Change-Id: Ic2a9be0222e122ae087b9cc8e1859d257e3411d6
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71967
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-01 09:28:05 +00:00
Subrata Banik
6ee454a031 soc/intel/meteorlake: Add BUILDING_WITH_DEBUG_FSP
Intel FSP has "debug" build which is not public, used for debugging by
approved developers. Add a Kconfig to indicate that coreboot is building
with debug version of FSP so we can adjust few things (i.e. flash
layout) in the case.

BUG=b:262868089
TEST=Able to build and boot google/rex.

Change-Id: I5555a2ab4182ad0036c42be6fea3d934ffd0db8c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01 06:07:43 +00:00
Ivy Jian
c5c6372395 soc/intel/meteorlake: Fix PortUsb30Enable configuration
PortUsb30Enable has been overridden unexpectedly, this patch fixed it.

BUG=b:276181378
Test=boot to rex and check USB3 ports are working.

Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ic04b9eb236ed28a76ee516c52fc0c983cb8f2c0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-01 06:07:18 +00:00
Sridhar Siricilla
2afac1956f soc/intel/meteorlake: Enable 'struct cpu_info' update for MTL
The patch enables addition of core_type member to 'struct cpu_info'
for MeteorLake platform.

TEST=Build and verify the code for Rex

Change-Id: I01abed6b87bec2f8eb39bfc941faff070b83abe6
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74130
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-01 05:38:24 +00:00
Jeremy Compostella
11f2f88a27 mb/google/brya: Enable asynchronous End-Of-Post
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.

With these settings we have observed a boot time reduction of about 20
to 30 ms on brya0.

BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
     End-Of-Post after PCI initialization and EOP message received at
     `BS_PAYLOAD_BOOT'.

Change-Id: I81e9dc66f952c14cb14f513955d3fe853396b21c
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73922
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-31 20:04:43 +00:00
Jeremy Compostella
e7a1204f26 soc/intel/cmn/cse: Handle EOP completion asynchronously
coreboot supports three instances of sending EOP:
1. At CSE `.final' device operation
2. Early as with Alder Lake in chip_operations.init if
   `SOC_INTEL_CSE_SEND_EOP_EARLY' is selected
3. At BS_PAYLOAD_BOOT as designed for Meteor Lake if
   `SOC_INTEL_CSE_SEND_EOP_LATE' is selected

Currently, Alder Lake uses #3 as it results in better and more stable
boot time. However, what would deliver even better result is to not
actively wait for CSE completion.

This patch introduces a new `SOC_INTEL_CSE_SEND_EOP_ASYNC' Kconfig
which split the action of sending EOP request and receiving EOP
completion response from the CSE.

This patch used in conjunction with #1 can significantly
improves the overall boot time on a Raptor Lake design. For example
`SOC_INTEL_CSE_SEND_EOP_ASYNC' on a skolas board can deliver up to 36
ms boot time improvement as illustrated below.

   |    #     | Late EOP | Async EOP |
   |----------+----------+-----------|
   |    1     | 1020.052 |   971.272 |
   |    2     | 1015.911 |   971.821 |
   |    3     | 1038.415 |  1021.841 |
   |    4     | 1020.657 |   993.751 |
   |    5     | 1065.128 |  1020.951 |
   |    6     | 1037.859 |  1023.326 |
   |    7     | 1042.010 |   984.412 |
   |----------+----------+-----------|
   | Mean     |  1034.29 |    998.20 |
   | Variance |   4.76 % |    5.21 % |

The improvement is not stable but comparing coreboot and FSP
performance timestamps demonstrate that the slowness is caused by a
lower memory frequency (SaGv point) at early boot which is not an
issue addressed by this patch.

We also observe some improvement on an Alder Lake design. For example,
the same configuration on a kano board can deliver up to 10 ms boot time
improvement as illustrated below.

   |        # | Late EOP | Async EOP |
   |----------+----------+-----------|
   |        0 | 1067.719 |  1050.106 |
   |        1 | 1058.263 |  1056.836 |
   |        2 | 1064.091 |  1056.709 |
   |        3 | 1068.614 |  1055.042 |
   |        4 | 1065.749 |  1056.732 |
   |        5 | 1069.838 |  1057.846 |
   |        6 | 1066.897 |  1053.548 |
   |        7 | 1060.850 |  1051.911 |
   |----------+----------+-----------|
   |     Mean |  1065.25 |   1054.84 |

The improvement is more limited on kano because a longer PCIe
initialization delays EOP in the Late EOP configuration which make it
faster to complete.

CSME team confirms that:
1. End-Of-Post is a blocking command in the sense that BIOS is
   requested to wait for the command completion before loading the OS or
   second stage bootloader.
2. The BIOS is not required to actively wait for completion of the
   command and can perform other operations in the meantime as long as
   they do not involve HECI commands.

On Raptor Lake, coreboot does not send any HECI command after
End-Of-Post.  FSP-s code review did not reveal any HECI command being
sent as part of the `AFTER_PCI_ENUM', `READY_TO_BOOT' or
`END_OF_FIRMWARE' notifications.

If any HECI send and receive command has been sent the extra code
added in `cse_receive_eop()' should catch it.

According to commit 387ec919d9 ("soc/intel/alderlake: Select
SOC_INTEL_CSE_SEND_EOP_LATE"), FSP-silicon can sometimes (on the first
boot after flashing of a Marasov board for instance) request coreboot
to perform a global request out of AFTER_PCI_ENUM notification. Global
request relies on a HECI command. Even though, we tested that it does
not create any issue, `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag should not
be associated to the `SOC_INTEL_CSE_SEND_EOP_EARLY' flag to prevent
potential a global reset command to "conflict" with the EOP command.

BUG=b:276339544
BRANCH=firmware-brya-14505.B
TEST=Tests on brya0 with and `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
     End-Of-Post sent soon after FSP-s and EOP message receive at
     `BS_PAYLOAD_BOOT'.  Verify robustness by injecting a
     `GET_BOOT_STATE' HECI command with or without `heci_reset'. The
     implementation always successfully completed the EOP before
     moving to the payload. As expected, the boot time benefit of the
     asynchronous solution was under some injection scenario
     undermined by this unexpected HECI command.

Change-Id: Ib09dcf9140eb8a00807a09e2af711021df4b416f
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73619
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-31 20:04:14 +00:00
Sridhar Siricilla
44c1b5e117 soc/intel/alderlake: Enable 'struct cpu_info' update for ADL
The patch enables addition of core_type member to 'struct cpu_info' for
Alderlake platform.

TEST=Build and verify the code for Gimble

Change-Id: Ia065b98c2013e78328fd38bed9c667792d6d1f4d
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74089
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31 08:37:28 +00:00
Sridhar Siricilla
1b04e811fb soc/intel/common: Add core_type member to 'struct apic_path'
The patch adds new member 'core_type' to the 'struct apic_path' and
updates core type information.

TEST=Build the code for MTL

Change-Id: I1d34068fd5ef43f8408301bf3effa9febf85f683
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74088
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-31 08:36:47 +00:00
Subrata Banik
603dd56618 soc/intel/alderlake: Avoid reprogramming the SRAM BAR
This patch avoids the redundant programming of SRAM BAR when
the SRAM PCI device is enabled. Rather read the PCH SRAM Base
Address Register while enabling crashlog feature.

Additionally, this patch relies on PCI enumeration to get the
SRAM BAR rather than hijacking the SPI temporary base address
which might have resulted in problems if SPI is disabled on
some platform with BAR being implemented.

TEST=Able to build and boot google/marasov and crashlog is working.

Change-Id: I8eb256aa63bbf7222f67cd16a160e71cfb89875a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-30 13:35:06 +00:00
Pratikkumar Prajapati
0a71e09cf9 soc/intel/common: Add Intel Trace Hub driver
From Meteor Lake onwards Intel FSP will generate the Trace Hub related
HOB if the Trace Hub is configured to save data in DRAM. This memory
region is used by Trace Hub to store the traces for debugging purpose.
This driver locates the HOB and marks the memory region reserved so
that OS does not use it.

Intel Trace Hub developer manual can be found via document #671536 on
Intel's website.

Change-Id: Ie5a348071b6c6a35e8be3efd1b2b658a991aed0e
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-03-29 13:15:48 +00:00
Subrata Banik
b0ddae6a5b soc/intel/cmn/crashlog: Add check for zero based SRAM BAR
This patch adds a check for zero based SRAM base address. It will
help to avoid running into problems if the SRAM is disabled and
the base address register is zero.

TEST=Able to build and boot google/marasov with PCH SRAM being
disabled.

Change-Id: Iebc9dc0d0851d5f83115f966bf3c7aad1eb6bc01
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-29 07:36:18 +00:00
Jonathan Zhang
ffc5a1ce30 soc/intel/xeon_sp: Use simple device function for setting PMAX_LOCK
Change to use simple device function for setting PMAX_LOCK because
the Sapphire Rapids PCU device is not scanned during coreboot PCIe
bus scan and would see "PCI: dev is NULL!" failure.

Change-Id: I3156a6adf874b324b5f4ff5857c40002220e47ab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72400
Reviewed-by: Simon Chou <simonchou@supermicro.com.tw>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-28 13:28:46 +00:00
Subrata Banik
36ca7b3104 soc/intel: Move USB PORTSC definition into IA common code
This patch moves USB Port Status and Control (PORTSC) Reg definition
into IA common code to allow other SoC code to reuse it without
redefining the same for each SoC.

TEST=Able to build and boot google/taeko where USB wake is working.

Change-Id: I6b540eab282403c7a6038916f5982aa26bd631f8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-26 19:44:15 +00:00
Jonathan Zhang
532e8c059e soc/intel/xeon_sp/chip_common.c: Probe all buses in attach_iio_stacks()
For some Xeon-SP (such as SPR-SP), more buses should be probed.

Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ica3c61493a0ff6c699b500f30788b2cf5a06c250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
2023-03-25 16:42:06 +00:00
Tim Chu
5c1964058f soc/intel/xeon_sp/uncore_acpi.c: Add SPR-SP support
Add support for Intel SPR-SP to uncore_acpi.c.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Signed-off-by: Shelly Chang <Shelly_Chang@wiwynn.com>
Change-Id: I4c436a60743bee21b3b6e4060d7874a6cdc75ecf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jon.zhixiong.zhang@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-25 16:33:36 +00:00
Tim Chu
3ba1621dab soc/intel/xeon_sp/smihandler.c: enable support for spr-sp
For SPR-SP, the SMM_FEATURE_CONTROL register is in UBOX_URACU_FUNC
instead of UBOX_DEV_PMON.

Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ide46c5f9cdf65b7e05552449b08ad4d7246664cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-24 16:07:23 +00:00
Naresh Solanki
08135332dd soc/intel/xeon_sp: Report platform cpu info
Add platform cpu info for known microcode, print cpuid & processor
branding string. This will print as in the following example:

CPU: Intel(R) Xeon(R) Platinum 8468H
CPU: ID 806f6, Sapphire Rapids E3, ucode: 2b000130
CPU: AES supported, TXT supported, VT supported

Change-Id: I9c08fb924aad81608f554523432ab6a549b1b75f
Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-03-23 21:21:09 +00:00
Patrick Rudolph
57ddd682ce soc/intel/xeon_sp: Fix PCH IOAPIC ID
FSP may program a different ID under certain circumstances.

Read IOAPIC ID from hardware instead of using some define that
might not reflect how hardware is configured.

Change-Id: Ia91cb4aef9d15520b8b3402ec10e7b0a4355caeb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-23 15:15:55 +00:00
Jeremy Compostella
0e1be046ac soc/intel/cmn/cse: Make heci_(send|receive) public functions
Having these two functions public allow "asynchronous"
HECI command implementation.

Typically, these function can be use to implement an asynchronous
End-Of-Post.

BUG=b:268546941
BRANCH=firmware-brya-14505.B
TEST=Successful compilation for brya0

Change-Id: I7d029bb9af4b53f219018e459d17df9c1bd33fc1
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-23 13:53:10 +00:00
Michał Żygowski
14701a4df3 soc/intel/elkhartlake: Define DIMM_SPD_SIZE in SoC Kconfig
The default SPD size is set to 256 bytes, instead of 512 for
LPDDR4/DDR4 if not overridden by the mainboard Kconfig. This caused
the SMBus libraries to read only the lower half of the DIMM SPD on
protectli/vault_ehl. The lower half of the SPD passed to FSP causes
a bug in DIMM change detection, which relies on the CRC of the
manufacturer bytes in the upper half of the SPD (CRC of zero bytes
always gives zero so no change was assumed). Setting the DIMM SPD size
to 512 fixes it.

Setting the SPD size in SoC will also avoid such problems in the future
Elkhart Lake ports. Elkhart Lake supports only LPDDR4/DDR4 so providing
the correct default of 512 bytes is an obvious thing to do.

TEST=Boot Protectli VP2420 (vault_ehl) with different DIMMs and see
FSP is retraining the memory instead of doing the fastboot with old
DIMM data.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I998ed8781951034419cadc26c04ff1e0a124b267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73933
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23 08:46:34 +00:00
Subrata Banik
30a011417f soc/intel: Rename IA common code module from TOM to RAMTOP
This patch renames all references of `top_of_ram` (TOM) in IA common
`basecode` module (for example: functions, variables, Kconfig,
Makefile and comments) with `ramtop` aka top_of_ram to make it more
meaningful and to avoid conflicts with Intel SA chipset TOM registers.

BUG=Able to build and boot google/rex with the same ~49ms savings
in place.

Change-Id: Icfe6300a8e4c5761064537fb256cfecbe2afb2d8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73881
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-23 05:54:28 +00:00
Yuchen He
ff4a3a62c2 intel/common/block/smm: remove return statements from void functions
To be consistent with other occurrences in soc/intel/common, remove the
return statements of weak void funtions since they are not generally
useful.

Found by the linter.

Signed-off-by: Yuchen He <yuchenhe126@gmail.com>
Change-Id: I3fb8217cfcae65b5dc317458b59aa431f1ccdaef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-23 00:18:27 +00:00
Jonathan Zhang
907b6f54ef soc/intel/xeon_sp/uncore.c: Add CXL memory into memory map
If the host supports CXL, get proximity domain info from FSP HOB. The
proximity domains may include both processor domains and CXL domains.

Add header definition for proximity domain.

Add CXL memory into memory map.

Change-Id: If3f856958a3e6ed3909240ee455bb639e487087f
Signed-off-by: Jonathan Zhang <jonzhang@meta.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-03-22 12:07:19 +00:00