Commit Graph

1779 Commits

Author SHA1 Message Date
Julius Werner 985ff36bee armv7: Support stack dump after exceptions
This patch enhances the armv7 exception handlers in Coreboot and
libpayload to show the correct SP and LR registers from the aborted
context, and also dump a part of the current stack. Since we cannot
access the banked registers of SVC mode from a different exception mode,
it changes Coreboot (and its payloads) to run in System mode instead. As
both modes can execute all privileged instructions, this should not have
any noticeable effect on firmware operation (please correct me if I'm
wrong!).

Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170045
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit d0db2f5e938200e3f5899c5e1f1606ab2dd5b334)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6538
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10 22:18:50 +02:00
Aaron Durbin a438049422 model_106cx: don't blindly set Kconfig settings
The CPU_ADDR_BITS was being unconditionally set.
Don't do that.

Change-Id: Idbc63328fade8f5f05f7f46282139b86e6694989
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169711
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 858f96d28d8d0aeffe58e1d4d1d559ad161aab66)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6535
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10 16:34:46 +02:00
Gabe Black 7d8a91d0a5 exynos: Get rid of the unused reset.c.
The source file reset.c, present in both the exynos5250 and 5420 directories,
is not being built for either SOC. Let's get rid of the clutter.

Change-Id: Iab4c7982a271d08cbaf3207b6f5431f0ef52697e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/170402
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendrix <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 0ce3898276ff49d171a0d8a650806f0305c0576f)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6542
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10 13:00:31 +02:00
Patrick Georgi f17c58b415 cpu/intel/model_1067x: avoid null-pointer dereference
Change-Id: I7467d4a947e9e447707e1370b7e639ddddc20d3d
Found-by: Coverity Scan
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6570
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-10 08:19:24 +02:00
Edward O'Callaghan a0a019698d cpu/amd/geode_lx: Trivial - remove useless comment
Change-Id: I4b04f84fb2be7da4b7ffab71bb2c41142f455440
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6567
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-08-09 18:32:11 +02:00
Edward O'Callaghan cd2c1245f0 cpu/amd/geode_lx: Reduce fancy ASCII art with embedded comments
Lets try not to play games with the Lexer with fancy ASCII art. Doxygen
has a more well defined and useful syntax for annotations.

Change-Id: I6f6c58971f509064ae1e28a1740e50e2ae721513
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6550
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-09 18:06:09 +02:00
Edward O'Callaghan 728ff392e7 cpu/amd/geode_lx/cache_as_ram.inc: Trivial - Fix indent with tabs
Change-Id: Ic65f8d2cbb5bc459cf513c6b34a5f1846cb2b897
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6549
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-09 18:04:32 +02:00
Stefan Reinauer ff0df2bba5 Exynos5420: clean up SPI driver
That extra struct is not needed, we already defined it earlier on.
Also fix coding style in the file.

Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I586d290f2f3ba2f44aca7fdee400b88547465599
Reviewed-on: https://chromium-review.googlesource.com/169780
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit f7df9f05fb707cac7976cd8a0b36bcf30cef8e0f)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6532
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09 17:36:40 +02:00
Julius Werner 45d2ff317c exynos5420: Implement support to boot with USB A-A firmware upload
This patch ports the USB A-A firmware upload functionality from
exynos5250 over to exynos5420. Essentially just like a conflictless
cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes
the exact same bug with SPI initialization for Pit and Kirby.

Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65751
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132)

exynos5: Fix trivial style nits

A few curly braces on the wrong line.

Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66153
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb)

Squashed two related commits.

Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6500
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08 17:41:46 +02:00
Ronald G. Minnich 71e1c8303b Exynos 5420: skip the EDID read if there is already an EDID.
For many boards, the EDID is known and is set in the ramstage. Reading
the EDID is slow and if we have it we do not want to reread it.

If the raw_edid struct member is non-null, skip reading the EDID.

Change-Id: I63fb11aa90b2f739a351cdc3209faac2713ea451
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://chromium-review.googlesource.com/167116
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: ron minnich <rminnich@chromium.org>
Commit-Queue: Ronald Minnich <rminnich@google.com>
(cherry picked from commit 80f48655570de544a7e1939c4f5f28713f11d829)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6514
Tested-by: build bot (Jenkins)
2014-08-07 23:55:37 +02:00
David Hendricks 0ffa11bdbb exynos5420: Set the CLK_DIV_CPERI1 value as per manual
Set the CLK_DIV_CPERI1 value as recommended by the
0.02 UM section 7.9.1.25.
This suggests to use 0x3F3F0000 as the value to be
set to save power.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64905
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I89a6a72d20374a513019a272628a05e139b31773
Reviewed-on: https://gerrit.chromium.org/gerrit/66787
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 34be13b008e262c641268b7c1c6a08e49f18fc37)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6512
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-07 23:54:54 +02:00
Gabe Black ee4bfbf3e1 exynos: Set up caching in the bootblock.
This improves firmware boot time substantially. Because cbmem isn't available
yet, we need to allocate some space in sram for the ttb. Doing cache
initialization in the bootblock means we can implement this once per CPU
instead of once per mainboard.

Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65938
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73)

exynos5420: flush caches and disable MMU in resume path

This patch flushes the caches and disables the MMU before resuming.

c32b9b3 ("Set up caching in the bootblock.") had a bug where the
dcache and MMU remained enabled in the resume path. This caused
the machine to hang on resume. However, other bugs were preventing
us from testing this properly earlier on so it went unnoticed until
now.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e
Reviewed-on: https://chromium-review.googlesource.com/67007
Reviewed-by: ron minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d)

Squashed two related commits.

Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6511
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07 23:05:10 +02:00
Ronald G. Minnich e10ef42a55 Exynos5420: invoke the cooperative threading in udelay
Call thread_yield_microseconds in udelay. This works with and without
COOP_MULTITASKING enabled.

Change-Id: Ib3eab00d1630dc4daada850e7458ab89702d1864
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66327
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 12e55ba8a68e5d40e08ad169848bdf274887ce0b)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6510
Tested-by: build bot (Jenkins)
2014-08-07 23:04:28 +02:00
Stefan Reinauer 61fcd14561 Exynos5: Remove unneeded USB delays
Change-Id: I1144e9d6d6c4278842fdd36743c8a88555f81707
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65912
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 95b518877edc88347ce9725ffee32f3aed0de7dc)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6505
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 23:09:46 +02:00
Ronald G. Minnich bc6cc112e2 Exynos5420: tighten up display port delays
Shorten a few delays, and make some delays shorter but let the
loops have a higher termination count (i.e. give it the same
amount of time to warm up, but check more frequently).

Change-Id: Id9fe846ae3a8d792b14d62aea4e98d8aad05be43
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66156
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit a112e77f2f21f41f982ca22bebdac213cc8d233a)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6506
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06 23:09:32 +02:00
Hung-Te Lin f2c4241b81 exynos5420: Fix mmc clock source.
The DWMMC controller internally divided clock by values in CLKSEL registers,
so we must adjust MMC clock for that.

Change-Id: I44f55b634cfc6fd81d76631595b6928c862a219f
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66657
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 89ed6c9154f16c6b8d01af03c0b78914773eb469)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6504
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06 23:09:02 +02:00
Ronald G. Minnich d6b16f54b9 Set armv7 up for cpu_info to work as on x86 (so threads can work)
On x86, cpu_info lives at the top of stack. Make the arm do that as
well, as the threading model needs that and so will multicore support.

As part of this change, make the stack size a power of 2.
Also make it much smaller -- 2048 bytes is PLENTY for ram stage.

Note that the small stack size is counterintuitive for rom stage.  How
can this work in rom stage, which needs a HUGE stack for lzma? The
main use of STACK_SIZE has always been in ram stage; since 2002 or so
it was to size per-core stacks (see, e.g.,

src/arch/x86/lib/c_start.S:.space CONFIG_MAX_CPUS*CONFIG_STACK_SIZE

and, more recently, thread stacks. So, we define the STACK_TOP for rom
and ram stage, but the STACK_SIZE has no real effect on the ROM stage
(no hardware red zones on the stack) and hence we're ok with actually
defining the "wrong" stack size. In fact, the coreboot_ram ldscript
for armv7 sizes the stack by subtracting CONFIG_STACK_BOTTOM from
CONFIG_STACK_TOP, so we replicate that arithmetic in bootblock.inc

Observed stack usage in ramstage:
BS: BS_PAYLOAD_LOAD times (us): entry 1 run 153887 exit 1
Jumping to boot code at 23104044
CPU0: stack: 02072800 - 02073000, lowest used address 020728d4, stack used: 1836 bytes
entry    = 23104044

Which means we do need 2K, not 1K.

Change-Id: I1a21db87081597efe463095bfd33c89eba1d569f
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/66135
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit f011097e9f2bfb2f4c1109d465be89a79a65ba3e)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6501
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06 22:07:06 +02:00
David Hendricks b77431336e exynos5420: get rid of old exynos5420_config_l2_cache()
We set up L2 cache early in romstage now so the old
function is now redundant.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef
Reviewed-on: https://gerrit.chromium.org/gerrit/65428
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f)

exynos: stack size: Increase the stack size to 16KB.

The lzma decoding function in the RAM stage allocates nearly 16KB on the stack
which is shared between the bootblock, rom stage, and ram stage. The stack had
been much too small and needed to be expanded.

Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65937
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b)

exynos: gpio: add a bigger delay when reading board strappings

Z-state pins were not reading reliably with a 5us delay, so increase
it to 15us.

This is ported from https://gerrit.chromium.org/gerrit/64338

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35
Reviewed-on: https://gerrit.chromium.org/gerrit/65727
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084)

exynos5420: enable DMC internal clock gating

lets enable memory controller internal clock gating for ddr3.
with these bits enabled we save some power out of ddr3.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60774

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f
Reviewed-on: https://gerrit.chromium.org/gerrit/65728
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781)

exynos5420: Correct the 600MHz PMS value

In UM ver0.02, 600MHz clock PMS values differs from what is programed
currently. Though this also results in 600MHz clock, but it is better to
match what UM says. This patch chnage this as per UM

This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3
(Note: we already used the correct 600MHz value for KPLL)

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5
Reviewed-on: https://gerrit.chromium.org/gerrit/65726
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f)

Squashed five commits pertaining to  exynos.

Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6425
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-05 18:43:42 +02:00
Edward O'Callaghan 5cfef13f8d cpu/intel: Fix out-of-bounds read due to off-by-one in condition
If power_limit_1_time > 129 is false then power_limit_1_time can have a
value of up to 129 leading to an out-of-bounds illegal read indexing the
power_limit_time_sec_to_msr[] array. Thankfully all call sites have been
doing the right thing up until now so the issue has not been visible.

Change-Id: Ic029d1af7fe43ca7da271043c2b08fe3088714af
Found-by: Coverity Scan
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6478
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-04 13:58:14 +02:00
Daniele Forsi 9faacba66b cpu/x86/lapic/lapic.c: trivial: fix comment on #else
The preprocessor symbol has only one "L".

Change-Id: I3ec302f18d3bcc81bb45a9d53140f8aedd019317
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6469
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-03 09:57:50 +02:00
Gabe Black 6ccc45d7d5 timer: Add functions to initialize absolute timer structures.
Otherwise there's no good way to create an absolute timer structure without
fiddling with its internal structure or assuming a zero initialized structure
has a value of zero.

Old-Change-Id: Iffe3b6b25ed7963fcfb66f749c531ea445ea4aeb
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65301
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit e2e5c1ef3bb2df95fdf0e33cb2d975a990d07a4a)

exynos: Simplify the monotonic timer implementation.

The previous implementation was overly complicated, and when used in the
timestamp implementation produced some weird and broken results.

Old-Change-Id: I3048028ddea0657b01b0c94f312764b38d1397e4
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65302
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit 6a3fde9a5b80cdac76d79c65d20d7dd1f1d9e557)

Squashed two closely related commits.

Change-Id: Ifc32d773f4f93d34275a81781001d080357fe8ef
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6406
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31 18:32:52 +02:00
Hung-Te Lin 0682cfefdb armv7/exynos5420: Configure CPU cores for kernel to enable SMP.
The SMP on Exynos 5420 requires setting a special page and entry wrappers in
firmware side (SRAM) so kernel can start cores (and to switch clusters).

Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64770
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
(cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6405
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-31 18:31:53 +02:00
Edward O'Callaghan 370adeedb4 model_206ax_init.c: Trivial - fix indent
Change-Id: I84876c95522fca5560bcbc8e81dfcb09faf3b326
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6412
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-30 23:33:35 +02:00
Martin Roth 09670265b6 cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)
This adds the CPU initialization pieces for Intel's Atom C2000 processor
(Formerly Rangeley).

Change-Id: I77d69f42c959bbc294784f044b7b0dcc2e30f30c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/6368
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 18:59:35 +02:00
Daniele Forsi b532b12b41 model_fxx/processor_name.c, hudson/lpc.c: add missing break statements
Found by Cppcheck 1.65. Fixes:
(warning) Variable 'processor_name_string' is reassigned a value before the old one has been used. 'break;' missing?
(warning) Variable 'rsize' is reassigned a value before the old one has been used. 'break;' missing?

Change-Id: I4a5c947fd5cc5797eb026475ec7036bc5eaf58db
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30 10:35:27 +02:00
Edward O'Callaghan 76a1437dbe cpu/intel/model_2065x/model_2065x_init.c: Remove dead code
Unused array is dead code. Spotted by Clang build.

Change-Id: I11397716b39de08f1226413019e3beeeeaac6149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6131
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-07-30 02:05:00 +02:00
Elyes HAOUAS 0f92f63055 Uniformly spell frequency unit symbol as Hz
Change-Id: I1eb8d5bd79322ff3654a6ad66278a57d46a818c1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: http://review.coreboot.org/6384
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29 04:40:27 +02:00
Vladimir Serbinenko 7686a56574 sandy/ivybridge: Native raminit.
Based on damo22's work and my X230 tracing.

Works for my X230 in a variety of RAM configs.

Also-By: Damien Zammit <damien@zamaudio.com>
Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: http://review.coreboot.org/5786
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29 00:52:28 +02:00
Kyösti Mälkki f8e96f07d4 AGESA boards: Drop get_bus_conf.c files
The only remaining purpose for get_bus_conf() was to fill in obscure
bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete
enumeration is available in devicetree and PCI configuration space so
discard these arrays.

Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6360
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28 17:26:47 +02:00
Kyösti Mälkki 32d9e9296e AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()
Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6357
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28 17:20:35 +02:00
Kyösti Mälkki 526c2fb278 AGESA: Drop some excessive agesawrapper.h includes
Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6262
Tested-by: build bot (Jenkins)
2014-07-28 17:20:01 +02:00
Kyösti Mälkki 9248bb35ab AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()
Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6355
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24 14:00:43 +02:00
Paul Menzel e6f43d2e41 cpu/intel/fsp_model_206ax/model_206ax_init.c: Use macro `IS_ENABLED()`
Change-Id: I91cd84d155a2cb1200cb82c31256cfa743e8ea9b
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6227
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-23 10:18:50 +02:00
Daniele Forsi 53847a211b src/.../Kconfig: various small fixes to texts
Fixed spelling and added empty lines to separate the help
from the text automatically added during make menuconfig.

Change-Id: I6eee2c86e30573deb8cf0d42fda8b8329e1156c7
Signed-off-by: Daniele Forsi <dforsi@gmail.com>
Reviewed-on: http://review.coreboot.org/6313
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-23 09:07:47 +02:00
Vladimir Serbinenko 4af1245ea1 intel/model_2065x: Remove dead code.
nehalem uses gm45-like approach to resume backup so this code is never
used.

Change-Id: Ic32aa73f8d5b164b1c57815f6f44b2732fdbdcdb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5975
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-19 14:25:44 +02:00
Edward O'Callaghan dc112e3515 cpu,Makefile.inc: Trivial - drop trailing blank lines at EOF
Change-Id: I7e8866d76d7f286e10160d7dc4f21f01a913bfee
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6286
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:20:12 +02:00
Edward O'Callaghan 4202f5d3b3 misc,ASL: Trivial - drop trailing blank lines at EOF
Change-Id: I5060052e268c6a6303d77fdf4380a55ac2ad5ae2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6296
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17 02:18:01 +02:00
Kyösti Mälkki d005f78d29 AGESA fam15: Fix entry to cimx/sb900
Move SB900 call to match comments and changes already made for
family14 et al.

Change-Id: I22aa0bbeeabf9cff929c49c23014005bc3d53ccb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6238
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:49:32 +02:00
Kyösti Mälkki b6f3da4ddc AGESA CIMx: Move late init out of get_bus_conf()
Followup deals further with Fam15 case. For unknown reasons calls
were commented out for amd/dinar and they remain that way.

Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6237
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:48:51 +02:00
Kyösti Mälkki 7b23ae0e89 AGESA: Trace execution with AGESAWRAPPER()
Implement logging just once to have uniform output.

Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6180
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:48:00 +02:00
Kyösti Mälkki 9f0a2be165 AMD SPI: Optimise for longer writes
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.

Kconfig AMD_SB_SPI_TX_LEN can be kept as local.

Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14 19:43:03 +02:00
Edward O'Callaghan 7116ac8037 src: Make use of 'CEIL_DIV(a, b)' macro across tree
The objective here is to tighten coreboot up a bit by not repeating
common helpers. This makes the code base more consistent and
unified/tight.

Change-Id: Ia163eae68b4a84a00ed118125e70308fab1cea0c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6215
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-11 08:39:07 +02:00
Matt DeVillier b2a14fb4f1 intel/haswell: add vmx support w/Kconfig option
patch based on VMX support in intel/fsp_model_206ax and intel/model_6fx
tested/verified working on google/panther

Change-Id: I61232fdc2a29c53aa3bea5ea78b2fdc41fd7396a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: http://review.coreboot.org/6223
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-10 16:46:41 +02:00
Edward O'Callaghan f7c55148c0 cpu: Trivial - drop trailing blank lines at EOF
Change-Id: I9004f34ba0c13b4489b26ac8c1476d00a6c6d01d
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6207
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-08 13:52:43 +02:00
Gabe Black 93d9f92cfb spi: Change spi_xfer to work in units of bytes instead of bits.
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.

BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None

Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6175
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:20 +02:00
Gabe Black 1e187356e8 spi: Remove unused parameters from spi_flash_probe and setup_spi_slave.
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.

BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None

Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6174
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:36:11 +02:00
Kyösti Mälkki c06af9eb8b Drop redundant select CACHE_AS_RAM
The few remaining boards without CAR override this with
select ROMCC.

Change-Id: Ifd5223e67f6a2dadb47846bdaab40b1be763cf69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6172
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-05 11:33:23 +02:00
Edward O'Callaghan ba92428514 intel: Make monotonic timer a first class citizen
The monotonic time now needs to be a first class citizen in Coreboot as
it is a hard dependency of the drivers/spi flash command polling
function.

Change-Id: I4e43d2680bf84bc525138f71c2b813b0f6be5265
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6135
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-07-05 00:38:06 +02:00
Kyösti Mälkki ef40ca57eb AGESA: Call get_bus_conf() just once
Instead of calling get_bus_conf() three times from write_tables()
and executing it once, just make one call before entering write_tables().

Change-Id: I818e37128cb0fb5eaded3c1e00b6b146c1267647
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6133
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:48:57 +02:00
Kyösti Mälkki 005028e0a9 AGESA: Add agesawrapper_post_device()
NOTE: The procedure is moved across a collected timestamp
TS_WRITE_TABLES, so the delay of SPI erase/write will be accounted
for in an earlier entry in cbmem -t output.

Change-Id: I0f082e7af1769c8d7d03cdd51fdb5dacbf3402b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6132
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:47:48 +02:00
Kyösti Mälkki e1b468e1a7 AGESA boards: Use acpi_s3_resume_allowed()
This adds use of BROKEN_CAR_MIGRATE to include CBMEM symbols for the
build of romstage also for boards without HAVE_ACPI_RESUME.
These symbols got exposed as the use of preprocessor directives was
reduced.

We expect the linker to do a fair job and optimize away function
bodies that are on unreachable execution paths.

Change-Id: Ibf5181d3eecb87ce647abe0be01072594b05aa5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6067
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-03 09:46:50 +02:00
Kyösti Mälkki adf3d6ff52 AGESA: Clean separation of SPI flash
To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.

For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.

Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-03 09:46:15 +02:00
Kyösti Mälkki 23b4f0c734 AGESA boards: Add prepare_for_resume()
Use one common implementation for all AGESA platforms.

Change-Id: I410f8e0a9c75445882d67659cde00004eb7ad6b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6084
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-03 09:45:58 +02:00
Kyösti Mälkki 31eff28f4f AGESA S3: Refactor S3 backup store locations in SPI
Prepare code to locate S3 backup from CBFS as a file. Follow-up will
replace remaining use of CONFIG_S3_DATA_POS with cbfs_get_file_content().

Change-Id: I693c41c90e61d1a7c7b10e43c9f264d099c9a400
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6083
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-07-03 09:45:43 +02:00
Kyösti Mälkki 38a8fb0c18 x86 MTRR: Drop unused return value
It was never well-defined what value this function should return.

Change-Id: If84aff86e0b556591d7ad557842910a2dfcd3b46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6166
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30 17:55:36 +02:00
Kyösti Mälkki 599cda8228 Use MTRR defines
Change-Id: I60ae6dcb8c3b280fe74f27f4d61de70cc1ba190b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6123
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-30 17:55:16 +02:00
Edward O'Callaghan 4d7539eefd cpu/x86/pae/pgtbl.c: Unsigned comparison < 0 always false
Comparison of unsigned expression < 0 is always false.

Change-Id: Idf4e7846b50f4376a5d33515681efbd773d1caca
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6146
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-29 13:02:13 +02:00
Edward O'Callaghan efe2435fec cpu/amd/geode_gx2/cache_as_ram.inc: Remove illegal ASCII art
Embedding comments inside comments is illegal in the C specification,
Clang enforces this.

Change-Id: I0a468e4196034b00dfc5860fdbbab7788e4fef77
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6154
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-06-29 04:10:15 +02:00
Patrick Georgi 9c41063713 Don't add .eh_frame sections to SMM image
We don't need exception handlers and they waste space.

Change-Id: I98a34d1c9638e8c4168edbfb4b1cddde8a64623f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/6105
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-06-28 16:40:50 +02:00
Kyösti Mälkki 4f7cb87df2 AGESA: Move config parameters for non-volatile S3 data
These parameters are not specific to the southbridge device, but
the implementation of S3 storage defined by CPU code.

Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6081
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 05:43:43 +02:00
Kyösti Mälkki 207880cd11 Declare acpi_is_wakeup_early() only once
Change-Id: I5314d76168c40a6327d4a9ac3b4f4fb05497d6fc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4525
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-25 05:43:18 +02:00
Kyösti Mälkki 9107e53756 cpu/amd/agesa: Use acpi_is_wakeup()
Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.

Change-Id: I6ad5fb7e32c59be7d84f28461c238c3975e1e04e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6078
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:58 +02:00
Kyösti Mälkki c3c4a38c95 Misc: Use acpi_is_wakeup_s3()
Change-Id: I46906e6d68775edc5cfe199cfeb465db4da2691f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6072
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-21 08:04:53 +02:00
Vladimir Serbinenko cc483aee96 intel/model_2065x: Add 20652 microcode.
Change-Id: I2a46806a3f0a57497edebd49e69b97f90948adb9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5117
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-06-17 21:31:01 +02:00
Kyösti Mälkki ef9343cac1 AGESA: Use common heap allocator
Change-Id: I5df1f0efdef2592b762fe391edaadbca4593e85a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5689
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-06-06 13:31:31 +02:00
Martin Roth ae6e0c6beb cpu/intel/fsp_model_206ax: change realpath to readlink
realpath and readlink can be used to do the same thing - in this case
we're turning path1/path2/../path3/path4 into path1/path3/path4 so
that the makefile's wildcard routine can evaluate it.

Debian derivatives don't seem to include realpath. (and even when it's
installed, it's not the gnu coreutils version.)

Change-Id: I0a80a1d9b563810bdf96aea9d5de79ce1cea457a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/5793
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2014-05-30 23:52:17 +02:00
Patrick Georgi 5930774f57 build: use CFLAGS_* in more places where they're needed
After moving out -m32 from CC_*, 64bit compilers need
CFLAGS_* in more places to handle everything in 32bit
as appropriate.

Change-Id: I692a46836fc0ba29a3a9eb47b123e3712691b45d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5789
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-19 15:21:52 +02:00
Patrick Georgi 58f73a69cd build: separate CPPFLAGS from CFLAGS
There are a couple of places where CPPFLAGS are
pasted into CFLAGS, eliminate them.

Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5765
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:29 +02:00
Patrick Georgi 98f49d2823 build: CPPFLAGS is more common than INCLUDES
Rename INCLUDES to CPPFLAGS since the latter is more
commonly used for preprocessor options.

Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5764
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-17 21:14:24 +02:00
Zaolin 3d68b1a62a cpu/intel: Add CPU socket rPGA988B
Used by the Lenovo ThinkPad T520

Change-Id: I1009616cc4c18ebd0e3be7ceb50398617b49e3a3
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: http://review.coreboot.org/5671
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Tested-by: build bot (Jenkins)
2014-05-13 21:58:16 +02:00
Kyösti Mälkki 5c3f384f06 Replace SERIAL_CPU_INIT with PARALLEL_CPU_INIT
Lines with 'select SERIAL_CPU_INIT' where redundant with the
default being yes. Since there is no 'unselect SERIAL_CPU_INIT'
possibility, invert the default and rename option.

This squelches Kconfig warnings about unmet dependencies.

Change-Id: Iae546c56006278489ebae10f2daa627af48abe94
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5700
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-05-10 11:27:25 +02:00
Martin Roth 2dd3f877cc cougar_canyon2: Switch CPU/NB/SB to the shared FSP code
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.

These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda

Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:36:12 +02:00
Martin Roth a6427161c2 Intel FSP: add a shared set of functions for the FSP
- Move the non chipset-specific fsp pieces out of the chipset into a
shared area.  This is used by northbridge / southbrige / SOC code.  It
pulls in pieces from Kconfig, Makefile and FSP specific code.
- Enabled in the CPU code with a Kconfig "select PLATFORM_USES_FSP"

Change-Id: I7ffa934c1df09b71d48a876a56e3b888685870b8
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-09 21:35:56 +02:00
Furquan Shaikh 99ac98f7e1 Introduce stage-specific architecture for coreboot
Make all three coreboot stages (bootblock, romstage and ramstage) aware of the
architecture specific to that stage i.e. we will have CONFIG_ARCH variables for
each of the three stages. This allows us to have an SOC with any combination of
architectures and thus every stage can be made to run on a completely different
architecture independent of others. Thus, bootblock can have an x86 arch whereas
romstage and ramstage can have arm32 and arm64 arch respectively. These stage
specific CONFIG_ARCH_ variables enable us to select the proper set of toolchain
and compiler flags for every stage.

These options can be considered as either arch or modes eg: x86 running in
different modes or ARM having different arch types (v4, v7, v8). We have got rid
of the original CONFIG_ARCH option completely as every stage can have any
architecture of its own. Thus, almost all the components of coreboot are
identified as being part of one of the three stages (bootblock, romstage or
ramstage). The components which cannot be classified as such e.g. smm, rmodules
can have their own compiler toolset which is for now set to *_i386. Hence, all
special classes are treated in a similar way and the compiler toolset is defined
using create_class_compiler defined in Makefile.

In order to meet these requirements, changes have been made to CC, LD, OBJCOPY
and family to add CC_bootblock, CC_romstage, CC_ramstage and similarly others.
Additionally, CC_x86_32 and CC_armv7 handle all the special classes. All the
toolsets are defined using create_class_compiler.

Few additional macros have been introduced to identify the class to be used at
various points, e.g.: CC_$(class) derives the $(class) part from the name of
the stage being compiled.

We have also got rid of COREBOOT_COMPILER, COREBOOT_ASSEMBLER and COREBOOT_LINKER
as they do not make any sense for coreboot as a whole. All these attributes are
associated with each of the stages.

Change-Id: I923f3d4fb097d21071030b104c372cc138c68c7b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5577
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-05-06 20:23:31 +02:00
Aaron Durbin 014baea1ce haswell: move to mp_init library
The mp_init library was based off of haswell code, but baytrail
was the first chipset to take advantage of it. Move haswell over
to using it so that the code duplication can be removed.

Change-Id: Id6e9464df028aa6ec138051f925817c85b4c13e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5413
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-05-05 23:38:22 +02:00
Furquan Shaikh fd33781fbf Move ARCH_* from board/Kconfig to cpu or soc Kconfig.
CONFIG_ARCH is a property of the cpu or soc rather than a property of the
board. Hence, move ARCH_* from every single board to respective cpu or soc
Kconfigs. Also update abuild to ignore ARCH_ from mainboards.

Change-Id: I6ec1206de5a20601c32d001a384a47f46e6ce479
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5570
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-05-03 00:25:20 +02:00
Kyösti Mälkki f385ba42e3 console: Move UART port defaults to mainboard
Correct selection of UART depends of board layout, not the CPU
internals, so default setting should originate from mainboard.

Change-Id: Ibf0ab0847ccce73c22704e86983dbe3d24ebc8a0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5618
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:43 +02:00
Kyösti Mälkki 48713a1bf7 console: Drop EARLY_CONSOLE option
We have means to easily disable a specific console in romstage if
necessary, so this global option makes little sense.

The option was initially introduced as a work-around for build issues
around CACHE_AS_RAM, ROMCC and ARCH_ARMV7 dependencies for UARTs.

Change-Id: I797bdd11a48ddd813d3ee7ccef9a0c050f16f669
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5607
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 07:00:20 +02:00
Kyösti Mälkki 28837c6b01 allwinner/a10: Hide SoC specific UART functions
If platform has a component coreboot has to communicate with using
one of the UARTs, that device would not be part of the SoC and
must not use functions specific to a10 UART.

Change-Id: Ifacfc94dfde9979eae0b0cfb723a6eaa1fbcd659
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5469
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:37 +02:00
Kyösti Mälkki 70342a7f51 uart: Support multiple ports
The port for console remains to be a compile time constant.
The Kconfig option is changed to select an UART port with index
to avoid putting map of UART base addresses in Kconfigs.

With this change it is possible to have other than debug console
on different UART port.

Change-Id: Ie1845a946f8d3b2604ef5404edb31b2e811f3ccd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5342
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-30 06:59:05 +02:00
Kyösti Mälkki bb6c2162d1 AGESA SPI: Fix Kconfig options
Option AMD_SB_SPI_LEN leaked to non-AMD configs.
Option SPI_FLASH is compulsory with HAVE_ACPI_RESUME.

Change-Id: Ib84c4d9e4fdf670b32b0cae7280fcbb6d3aecaf5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5606
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-29 17:31:40 +02:00
Kyösti Mälkki 2458f42b27 AMD: Add common header file for CAR setup
Change-Id: I24b2cbd671ac3a463562d284f06258140a019a37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-04-28 18:36:35 +02:00
Furquan Shaikh 20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Furquan Shaikh 817149643c Get rid of HAVE_INIT_TIMER config option
There is redundancy in terms of use of init_timer. We have a Kconfig option to
decide whether a board has init_timer as well as we use a stub for init_timer in
places where we do not have any init_timer defined. Thus, remove the Kconfig
option. Henceforth, all boards that do not have init_timer functionality can
include a stub_timer if required.

Change-Id: I35d38ec686f4dc92861cf9248f9b540323cd98ae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-26 13:25:28 +02:00
Kyösti Mälkki 46b0951182 Move MAX_PHYSICAL_CPUS to AMD k8 and fam10
This was always AMD-only and it was never properly used with AGESA.

Change-Id: Ifb461ee845e442f6cf90aca52470cfb66e862bfc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5540
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-20 20:04:07 +02:00
Kyösti Mälkki 4076072b6c console: Use romstage code for ramstage and SMM
Console is arch-agnostic and there is no need for separate
implementations for romstage and ramstage.

For SMM there is console only if DEBUG_SMI is selected.

Change-Id: I7028eeeff8bfbb9c8552972436b29a7508834d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-18 16:39:19 +02:00
Alexandru Gagniuc 065b7da298 cpu/amd/agesa/family15tn: Add udelay implementation for SMM
This is a small implementation which uses only MSRs and rdtsc, without
relying on northbridge or other system hardware. It's SMM safe in that
it only reads registers, and doesn't modify the state of the hardware.

Change-Id: Ifa02ca73455b382f830c9b30b80b4f1bb18706b4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5501
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-04-16 23:42:19 +02:00
Alexandru Gagniuc 53072d869a cpu/amd/agesa/family15tn: Add initial support for SMM mode
This is the minimal setup needed to be able to execute SMI handlers.
Only support for ASEG handlers is added, which should be sufficient
for Trinity (up to 4 cores).

There are a few hacks which need to be introduced in generic code in
order to make this work properly, but these hacks are self-contained.
They are a not a result of any special needs of this CPU, but rather
from a poorly designed infrastructure. Comments are added to explain
how such code could be refactored in the future.

Change-Id: Iefd4ae17cf0206cae8848cadba3a12cbe3b2f8b6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5493
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-04-16 23:42:00 +02:00
Edward O'Callaghan e07cb65c20 vendorcode/amd/agesa/fam14: Build as a static library
Following the same reasoning as commit
ee905a8 vendorcode/amd/agesa/fam15tn: Build as a static library
Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

Change-Id: I8b78c462f4963fbb3a40d739196529fffedccb4c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5441
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-15 17:23:37 +02:00
Alexandru Gagniuc ee905a8161 vendorcode/amd/agesa/fam15tn: Build as a static library
Up until now, we were building AGESA by specifying each AGESA source
file and adding it to the list of romstage and ramstage source files.
As a result, we were compiling each AGESA source twice, despite the
fact that it does not depend on the stage we're in.

Since AGESA is stage-independent, we can build it just once, and use
the resulting static library in both rom and ram stages.

We still keep the practice of specifying every single AGESA directory
as an include dir and adding the AGESA CFLAGS to our global CFLAGS;
this is needed due to the way AGESA builds.

Change-Id: I9b23264129d1c08cb67cabc31d15a68d43ed7624
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5430
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-04-15 01:30:25 +02:00
Alexandru Gagniuc 374251d901 cpu/amd/agesa/s3_resume.c: Specify include paths from AGESA_ROOT
Following the same reasoning as in commit
* 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
include AGESA files with a path relative to AGESA_ROOT. We cannot
with more than one generation of AGESA, hence the path being relative
to AGESA_ROOT.

Change-Id: If15c4cbfd42e0264264fdb3e8c426a47609ad41f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5426
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-13 08:25:23 +02:00
Patrick Georgi 5d41c1a7f9 agesa: Always include family* Kconfig
Otherwise we generate a recursive dependency because
CPU_AMD_AGESA depends on the per-family configurations
while those only exist if CPU_AMD_AGESA is selected.

Change-Id: Ic08d517ff4ca8bb76afc1574b55c54b28ec3f1b0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5490
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-04-12 13:34:36 +02:00
Kyösti Mälkki 657e0be464 console: Move newline translation outside console_tx_byte
This gives us completely transparent low-level function to transmit
data.

Change-Id: I706791ff43d80a36a7252a4da0e6f3af92520db7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5336
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 13:21:25 +02:00
Kyösti Mälkki afa7b13b93 uart: Redefine Kconfig options
Option DRIVERS_UART builds with support for UART hardware.
Option CONSOLE_SERIAL enables the console output for UART.

Those x86 boards that do not have serial port on SuperIO should select
NO_UART_ON_SUPERIO to disable 8250 UART for the default configuration.

Removes:
  CONSOLE_SERIAL_UART
  HAVE_UART_IO_MAPPED
  HAVE_UART_MEMORY_MAPPED

Renames:
  CONSOLE_SERIAL8250     ->  DRIVERS_UART_8250IO
  CONSOLE_SERIAL8250MEM  ->  DRIVERS_UART_8250MEM

Change-Id: Id3afa05f85c0d6849746886db8b6c2ed6c846b61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5311
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:24:43 +02:00
Kyösti Mälkki bbf6f3d384 console uart: Fill coreboot table entries
Also fixes the reported baudrate to take get_option() into account.

Change-Id: Ieadad70b00df02a530b0ccb6fa4e1b51526089f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5310
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-09 11:19:27 +02:00
Kyösti Mälkki c2610a4a18 uart: Prepare to support multiple base addresses
Prepare low-level register access to take UART base address as a
parameter. This is done to support a list of base addresses defined
in the platform.

Change-Id: Ie630e55f2562f099b0ba9eb94b08c92d26dfdf2e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5309
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 11:13:03 +02:00
Patrick Georgi e5760af398 cpu/amd/car: Use define MSR_MCFG_BASE rather than hardcoded value
Change-Id: I0b40c9811115b204f1cae70546d236049c1b3d30
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5431
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-04-09 10:55:27 +02:00
Edward O'Callaghan c814be4158 amd/agesa/s3_resume: Make compiler agnostic.
Clang does not like inline functions defined in C files with prototypes
in headers. Rather Clang expects inline function bodies to be in headers
if they are to be used out of scope. Since inline is purely advisory to
the compiler, drop its usage here.

Change-Id: I08a7a3d2cdf841ffbab10c017c75917768aac209
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5429
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-03 10:00:52 +02:00
Aaron Durbin 905bfb05dc x86: use car_(get|set)_var accessors for apic timer
The timer_fsb variable was not correctly being accessed in the
presence of cache-as-ram. The cache-as-ram backing store could
be torn down but then udelay() could be called causing hangs from
accessing variables that have unknown values.

Instead change the timer_fsb variable to g_timer_fsb and obtain
the value through a local access method that does the correct things
to obtain the correct value.

Change-Id: Ia3e30808498cbe4a7f6f116c17a8cf1240a807a3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5411
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-01 14:31:36 +02:00
Kyösti Mälkki deb2cb27e9 Static CBMEM / CAR: Flag boards with BROKEN_CAR_MIGRATE
Use of CAR_GLOBAL is not safe after CAR is torn down, unless the
board properly implements EARLY_CBMEM_INIT.

Flag vulnerable boards that only do cbmem_recovery() in romstage on S3
resume and implementation with Intel FSP that invalidates cache before
we have a chance to copy the contents.

Change-Id: Iecd10dee9b73ab3f1f66826950fa0945675ff39f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-04-01 11:36:00 +02:00
Alexandru Gagniuc 01c44000be cubieboard: Enable the SD controller and mux SD pins
This step needs to be done before calling any MMC functionality.

Change-Id: I88763072c8a541ddba794e79fb55e82eb2f187a9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-03-29 22:28:44 +01:00
Aaron Durbin 3eb8eb7eba rmodules: use rmodtool to create rmodules
Start using the rmodtool for generating rmodules.
rmodule_link() has been changed to create 2 rules:
one for the passed in <name>, the other for creating
<name>.rmod which is an ELF file in the format of
an rmodule.

Since the header is not compiled and linked together
with an rmodule there needs to be a way of marking
which symbol is the entry point. __rmodule_entry is
the symbol used for knowing the entry point. There
was a little churn in SMM modules to ensure an
rmodule entry point symbol takes a single argument.

Change-Id: Ie452ed866f6596bf13f137f5b832faa39f48d26e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5379
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2014-03-20 23:55:55 +01:00
Idwer Vollering 5809a7395d Make POST device configurable.
Change-Id: If92b50ab3888518228d2d3b76f5c50c4aef968dd
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4561
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-03-16 21:42:49 +01:00
Aaron Durbin c34713d33e x86: add MIRROR_PAYLOAD_TO_RAM_BEFORE_LOADING option
Boot speeds can be sped up by mirroring the payload into
main memory before doing the actual loading. Systems that
would benefit from this are typically Intel ones whose SPI
are memory mapped. Without the SPI being cached all accesses
to the payload in SPI while being loaded result in uncacheable
accesses. Instead take advantage of the on-board SPI controller
which has an internal cache and prefetcher by copying 64-byte
cachelines using 32-bit word copies.

Change-Id: I4aac856b1b5130fa2d68a6c45a96cfeead472a52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5305
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-03-07 15:30:27 +01:00
Kyösti Mälkki 0567c91b22 console: Use single driver entry for UARTs
UARTs now have unified prototypes and can use a single entry
in the list of drivers for ramstage.

Change-Id: I315daaf9a83cfa60f1a270146c729907a1d6d45b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5308
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:40:34 +01:00
Kyösti Mälkki 9c479c9a3e SMM: Only have console with DEBUG_SMI
Existing code compiled serial communication and printk() for SMM
even when DEBUG_SMI was not selected.

Change-Id: Ic5e25cd7453cb2243f7ac592b093fba752a299f7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5142
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-03-04 15:36:27 +01:00
Kyösti Mälkki bea6bf07df uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5236
Tested-by: build bot (Jenkins)
2014-03-04 15:34:27 +01:00
Kyösti Mälkki 2b95da01e6 uart8250mem: Unify calls with generic UART
NOTE: UART base for SMM continues to be broken, as it does not use
the address resource allocator has assigned.

Change-Id: I79f2ca8427a33a3c719adfe277c24dab79a33ef3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5235
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:28:41 +01:00
Kyösti Mälkki 4770749edc uart8250io: Unify calls with generic UART
Change-Id: I6d56648e56f2177e1d5332497321e718df18300c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5234
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:27:53 +01:00
Kyösti Mälkki 1d7541feeb console: Fix includes
Do not pull in console hw-specific prototypes everywhere
with console.h as those are not needed for higher levels.

Move prototypes for UARTs next to other consoles.

Change-Id: Icbc9cd3e5bdfdab85d7dccd7c3827bba35248fb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5232
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:26:08 +01:00
Kyösti Mälkki 2cbcd2b710 ti/am335x: Fix baudrate calculation
UART input clock is platform dependent. Also account for possible
use of get_option() where baudrate is not compile-time constant.

The hardware reference on BeagleBone is from a 48 MHz oscillator input.
With pre-divisor of 16 we get same register values as in table 19-25.

Change-Id: I89aee27c958f8618ce79a968ae7520a867e7e8a2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5290
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:50 +01:00
Kyösti Mälkki 65ba20e17b allwinner/a10: Fix baudrate calculation
UART input clock is platform dependent. Also account for possible
use of get_option() where baudrate is not compile-time constant.

Change-Id: Ie1c8789ef72430e43fc33bfa9ffb9f5346762439
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5289
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:32 +01:00
Kyösti Mälkki c5332e30da samsung/exynos5: Fix baudrate calculation
Account for possible use of get_option() when baudrate is no longer
compile-time constant.

Change-Id: Ib45acd98e55c5892dbce9903830665aefeda5be0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5288
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:24:10 +01:00
Kyösti Mälkki c76b3d6cca uart: Drop HAVE_UART_MEMORY_MAPPED
This option is used to make uart8250mem option visible in menuconfig.
Showing it for these ARMs is incorrect.

Change-Id: I2c28e1c3781df41c09c365355a5105c9fe4945ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5259
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:19:28 +01:00
Kyösti Mälkki a172ea5469 uart: Do not guard entire include file by config options
Do not guard the file by CONFIG_CONSOLE_SERIAL8250 or
CONFIG_CONSOLE_SERIAL8250MEM or CONFIG_CONSOLE_SERIAL.

Don't do indirect includes for <uart8250.h>.

The config-specific options are already properly guarded, and there
is no need to guard the register and bit definitions.

Change-Id: I7528b18cdc62bc5c22486f037e14002838a2176e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4585
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-03-04 15:18:27 +01:00
Vladimir Serbinenko 4337020b95 Remove CACHE_ROM.
With the recent improvement 3d6ffe76f8,
speedup by CACHE_ROM is reduced a lot.
On the other hand this makes coreboot run out of MTRRs depending on
system configuration, hence screwing up I/O access and cache
coherency in worst cases.

CACHE_ROM requires the user to sanity check their boot output because
the feature is brittle. The working configuration is dependent on I/O
hole size, ram size, and chipset. Because of this the current
implementation can leave a system configured in an inconsistent state
leading to unexpected results such as poor performance and/or
inconsistent cache-coherency

Remove this as a buggy feature until we figure out how to do it properly
if necessary.

Change-Id: I858d78a907bf042fcc21fdf7a2bf899e9f6b591d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5146
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-25 00:57:35 +01:00
Kyösti Mälkki d47c08affd TI am335x: Apply Kconfig use conventions
Change-Id: Ic3c26fd7b1dd8a6731abc9a63b9ca17e084074b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5291
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-02-24 14:57:22 +01:00
Edward O'Callaghan d777d86ab2 CAR_GLOBAL: enforce compiler to check if _start != _end
There are some fun rules C compilers can use to optimize their code.
One of them is the assumption that two symbols point to two different
addresses.
In this case this wasn't true, resulting in unintended code execution
(and later, a crash) with a clang build.

Change-Id: I1496b22e1d1869ed0610e321b6ec6a83252e9d8b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/4719
Tested-by: build bot (Jenkins)
2014-02-24 13:54:02 +01:00
Vladimir Serbinenko 10b3974811 intel/model_2065x: Fix APICID generation.
APIC IDs always step by 4 on 2065x independently of number of threads.

Change-Id: I5abd4005c8ce1740bb0862d952af66236b609aa8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-20 14:03:56 +01:00
Kyösti Mälkki e7f7d990df SMM: Fixes for DEBUG_SMI
Get the required UART includes directly.
The ne2k part is old copy-paste leftover.

Change-Id: Ifd9253abb5a50b515887459faf06b63f907eeda9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5258
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-20 12:56:56 +01:00
Patrick Georgi 938ef9fb8d x86 bootblock: improve clang compatibility
Its linker doesn't like "." arithmetics, so use .org,
while its assembler doesn't like data32 prefixes.

Change-Id: I3f5bbb350493d6510b8013df15d44c44c5db63c7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4714
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-02-19 20:56:19 +01:00
Aaron Durbin 6a360048a1 haswell: backup the default SMM region on resume
Haswell CPUs need to use the default SMM region for
relocating to the desired SMM location. Back up that
memory on resume instead of reserving the default
region. This makes the haswell support more forgiving
to software which expects PC-compatible memory layouts.

Change-Id: I9ae74f1f14fe07ba9a0027260d6e65faa6ea2aed
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5217
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16 20:42:41 +01:00
Aaron Durbin b4b9eb399e x86: provide infrastructure to backup default SMM region
Certain CPUs require the default SMM region to be backed up
on resume after a suspend. The reason is that in order to
relocate the SMM region the default SMM region has to be used.
As coreboot is unaware of how that memory is used it needs to
be backed up. Therefore provide a common method for doing this.

Change-Id: I65fe1317dc0b2203cb29118564fdba995770ffea
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5216
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-16 20:42:07 +01:00
Aaron Durbin 0f333071ef coreboot: infrastructure for different ramstage loaders
There are 2 methods currently available in coreboot to load
ramstage from romstage: cbfs and vboot. The vboot path had
to be explicitly enabled and code needed to be added to
each chipset to support both. Additionally, many of the paths
were duplicated between the two. An additional complication
is the presence of having a relocatable ramstage which creates
another path with duplication.

To rectify this situation provide a common API through the
use of a callback to load the ramstage. The rest of the
existing logic to handle all the various cases is put in
a common place.

Change-Id: I5268ce70686cc0d121161a775c3a86ea38a4d8ae
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5087
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-02-15 18:39:29 +01:00
Alexandru Gagniuc 6d51f5dfe9 cpu/allwinner/a10: Add minimal ramstage driver
Change-Id: I857755976b17b0e492c086162f395a77933eeed8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4698
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-02-13 17:03:58 +01:00
Kyösti Mälkki 2c78726897 PCI: Drop includes under cpu
The files affected do not make any PCI configuration calls.
If they did, the more correct includes would be pci_ops.h,
pci_defs.h and pci_ids.h.

Change-Id: I3e7f009371be6ea50318eaabf0c15500cb3f1210
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5200
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-12 21:57:11 +01:00
Kyösti Mälkki 5a5c886b8d SMP: Add arch-agnostic boot_cpu()
We should not have x86 specific includes in lib/.

Change-Id: I18fa9c8017d65c166ffd465038d71f35b30d6f3d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5156
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-11 21:55:30 +01:00
Aaron Durbin ca4f4b8c9e mtrr: only add prefetchable resources as WRCOMB for VGA devices
Be more conservative and only add VGA devices' prefetchable
resources as write-combining in the address space. Previously
all prefetchable memory was added as a write-combining memory
type. Some hardware incorrectly advertises its BAR as
prefetchable when it shouldn't be.

A new memranges_add_resources_filter() function is added
to provide additional filtering on device and resource.

Change-Id: I3fc55b90d8c5b694c5aa9e2f34db1b4ef845ce10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5169
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-09 22:08:53 +01:00
Kyösti Mälkki 732cee31a6 ARMv7: Remove static CBMEM allocation
The calculations for static allocation are no longer valid.

Change-Id: I6740cdcec789abddf78485a0edaf24882ef8c2a5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4569
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-02-06 11:22:14 +01:00
Kyösti Mälkki 9db1c4e51a usbdebug: Drop obsolete code
Change-Id: I918ca1d0d0d7bcb7e16d41a12830a0357f15b8ed
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5130
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-06 11:13:31 +01:00
Vladimir Serbinenko 30fe6120ca MTRR: Mark all prefetchable resources as WRCOMB.
Change-Id: I2ecfd9733b65b6160bc2232d22db7b16692a847f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5149
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-02-06 00:55:13 +01:00
Aaron Durbin 5b9e3b6051 mtrr: retry fitting w/o WRCOMB if usage exceeds BIOS allocation
If the MTRR usage exceeds the BIOS allocation for MTRR usage
re-try without the WRCOMB type.

Change-Id: Ie70ce84994428ff6700c36310264c3c44d9ed128
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5151
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
2014-02-06 00:09:09 +01:00
Oskar Enoksson d9b5d897d7 cpu/amd/model_fxx: Add coolnquiet for two new (old) AMD K8 models
The added CPU's are OSA248CEP5AU and a OSP280 processors.
The OSP280 VID/FID numbers have been found by experimentation
and extrapolation/guesses from similar models. It has been
verified to work fine under Linux (OpenSuse 12.2, kernel
3.4.63-2.44) with four different test-processors.
Windows is untested.

Change-Id: I3afa1cba5f55c8a78917b3636382af7706a80fee
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5095
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-02-03 22:24:17 +01:00
Vladimir Serbinenko 5ef4220693 cpu/intel/model_2065x: Add model 20652
Found in some X201t.
Tested on X201t.

Change-Id: I3fc4c3f5b1abf9fe61746ab8f401d1b6ee67f3ea
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5090
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-02-01 16:41:11 +01:00
Aaron Durbin ba6b07e888 cpu/intel: allow non-packaged scoped turbo setting
In the past the turbo disable setting (bit 38) of the
IA32_MISC_ENABLES msr has been package scoped. That means
knocking the turbo disable bit down enabled turbo for the
entire package. Sadly, that's no longer true on all Intel
processors. Therefore, allow non-packaged scoped turbo
setting by introducing the CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED
Kconfig option. It defaults to false which was the original
assumption.

BUG=chrome-os-partner:25014
BRANCH=baytrail
TEST=Built and ran both ways successfully.

Change-Id: I71a31e76ff47878023081fc47da643187517b597
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182405
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5047
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 06:10:26 +01:00
Aaron Durbin cd3f8ad235 x86: Add SMM helper functions to MP infrastructure
In order for the cpu code to start SMM relocation 2 new
functions are added to be shared:
- void smm_initiate_relocation_parallel()
- void smm_initiate_relocation()
The both initiate an SMI on the currently running cpu.
The 2 variants allow for parallel relocation or serialized
relocation.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted rambi using these functions.

Change-Id: I325777bac27e9a0efc3f54f7223c38310604c5a2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173982
Reviewed-on: http://review.coreboot.org/4891
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 06:05:38 +01:00
Aaron Durbin e0785c0331 x86: parallel MP initialization
Provide a common entry point for bringing up the APs
in parallel. This work is based off of the Haswell one
which can be moved over to this in the future. The APs
are brought up and have the BSP's MTRRs duplicated in
their own MTRRs. Additionally, Microcode is loaded before
enabling caching. However, the current microcode loading
support assumes Intel's mechanism.

The infrastructure provides a notion of a flight plan
for the BSP and APs. This allows for flexibility in the
order of operations for a given architecture/chip without
providing any specific policy. Therefore, the chipset
caller can provide the order that is required.

BUG=chrome-os-partner:22862
BRANCH=None
TEST=Built and booted on rambi with baytrail specific patches.

Change-Id: I0539047a1b24c13ef278695737cdba3b9344c820
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/173703
Reviewed-on: http://review.coreboot.org/4888
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2014-01-30 06:05:02 +01:00
Aaron Durbin 75e297428f coreboot: config to cache ramstage outside CBMEM
Haswell was the original chipset to store the cache
in another area besides CBMEM. However, it was specific
to the implementation. Instead, provide a generic way
to obtain the location of the ramstage cache. This option
is selected using the CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM
Kconfig option.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built and booted with baytrail support. Also built for
     falco successfully.

Change-Id: I70d0940f7a8f73640c92a75fd22588c2c234241b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172602
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4876
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 06:04:02 +01:00
Aaron Durbin d37705c3b0 vboot: provide empty vboot_verify_firmware()
In the case of CONFIG_VBOOT_VERIFY_FIRMWARE not being
selected allow for calling vboot_verify_firmware()
with an empty implementation. This allows for one not to
clutter the source with ifdefs.

BUG=chrome-os-partner:23249
BRANCH=None
TEST=Built with a !CONFIG_VBOOT_VERIFY_FIRMWARE and non-guarded
     call to vboot_verify_firmware().

Change-Id: I72af717ede3c5d1db2a1f8e586fefcca82b191d5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172711
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: http://review.coreboot.org/4879
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-30 04:13:00 +01:00
Aaron Durbin 029aaf627c x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
     assembly to ensure consistency (objdump -d -r -S | grep xmm).

Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 23:12:27 +01:00
Aaron Durbin e6767674af intel: fix microcode compilation failure in bootblock
When not building with CONFIG_SSE there are not enough
registers for ROMCC to use for spilling. The previous
changes to this file had too many local variables that
needed to be tracked -- thus causing romcc compilation
issues.

Change-Id: I3dd4b48be707f41ce273285e98ebd397c32a6a25
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4845
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 19:54:29 +01:00
Paul Menzel 4fe9813adb src/cpu: Fix spelling of MTTR to MTRR
Change-Id: Ia4718ac31a5b2bd12f8cda5e107aa878d74d2a03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4805
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-26 15:59:46 +01:00
Vladimir Serbinenko 9c70adf26d intel/microcode: Remove leftover MICROCODE_INCLUDE_PATH.
Not used anymore since microcode was moved.

Change-Id: Id666c80cb20e90e3664c4dcfcc0c41a4aeb4864c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4788
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-23 20:51:49 +01:00
Kyösti Mälkki fa8cedae2a AMD K8/fam10: Fix CBMEM on S3 resume
Change to use cbmem_recovery() to wipe CBMEM region and reset
ACPI wakeup if CBMEM TOC was not found.

Change-Id: Ic362253eaa00bd442d4cc0514632f9096e20bfa6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4673
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 20:55:55 +01:00
Kyösti Mälkki 47770c0769 AMD AGESA: Fix CBMEM on S3 resume
Change to use cbmem_recovery() to wipe CBMEM region and reset
ACPI wakeup if CBMEM TOC was not found.

Change-Id: I6648570d76b5c137f50addcc5bce9c126d179c65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4672
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-22 20:55:20 +01:00
Alexandru Gagniuc 07d881a02d cpu/intel: Remove dummy terminators from microcode blobs
Now that CBFS microcode no longer requires a NULL termination, remove the
dummy terminators from all microcode blobs. This also enables microcode
blobs from different CPU models to be linked in the same
cpu_microcode_blob.bin without the terminators getting in the way.

Change-Id: I25a6454780fd5d56ae7660b0733ac4f8c4d90096
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4506
Tested-by: build bot (Jenkins)
2014-01-16 05:35:28 +01:00
Alexandru Gagniuc 2c38f50b4a cpu/intel: Make all Intel CPUs load microcode from CBFS
The sequence to inject microcode updates is virtually the same for all
Intel CPUs. The same function is used to inject the update in both CBFS
and hardcoded cases, and in both of these cases, the microcode resides in
the ROM. This should be a safe change across the board.

The function which loaded compiled-in microcode is also removed here in
order to prevent it from being used in the future.

The dummy terminators from microcode need to be removed if this change is
to work when generating microcode from several microcode_blob.c files, as
is the case for older socketed CPUs. Removal of dummy terminators is done
in a subsequent patch.

Change-Id: I2cc8220cc4cd4a87aa7fc750e6c60ccdfa9986e9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4495
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
2014-01-16 05:34:25 +01:00
Paul Menzel be8d23a3b5 cpu/amd/model_fxx/powernow_acpi.c: Comment out set but unused variable `Start_vid`
When adding support for PSS object generation for AMD pre Family Fh CPUs
(199c694f) the function `pstates_algorithm` was copied and adapted, but
`Start_vid` is not needed anymore as a static table is used. I’d remove
the variable, but Ron Minnich requested to leave it there for
documentation purposes. So just comment it out.

Change-Id: I3002951d168cade6461941c16d78373c47792e13
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4036
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-01-15 22:20:20 +01:00
Kyösti Mälkki bbf013c38f nehalem/sandy/ivy/haswell: Enable WRPROT cache for all of flash
CBFS could start from below 4MB, and should be cacheable for the
purpose of early microcode update and CBFS search for romstage file.

Change-Id: Ia2a1c6e5fdcc3201fafc8cf5c841cebbbf0b30c9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4626
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15 15:27:33 +01:00
Kyösti Mälkki 107f72e674 Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be
set with values that are not power of 2. The region programmed
as WB cacheable will include all of ROM_SIZE.

Side-effects to consider:

Memory region below flash may be tagged WRPROT cacheable. As an
example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB.
Since this can overlap CAR, we add an explicit test and fail
on compile should this happen. To work around this problem, one
needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and
define a smaller region for WB cache.

With this change flash regions outside CBFS are also tagged WRPROT
cacheable. This covers IFD and ME and sections ChromeOS may use.

Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4625
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-15 15:26:48 +01:00
Alexandru Gagniuc 1b4cbafe1d cpu/allwinner/a10: Clarify positioning of boot stages
This fixes a number of potential issues, such as generating a build
failure if the bootblock is too large, and making sure romstage and
ramstage cannot overlap in memory.

Change-Id: I4ca9ad097b145445316bcd962e007731b08a7fda
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4687
Tested-by: build bot (Jenkins)
2014-01-14 14:15:25 +01:00
Alexandru Gagniuc 601b5b5302 cpu/allwinner/a10: Add helper to configure CPU clock
Change-Id: I5a3bb3220aeefdd6822a7dbecf210ff77095dad6
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4685
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-14 14:14:58 +01:00
Alexandru Gagniuc 910ce01757 cpu/allwinner/a10: Provide utility to make a bootable image
Up until now, we relied on mksunxiboot to prepend the header which
makes coreboot.rom bootable on Allwinner SoCs. If that tool was not
present, the build silently failed.

Integrate this tool into our util/ package, so that we do not have to
rely on mksunxiboot being in PATH.
Our version of mksunxiboot also eliminates some limitations of the
original tool, so we no longer have to use 'dd' to limit the file
size.

Change-Id: Id5a4b1e2a3cb00cd1d6c70e6cbc3cfd8587e8a24
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4656
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:00 +01:00
Alexandru Gagniuc d7b07af621 cpu/allwinner/a10: Clean up include order in Makefile.inc
Alphabetize the sources for each stage (bootblock, rom, ram), and
include twi.c in both romstage and ramstage.

Change-Id: I5526f5a66f6600560005731a3ee536eb858f4ff0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4639
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:02:48 +01:00
Vladimir Serbinenko 1287416822 CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_file
Number one reason to use cbfs_get_file was to get file length.
With previous patch no more need for this.

Change-Id: I330dda914d800c991757c5967b11963276ba9e00
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4674
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:58 +01:00
Patrick Georgi 5d1ada0f64 intel/fsp: Fix microcode including
IS_ENABLED() requires the full define (incl. CONFIG_ prefix)
but isn't needed here.

Change-Id: I91d504367c75ce3fcecc6fa2499afaa0896595d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/4646
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-11 09:46:47 +01:00
Alexandru Gagniuc ffd4a610ba cpu/allwinner/a10: Import raminit code from uboot
The memory initialization code is a work in progress for uboot, so we
only import the bits needed to get RAM up and running. Any refactoring
is cosmetic, and any functional refactoring should be done in separate
patches, and preferably, in coordination with the sunxi team.
Since it's not yet determined if we should initialize memory during
the bootblock or romstage, we don't add raminit to the build just yet.

Change-Id: I2ec1821942c6970150a02fa3806a257da649e1c9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4597
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 06:37:25 +01:00
Alexandru Gagniuc cce6c1c92a cpu/allwinner/a10: Add low-level helpers for DRAM clock control
PLL5 is special in that it controls the DRAM clock, and requires a
fine-grained low-level control which will be needed by raminit code.
This change also brings functionality which will be needed by
raminit.

Change-Id: I25ecc91aa2154e504ceebb9003a5e5728d47f4a3
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4593
Tested-by: build bot (Jenkins)
2014-01-09 06:37:13 +01:00
Alexandru Gagniuc 5d8b0a9fb3 cubieboard: Initialize memory in bootblock
Even though the Allwinner A10 is limited to a 24KiB bootblock, the
memory initialization takes only about 3KiB and leaves enough room for
an MMC or NAND driver, so init the memory early on. The advantage is
that we can eliminate complicated logistics of where to cache CBFS and
where to load the ramstage in SRAM.

Change-Id: Id549552ed509434e831db60deaef28e04d62417f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4630
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:12:56 +01:00
Alexandru Gagniuc 919e499a36 cpu/allwinner/a10: Add functions for driving GPIO pins
Change-Id: I9473a6e574c3af02d154a7e30245f0dc0b238300
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4599
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:05:29 +01:00
Alexandru Gagniuc 6ed574a661 cpu/allwinner/a10: Add definitions for in/output GPIO functions
Change-Id: I2b857d3b4c01e39c62e54f753e400e6049f1dbc9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4598
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:04:07 +01:00
Alexandru Gagniuc a94bed0116 cpu/allwinner/a10: Add function for reading chip revision
Change-Id: Iafbd253235db3914b9382fdb41de2622ef83c6d8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4596
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:03:01 +01:00
Alexandru Gagniuc bd09dbe330 cpu/allwinner/a10: Implement udelay using timer 0
Change-Id: I4825f0d57696cd28751c59ae133b7e3315fb78e5
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4595
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:02:47 +01:00
Alexandru Gagniuc b70a140bd0 cpu/allwinner/a10: Add definition for gating GPIO S clock
This bit is not documented in the datasheet, but is used in the
upcoming RAM init code.

Change-Id: I697ec222496236ac7690460ee62313ab8b1a2f0b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09 01:02:05 +01:00
Alexandru Gagniuc 5c4bde70ae cpu/allwinner/a10: Add basic TWI (I²C) driver
Change-Id: I11b10301199e5ff1a45d9b7d2958cc7b6667a29c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4588
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:46 +01:00
Alexandru Gagniuc bc30b2b225 cpu/allwinner/a10: Refactor API for gating clocks to peripherals
Rather than having to track which bit in which register should be
cleared or set to gate or ungate the clock to a certain peripheral,
provide a simplified enum which encodes the register and bit. This
change comes with a function which decodes the enum and gates/ungates
the clock.

This also removes the register-dependent bitmasks for APB0 and APB1
gating registers.

Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4571
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:34 +01:00
Alexandru Gagniuc 8226dbbf1d cpu/allwinner/a10: Refactor and document pinmux API
Include a function to multiplex more than one pin at a time. This
is useful for peripherals that have the same function number for
all their pins.
Since we now have two functions for muxing pins, also document
them.

Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4565
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:03:19 +01:00
Alexandru Gagniuc be32f51aa1 cpu/allwinner/a10: Clarify the usage of SRAM during bootblock
We have 32KiB of usable SRAM right when we boot. The first 24KiB can
be loaded with our bootblock, while the other 8KiB can be used as
stack during the bootblock stage.

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I48d3a37869031c3c1dbc1fab71204d473d64deeb
Reviewed-on: http://review.coreboot.org/4563
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 23:02:49 +01:00
Alexandru Gagniuc f64111b486 cpu: Add initial support for Allwinner A10 SoC
Add minimal support needed to get a bootblock capable of initialising
a serial console.

Change-Id: I50dd85544549baf9c5ea0aa3b4296972136c02a4
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4549
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08 22:54:08 +01:00
Kyösti Mälkki 7d3045b517 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30 07:17:16 +01:00
Kyösti Mälkki 239c3d32f0 AMD fam10: Drop RAMINIT_SYSINFO
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this
is not a true option but copy-paste remainder from AMD K8.

Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:41 +01:00
Kyösti Mälkki 2e77461051 AMD K8: Socket implies K8_REV_F_SUPPORT
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1).

Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-29 00:04:02 +01:00
Kyösti Mälkki 142b52cd32 AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includes
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4524
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26 23:22:17 +01:00
Kyösti Mälkki 88a67f0cc9 AMD boards (non-AGESA): Cleanup earlymtrr.c includes
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4523
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26 23:19:11 +01:00
Alexandru Gagniuc c6c8cb7f79 Fix linking microcode with more than one microcode file
When assembling microcode , the rule to link individual object files into
one larger file only passed the first dependency to the linker. As a results
only microcode from one object file would actually get linked. This is fixed
 by replacing $^ with $+ inside the make rule.

Change-Id: I65c0565f2e03777af23e530c08d1241804ca19b1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4500
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-22 19:26:31 +01:00
David Hendricks c81187f231 pit: disable LCD FETs before doing any graphics init
This ensures that the LCD FETs are off before we do graphics init.

FIXME: The location of the code is sub-optimal and should probably be
done in romstage, but there are __PRE_RAM__ considerations to take
into account.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I0844030d0a0e51eee1d29f1762f0b495777268df
Reviewed-on: https://gerrit.chromium.org/gerrit/64305
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4470
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:47:01 +01:00
David Hendricks 1ad77de62d exynos5420: Assign corect parent PLLs
Assign correct parent PLL's for the following clocks:
ACLK_400_WCORE (MPLL->CPLL) (400 -> 333MHz)
PCLK_200_FSYS (MPLL->DPLL) (200 -> 200MHz)
MUX_ACLK_100_NOC_SEL (MPLL -> DPLL) (100 -> 100MHz)
ACLK_266 (DPLL->MPLL) (300 -> 266MHz)
ACLK_200_DISP1(MPLL->DPLL) (200 -> 200MHz)
ACLK_400_MSCL(MPLL->CPLL) (400 -> 333MHz)
ACLK_66 (MPLL->CPLL) (66.666 -> 66.6MHz)
MUX_ACLK_400_DISP1_SEL (CPLL->DPLL) (666 -> 300MHz)
MUX_MPHY_REFCLK (MPLL->OSC)
MUX_UNIPRO (MPLL->OSC)
MUX_MIPI1 (EPLL->OSC)
MUX_DP1_EXT_VID (EPLL->OSC)
MUX_FIMD1_OPT (EPLL->OSC)
MUX_IPLL(IPLL->OSC)
This also corrects the clock dividers for few of the clocks,
as the clock parent changes affect the final frequency of the
clocks.

This is ported from: https://gerrit.chromium.org/gerrit/#/c/62437/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ie833c01913d0961a6190446bd573511de8dee5f8
Reviewed-on: https://gerrit.chromium.org/gerrit/65620
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4469
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:56 +01:00
David Hendricks 7f35bbb0d4 exynos5420: don't assume MPLL for i2c parent clock
This reads the clock select field for MUX_ACLK_66_SEL in the
CLK_SRC_TOP1 register in order to obtain the source clock rate
for I2C peripherals. Before we were always assuming that the source
was the MPLL.

Unfortunately not all fields in the CLK_SRC_TOPn registers are
enumerated the same with regard to clock select. So this is just
a one-off for now.

This is basically ported from https://gerrit.chromium.org/gerrit/#/c/62443.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I9fa85194ae1a1fadab79695f059efdc2e2f1f75f
Reviewed-on: https://gerrit.chromium.org/gerrit/65611
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4468
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:52 +01:00
David Hendricks b783d4585f exynos5420: Set SPLL to 400MHz
Increase SPLL to 400MHz from 300MHz as we set SPLL as the
switching parent for ARM and KFC. This value is as per
recommendation of the hardware team.

This is ported from https://gerrit.chromium.org/gerrit/62618

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I8a5a5b957083b0b1f3e3e318fe5753cf7ae19223
Reviewed-on: https://gerrit.chromium.org/gerrit/65432
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4464
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:43 +01:00
David Hendricks 401da25827 exynos5420: re-factor clock_get_periph_rate()
This re-factors clock_get_periph_rate() to be a simpler and also
make a few corrections along the way. To summarize:

- clk_bit_info is no longer used. It had numerous errors and was
  really painful anyway since it was just a bunch of opaque magic
  numbers that made bugs non-obvious.

- Clock source bitfields for peripherals handled in the switch
  statement are 3 bits, not 4. Some divider values are 3 bits,
  some are 4. The earlier code always assumed 4 bits for both
  which included reserved bits in many cases.

- UART source clock and divider shift values were wrong.

- PWM clock divider was being read from the wrong register.

- SPI3 divider value was being read from the wrong register.

- There was a really confusing calculation for SDMMC0 and SDMMC2
  clock rates, but it was never actually used since the switch
  statement never handled PERIPH_ID_SDMMC{0,2} and would thus
  return if they were ever passed into this function.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I0a03a64d8b42fbe83dbf377292597ce681b22f4b
Reviewed-on: https://gerrit.chromium.org/gerrit/65284
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4463
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:38 +01:00
David Hendricks efd4b9e936 exynos5420: add a peripheral clock select --> PLL decoder
This adds a helper function to translate between peripheral clock
select fields in clock source registers and PLLs. Some of this was
already done to handle a few special cases, this generalizes the
earlier work so that follow-up patches can do further clean-up.

Unfortunately, the PLLs represented by clock select fields in
various modules are not uniformly ordered. So for now we focus on
peripheral clock sources only.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Id58a3e488650d09e6a35c22d5394fcbf0ee9ddff
Reviewed-on: https://gerrit.chromium.org/gerrit/65283
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4462
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:33 +01:00
David Hendricks 5f6ffbab1b exynos5420: add CPLL and DPLL to the known list of PLLs
This patch adds CPLL and DPLL to the known list of PLLs.

This is ported from https://gerrit.chromium.org/gerrit/#/c/62617/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I2f2614e44cd9c98d98b8db9347f29de21703d1af
Reviewed-on: https://gerrit.chromium.org/gerrit/65282
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4461
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:28 +01:00
David Hendricks bd56bf0dcf exynos5420: correct the PMS value for CPLL
This patch matches the User Manual Table 7-2 about the PMS value for
CPLL. This doesn't change the PLL frequency (before and after both make
666MHz) but this is the suggested PMSK values for obtaining 666.
(Suggested as per user manual).

This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia33e1971ab88da761000d443792560476514626b
Reviewed-on: https://gerrit.chromium.org/gerrit/65281
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:24 +01:00
Gabe Black 136e709015 exynos5420: Configure the UART pins unconditionally
Configure the pins for the UART unconditionally in the mainboard code (when we
know which UART to configure) instead of in the UART driver. This also means
the UART will work if later software wants to use it without setting up the
pins.

Built and booted on pit with the serial turned off and some serial init
in the kernel decompression stub fixed.

Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/65299
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4457
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:20 +01:00
Julius Werner ce011ec131 exynos5250: Implement support to boot with USB A-A firmware upload
This patch implements the basic infrastructure required to use the USB
A-A firmware upload feature on Exynos5 processors with Coreboot. It will
require a corresponding host-side script that activates the feature and
uploads the correct image parts in the correct order to harcoded target
addresses, as described in the comments of alternate_cbfs.c.

Also fixes a bug in the Google Snow mainboard where it would not
correctly initialize the pinmux configuration for the SPI flash bus.
During a normal SPI boot the IROM would already do that for you, but
when booting from USB you have to do it yourself.

Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/64875
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4456
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:15 +01:00
David Hendricks e0cfad2b56 exynos5420: re-factor the SDMMC GPIO config routines
The existing GPIO config routines for SDMMC0-2 are over-generalized
and somewhat confusing as a result. It would work nicely if all SDMMC
ports were configured in the same fashion, but there are a few
exceptions.

For example, the inner function runs differently if we're using 8 bits
of data instead of 4, so a big chunk is skipped for SDMMC2. SDMMC0
requires SD_0_CDn to be an output rather than alternate function and
must have a value set.

This patch trades some verbosity for simplicy. Now the SDMMC GPIO
configuration a straight-forward sequence of GPIO operations
without any exceptions.

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: If75075b24c6588c4c1b3be3fb9b1aa95e2fac2d1
Reviewed-on: https://gerrit.chromium.org/gerrit/65248
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4446
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:05 +01:00
David Hendricks b9f267ce23 exynos5420: configure SD_0_CDn as VDDEN for eMMC
On Exynos5420 the MMC channel 0 is connected to eMMC
Which does not have a card detection pin. Also this pin
is connected as VDDEN to PMIC.

This is ported from https://gerrit.chromium.org/gerrit/#/c/60732/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I19048d22b7dd00df1716b6b5b332a7eb70fe0836
Reviewed-on: https://gerrit.chromium.org/gerrit/65247
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4445
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:46:01 +01:00
David Hendricks 792b621ac0 exynos5420: init APLL at 1800MHz
This initializes the APLL at 1800MHz.

Change-Id: I366bf4e75510847ab93d9c9f214a49c731cca08a
Reviewed-on: https://gerrit.chromium.org/gerrit/64745
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:52 +01:00
David Hendricks f05e871300 exynos5xxx: use oscillator clock when changing ARM frequency
Switch ARM clock source when changing the APLL frequency to avoid
stability issues.

This is ported from https://gerrit.chromium.org/gerrit/#/c/64189/5

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I923107555e6d3287b3694cbf9e4bb548d3e5f4a8
Reviewed-on: https://gerrit.chromium.org/gerrit/64838
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4442
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:48 +01:00
David Hendricks 49c1be95d3 exynos5420: set L2ACTLR parameters for A15 cores
This patch does the following for the A15 cores:
- Disable clean/evict push to external
- Enable hazard detect timout
- Prevent gating the L2 logic clock

This is ported from https://gerrit.chromium.org/gerrit/#/c/60154

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: I7ac9f40acecfa7daee6fb81772676bf5119d0536
Reviewed-on: https://gerrit.chromium.org/gerrit/64862
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4441
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:41 +01:00
Gabe Black 4e195afdf7 exynos5250: Add a pinmux function to set up i2s bus 0
This bus is hooked up on snow and, as it's the only bus hooked up on some
other boards, having it available in firmware to test is handy.

Change-Id: Icb48b9af4a67d382bd6fbce1e4c6a320d811d365
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64877
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4438
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:32 +01:00
David Hendricks 56a7cff7f6 exynos5420: minor correction to CPU frequency print
This divides the CPU frequency by 1,000,000 instead of 2^20.

serial console shows "CPU:   S5P5420 @ 800MHz" instead of
claiming 762MHz.

Change-Id: I70cc5b62f689c5553b57c82be61233fb9f733f6e
Reviewed-on: https://gerrit.chromium.org/gerrit/64743
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4434
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:15 +01:00
Hung-Te Lin c0491d4fb5 armv7/exynos: Fix and remove memory reset workarounds
The memory corruption problem in Exynos suspend/resume process is caused by two
things together: PHY_RESET and MRS command.

After stop sending MRS on resume, we can now remove the workaround of skipping
PHY_RESET.

Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c
Reviewed-on: https://gerrit.chromium.org/gerrit/64736
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4433
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:11 +01:00
Ronald G. Minnich c0d5eb2a33 Pit: graphics
This includes the new dp code, which is better, and the fimd code,
which is changed and improved. We took the chance to remove un-needed
files, and also to remove some foolish u-boot habits, but not all of
them. That will take time.

With these changes we get graphics.

Since the only mainboards we have with 16 bit graphics are 5:6:5,
adjust edid.c to just use that format. If at some future time we need
4:4:4, which seems unlikely, we'll need to add a function to adjust
the lb_framebuffer. Note that you can't just divine this from the EDID,
as the graphics pipe format need not match the actual final format used.

The EDID reading works. We've been requested to support hard-coded
EDIDs and that will come in the next revision. Currently the hard-coded
EDID is ignored for testing.

Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64240
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 22:45:06 +01:00
Ronald G. Minnich 01b438367c Snow: correctly disable trust zone hardware
The kernel assumes that trust zone is disabled.

Change-Id: Ia8d6fa69adcb812a747d8b89eb77e57144423eaa
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64722
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4431
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:45 +01:00
Ronald G. Minnich b0efbd3910 Pit: correctly initialize trust zone
This ensures that various trust zone things are reset,
which is important because the kernel assumes they are.

Change-Id: Ie02ea89885621f58a3ccc4f1729617208a264153
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64697
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4430
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:41 +01:00
David Hendricks d598cac656 exynos5420: update set_cpu_id()
The current function seems to be outdated...

Signed-off-by: David Hendricks <dhendrix@chromium.org>

built and booted. Now we see "CPU:   S5P5420 @ 762MHz"
instead of "CPU:   S5PC420 @ 762MHz"

Change-Id: Ieb103a5fa62bda9a6b2cbd9a82fb4f72c5dd6466
Reviewed-on: https://gerrit.chromium.org/gerrit/64302
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4425
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:31 +01:00
Gabe Black 88fdd930ac exynos5250: Add mct_start to the timer init blob in timer_monotonic_get
A previous change removed init_timer from timer_monotonic_get because its old
implementation set up the PWM based timer which was going away. It would still
be a good idea to initialize the timer at that point, just not the pwm.

Change-Id: I4816710ec2c9d5ca53b704c6b9397bcfac183fdc
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64160
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4419
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 21:02:17 +01:00
Stefan Reinauer 80e6293a89 Exynos 5420: Enable dynamic CBMEM
...  In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.

Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63657
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4391
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 18:30:54 +01:00
Stefan Reinauer 662874446a Exynos 5250: Enable dynamic CBMEM
...  In order to do this, the graphics memory has to move into
the resource allocator and out of CBMEM.

Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/59326
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4390
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 18:30:47 +01:00
Gabe Black e13680bdd0 exynos5420: Fix some clock settings
Some registers and bit fields were wrong, but the difference is mostly
academic since the code that uses them are never called.

Change-Id: I0ce5e1529cdda1a4973765af8c31b79130b1111c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63189
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4385
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:04 +01:00
Gabe Black ad88fda1cf exynos5420: Fix the clock divisor mask
The divisor mask had been set to 0xff, but the bitfield is 4 bits wide.

Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63188
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4384
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:49:00 +01:00
Gabe Black 713853a9c8 exynos5420: Get rid of the PWM code like on the 5250
The timer code was supposed to be using the mct, and also using the monotonic
timer infrastructure instead of the get_timer function. This change had been
made for the 5250 but not yet for the 5420.

Change-Id: I03a4fbb434f2346761f28fb6bd2218b526f2a4a2
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64159
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4418
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:53 +01:00
Gabe Black 9b764a0dcc exynos5250: Get rid of the PWM timer code we shouldn't be using anymore
This code was left over from U-Boot and was superceded by the MCT.

Change-Id: Ia85e3b7281dcdd4740238dddd0dfc6f0ba2c94da
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63778
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4401
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:49 +01:00
Gabe Black 2c116febab exynos5420: Apply pwm const fix to the 5420 as well
When the const was removed from write function arguments, a related bug in the
5250 code was fixed so that it would still compile. Unfortunately, that same
change needed to be made to the 5420.

Change-Id: If15057c92422de91dc8e35dbd8b5c978bfae122a
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/64154
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4417
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 10:48:46 +01:00
Gabe Black 9a9d7e8ad0 exynos5250: Fix consts in the pwm code
The code generally intended to make the pointer const instead of the thing it
pointed at, but it had const backwards. Sometimes both the pointer and the
data could be const, but sometimes there were writes where only the pointer
should be.

Change-Id: Ifcd5495769b86b47d7b583cce63ed5c2158bec4e
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/63775
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/4397
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-12-21 10:48:40 +01:00
Duncan Laurie 68a8431fcf haswell: Update microcode revision
CPUID 306C3 Haswell MOB C-0 microcode to 12h
CPUID 40651 Haswell ULT C-0 microcode to 15h

localhost ~ # grep microcode /proc/cpuinfo
microcode       : 0x15
microcode       : 0x15

Change-Id: Ibdfe2b8ef0969b1ccc6dd1642a9fc352b5d11f27
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21 07:39:04 +01:00
Hung-Te Lin f584218544 armv7: Remove SYS_TEXT_BASE config.
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory
layout, remove it from current configurations.

Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b
Reviewed-on: https://gerrit.chromium.org/gerrit/61853
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4371
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-20 21:56:20 +01:00
Alexandru Gagniuc b1ae0303ce cpu/intel: Do not rely on CBFS microcode having a terminator
Up until now, a dummy terminator was required for CBFS microcode files.
This was a coreboot only requirement in order to terminate the loop which
searches for updates.

Figure out where the microcode file ends, and exit the loop if we pass the
end of the CBFS without finding any updates.

Change-Id: Ib61247e83ae6b67b27fcd61bd40241d4cd7bd246
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4505
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-17 22:59:19 +01:00
Kyösti Mälkki 75b68d8f5b cpu/amd: Remove error messages on non-matching microcode patches
Microcode update file contains patches for various processor
revisions, it is not an error to have those.

Change-Id: Ifbca26276b66f17092afe249a2cfc229713a9fec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4520
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-13 09:07:46 +01:00
Alexandru Gagniuc 66e0c4c8c4 cpu: Rename CPU_MICROCODE_IN_CBFS to SUPPORT_CPU_UCODE_IN_CBFS
CPU_MICROCODE_IN_CBFS was designed to mean that loading microcode updates
from a CBFS file is supported, however, the name implies that microcode is
present in CBFS. This has recently caused confusion both with contributions
from Google, as well as SAGE. Rename this option to
SUPPORT_CPU_UCODE_IN_CBFS in order to make it clearer that what is meant is
"hey, the code we have for this CPU supports loading microcode updates from
CBFS", and prevent further confusion.

Change-Id: I394555f690b5ab4cac6fbd3ddbcb740ab1138339
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4482
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-12-13 01:28:36 +01:00
Ronald G. Minnich 6da7046f73 EXYNOS5250: be less chatty at critical moments
The 5250 DRAM code is *really* chatty. That's not a great
idea in time critical code, and DRAM init is generally
very sensitive about such things.

Finally, for those things that are errors, print them
at an error level, not a debug level.

Change-Id: Ifa86b019dfd5f8ae6c8a1da2a35b5d0808dc3623
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: https://gerrit.chromium.org/gerrit/60100
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Ronald G. Minnich <rminnich@chromium.org>
Tested-by: Ronald G. Minnich <rminnich@chromium.org>
Reviewed-on: http://review.coreboot.org/4359
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:07:00 +01:00
Hung-Te Lin c5aac958ae exynos5250: Correct DDR3 Phy-reset value names.
The name "LPDDR3PHY_CTRL_PHY_RESET_OFF" is not appropriate because the real
phy-reset is a low-active pin, so "off(0)" will trigger "start to reset".

To prevent confusion, we should rename the constants to "RESET_ENABLE" and
"RESET_DISABLE".

Change-Id: Iccba5ef3a2e992f877dea90741f0308c161758c9
Reviewed-on: https://gerrit.chromium.org/gerrit/61081
Tested-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/4357
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:06:08 +01:00
Duncan Laurie 118d105a37 haswell: Export functions for CPU family+model and stepping
These are needed to enable workarounds/features on specific
CPU types and stepping.  The older northbridge function and
defines from sandybridge/ivybridge are removed.

Change-Id: I80370f53590a5caa914ec8cf0095c3177a8b5c89
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61333
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4355
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:57 +01:00
Hung-Te Lin f6d6e62aaf exynos5420: Setup clocks for MMC bus controller.
To configure source clocks on Exynos 5420 for MMC drivers.
Some registers are different from the 5250. FSYS now has two parts
and MMC uses FSYS2. The MMC block uses MPLL as the clock source.
The "high-speed" MMC interface runs as 52MHz, so divider is set
accordingly.

Also, the MMC driver has changed from MSHCI (Mobile Storage Host Controller
Interface) to DWMCI (DesignWare MMC Controller Interface).

Change-Id: I9ba9cf43e2f2dcd9da747888c0c7676bd545177b
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60858
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4354
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:05:52 +01:00
Duncan Laurie 768903eac9 haswell: Update ULT microcode to rev 14h
localhost ~ # grep ^microcode /proc/cpuinfo
microcode       : 0x14
microcode       : 0x14

Change-Id: I839f29cff61abf798a619b30ad945e25c79f548f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60658
Reviewed-on: http://review.coreboot.org/4348
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-12 22:03:35 +01:00
Kyösti Mälkki f0a13ceb63 AMD boards: Fix includes for microcode updates
No ROMCC involved, no need to include .c files in romstage.c.

Change-Id: I8a2aaf84276f2931d0a0557ba29e359fa06e2fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4501
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-09 23:28:43 +01:00
Aaron Durbin 16cbf8983c haswell: VR controller configuration
Configure the VR controller. This enables the PSIx levels
as well as C-state ramping. PSIx thresholds are:
 - PSI3: 1A.
 - PSI2: 5A.
 - PSI1: 15A.

Before:
0x601 0x0000000000000100
0x603 0x0036000000262626
0x636 0x000000000000006f
After:
0x601 0x4010140f00000100
0x603 0x0036000000262626
0x636 0x000000000000006f

Change-Id: I6958845ac4164ebd0f1bb2d6d9be55ba63ed9344
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60931
Reviewed-by: Sameer Nanda <snanda@chromium.org>
Reviewed-on: http://review.coreboot.org/4338
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:51:52 +01:00
Duncan Laurie c70353f1eb haswell: Misc power management setup and fixes
1) fix enable of power aware interrupt routing
2) set BIOS_RESET_CPL to 3 instead of 1
3) mirror PKG power limit values from MSR to MMIO on all SKUs
4) mirror DDR power limit values from MMIO to MSR
5) remove DMI settings that were from snb/ivb as they do
not apply to haswell

1) verify power aware interrupt routing is working by looking
in /proc/interrupts to see interrupts routed to both cores
instead of always to core0

BEFORE: 58:       4943          0   PCI-MSI-edge      ahci
AFTER:  58:       4766        334   PCI-MSI-edge      ahci

2) read back BIOS_RESET_CPL to verify it is == 3

localhost ~ # iotools mmio_read32 0xfed15da8
0x00000003

3) read PKG power limit from MMIO and verify it is the same
as the MSR value

localhost ~ # rdmsr 0 0x610
0x0000809600dc8078
localhost ~ # iotools mmio_read32 0xfed159a0
0x00dc8078
localhost ~ # iotools mmio_read32 0xfed159a4
0x00008096

4) read DDR power limit from MSR and verify it is the same
as the MMIO value (note this is zero based on current MRC input)

localhost ~ # rdmsr 0 0x618
0x0000000000000000
localhost ~ # iotools mmio_read32 0xfed158e0
0x00000000
localhost ~ # iotools mmio_read32 0xfed158e4
0x00000000

Change-Id: I6cc4c5b2a81304e9deaad8cffcaf604ebad60b29
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/60544
Reviewed-on: http://review.coreboot.org/4333
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-07 03:31:06 +01:00
Idwer Vollering 8c0cb8ae3b Correct file permissions.
Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:39:09 +01:00
Alexandru Gagniuc a406119e9b arch/x86: Do not run UPDATE-FIT if we don't include microcode
The original intention was to only run UPDATE_FIT when a microcode file was
included in CBFS. This happens when either CPU_MICROCODE_CBFS_GENERATE or
CPU_MICROCODE_CBFS_EXTERNAL is selected, however, the makefile checked that
CPU_MICROCODE_IN_CBFS was selected instead. The end result was that on
hasswell, the UPDATE-FIT step was always run, even when no microcode was
included, generating a build error.

Instead, introduce a new variable which tells if a microcode update is
added in CBFS during the build.

Change-Id: I28638912ed6f77761ef8a584f7636dc907b7a9b7
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4480
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-12-06 23:39:50 +01:00
Alexandru Gagniuc f589909b91 cpu: Remove BOARD_MICROCODE_CBFS_GENERATE Kconfig option
Commit * bdafcfa Add the Intel FSP 206ax CPU core support
Introduced this option. This option was meant to have a board generate
a CBFS file containing microcode. However, microcode generation used to be
enabled by default when CPU_MICROCODE_IN_CBFS was selected.

The introduction of BOARD_MICROCODE_CBFS_GENERATE killed that automatic
default, which is not what we want. This option is misguided in the sense
that it tends to introduce a non-default which had been intentionally a
default. We now have to select two Kconfig options in order to generate
microcode in CBFS, meaning one option is redundant.

Change-Id: I3034833df1a9afa7d6d9d537484cb4ac89d30183
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4478
Tested-by: build bot (Jenkins)
2013-12-05 03:33:40 +01:00
Stefan Reinauer 9531692ee1 qemu-armv7 CPU: Move Kconfig code into CPU directory
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: Icae8042add5f4dd5c707369ffc4587c613d69d29
Reviewed-on: https://gerrit.chromium.org/gerrit/59324
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4315
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-05 00:38:06 +01:00
Marc Jones 0da082b625 Update SMM for FSP systems
Add the FSP northbridge and southbridge includes.

Change-Id: I5c7f395dc033caa8d0bf0313382769595d77f2a5
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4019
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-04 19:35:34 +01:00
Marc Jones bdafcfa555 Add the Intel FSP 206ax CPU core support
Add support for 206ax using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. It has different CAR code, micorcode, and FSP inclusion.
It may be possible to combine this code with the mrc based
solution used by the chromebooks in the future.

Change-Id: I5105631af34e9c3a804ace908c4205f073abb9b4
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4016
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-04 18:45:42 +01:00
Alexandru Gagniuc 72dccce0c9 global: Fix usage of get_option() to make use of CB_CMOS_ codes
Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.

Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 22:11:20 +01:00
Vladimir Serbinenko a6c29fe684 amd/car/post_cache_as_ram: Switch stack in assembly rather than in C
Compiler may do loads of optimisations around stack switch and so it's allowed
to break stack switch as it sees fit. Do it in assembly instead.

Not tested.

Change-Id: I277a62a9052e8fe9b04e7c65d149e087282ac2a2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4286
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 20:10:38 +01:00
Aaron Durbin c7633f4f5e slippy/falco/peppy: Fix SPD GPIO initialization.
SPD GPIOs were being read prior to initialization in romstage_common. To
fix, pass the copy_spd function to romstage_common, to be called at the
appropriate time (after PCH init, before DRAM init).

Change-Id: I2554813e56a58c8c81456f1a53cc8ce9c2030a73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/58608
Reviewed-on: http://review.coreboot.org/4237
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-12-01 23:27:10 +01:00
Andrew Wu 1fefa84405 dmp/vortex86ex: Add timeout for keyboard system flag checking.
If Vortex86EX PS/2 keyboard controller system flag bit times out,
reload controller firmware code and try again.

Abort and die after 11 tries as this means the CPU is defect. Also
inform the user by printing a message.

Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3988
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-30 20:18:06 +01:00
Aaron Durbin 5afca1357f haswell: check for clean reset
When an INIT# is delivered to the CPU the CPU starts
executing from the reset vector. However, the internal state
is maintained. Therefore, check for such a condition and
reset the system.

Issues 'apreset warm' on the EC console. INIT# is sent and
CPU notices it's not a clean reset and forces one. No hangs.

Change-Id: I71229e0e5015ba8c60f5989c533268604ecc1ecc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57111
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-25 23:55:00 +01:00
Vladimir Serbinenko c6f6be0929 Support for nehalem northbridge
Including raminit

Change-Id: If1dd3855181481b8b928adf0fdb40b29d15897db
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4044
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-25 20:23:38 +01:00
Vladimir Serbinenko 888d559b03 Support for Ibexpeak southbridge
Part of X201 port.

Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4052
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-11-25 19:32:36 +01:00
Duncan Laurie fd0bc14844 haswell: Update ULT microcode to 0x10
[    1.503741] microcode: CPU0 sig=0x40651, pf=0x40, revision=0x10
[    1.510483] microcode: CPU1 sig=0x40651, pf=0x40, revision=0x10
[    1.517213] microcode: CPU2 sig=0x40651, pf=0x40, revision=0x10
[    1.523947] microcode: CPU3 sig=0x40651, pf=0x40, revision=0x10

Change-Id: I19ef40b636eebeb8cc29cc0404abbe263ec8eaa7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50655
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4165
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:11:04 +01:00
Duncan Laurie 1c09710709 haswell: Remove limit on package C-state
With the XHCI controller enabled we no longer hang the
system when dropping into a package C-state so remove
the code that was disabling it.

Change-Id: Icd60488fd2506dac04fb6ec96a77bec265b10d8c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50355
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4163
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:10:46 +01:00
Aaron Durbin 5b4178575f haswell: split microcode between ULT and non-ULT
The current microcode blobs contain both ULT and non-ULT
revisions. Only include one or the other based off of the
CONFIG_INTEL_LYNXPOINT_LP Kconfig option.

Change-Id: I3e4e41d4cd727b1a974361fb469267e6f6022d5a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50318
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4160
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:08:39 +01:00
Duncan Laurie 3e996a55cd haswell: Update ULT microcode to rev 'a'
Change-Id: I714208da23bf7cbd1232874c05ad3100551f5f7c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49647
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4146
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:04:36 +01:00
Duncan Laurie e1e87e0ed6 haswell: Configure PCH power sharing for ULT
This reads PCH power levels via PCODE mailbox and writes the
values into the PMSYNC registers as indicated in the BWG.

Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4143
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:04:12 +01:00
Aaron Durbin f24262d018 haswell: calibrate 24MHz clock against BCLK
On haswell ULT systems there is a 24MHz clock that continuously runs
when deep package c-states are entered. The 100MHz BCLK is shut down
in the lower c-states. When the package wakes back up a conversion
formula needs to be applied. The 24MHz calibration is done using the
internal PCODE unit.

Change-Id: I6be7702fb1de1429273724536f5af9125b98da64
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48292
Tested-by: Stefan Reinauer <reinauer@google.com>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4136
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:03:18 +01:00
Aaron Durbin 7c35131642 haswell: configure c-states
The c-states are configured according to the BWG, however the
package c-states are disabled as they currently cause platform
instability. The exposed ACPI c-state to processor c-state mapping
are as follows for ULT boards:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C7S long latency)
	ACPI(C3) = MWAIT(C10)
The non-ULT boards have an expoed c-state mapping:
	ACPI(C1) = MWAIT(C1E)
	ACPI(C2) = MWAIT(C3)
	ACPI(C3) = MWAIT(C7S)

Included in this patch is removing the updating of current limit
registers as some of the MSRs are different and the proper values
are currently unknown. Lastly, some of the MSRs were renamed to
match the BWG.

Booted 3.8 kernel and used powertop to note package, core, and acpi
c-state residency.

Change-Id: Ia428d4a4979ba3cba44eb9faa96f74b7d3f22dfe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48291
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4133
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 16:01:38 +01:00
Duncan Laurie 0edc22490a smi: Update mainboard_smi_gpi() to have 32bit argument
With the LynxPoint chipset there are more than 16
possible GPIOs that can trigger an SMI so we need
a mainboard handler that can support this.

There are only a handful of users of this function
so just change them all to use the new prototype.

Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49530
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4145
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-11-24 07:40:22 +01:00
Andrew Wu 33b09567d2 dmp/vortex86ex: Move DMP specific POST code defines into one file
Move into src/cpu/dmp/dmp_post_code.h

Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:36:36 +01:00
Duncan Laurie 25b8b7b881 haswell: Put each logical processor in its own P-state domain
The recommendation from Intel is to report each core as a
separate logical domain in the _PSD table.

This goes against the recommendation in the ACPI specification
because all of these cores are on the same package and share a
VR so they will do voltage transitions together.

The reasoning is that with a larger number of logical processors
the P-state often ramps too quickly resulting in higher power
consumption.  By exposing each core as a separate domain the OS
can manage them individually allowing the socket to select the
optimum frequency.

$ cat /sys/firmware/acpi/tables/SSDT > /tmp/SSDT
$ iasl -d /tmp/SSDT

Processor (\_PR.CPU0, 0x00, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000000,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU1, 0x01, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000001,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU2, 0x02, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000002,
      0x000000FE,
      0x00000001
    }
  })
}

Processor (\_PR.CPU3, 0x03, 0x00000000, 0x00)
{
  Name (_PSD, Package (0x01)
  {
    Package (0x05)
    {
      0x05,
      0x00,
      0x00000003,
      0x000000FE,
      0x00000001
    }
  })
}

Change-Id: I5ef41b6ead4d88e9ba117003293dbc629c376803
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4130
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:34:25 +01:00
Duncan Laurie 77647b33cf haswell: Update microcode for ULT/40651 to rev 8
$ cat /sys/devices/system/cpu/cpu*/microcode/version
0x8
0x8
0x8
0x8

Change-Id: Id6491ae96c516ae0b55471e53f79f0407cf3ffdb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4129
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-11-24 05:31:06 +01:00
Vladimir Serbinenko 71f35ebdaa Rename SANDYBRIDGE_BCLK to NEHALEM_BCLK in 2065x.
2065x is with nehalem and not sandybridge.

I don't care much eitherway but it clears some confusion.

Change-Id: Ib2b8e570b830a12ed8d0d313ee4eb56755796d4b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4046
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2013-11-23 14:32:29 +01:00
Vladimir Serbinenko 75b90a1f50 Remove MRC variables from 2065x CAR init.
2065x boards don't use MRC. And the space in question isn't used either.

Read number of variable range MTRRs from MSR rather than hardcoding it.

2ff is still zeroed out as unless you zero-out undocumented bits as well
boot fails.

Tested on Lenovo X201.

Change-Id: Ic574193094e7d27c2d6a4d7d3e387d989578532e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4080
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-23 13:08:50 +01:00
Vladimir Serbinenko 533ad10583 Don't wait on 2065x
The mdelay is not necessarry on 2065x.

Tested on X201 that it works without delay.

Change-Id: Ida9e85be7c214f3ba4c9476b5d8a0351e7980e5e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4083
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-11-22 22:35:58 +01:00
Vladimir Serbinenko fe6bdd96d8 Fix error message on wrong compiles of 2065x
Current error message refers to sandybridge chipset. Instead error
should be that 2065x needs Ibex Peak.

Change-Id: I8cc8a34f496aec7af0ce95b4b65fd25e165f43fb
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4202
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-11-21 00:30:41 +01:00
Vladimir Serbinenko d8cfd23f6a intel/2065x: Use TSC for udelay()
For the ram init of Intel Nehalem ram init we need a udelay implementation.
Use common TSC framework for it as Intel Haswell already does.

Change-Id: I360a6db1ec1ba32c92698a7d6f6968c93ead5c52
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4043
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-13 00:38:45 +01:00
WANG Siyuan 7b6d412dbc vendorcode/amd/agesa/f16kb: Update Kabini PI from v1.0.0.0 to v1.0.0.7
The platform initialization (PI) code v1.0.0.7 for Kabini has some
enhancements like ECC DIMM support, new CPU microcode rev 0700010B, FCH
bug fix (RTC) and so on.

Use the name Kabini instead of Kerala everywhere.

Note, the former PI code was indeed version v1.0.0.0 instead of v0.0.1.0
as used in `AGESA_VERSION_STRING`.

Change-Id: I186de1aef222cd35ea69efa93967a3ffb8da7248
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3935
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-10-15 05:01:11 +02:00
Kyösti Mälkki f8bf5a10c5 Revert "CBMEM: Always have early initialisation"
This reverts commit de1fe7f655.

While things appeared to work, there were actually invalid references
to CAR storage after CAR was torn down on boards without
EARLY_CBMEM_INIT. It was discussed use of CAR_GLOBAL should be
restricted to boards that handle CAR migration properly.

Change-Id: I9969d2ea79c334a7f95a0dbb7c78065720e6ccae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-14 17:16:22 +02:00
Stefan Reinauer fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Paul Menzel 11b47801b2 cpu/x86/mtrr/mtrr.c: Remove superfluous assignment to `type_index`
When building coreboot with the Clang static analyzer scan-build,
it reports »Value stored to 'type_index' is never read«. Indeed,
in `memranges_each_entry()` `type_index` is assigned a value
before being read. So remove that line.

Change-Id: I6da2fb8be7157bb98c57281babd4a08ca0d9f7a7
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3953
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-10-03 15:17:05 +02:00
Allen Martin 681d17e0bf exynos5420: Fix build warning
Fix "set but not used" variable warning with gcc 4.7.3

Change-Id: Ia27291ecb4f993c4ba6f29b134167dc23a449bf5
Signed-off-by: Allen Martin <amartin@nvidia.com>
Reviewed-on: http://review.coreboot.org/3949
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
2013-09-28 22:25:14 +02:00
Kyösti Mälkki cbf5bdfe67 CBMEM: Always select CAR_MIGRATION
If romstage does not make cbmem_initialize() call, linker should
optimize the code for CAR migration away.

This simplifies design of CBMEM console by a considerable amount.
As console buffer is now migrated within cbmem_initialize() call there
is no longer need for cbmemc_reinit() call made at end of romstage.

Change-Id: I8675ecaafb641fa02675e9ba3f374caa8e240f1d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3916
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:34:55 +02:00
Kyösti Mälkki 3d45c40776 timestamps: Stash early timestamps in CAR_GLOBAL
Change-Id: I87b454c748cf885491d5b38bfe53a2ec0e9f38c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3910
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:44 +02:00
Kyösti Mälkki e28bd4ade6 timestamps intel: Move timestamp scratchpad to chipset
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.

Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-21 06:20:02 +02:00
Gabe Black ccf4fdd1cd am335x: Update the config vars selected by CPU_TI_AM335X.
The way those variables work has changed twice since this file was last
changed, and console output was no longer working. Now that they're up to
date there's serial output from beaglebone again.

Change-Id: I5167fd8c0a8c33438d7f056fdf5951bd054010ed
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3923
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-09-17 00:41:01 +02:00
Kyösti Mälkki d50cdf108f CBMEM: Drop parameter from cbmem_reinit()
Function is always called with get_top_of_ram() - HIGH_MEMORY_SIZE
which equals cbmem_base, thus no need to pass it as a parameter.

Change-Id: If026cb567ff534716cd9200cdffa08b21ac0c162
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3564
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:20:25 +02:00
Kyösti Mälkki bc90e15d3f CBMEM: Backup top_of_ram instead of cbmem_toc
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.

TODO: Redesign these get_top_of_ram() functions from scratch.

Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:18:02 +02:00
Kyösti Mälkki c984f4f303 AMD AGESA: Place CAR_GLOBAL in BSP stack
Use BSP CPU's stack space to store CAR GLOBALS for the
duration of romstage before CAR migration.

NOTE: Such globals can only be accessed from BSP CPU due
the way AMD platform has memory architecture set up.

TODO: Add compile-time assertions to verify CAR configuration
matches with the programming in vendorcode.

Change-Id: Ica4700433268f484ce69a24d934732f9cfd4ba41
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3832
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-09-11 07:03:44 +02:00
Kyösti Mälkki 93b2bd70ff usbdebug: Do not support logging from SMM
Letting SMI handler touch EHCI controller is an excellent source
of USB problems. Remove usbdebug entirely from SMM.

It may be possible to make usbdebug console work from SMM
after hard work and coordination with payloads and even
OS drivers. But we are not there.

Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3858
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2013-08-23 05:05:34 +02:00
Bruce Griffith 59c3a06154 AMD AGESA: Remove INVD instruction when transitioning from CAR
The AMD AGESA function to move the stack from cache-as-ram to
actual RAM doesn't need any help.  The current implementation has
an INVD instruction just before cache-as-RAM is torn down. It isn't
needed for Trinity processors and makes Kabini boot unreliable.

Change-Id: Ibe9e4105eee032471ccbb2d537471d5fa5847d22
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3852
Tested-by: build bot (Jenkins)
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-08-16 11:20:05 +02:00
Kyösti Mälkki c66f1cbdae Include boot_cpu.c for romstage builds
ROMCC boards were left unmodified.

Change-Id: I3d842196b3f5b6999b6891b914036e9ffcc3cef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3853
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-08-15 20:49:03 +02:00
Mike Loptien ac90d8013a AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.

Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
2013-08-15 18:40:11 +02:00
Kyösti Mälkki da940c5835 Make EARLY_CONSOLE optional
This change brings back the possibility to disable console
output while in romstage, like before commit d2f45c65.

For some platforms (AMD multi-socket) USBDEBUG and/or CBMEM
CONSOLE do not work correctly for romstage due the way
cache-as-ram is set up, but might already work for ramstage.

Change-Id: Id8d830e02a18129af419d3b5860866acf315d531
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3846
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-08-07 19:12:48 +02:00
Siyuan Wang 5d7d09c4ab AMD Kabini: Add CPU AGESA wrapper for new AMD processor family
Change-Id: I4a1d2118aeb2895f3c2acea5e792fbd69c855156
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Mike Loptien <mike.loptien@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:21:29 +02:00
Kyösti Mälkki 8eaf1e765d cpu/intel/model_67x: Add missing include
The added device.h file was indirectly picked from cpu.h, which will
have this include removed in a follow-up patch.

Change-Id: Ifc0a4800de3b1ef220ab1034934f583be8c527b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3826
Tested-by: build bot (Jenkins)
2013-07-30 08:23:01 +02:00
Ronald G. Minnich b5e777c433 X86: make the SIPI num_starts a config variable
The code to figure out how to set num_starts was
starting to get kludgy. It's a constant for a given
CPU; constants should be constant; make it a config variable.

This change includes an example of how to override it.
Build but not boot tested; drivers welcome.

Change-Id: Iddd906a707bb16251615c7b42f2bfb5a044379b4
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/3796
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-07-22 20:46:51 +02:00
Steve Goodrich bf0988b0a2 AMD Fam15tn: Split DSDT into common sections
Split the Parmer, Family 15tn, and Hudson DSDT into groups.  This splits
the DSDT table into includable ASL files which carry details specific
to the Family 15tn APU, the Parmer platform, and the Hudson FCH.  The
dsdt.asl file in the mainboard directory contains only #include
references to the appropriate files.

Initially, this split was done by moving each piece of functionality
into its own file (e.g. IRQ routing and mapping, processor tree, sleep
states and sleep methods, etc.) and those pieces were #included in
dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
with the extant version of the table.  Once the new tables were found
to exactly match the existing tables, the pieces were rearranged into
reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).

Some include files have no content but are left as a template for
other platforms and as placeholders for completing the ACPI
implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
sata.asl, etc.).

Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/3629
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-16 16:14:56 +02:00
Gabe Black 630e4e8c7e am335x: Make the default media for the bootblock sram instead of NAND flash.
The SOC's built in ROM loads the bootblock and the ROM stage into the on chip
memory before handing over control to the bootblock. To avoid having to add
one or more driver to the bootblock so that it can re-load the ROM stage from
whatever media Coreboot is stored on, we can just take advantage of the copy
that's already there. Loading the RAM stage/payloads won't be so simple,
so the ROM stage and the RAM stage will have to have different media drivers.

Change-Id: Id74ed4bc3afd2063277a36e666080522af2305dd
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3583
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15 18:36:49 +02:00
Gabe Black 6cfe223da0 am335x: Add the config variable ROMSTAGE_BASE to the CPU's Kconfig.
This variable wasn't being defined and was defaulting to zero when used in the
ROM stage's linker script. This change defines it as a variable, and gives it
a value which is slightly beyond the end of the bootblock. By making the ROM
stage request to be loaded slightly farther into memory than it was loaded by
the SOC's masked ROM, we ensure that it's moved away from the stage's metadata
instead of on top of it. When it moves the other way, it clobbers important
values like the entry point vefore the bootblock has had a chance to use them.

Change-Id: I027a1365d05f1d79d7fc1e1349965ccb7d4e81b9
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3582
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-07-15 18:34:59 +02:00
Martin Roth 4c3ab7376e cpu: Fix spelling
Change-Id: I69c46648de0689e9bed84c7726906024ad65e769
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/3729
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11 22:36:59 +02:00
Kyösti Mälkki 2c516ed3f3 usbdebug: Drop old includes
Change-Id: I4786bff41fef924c72087c354e394bdc1996cadc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3764
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-11 21:23:03 +02:00
Kyösti Mälkki 33e5df3f25 Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.

Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11 01:29:35 +02:00
Kyösti Mälkki 8ee04d784c usbdebug: Put ehci_debug_info in CAR_GLOBAL
Store EHCI Debug Port runtime variables in CAR_GLOBAL.
For platforms without CAR_MIGRATION, logging on EHCI Debug Port is
temporarily lost when CAR is torn down at end of romstage.

On model_2065x and model_206ax ehci_debug_info was overlapping the MRC
variable region and additionally migration used incorrect size for
the structure.

Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3475
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-07-10 23:25:53 +02:00
Gabe Black a5dc091129 i2c: Change the type of the data parameter to uint8_t.
Data is intended to be a byte array, so it should be described by a type which
has a fixed size equal to an 8 bit byte. Also, the data passed to write
shouldn't be modified and can be const.

Change-Id: I6466303d962998f6c37c2d4006a39c2d79a235c1
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3721
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:19:49 +02:00
Hung-Te Lin f473df1419 armv7/exynos5420: Remove the extra reopen when reading SPI.
The workaround of re-opening device in exynos_spi_read has been fixed by the new
correct open/close and xfer procedure. It's safe to be removed now.

Change-Id: I6b1bf717c916903999a137998a578b0a866829bd
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3715
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:18:04 +02:00
Hung-Te Lin a965a37810 armv7/exynos5420: Apply new implementation for SPI transmission.
Switch spi_xfer and exynos_spi_read to use the new spi_rx_tx function.

Change-Id: I01ab43509df1319672bec30dd111f98001d655d0
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3714
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:17:47 +02:00
Hung-Te Lin 864420766a armv7/exynos5420: Add output ability and half-duplex mode in SPI driver.
The SPI driver (exynos_spi_rx_tx) was implemented with only "read" ability and
only full-duplex mode. To communicate with devices like ChromeOS EC, we need
both output (tx) and half-duplex (searching frame header) features.

This commit adds a spi_rx_tx that can handle all cases we need.

Change-Id: I6aba3839eb0711d49c143dc0620245c0dfe782d8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3713
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:17:39 +02:00
Hung-Te Lin cab3621446 armv7/exynos5420: Revise SPI open/close/reset procedure.
The original Exynos SPI open/close procedure was copied from U-Boot SPL with
some assumptions that only works in SPL stage.  For example, it tries to always
work in 4-byte transmission mode with only RX data is swapped, and claims a
packet for initial address command (and with incorrect size).

This commit revises open/close and reset so only the required SPI registers are
configured.

Change-Id: Ieba1f03d80a8949c39a6658218831ded39853744
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3712
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:17:16 +02:00
Hung-Te Lin ed1742cafe armv7/exynos5420: Provide configuration for SPI0~SPI2.
Fill the SPI device parameters for spi_setup_slave on Exynos 5420.

Change-Id: I10b4b9e6cfe46d7bfa34e80e3727c7e7da99ba9d
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3711
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:17:07 +02:00
Hung-Te Lin ffa5bada72 armv7/exynos5420: Change SPI module to standard <spi-generic> interface.
The SPI module in Exynos 5420 didn't follow Coreboot's SPI API standard
(spi-generic.h) and will be a problem when we want to share SPI drivers.

This commit replaces exynos_spi_* by spi_* functions.

Note, exynos_spi_read is kept and changed to a static function because its usage
is different from the standard API "spi_xfer".

Change-Id: I6de301bc6b46a09f87b0336c60247fedbe844ca3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3710
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:16:58 +02:00
Hung-Te Lin 45d524d278 armv7/exynos5420: Clean up unused header and constants in spi.c
Remove unused header and constant definition in SPI module.

Change-Id: I339e603f48186e4a356e83518b0d0b4c907f11b8
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3709
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:16:22 +02:00
Hung-Te Lin 16cb010440 armv7/exynos5420: Revise SPI device list in cpu.h
Add SPI0 and SPI2 to Exynos 5 SPI list, and correct structure names.
Also removed the un-enumerated devices (SPI_BASE, base_spi()).

Change-Id: Ica6d9a41f9619c8c61eab664d5e988dd4a428e09
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3708
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:16:10 +02:00
Hung-Te Lin e42030d236 arm/exynos: Correct SPI session commands.
Some initialization / shutdown commands should be paired correctly in a SPI I/O
session. For example, setting CS should be enabled and disabled in each read;
and the bus width (byte or word) should be configured only when opening /
closing the SPI device.

Change-Id: Ie56b1c3a6df7d542f7ea8f1193ac435987f937ba
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3706
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:14:49 +02:00
Kyösti Mälkki 8b95c13420 AMD: Kconfig cleanup
Change-Id: Ie347b32575c26133d52c275622d29d1cd4c6c0c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3623
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10 23:14:28 +02:00
Gabe Black f396ad5a6c exynos5420: i2c: Fix error handling.
The functions which checked the status of a transfer would return success if
the bus was no longer occupied, even if it's no longer occupied because the
transfer failed. This change modifies those functions to return three possible
values, 0 if the transfer isn't done, -1 if there was a fault, and 1 if the
transaction completed successfully.

Change-Id: Idcc5fdf73cab3c3ece0e96f14113a216db289e05
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:00:56 +02:00
Gabe Black 7c2ae7ae53 exynos5420: Clock the mmc blocks off of the mpll.
The exynos manual suggests hooking the mmc ip blocks to the mpll. They had
been set to use a different pll. This changes them over and modifies the
divider so that the frequency stays the same.

Change-Id: I85103388d6cc2c63d1ca004654fc08fcc8929962
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3703
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:00:41 +02:00
David Hendricks be58278a86 exynos5420: use speed parameter in i2c_init() for HSI2C
This allows us to set different speeds for each HSI2C bus.

Change-Id: I50cc257aad9ef50025d0837b0516940b956efc02
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3701
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 23:00:17 +02:00
Gabe Black 2d2e37fc52 exynos5420: Change some clock settings.
This change adjusts some clock settings so that they match U-Boot. There are
three different changes.

1. Change the source for psgen from the oscillator clock to the pclk.
2. Change the pll feeding the SPI busses from epll to mpll, as suggested in
   the manual.
3. Change the SPI prescaller.

Change-Id: Ib54a255bc14fc286629dac86db9b8cf8e75a610b
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3700
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:50:27 +02:00
Gabe Black cf7509cfd1 exynos5420: Fix the way the rate of the input clock for i2c buses is found.
The clock divider was being read from registers incorrectly which meant that
the periph rate was wrong.

Change-Id: I50efb62849ef29bdfb0efc56c49642d3edca094c
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3699
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:49:33 +02:00
Hung-Te Lin 7dd581494d snow: Add flush to UART driver.
Wait for UART FIFO to be ready.
(Credit to dhendrix for finding the bits to test with.)

Change-Id: Ib6733e422cbc1c61b942bd90d85f88a3f412d6ff
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3698
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:49:18 +02:00
Stefan Reinauer 3a0d0d8622 Exynos5420: Initialize USB PHY
... this is needed for libpayload to talk to USB devices.
(forward ported from https://gerrit.chromium.org/gerrit/#/c/55554)

Change-Id: I5a20864689efd0c0149775e6d85b658e0cc6715c
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3697
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:47:53 +02:00
Stefan Reinauer 2ad63c2e08 Exynos5250: Initialize USB PHY
... this is needed for libpayload to talk to USB devices.

Change-Id: I7eb19003c9e96efb5fa7a3f97c7b15f3ef332687
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3696
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:47:44 +02:00
Stefan Reinauer 062c17bb78 Exynos: Only compile UART in if serial console is selected
Change-Id: I5cddffc2e524aae7a31a8f94f67e03a5b7e15c82
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3695
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:46:35 +02:00
Ronald G. Minnich 005151047e Exynos5420: add code to make sure resume will work on DRAM.
Found during a perusal of u-boot changes. It looks important.
For more info: http://git.chromium.org/gitweb/?p=chromiumos/third_party/u-boot.git;a=commit;h=56eab63922d2b2380518238ae03e8d69e99af4fe

Change-Id: Ida2fe2a98be008a4bdfe594cf00d01a33b511b4f
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3693
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:44:21 +02:00
Stefan Reinauer d2f45c6516 Simplify early / bootblock console code
Change-Id: I6b28bb95c7decbe3eed33b5b5a029bee48bbe403
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3691
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:43:56 +02:00
Gabe Black 46b57bbded exynos5420: Switch to fixed size types in dmc.h.
The members data structures in dmc.h are intended to have a particular size.
Rather than assume that particular types are the right size, we should use
types that are guaranteed to be the right size. Also, since the registers are
at particular offsets as well, the structures should be packed.

Change-Id: I9cc11d7451f92ba3eb85c6be88ecbc62c7a5652d
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3685
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:38:05 +02:00
Gabe Black becb3f62f7 exynos5420: Revamp the high speed I2C driver.
The previous driver was a bit awkward and not entirely correct. This change
primarily replaces the read/write functions with simpler and more robust
(hopefully) version.

Change-Id: I55f0ad8faec2de520e27577bd6dad9c0118d8171
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3684
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:37:26 +02:00
Stefan Reinauer 3511b92d31 Samsung CPUs: Unify Kconfig
For all other CPUs, we unconditionally include the CPU Kconfig
files in the CPU directory, not in the vendor directory. Do the
same thing for the Exynos CPUs. This allows us to make CPU dependent
changes in the directory of that CPU alone.
Also, drop some unused Kconfig variables from the Exynos Kconfig
files.

Change-Id: I4e4c22a0693988834e619dd33d121bf994ed57e8
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3683
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-10 22:36:53 +02:00