Bring all GNVS related initialisation function to global
scope to force identical signatures. Followup work is
likely to remove some as duplicates.
Change-Id: Id4299c41d79c228f3d35bc7cb9bf427ce1e82ba1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42489
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig 4.17 started using the $(..) syntax for environment variable
expansion while we want to keep expansion to the build system.
Older Kconfig versions (like ours) simply drop the escapes, not
changing the behavior.
While we could let Kconfig expand some of the variables, that only
splits the handling in two places, making debugging harder and
potentially messing with reproducible builds (e.g. when paths end up
in configs), so escape them all.
Change-Id: Ibc4087fdd76089352bd8dd0edb1351ec79ea4faa
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
At least one mobile 945 series northbridge supports 4 threads, because
the dual-core Atom 330 CPU supports Hyper-threading. Therefore, we use
that as the default for this chipset.
Change-Id: I899ed1644d9b2da4fc72f09233a421200770110d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41845
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
LGA775 CPUs can have at most 4 threads, and Eaglelake supports them.
As this socket is also used by other chipsets, temporarily place this
symbol into the northbridge scope until all chipsets are factored out.
Change-Id: I6e01363d995e135815cc70779e0cd5baf806cf60
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Port commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD AGESA Hudson boards.
No idea, if this is correct for the two laptops. The Lenovo G505s also
incorrectly defines two power buttons.
[ 0.911423] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input1
[ 0.911434] ACPI: Power Button [PWRB]
[ 0.911493] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input2
[ 0.912326] ACPI: Power Button [PWRF]
If the generic power button device is needed, the POWER_BUTTON flag
should be set in FADT.
The GPE ACPI code seems to originate from commit 806def8c (I missed the
svn add on r3787. These are the additional files., Add AMD dbm690t ACPI
support.), and was copied over.
Change-Id: I88950e15faf1b90ca6e688864bac40bf9779c32e
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Until now, the buildOpts.c files were primarily made out of copy-pasted
AGESA options, commented-out definitions and several useless comments;
that is, the materialization of technical debt in GCC-parsable form...
Until now.
It is assumed that the boards in the tree still boot. So, by comparing
their settings, we can extract saner defaults to place into AGESA. Many
of the settings were common across all boards of the same family, so we
promote those values to default settings. In some cases flipping a flag
was required, so the macros to alter that option had to be adapted as
well. Since those AGESA versions are expected to never receive updates,
it should not be a problem to change their files to suit our needs.
As a result, all but two buildOpts.c files now have less than 100 lines.
AGESA f14 boards need less than 50 lines, and f15tn/f16kb just require
about 60 or 70 lines in those files. Hopefully, this will make porting
more mainboards using AGESA f14/f15tn/f16kb a substantially easier task.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ife1ca5177d85441b9a7b24d64d7fcbabde6e0409
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Run the command below to fix all occurrences.
git grep -l OVERIDES | xargs sed -i 's/OVERIDES/OVERRIDES/g'
Change-Id: I5ca237500a0ecff59203480ecc3c992991f08130
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
On AGESA f14/f15tn, various RAM-related options were defined in an enum.
However, the preprocessor mess can't compare enum values. To make AGESA
build, each board redefined them as macros, shadowing the enum elements.
Clean this up by replacing the enums with macros in AGESA headers, and
delete the now-redundant redefinitions from all the mainboards.
Note that AGESA f16kb already uses macros, but each mainboard still had
commented-out definitions. Remove them as well, as they are unnecessary.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ie1085539013d3ae0363b1596fa48555300e45172
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41666
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All AGESA f16kb boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I236e9d45505e92027acc3ba5ff496f5e2f09b9f3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
All AGESA f15tn boards use the same MTRR values. Factor them out,
while still allowing a board to override them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I90c95493de1bb5b8f32c06b9575fef3aa7aca031
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
We use the same values everywhere, so we might as well factor them out.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ie6f166034d5d642dff37730a8d83264fb2e019b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
We set BLDCFG_PCI_MMIO_BASE and BLDCFG_PCI_MMIO_SIZE to the same values
everywhere, so we might as well factor them out. As we have equivalent
Kconfig options in coreboot, also deprecate overriding them via BLDCFG.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I7244c39d2c2aa02a3a9092ddae98e4ac9da89107
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
We use the same AGESA version numbers on all but one mainboard, so we
might as well factor them out. The only exception is asrock/e350m1,
which has the f15tn/f16kb version number even though it actually uses
AGESA f14. To preserve reproducibility, do not change it in this commit.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I0dad2352ccda454d5545f17228d52e4ff4f23f20
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41591
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We use the same value everywhere, so factor it out. Note that the field
where this value ends up in was doubled in size for AGESA fam16kb, but
we did not update the definition to fill in the additional space. We are
not changing it in this commit so as to preserve binary reproducibility.
In any case, add a FIXME explaining why this value may not be correct.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ied118d534ee1e9728db843944d1e042760b4f32c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Drop multiple blank lines and use one space inside C-style comments.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: Ibe1f279dd22ae7657ea7b7766f88004dbf4dceb5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
This does not exist anywhere in the entire coreboot tree. Drop it.
TEST=Use abuild --timeless to check that all AGESA f14/f15tn/f16kb
mainboards result in identical coreboot binaries.
Change-Id: I80320a20f4b44896e72d701a1d98786cb3a93dcc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
With conversion to variant structure complete, remove temporary guards
inserted to help validate the move.
With this change, all P2B family boards (currently p2b and p2b-ls)
share the same S-state declarations.
TEST=No apparent ACPI regression observed on p2b-ls.
Change-Id: Ibd6e49adeae2a42800ee5bfd74b3850eb19843a5
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Stefan thinks they don't add value.
Command used:
sed -i -e '/file is part of /d' $(git grep "file is part of " |egrep ":( */\*.*\*/\$|#|;#|-- | *\* )" | cut -d: -f1 |grep -v crossgcc |grep -v gcov | grep -v /elf.h |grep -v nvramtool)
The exceptions are for:
- crossgcc (patch file)
- gcov (imported from gcc)
- elf.h (imported from GNU's libc)
- nvramtool (more complicated header)
The removed lines are:
- fmt.Fprintln(f, "/* This file is part of the coreboot project. */")
-# This file is part of a set of unofficial pre-commit hooks available
-/* This file is part of coreboot */
-# This file is part of msrtool.
-/* This file is part of msrtool. */
- * This file is part of ncurses, designed to be appended after curses.h.in
-/* This file is part of pgtblgen. */
- * This file is part of the coreboot project.
- /* This file is part of the coreboot project. */
-# This file is part of the coreboot project.
-# This file is part of the coreboot project.
-## This file is part of the coreboot project.
--- This file is part of the coreboot project.
-/* This file is part of the coreboot project */
-/* This file is part of the coreboot project. */
-;## This file is part of the coreboot project.
-# This file is part of the coreboot project. It originated in the
- * This file is part of the coreinfo project.
-## This file is part of the coreinfo project.
- * This file is part of the depthcharge project.
-/* This file is part of the depthcharge project. */
-/* This file is part of the ectool project. */
- * This file is part of the GNU C Library.
- * This file is part of the libpayload project.
-## This file is part of the libpayload project.
-/* This file is part of the Linux kernel. */
-## This file is part of the superiotool project.
-/* This file is part of the superiotool project */
-/* This file is part of uio_usbdebug */
Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fold this last ASUS 440BX board into the P2B family, while bringing in
some changes:
- Devicetree becomes overridetree.
- Remove non-existent IR device and disable ACPI device on Super I/O to
match OEM firmware.
- Add SB GPO settings from OEM firmware to devicetree. This disables
the SPD enabling magic this board needs. By moving the enabling part
to bootblock the hacky enable_spd hook can be eliminated.
- Initialize the serial port in bootblock, like the other boards.
Boot tested on hardware.
Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This replaces GPLv2-or-later and GPLv2-only long form text with the
short SPDX identifiers.
Commands used:
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.*of.*the.*License.*or.*(at.*your.*option).*any.*later.*version.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-or-later */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*as.*published.*by.*the.*Free.*Software.*Foundation[;,].*version.*2.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This program is free software[:;].*you.*can.*redistribute.*it.*and/or.*modify.*it.*under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation[.;,].+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
perl -i -p0e 's|/\*[*\n\t ]*This software is licensed under.*the.*terms.*of.*the.*GNU.*General.*Public.*License.*version.*2.*as.*published.*by.*the.*Free.*Software.*Foundation,.+This.*program.*is.*distributed.*in.*the.*hope.*that.*it.*will.*be.*useful,.*but.*;.*without.*even.*the.*implied.*warranty.*of.*MERCHANTABILITY.*or.*FITNESS.*FOR.*A.*PARTICULAR.*PURPOSE..*.*See.*the.*GNU.*General.*Public.*License for more details.[\n\t ]*\*/|/* SPDX-License-Identifier: GPL-2.0-only */|s' $(cat filelist)
Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
That makes it easier to identify "license only" headers (because they
are now license only)
Script line used for that:
perl -i -p0e 's|/\*.*\n.*This file is part of the coreboot project.*\n.*\*|/* This file is part of the coreboot project. */\n/*|' # ...filelist...
Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It is only used with the Lenovo-specific H8 EC code.
Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
There's no reason not to.
Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The SVID functionality is not used on this mainboard. Turn it off.
Change-Id: Iea891975b32d24f54edec9d8c36391ec60a37d0c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
SB-TSI is specific to AMD platforms, but this is an Intel board.
Change-Id: I5eb7e3bc920103279dfca3a9ec14a41666404993
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40738
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board uses the pin for Deep S5, but the code was setting 3VSBSW.
Change-Id: I81c865358002e6af500658efea851ab8c8202950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This change moves all ACPI table support in coreboot currently living
under arch/x86 into common code to make it architecture
independent. ACPI table generation is not really tied to any
architecture and hence it makes sense to move this to its own
directory.
In order to make it easier to review, this change is being split into
multiple CLs. This is change 3/5 which basically is generated by
running the following command:
$ git grep -iIl "arch/acpi" | xargs sed -i 's/arch\/acpi/acpi\/acpi/g'
BUG=b:155428745
Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
These boards have the same issue as [27272]:
Currently, two power buttons are exposed in ACPI, and detected by the
operating system.
> As per the ACPI specification, there are two types of power button
> devices:
> 1. Fixed hardware power button
> 2. Generic hardware power button
>
> Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
> is not set in FADT by the BIOS. This device has its programming model
> in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
> power button device by default if the power button FADT flag is not
> set.
>
> On the other hand, generic hardware power button can be used by
> platforms if fixed register space cannot be used for the power button
> device. In order to support this, power button device object with HID
> PNP0C0C is expected to be added to ACPI tables. Additionally,
> POWER_BUTTON flag should be set to indicate the presence of control
> method for power button.
>
> [i440BX] mainboards implemented the generic hardware power button in
> a broken manner i.e. power button object with HID PNP0C0C is added to
> ACPI however none of the boards set POWER_BUTTON flag in FADT. This
> results in Linux kernel adding both fixed hardware power button as
> well as generic hardware power button to the list of devices present
> on the system. Though this is mostly harmless, it is logically
> incorrect and can confuse any userspace utilities scanning the ACPI
> devices.
Hardware tests on the P2B-LS shows the generic hardware power button
is not working anyway - with FADT power button flag set, the board
could not power off with the button.
This change removes the generic hardware power button from all P2B
mainboards and relies completely on the fixed hardware power button.
TEST=Booted on P2B-LS, Linux detects only fixed hardware power
button, button still powers off.
[27272]: https://review.coreboot.org/27272
Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replicate the GPO configurations from OEM BIOS, obtained via inteltool.
Among the GPOs are termination controls for the onboard SCSI buses.
TEST=read/write Maxtor Atlas 10k3 18GB HDD connected to Ultra2 LVD port
Change-Id: I86183acd8e1a830d7639c21ec179fbdbe937f8ee
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a micro ATX board with a LGA1155 socket and two DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
Actually, I have the PLUS variant, but they use the same PCB. The only
difference is the capacitor quality.
Working:
- Both DIMM slots
- PS/2 keyboard
- S3 suspend/resume
- Rear USB ports
- Integrated graphics (libgfxinit)
- VGA
- All PCIe ports
- Realtek GbE (coreboot must set the MAC address)
- SATA ports
- Native raminit
- Flashing with flashrom
- Rear audio output
- VBT
- Arch Linux using CorebootPayloadPkg
Untested:
- PS/2 mouse
- The other audio jacks
- EHCI debug
- Front USB headers
- Non-Linux OSes
Change-Id: I385ee72673202d896041209ff2911995307cb6af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All variants will use the same lid/thermal-polarity config as a result,
which looks the same for all recently boot-tested variants anyway.
Change-Id: Iaaae4eae41ab0037e72375b255d9d1c3eca8d383
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39905
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original AMD_PLATFORM_MOBILE is incorrect because this board is a desktop one.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I02adedffe8624c38e7b93fadd0449ddf094388fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33919
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like the guard was dropped by mistake.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ie73c4d6cb557820ae7427fef15ca8110722c5b68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33916
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These comments exist in other buildOpts.c files, but not in this one.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic0aab06f1956bc0bf9f96d6176643c113a1e4cc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This makes it easier to know which files are being included.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ic096848f23910e2ad9183e44d882450ab8d4fdf1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reorder lines to make it more similar to buildOpts.c of Lenovo G505S.
This improves diff results, which is convenient for debugging.
Tested with BUILD_TIMELESS=1, hashes do not change.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I1674252fab2fc6fbf9be2b37e97a6f5ff97a04b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sb/intel/i82371eb/isa.c has code that fills this path with CPU info.
Because it was not declared in the DSDT, Linux kernel 4.4.18 as used in
Slackware 14.2 complains.
Change-Id: Ib85dd02504b068bb7ea71be2f22e425f3831595a
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38601
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this bootblock messages are transmitted over serial too.
TEST=Serial messages transmitted normally on asus/p2b-ls.
Change-Id: I6f3ee68e7c76a8c6db6d75956e6a7fb75ef83850
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Done with sed and God Lines. Only done for C-like code for now.
Change-Id: I92d0dc8d93a8b409959d79834ccb5093224285cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here.
Additionally add processor scope patching for P-State SSDT created by
AGESA, becasue AGESA creates the tables with processors in \_PR scope.
TEST=boot Debian Linux on PC Engines apu2, check dmesg that there are
no errors, decompile ACPI tables with acpica to check whether the
processor scope is correct and if IASL does not complain on wrong
checksum, run FWTS
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I35f112e9f9f15f06ddb83b4192f082f9e51a969c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39698
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
They're listed in AUTHORS and often incorrect anyway, for example:
- What's a "Copyright $year-present"?
- Which incarnation of Google (Inc, LLC, ...) is the current
copyright holder?
- People sometimes have their editor auto-add themselves to files even
though they only deleted stuff
- Or they let the editor automatically update the copyright year,
because why not?
- Who is the copyright holder "The coreboot project Authors"?
- Or "Generated Code"?
Sidestep all these issues by simply not putting these notices in
individual files, let's list all copyright holders in AUTHORS instead
and use the git history to deal with the rest.
Change-Id: I57fc98788bb47df16d6aedd0f0701e9991801743
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to clobber the registers with
garbage in ramstage.
Tested, my Asus P5G41T-M LX still boots and it does not need a full
reset on almost every reboot.
Change-Id: I6ea498119df44243ec42e3cb5c2903de32a17373
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39384
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all GPIO4 pins on the SuperIO are configured as outputs.
Change-Id: Idf6350551a91c4c1a25a83e3fb9b1a6722a81c36
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This mainboard has the FSB BSEL straps wired to SuperIO GPIOs. They are
set up in romstage, so it makes no sense to rewrite their values in
ramstage.
Tested, my Asus P5QPL-AM still boots.
Change-Id: Ic47f96d12420ebcc70ab5cea940c4c09620c03ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is an ATX mainboard with a LGA1155 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
Working:
- All four DIMM slots
- Serial port to emit spam
- PS/2 keyboard
- S3 suspend/resume
- Rear USB ports
- Integrated graphics (libgfxinit)
- HDMI and VGA
- All PCIe ports
- Realtek GbE (coreboot must set the MAC address)
- Both PCI ports behind the ASM1083 PCI bridge
- SATA ports
- Native raminit
- Flashing with flashrom
- Rear audio output
- VBT
- SeaBIOS to boot Arch Linux
Untested:
- PS/2 mouse
- The other audio jacks
- EHCI debug
- Front USB headers
- Non-Linux OSes
Change-Id: Ia5d9176b6f435977ecdd4fc82fc4bc0974d8d6a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Only some mainboard vendors have a prompt for this option. Let's be fair
and give this ability to everyone.
Change-Id: I03eec7c13d18b42e3c56fb1a43dc665d5dbd1145
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
They are downright useless and result in ACPI errors. So, burn them.
Also, do a minor update to autoport's README about these values.
Change-Id: Idb5832cfd2e3043b8d70e13cbbe8bd94ad613120
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Set up the proper IRQ routing for OHCI/EHCI devices which appear if
XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set).
Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode.
They also work fine if XHCI controller is enabled.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Use lowercase for hex constants, remove registers that default to zero
already and drop outdated comment about AHCI mode.
Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
They default to zero already. Moreover, the comment about AHCI mode no
longer applies, as it was made the default mode.
Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Replace a bunch of spaces with tabs, put host bridge and friends above
southbridge, fix "TPM Module" (Trusted Platform Module Module) and add
some empty lines to help the reader.
Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This touches several mainboards. Replace the macro with C functions.
The presence of bootblock.c is assumed.
Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Long-term plan is to support loading runtime configuration
from SPI flash as an alternative, so move these prototypes
outside pc80/.
Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The majority of Socket AM1 APUs [1] - three out of five - have the integrated
VGA with 1002,9830 ID, while only one Sempron has 1002,9836. Since VGA_BIOS_ID
is already defined in fam16kb Kconfig as 1002,9830 ID, drop the value here.
[1] https://en.wikipedia.org/wiki/List_of_AMD_accelerated_processing_units#%22Kabini%22_(2013,_SoC)
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I75c815b13934afcb5be316f85933f7c200d55bbd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33777
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: I7f2937bb7715e0769db3be8cb30d305f9d78b6f8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Remove commented-out entries in dsdt.asl, and then remove files that do
not get built.
Change-Id: I579e7ffbc2d6596fd7ffe6863ff3b3fb14b0ade6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Don't initialize fields with zeroes since gnvs structs were zeroed out
in southbridge already. See
* src/southbridge/intel/*/lpc.c
Change-Id: I5228f2cdc94df722ffa687c45b4e4fd25e82df82
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gnvs structure was zeroed out before calling acpi_create_gnvs(...)
in the following files:
* src/southbridge/intel/*/lpc.c
Change-Id: Id7755b1e4b8f5cb8abd1f411b5dc174b6beee21c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37956
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, each Intel chipset had its own sleepstates.asl file.
However, this is no longer the case, so drop these comments.
Change-Id: I50aba6e74f41e2fa498375b5eb6b7e993d06bcac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Switching was done by moving a SIO configuration and
the clocks setup from 'romstage.c' to 'bootblock.c',
following the example of change CB:37719 (fc749b2).
TEST=Boots into Artix Linux 2019 without a problem.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I780fa87cb9cb3c45844c388331ef89eb8eb70ebb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
It provides no useful information, so it might as well vanish.
Change-Id: I0df6f4639a16058486c2e2d40fe4067d65670731
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Also, don't define the default as this results in spurious lines in the
.config.
TEST: Build all boards with where config.h differed with
BUILD_TIMELESS=1 and remained the same
Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y
is a mandatory feature, which most AGESA and binaryPI boards lack.
Disable such platforms from the build for the time being.
The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the
same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y.
If a platform does not reach ROMCC_BOOTBLOCK=n within a
reasonable timeframe both the mainboard and the respective
unused platform support code will get removed.
Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These entries have no functional purpose, followup work will
disallow chip entries that do not link in the respective
driver.
Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIe root port clock gate is already enabled at i945/early_init.c
Also fix comments when only PCIe root port is enabled.
Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Allows boards to be transformed to C env bootblock one
at a time.
Change-Id: I1cc1910a8bfb6b3495593979cbf7194b0d82c8e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37345
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kconfig became stricter on what it accepts, so accomodate before
updating to a new release.
Change-Id: I92a9e9bf0d557a7532ba533cd7776c48f2488f91
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is some overlap between romstage and bootblock.
LPC setup and BAR initialization is now done twice.
The rationale is that the romstage should not depend too
much on the bootblock, since it can reside in a RO fmap
region.
Enabling the console will be done in a followup patch.
Change-Id: I4d0ba29111a5df6f19033f5ce95adcc0d9adc1fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This also changes the name to mainboard_pch_lpc_setup to better
reflect that it is an optional mainboard hook.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: Ie8e6056b4c4aed3739d2d12b4224de36fe217189
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This also changes the name to mainboard_late_rcba_config to better
reflect what it does.
This adds an empty weakly linked default. The rationale behind this
change is that without an implementation of the hook some features
might not work but that the result is likely still able to boot, so it
can be made optional.
Change-Id: I1897d0f5ca7427d304a425f5256cd43c088ff936
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36781
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This adds an empty weakly linked default. The rationale behind this
change is that without the callback some features might not work
but that the result is likely still able to boot, so it can be made
optional.
Change-Id: I62c8010aa81fc45d208e9293feb2f45b45f34a82
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There is some overlap between things done in bootblock
and romstage like setting BARs.
Change-Id: Icd1de34c3b5c0f36f2a5249116d1829ee3956f38
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36759
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds 3 mb romstage callbacks:
- void mb_lpc_setup(void) to be used to set up the superio
- void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs
- (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard
specific things before the raminit.
Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One functional change is that southbridge GPIO init is moved
after console init.
Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting southbridge GPIO is now done after console init,
which should be fine. This code is partially copied from
i82801ix.
Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove some of the code duplication on i82801gx.
x4x boards are left untouched for now since that northbridge
also supports i82801jx.
The order of some things has changed:
- on i945 early_ich7_init is now done before the raminit
- enabling the IOAPIC is done before the raminit
Change-Id: Ie39549938891e17667a8819b49a78b9c71c8ec9e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36754
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The superio VSBGATE# functionality needs to be enabled for ram to be
powered during S3.
Change-Id: I7b827e025de7d5b53c587872238a411fc9c2e762
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36709
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested, working:
- First dimm slot of each channel
- USB, SATA
- CPU FSB at 800, 1067 and 1333MHz
- Libgfxinit on DVI and VGA slot
- PCI slot
- Realtek NIC (configure MAC address in Kconfig)
- PEG slot
- PS2 keyboard
Tested, not working:
- second dimm slot for each channel. Those are hooked up to the second
rank of the channel, instead of rank 3 and 4. The raminit does not
support such setups.
Untested:
- PCIe x1 slot, likely works fine
- HDMI
Tested using SeaBIOS 1.12, Linux 4.19.
Change-Id: I88fe9c66dae079cd7eedcc9736c5922defbc0e5a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These are likely not properly set up and L1 is not even supported on
the desktop variant of the southbridge.
This fixes observed instability on some PCIe GPUs.
Change-Id: I70d3536984342614a6ef04a45bc6591e358e3abe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a common instance of sleepstates.asl inside intel common
code (southbridge/intel/common/acpi) and asks all IA CPU/SOC code to
refer sleepstates.asl from common code block.
TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify
S0/S3/S4/S5 entries after booting to OS.
Change-Id: Ie2132189f91211df74f8b5546da63ded4fdf687a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36463
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI Version 6.3 Section 6.1: "A device object must contain either an _HID
object or an _ADR object, but should not contain both."
Change-Id: I50cafce0aaf465ee95562ccff6c8f63fb22096c0
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This sets up some common default LPC decode ranges in a common place.
This may set up more decode ranges than needed but that typically does
not hurt. Mainboards needing additional ranges can do so in the
mainboard pch_enable_lpc hook.
Change-Id: Ifeb5a862e56f415aa847d0118a33a31537ab8037
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33549
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some boards with the G41 chipset lacked programming CIR, so this
change add that to those boards too.
Change-Id: Ia10c050785170fc743f7aef918f4849dbdd6840e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The superio driver that was linked in is nct6779d but static
devicetree expected symbol superio_nuvoton_nct5572d_ops.
Change-Id: I648b7680bb39b9ff5b38cc3bd5147bd336e0b282
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove duplicated code and instead use the IPMI KCS driver, which provides
the same functionality.
Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It probably doesn't make sense to continue if the CK804 isn't found, and
doing so would perform uninitialized reads of the busn and io_base
arrays anyway, so let's return early.
Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1370586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Autoport generates these structures as static so let's make it consistent.
See also commit 128205fd with Change-Id
I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve
gpio.c generation").
Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO46 is wired to a tiny switch on the board labelled "GPU Boost".
Since coreboot could make use of it, add a comment about it on gpio.c.
Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.
Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that
the boot process of this board is super slow when UART 0 is being used -
even if nothing is connected to it. Enable UART according to
CONFIG_UART_FOR_CONSOLE - and, if UART 0 is selected, it will be initialized
at romstage and this problem will not happen.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some variants only support 4 PCIe ports so there is no need to have
those unavailable ports in the devicetree.
Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use common code to detect ACPI S3.
Untested.
Change-Id: I2264c087b317f70506817b5458295a17e83b1efc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Select support in Kconfig and configure device in devicetree
Tested with ASUS addon TPM modules, v1.2 (ASUS TPM-L FW3.19 rev1.02H) and v2.0 (ASUS TPM-L R2.0 rev1.00) using SeaBIOS and Linux OS
Change-Id: Icdad9a41b61221b536f2ac695f44319f6b0599e7
Signed-off-by: Simon Newton <simon.newton@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32080
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
There are 3 PCI-E 1x ports on p5q_pro and p5qc, which correspond to
the first three functions of 1c.
Confirmed on a p5q_pro board.
Change-Id: I779400494e27bf046996512d1f772311e6e4e091
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Avoid preprocessor here, also we never set loglevel
to value of >8 so the call would not be made.
The calls to ram_check() were removed, for a long
time that function has not tested start..stop region.
Change-Id: Ib952b8905c29a5c5c289027071eb6ff59aaa330b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Also includes lines sorted
Change-Id: Idf2b41f471f531b2a9c3e620563e3c658dea4729
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31267
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Working:
- USB (Partially. Check "Not working")
- PCIe
- PCIe graphics
- All SATA ports
- Native memory init
- On-board audio (back and front)
- S3 (Sleep and wake)
Not working:
- Fan control
- USB (If the keyboard has a USB Hub or if the keyboard
is connected through 2 or more hubs then it doesn't
initialize in time. A simple reboot allows the
keyboard to be used in SeaBIOS and the bootloader)
Untested:
- PS/2
- On board graphics
Change-Id: I4ed2077248a8d7123c728c790d9b81fe37956ed2
Signed-off-by: Abhinav Hardikar <realdevmaster64@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30767
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
