This patch adds the functionality to write the DXIO and DDI descriptors
to the UPD data structure to the SoC code and adds the
mainboard_get_dxio_ddi_descriptors function to each mainboard using the
Cezanne SoC that gets called to get the descriptors from the board code.
Change-Id: I1cb36addcf0202cd56ce99e610a13d6d230bc981
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows coreboot to easily iterate over the descriptors.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2ecb3b543f90b8c6a957794f0c55b0ba5c72d59d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51955
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The UPD header files get generated as part of the FSP build process. For
the initial Cezanne development we took the Picasso UPD data structures
as a starting point. This patch replaces it with the first version of
the Cezanne-specific UPD data structures that is present in version 12
of the internal work-in-progress FSP binary drops.
The serial_port_stride UPD-M field is removed, since the information is
already given by serial_port_use_mmio. The stride is 4 bytes for the
MMIO UART case and 1 byte for the legacy I/O case.
BUG=b:182524631
TEST=NVMe works on google/guybrush when the rest of the patch train is
applied as well.
Change-Id: Idca235029bf2e68d403230d55308820cab61a6c0
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIOs should be configured in ramstage even if they are configured in an
earlier stage.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I07d5c46d6ea6dc2bc9ab265d0c01772d653884cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
On VCCin there was an oscillation which occurred just as the kernel
started (kernel starting... message). On some devices, this behavior
seems even worse. In previous platforms VCCin toggled for a few ms
and then was stable. For volteer, this happens at the same point in
time for around 40ms. However, it starts oscillating again later in
the boot sequence. Once at the root shell, it seems to oscillate
indefinitely at around 100-200Hz (very variable though). To fix this
we need to control the deep C-state voltage slew rate.We have options
for controlling the deep C-state voltage slew rate through FSP UPDs.
This patch expose the following FSP UPD interface into coreboot:
- AcousticNoiseMitigation
- FastPkgCRampDisable
- SlowSlewRate
We are setting SlowSlewRate for all volteer boards to 2 which is Fast/8.
TGL has a single VR domain(Vccin). Hence, the chip config is updated to
allow mainboards to set a single value instead of an array and FSP UPDs
are accordingly set.
BUG=b:153015585
BRANCH=firmware-volteer-13672.B
TEST= Measure the change in noise level by changing the UPD values.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: Ica7f1f29995df33bdebb1fd55169cdb36f329ff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
From Skylake/Sunrise Point onwards, there are two BIOS_CNTL registers:
one on the LPC/eSPI PCI device, and another on the SPI PCI device. When
the WPD bit changes from 0 to 1 and the LE bit is set, the PCH raises a
TCO SMI with the BIOSWR_STS bit set. However, the BIOSWR_STS bit is not
set when the TCO SMI comes from the SPI or eSPI controller instead, but
a status bit in the BIOS_CNTL register gets set. If the SMI cause is not
handled, another SMI will happen immediately after returning from the
SMI handler, which results in a deadlock.
Prevent deadlocks by clearing the SPI synchronous SMI status bit in the
SMI handler. When SPI raises a synchronous SMI, the TCO_STS bit in the
SMI_STS register is continously set until the SPI synchronous SMI status
bit is cleared. To not risk missing any other TCO SMIs, do not clear the
TCO_STS bit again in the same SMI handler invocation. If the TCO_STS bit
remains set when returning from SMM, another SMI immediately happens and
clears the TCO_STS bit, handling any pending events.
SPI can also generate asynchronous SMIs when the WPD bit is cleared and
one attempts to write to flash using SPI hardware sequencing. This patch
does not account for SPI asynchronous SMIs, because they are disabled by
default and cannot be enabled once the BIOS Interface Lock-Down bit in
the BIOS_CNTL register has been set, which coreboot already does. These
asynchronous SMIs set the SPI_STS bit of the SMI_STS register. Clearing
the SPI asynchronous SMI source should be done inside the SPI_STS SMI
handler, which is currently not implemented. All of this goes out of the
scope of this patch, and is currently not necessary anyway.
This patch does not handle eSPI because I cannot test it, and knowing if
a board uses LPC or eSPI from common code is currently not possible, and
this is beyond the scope of what this commit tries to achieve (fix SPI).
Tested on HP 280 G2, no longer deadlocks when SMM BIOS write protection
is on. Write protection will be enforced in a follow-up.
Change-Id: Iec498674ae70f6590c33a6bf4967876268f2b0c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50754
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 52e6194558.
Reason for revert: Graphics actually works now. I should have abandoned this CL.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I83aac3a2c616bb434706f23e36549760bc764080
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
TPM_INIT is disabled by default. This prevents TPM to be operational
when VBOOT is disabled.
Remove the TPM_INIT disable.
BUG=N/A
TEST=tested on facebook monolith with VBOOT disabled.
Change-Id: I84d525a18c84643903922fef0a11dcf98abbbe4d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52052
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Make sure the standard for the board options are set when VBOOT is
enabled.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I9749eeeffbd26e7c5caaeb7c0407a765cf093337
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Added new LPC and IGD device IDs for Alderlake M.
Also, added entry for CPUID_ALDERLAKE_M_A0 in report_platform.c
TEST=Check if platform information print is coming properly in coreboot
Change-Id: If33c43da8cbd786261b00742e342f0f01622c607
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50138
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Bayhub SD card reader power-saving mode for Lindar and Lillipup.
BUG=b:173676531
TEST=Boot to OS and test with SD card function.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: I923d6e1beacd007c0e501f39c1f434c3e1085b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51623
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch changes the mem_pool implementation to track the last two
allocations (instead of just the last) and allow them both to be freed
if the mem_pool_free() calls come in in reverse order. This is intended
as a specific optimization for the CBFS cache case when a compressed
file is mapped on a platform that doesn't natively support
memory-mapping flash. In this case, cbfs_map() (chaining through to
_cbfs_alloc() with allocator == NULL) will call
mem_pool_alloc(&cbfs_cache) to allocate space for the uncompressed file
data. It will then call cbfs_load_and_decompress() to fill that
allocation, which will notice the compression and in turn call
rdev_mmap_full() to map the compressed data (which on platforms without
memory-mapped flash usually results in a second call to
mem_pool_alloc(&cbfs_cache)). It then runs the decompression algorithm
and calls rdev_munmap() on the compressed data buffer (the latter one in
the allocation sequence), leading to a mem_pool_free(). The remaining
buffer with the uncompressed data is returned out of cbfs_map() to the
caller, which should eventually call cbfs_unmap() to mem_pool_free()
that as well. This patch allows this simple case to succeed without
leaking any permanent allocations on the cache. (More complicated cases
where the caller maps other files before cbfs_unmap()ing the first one
may still lead to leaks, but those are very rare in practice.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic5c4c56a8482752ed65e10cf35565f9b2d3e4b17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
RETURN_FROM_VERSTAGE is a somewhat tricky construct that we don't
normally do otherwise in coreboot. While it works remarkably well in
general, new development can lead to unintentional interactions with
confusing results. This patch adds a debug print to the verstage right
before returning to the bootblock so that it's obvious this happens,
because otherwise in some cases the last printout in the verstage is
about some TPM commands which can be misleading when execution hangs
after that point.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I9ca68a32d7a50c95d9a6948d35816fee583611bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_VERIFICATION requires the CBFS metadata hash anchor to be linked
into an uncompressed stage, but for platforms using COMPRESS_BOOTBLOCK,
this is only the decompressor stage. The first CBFS accesses are made in
the bootblock stage after decompression, so if we want to make
CBFS_VERIFICATION work on those platforms, we have to pass the metadata
hash anchor from the decompressor into the bootblock. This patch does
just that. (Note that this relies on the decompressor data remaining
valid in memory for as long as the metadata hash anchor is needed. This
is always true even for OVERLAP_DECOMPRESSOR_ROMSTAGE() situations
because the FMAP and CBFS metadata necessarily need to have finished
verification before a new stage could be loaded.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I2e6d7384cfb8339a24369eb6c01fc12f911c974e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52085
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds file data hashing for CONFIG_CBFS_VERIFICATION. With
this, all CBFS accesses using the new CBFS APIs (cbfs_load/_map/_alloc
and variants) will be fully verified when verification is enabled. (Note
that some use of legacy APIs remains and thus the CBFS_VERIFICATION
feature is not fully finished.)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ic9fff279f69cf3b7c38a0dc2ff3c970eaa756aa8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the last external user to cbfs_load_and_decompress() gone, we can
stop exporting this function to the rest of coreboot and make it local
to cbfs.c. Also remove a couple of arguments that no longer really make
a difference and fold the stage-specific code for in-place LZ4
decompression into cbfs_prog_stage_load().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I4b459650a28e020c4342a66090f55264fbd26363
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This changes updates the iDisp-Link T-mode to 8T required for ADL-M.
The update is made because the HW on ADL now supports 8T mode.
BUG=None
TEST= build and boot ADL-M RVP and verify HDMI/DP audio playback.
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Change-Id: I9d0bf7dc76348f7e184e8496f042badc30bf3211
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51353
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Configure Power Enable, Reset and Clock GPIO for both camera
2. Use same ASL code as ADL-P RVP
Configure RST, PWR_EN and IMGCLKOUT signals for WFC and UFC
TEST=Build, Boot and Verify streaming in both Camera
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I70636eaa8d9bdf23d649e811b3ff4f33b1bc604e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50265
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config ANX7625 line data end same time on all line.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: Ia1dc217138a98a79ef2f31225b52ba2b1aaf8672
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Just do it already.
The two SCSI-specific options for p2b-{ls,ds} will be wired up in a
followup. They will be ignored by boards without the hardware.
Change-Id: Ia43d502219d7c23d21f49d651113e3d653c6e9f4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These p-suffixed helpers allow dropping pointer casts in call-sites,
which is particularly useful when accessing registers at an offset from
a base address. Move existing helpers in chipset code to arch/mmio.h and
create the rest accordingly.
Change-Id: I36a015456f7b0af1f1bf2fdff9e1ccd1e3b11747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51862
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 023fdaffd1 (mb/asus/p2b: Refactor southbridge ACPI stuff)
moved the southbridge ACPI stuff to its own file. It also
(prematurely) listed PM and SMBus I/O port ranges as a #defined
fixed value.
Since these two ranges are not expected to change at runtime anyway,
we can simply drop the ASL code doing the read.
Change-Id: Id5adb37d047621d7c8faf81607ceea4cbcac3d34
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41093
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Haswell MRC.bin can return zero even when raminit did not complete
successfully. When this happens, the memory controller will not have
acknowledged raminit: the mc_init_done_ack bit in the MC_INIT_STATE_G
register will be zero, and memory accesses will lock up the system.
To handle this situation more gracefully, check the mc_init_done_ack bit
after running MRC. If the bit is not set, log a fatal error and halt.
Tested on Asrock B85M Pro4:
- With badly-seated DIMMs, MRC raminit fails and coreboot dies.
- After reseating the DIMMs, the board still boots successfully.
Change-Id: I144bf827f65cd0be319c44bf3d407ddc116b129d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is locking up the OS. For now this will unblock booting.
BUG=b:183971103
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id2b96eedf38c9038169407418c6d36f13299fb62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51928
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Add definitions to describe GPIOs in generated ACPI objects.
The method allow either write a GpioInt() or Interrupt() descriptor.
Signed-off-by: Seven Lee <wtli@nuvoton.com>
Change-Id: I37fec7b0b9324dbfb61b7a8bea80f45026c54409
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51922
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using brackets here seems to break the build for _some_ environments.
Removing the brackets fixes it and works just fine.
Change-Id: I965b0356337fe74281e7f410fd2bf95c9d96ea93
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Iec9134e226382d32783342ef1d37c6f6f6caeb6e
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: I6c8f17b398fb4645feb830c2ad28ac98fb744280
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The define for color keyboard setting has never been used, as it was
added as a Kconfig selection when ec/system76/ec was introduced.
Change-Id: Ib83d4510c14ddf083660e42175ab093403792cac
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Each TCSS DMA is grouped together with two PCIe RPs in terms of PM flow.
This change ensures that SD3C is updated for the TCSS DMA devices
corresponding to the TBT RP ports. If TBT port is 0 or 1, SD3C for DMA0
is updated, else for DMA1.
BUG=None
TEST=Built Alderlake image successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3462dfbb287a374960a57bb4c3541db2a435611
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51965
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current get panel_id is over sku_id() >> 4, but sku_id is combined with
wfc_id/lcm_id/sku_id, so the panel_id value is wfc_id << 4 | lcm_id()
in fact. When wfc_id is not 0, the panel_id will be wrong. So only get
the low 4 bits for the panel_id.
BUG=b:183779755
BRANCH=kukui
TEST=emerge-kukui
Change-Id: I63e0c8a2719462a9b979afe52a27c78b9fc804e8
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The EDID and initial code are provided by STA (the vendor).
BUG=b:183969078
TEST=Boots on Chromebook Katsu and displayed developer firmware screen
successfully.
Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com>
Change-Id: I54e72c072b47d2be264ed7f0700812a6c704a104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51918
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is a bug acknowledged by Intel (IPS case 00600003) that has been
fixed for SRP but won't be fixed for CPX.
This fixes field offsets for fields that follow SYSTEM_STATUS.RcVersion
Change-Id: I5248734e2f086d39bb75b7b1359e60dfd8704200
Signed-off-by: Deomid "rojer" Ryabkov <rojer9@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
VENDORCODE_ELTAN_MBOOT should not be used when VBOOT is enabled.
Hide VENDOCODE_ELTAN_MBOOT when VBOOT is enabled.
BUG = N/A
TEST = run `make menuconfig` and boot Facebook FBG1701
Change-Id: Iac57103431cc7efac5b6019f180572d255e683ab
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
All known on-chip PCI devices are disabled in the chipset devicetree.
So they are removed from the mainboard devicetree.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Ie67cd8afc9ea92e9fd7caed4338cb25a68d94cb1
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52018
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The romstage does not fit in RO_SECTION.
Increase the CBFS size in RO_SECTION.
BUG = N/A
TEST = Boot Facebook FBG1701 with VBOOT enabled.
Change-Id: I2f1020acb3ec99d4cddbaa05b0998fe32b470d3e
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some functions/macros like assert() require redefinition for testing
purposes. ENV_TEST is introduced to make it possible without using
bypass hacks.
This patch also adds a global __TEST__ define to TEST_CFLAGS for
all test targets in order to enable ENV_TEST.
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ib8f2932902a73a7dbe181adc82cc18437abb48e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Change-Id: I7503dec4e72810db8dfe74f72638b466a3d66748
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48671
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On OCP Tioga Pass the pad GPP_B20 is used as output for signalling "POST
complete" to the BMC. According to the schematics and the code in
`ramstage.c`, the signal is active-low. There is an external pull-up
resistor.
To make the signalling work as it should, set the initial output value
to `high`.
Change-Id: I82fbda1caba9163ba3b2e38f494a0cefa27e657f
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48670
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TPM_INIT depends on VBOOT but should also depend on
VENDORCODE_ELTAN_xBOOT.
Add dependency. TPM_INIT will be enable for measured boot only.
BUG = NA
TEST = Boot Facebook FB1701 with possible combinaties of VBOOT, measured
boot and eltan security.
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I03f8457731c73c653bd82b1042bda3fc2d797feb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
The ERROR() and LOG() macros both used BIOS_ERR as the error level.
The messages generated by the LOG() macro are informational items.
Change to BIOS_INFO to reflect that.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I3827a7d65a9d70045a36fb8db4b2c129e1045122
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The recent refactor of console UART GPIOs to mainboard's bootblock
caused brya boards to lose the first ~5 lines of the logs from
bootblock. Rename bootblock_mainboard_init to
bootblock_mainboard_early_init so that the UART pads will be ready
by the time the console is initialized.
BUG=b:184319828
TEST=First lines from report_platform.c are now seen in UART output
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I4a4fadcc091bf9b1c9894f9afaf42baff63c73a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
The calloc() function is useful in addition to malloc and friends, so
add the obvious definition.
Change-Id: I57a568e323344a97b35014b7b8bec16adc2fd720
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51949
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To pack a struct, the `__packed` attribute must come after the `struct`
keyword. Moreover, unions cannot be packed (structs inside unions can,
though). Correct uses of `__packed` so that EEPROM structs get packed.
Change-Id: I39d2c9ebc370605d5623b134189aa95a074ec7c3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Background story (I think that's what great in opensource -
ppl leave there part of their lives): ;-)
While trying to fix audio jack not working with coreboot and
Windows 10 with some help from hell__ and nico_h on IRC nico_h
discovered that t420 and t430 hda_verb.c are the same:
<nico_h> oddly, in coreboot source T420 and T430 have the same
numbers for very different codecs... I suspect copy-pasta
Difference between /sys/class/sound/cardX/hwCXDY/init_pin_config
in vendor BIOS helped with the updated config. Connecting audio
jack now works flawless both in Linux and Windows.
Audio-related keyboard buttons: volup, voldown, mute works fine
both in Linux (Debian-based) and Windows 10. mutemic button works
(tested ie. with xev) but both in Linux and Windows 10 wont light
up or makes any effect.
+-----------------------------------+
| init_pin_config dump from: |
+----= VENDOR =---+---= coreboot =--+
| 0x19 0x04211040 | 0x19 0x04211040 |
| 0x1a 0x61a19050 | 0x1a 0x61a19050 |
| 0x1b 0x04a11060 | 0x1b 0x04a11060 |
| 0x1c 0x6121401f | 0x1c 0x6121401f |
| 0x1d 0x40f001f0 | 0x1d 0x40f001f0 |
| 0x1e 0x40f001f0 | 0x1e 0x40f001f0 |
| 0x1f 0x90170110 | 0x1f 0x90170110 |
| 0x20 0x40f001f0 | 0x20 0x40f001f0 |
| 0x22 0x40f001f0 | 0x22 0x40f001f0 |
| 0x23 0x90a60170 | 0x23 0x90a60170 |
+-----------------+-----------------+
Tested-by: Piotr Szymaniak
Signed-off-by: Piotr Szymaniak <szarpaj@grubelek.pl>
Change-Id: Ie5eba84e5ea590b7db00e189cd68e714bee7e410
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51612
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The only FSP 1.1 platform with MMA support is Skylake. As it now uses
Kaby Lake FSP 2.0, this code is no longer useful. Drop it.
Change-Id: I819c3152bdea0fdad629793d96136ef134429fbd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
The Intel FSP 2.0 driver contains a custom construct that basically
serves the same purpose as the new CBFS allocator concept: a callback
function to customize placement of a loaded CBFS file whose size is
initially unknown. This patch removes the existing implementation and
replaces it with a CBFS allocator.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I0b7b446a0d2af87ec337fb80ad54f2d404e69668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Right before CB:49334 was submitted, I changed the signature of
cbfs_allocator_t function pointers to include another argument passing
in the already loaded CBFS metadata (to allow for the rare edge case of
allocators needing to read CBFS attributes). This interface is not meant
to be able to modify the passed-in metadata, so to clarify that and
prevent potential errors, we should declare the argument const.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I7e3756490b9ad7ded91268c61797cef36c4118ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable I2C2 in devicetree and fill ACPI information for Codec and
Speaker amplifiers. Pass correct IRQ GPIO for headset jack.
BUG=None
BRANCH=None
TEST=Ensure that the Codec and Speaker Amplifiers are detected in
i2cdetect.
Change-Id: I1ae52a8bbaa0181c906cd14a94de22e0250ed4c1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52046
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure the BT disable GPIO to logic low in order to enable Bluetooth.
Add USB ACPI configuration for BT device.
BUG=b:182201890
TEST=Build and boot to OS.
Change-Id: I647c301e2db6d4a7c5c8cb31cbc47a44cba5e734
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a copy of picasso.
BUG=b:184151560
TEST=Compared with the cezanne PPR.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia4bc40daa971c126c2596837155312d411b91a06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Configure camera power GPIO to high
BUG=b:182207799
TEST=Build and boot to OS then checked camera device existence with lsusb
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: Ie894167e3c4f8efdb3710599c6ff3a9fc975adb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52017
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Initialize all eSPI signals including PCIE_RST0_L early for EC
communication.
- Set PCIE_RST0_L to a GPIO and set it high to release the bus. This is
a temporary workaround until PCIE_RST_L comes up on its own.
- Make sure all GPIO muxes initialized early are re-initialized.
BUG=b:183340503
TEST=Boot Guybrush
Change-Id: I512cb8b435dc8412cd46189e741ad94e5a24699e
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51675
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mancomb does not have a dedicated SCI pin so it uses VW.
BUG=b:182211161
TEST=builds
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Id315ab448209d9c93494f7689361e45f8a6ed001
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
espi_setup already clears most of the controller registers. So this
change consolidates the clear logic into one spot.
This shouldn't result in a behavior change on Picasso. Picasso already
has the eSPI decodes clear on boot, so this change is a nop.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic57689e50febd29796d8ac8d99c81e41fee5b41c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is only ever called after espi_setup.
55861 - AMD System Peripheral Bus Overview also says that io ranges
should be configured before enabling the BUS_MASTER bit.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I074e487d8768a578ee889a125b9948e3aa6c7269
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure I2C rise/fall time in device tree to ensure I2C CLK runs
accurately at I2C_SPEED_FAST (< 400 kHz).
Measured I2C frequency just as below after tuning:
I2C0(touchpad): 385 kHz
I2C4(audio): 380 kHz
BUG=b:180335053
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: Ic92ee0379456e80260a8026bc38ee41325dad6d2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tidy up the interrupt status. This will leave SLAVE0_INT_STS = 0.
BUG=b:183524609
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I950cfb81521e35758c120a482670cfdb924201d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This sets the eSPI registers to the reset values specified in the PPR.
On Cezanne, the PSP modifies these registers such that the eSPI
peripheral cannot send DEFER packets. This causes random bus errors.
These reset values are identical to what is currently used on Zork.
I didn't clear out ESPI_DECODE because it's currently being done by
cb:51749.
BUG=b:183524609
TEST=Boot guybrush to the OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic3a9860747aac78121358b4499d8a38052236c0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52058
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These are defined in the public Picasso PPR - 55570-B1 Rev 3.15.
BUG=b:183524609
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e601f767327e0a24a086146623af039388b2e7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52057
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are forthcoming designs that will be utilizing
a discrete TPM 2.0 solution. Split the existing dedede
configuration options so future mainboard variants can
easily select the appropriate Kconfig option using the
newly introduced options:
- BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50
- BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2
The existing variants all select the former option,
BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50 since all those
designs currently utilize Cr50.
BUG=b:184151664
Change-Id: I2bdb1ca4fd78cc0628256d49678ea042c55f6fba
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52030
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aseda Aboagye <aaboagye@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP v2081 has a bug where it uses the information about south XHCI
ports to enable TCSS XHCI ports. This change works around this bug by
enabling south XHCI ports 1 and 2 in brya baseboard devicetree. brya0
already enables south XHCI port 1 in overridetree.cb, however, it is
still enabled in baseboard/devicetree in case more variants are added
to brya before FSP is fixed.
BUG=b:184324979
TEST=Verified that TCSS XHCI ports 1 and 2 are now enabled.
Change-Id: I4b86a98b18234ba309ddf2f30b80d78472951637
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: If585b6044f58b1e5397457f3bfa906aafc7f9297
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52072
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no good reason to use values smaller than 2 GiB here. Well, it
increases available DRAM in 32-bit space. However, as this is a 64-bit
platform, it's highly unlikely that 32-bit limitations would cause any
issues anymore. It's more likely to have the allocator give up because
memory-mapped resources in 32-bit space don't fit within the specified
MMIO size, which can easily occur when using a discrete graphics card.
Change-Id: I6cdce5f56bc94cca7065ee3e38af60d1de66e45c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52070
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `pdwm` part was supposed to be an abbreviation of `power down`, but
it is neither self-explanatory nor properly-spelled. Rename the enum.
Change-Id: I7b83c71d4534b62e18ced04eebe6a65089e1d874
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These definitions are unused and not particularly useful. Drop them.
Change-Id: I40a824888701870b6713c1a16ab671c19b3770ae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51900
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the actual value as it is more informative.
Change-Id: Id3bd8ccdf79d1e3fdf97cda049f81271bb017ef7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Drop unnecessary typedefs and rename DDR4-specific definitions to avoid
name clashes, as done for DDR3 in earlier commits. This allows including
and using both DDR3 and DDR4 headers in the same compilation unit.
Change-Id: I17f1cd88f83251ec23e9783a617f4d2ed41b07f0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51898
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid name clashes with definitions for other DRAM generations,
rename the enum type and values to contain `ddr3` or `DDR3`.
Change-Id: If3710149ba94b94ed14f03e32f5e1533b4bc25c8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51896
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These typedefs are not necessary. Remove them, and rename some elements
to avoid any confusion with other DRAM generations, such as DDR4.
Change-Id: Ibe40f33372358262c540e371f7866b06a4ac842a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51895
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Cezanne PSP configures the eSPI with the assumption that it's a
majolica, setting up both the serial port and the majolica EC IO decode
ranges. Since guybrush is NOT a majolica, this doesn't work very well
there. Clearing the decode ranges allows the guybrush platform to set
the decode ranges needed for its EC.
BUG=b:183524609
TEST=Set up eSPI on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I77cfb948cb9ae6d1cf001bd9e66cede8d93f50b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously, the eSPI code would only add to existing decode ranges, and
there wasn't any way to clear ranges. This clears all the ranges so
the eSPI configuration can start fresh.
BUG=b:183207262, b:183974365
TEST=Verify on Guybrush
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic4e67c40d34915505bdd5b431a064d2c7b6bbc70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The sizeof() operator was being applied to a pointer-to-struct type.
Correct this, so that the entire struct space gets cleared.
Change-Id: Ieab3aaa2d07a928f27004b94132377d5dae935c0
Found-by: Coverity CID 1451732
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52054
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These used to be printed before CB:46605. Having them in the logs can be
a huge timesaver when debugging logs sent to you by other people
(especially from systems that don't boot all the way). Let's add them
back.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ifdbfdd29d25a0937c27113ace776f7aec231a57d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52011
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
These files were just renamed to put `adlrvp` in between `vbt`
and the memory technology type.
Change-Id: Icefbac462d0ec9c660541e9cf44686d6dcf82dfd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52032
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=None
TEST=Build and boot to OS in Guybrush. Ensure that the EC Software Sync
is complete.
Change-Id: Id8655b6f805e14ce3cb71777c1cc175f45841fcc
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Ideally we would like to perform EC Software Sync in payload. But with
the hardware requirement (EC_IN_RW) and firmware requirement (TPM
command to get EC execution environment) not met yet, adding the support
to perform early EC Software sync. With EFS2 enabled, this will also
help cr50 to set the boot mode as NORMAL instead of NO_BOOT.
BUG=None
TEST=Build and Boot to OS in Guybrush. Ensure that the EC software sync
is successfully complete.
CBFS: Found 'ecrw.hash' @0x50400 size 0x20 in mcache @0x020171ec
VB2:check_ec_hash() Hexp RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:check_ec_hash() Hmir: 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
<snip>
VB2:check_ec_hash() Heff RW(active): 2dd8dbb78d0c626358a626037973a3d81982f88f3f38e7f759039bf84e05ccc6
VB2:sync_ec() select_rw=RW(active)
Change-Id: I820e651c6b22a833fef6f17a4ceb5a8cfb6f1616
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Enable Touchpad by configuring the enable GPIO to logic high. Add
touchpad configuration for ELAN touchpad.
BUG=b:182207444
TEST=Build and boot to OS in Guybrush. Ensure that the trackpad events
are detected using evtest.
Change-Id: Ib47fbb33f2b181eb85f6ded98a5b0ce08fbc7b64
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51962
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change disables touchpad interrupt, as it sends spurious wake signal
via GPP_F14 and immediately wakes the system from S3. It happens because
touchpad's power is gated by deassertion of PLTRST#. The behaviour for
S0ix is unchanged.
BUG=183738135
TEST=manually
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: Ia7d282f38d205a94cc43eaa1832729f4606437c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51831
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change exposes the PCH_INT_ODL line in GPP_F17 as interrupt resource for
CREC device
BUG=none
TEST=manual test
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I0c05160cb7894b5f7beee93a0c93776f973eae56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
PCH_INT_ODL (GPP_F17) is used to wake AP from S3, however it was configured
to reset state on PLT reset assertion. This change reconfigures the pad
using DEEP instead of PLTRST to retain pad configuration across S3.
BUG=b:178545523
TEST=manual: verified that asserting PCH_INT_ODL wakes system and the wake
source is GPP_F17
Signed-off-by: Boris Mittelberg <bmbm@google.com>
Change-Id: I8df5dafedabc7b6af74c39621f0e1eb7019a9a17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reference code does an and-or operation with zero as or-value, reading
and writing to the same address. The accessed register is 32-bit, and
reference code programs bits 22, 21, 20, 16 to zero. However, coreboot
code reads the value from bits 7..0 instead. Correct this.
Change-Id: I33bf268449c2f799321be81a02bbccff855ee1fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no "volume" defined in cmos.layout now, so removing "volume="
from cmos.default, otherwise building will fail with
CONFIG_USE_OPTION_TABLE set.
Change-Id: I1d6bb68fb927882ddcc052b432bb34b42c58eac7
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Iru Cai (vimacs) <mytbk920423@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We've mostly stopped using Trogdor-rev0 now and are starting to bring up
rev2 instead. Therefore, the default revisions this builds for should be
the newer ones.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ie433ebb2a03fb1636b5012b4a0567ba6f982579d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52007
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The is used for AMD Grunt board which uses ALC5682 and MAX98357 codec.
kernel driver will need to retrieve MISC FCH memory resource for CLK
enabling per different CID/HID.
BUG=b:171755306
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I5f29a2d784a9fc749fff61a9c96c0a487b71a2d7
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51659
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Acoustic noise mitigation for lantis and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:183561593
BRANCH=dedede
TEST=EE verify acoustic noise test passes.
Change-Id: I5e5f24ed934910726c220678068d085b6ee2bcf6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51762
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed so we write the correct resource into the ACPI tables.
BUG=b:183737011
TEST=Boot OS and see GPIO devices working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2ba4349e0ed500912db40aa6ef9b649046f4358f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51961
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the cr50 on guybrush to show up in ACPI.
BUG=b:183737011
TEST=Boot OS and see I2C devices initialized
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifb5679b7bbefbf753217981874bb1bdaef35f6db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51958
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Needed so get_lid_switch will actually call the EC. Otherwise it
returns -1.
BUG=b:183524609
TEST=Depthcharge no longer halts complaining that coreboot didn't sample
the pin
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4639b3713d726192e251dcffa14381dd92518fa2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
It looks like we are having SI issues on eSPI at 33 MHz. Switching to 16
MHz makes everything a lot more stable.
BUG=b:183524609
TEST=Boot to OS and run `ectool version` 1000 times and see no problems.
Before with 33 MHz there was an error every few cycles.
declare -i i=0; while ectool version; do i+=1; echo "$i"; sleep .11; done; echo "Finished: $i"
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6ab515629703a157c1d1ac6adcf5cf379e80f8ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51953
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
pci_rom_ssdt reloads the oprom from cbfs. It then places it into cbmem
and writes the offsets as the ROM ACPI node. The GOP driver modifies the
VBIOS so we don't want to reread from cbfs. When using GOP we also pass
the offsets with the VFCT table.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iaf53e750564f1f0e115cd354790da62e672d74b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The coordtype parameter of acpigen_write_CSD_package expects a CSD_coord
enum value, but HW_ALL that got passed as parameter is a PSD_coord enum
value, so replace that with the correct CSD_HW_ALL enum value.
TEST=Timeless build results in identical binary for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: I90b19345b8dc6d386b6acfa81c6c072dcd6981ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This replays the changes made in commit 9b1f3cc6fb (cbfs: Pull
handling of the CBFS_CACHE mem_pool into CBFS core) for the latest
work on the BeagleBone port. I hope it's the right thing to do.
Fixes: Makes `master` compile again.
Change-Id: Ia51c66dbe425a662ea2a6b2527b2b6982f587891
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51943
Reviewed-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Causing the AOAC register access as part of system suspend (S3) causes
the suspend procedure to be stuck. Comment it for now to unblock
entering S3 and collecting the power numbers.
BUG=b:181766974
TEST=Build and boot to OS in Majolica. Enter S3 through "echo mem >
/sys/power/state".
Change-Id: Ie93bbe393b209b784b9a2257f3916b29d84b25d1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51926
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCR algorithms used for vboot are frequently causing confusion (e.g.
see CB:35645) because depending on the circumstances sometimes a
(zero-extended) SHA1 value is interpreted as a SHA256, and sometimes a
SHA256 is interpreted as a SHA1. We can't really "fix" anything here
because the resulting digests are hardcoded in many generations of
Chromebooks, but we can document and isolate it better to reduce
confusion. This patch adds an explanatory comment and fixes both
algorithms and size passed into the lower-level TPM APIs to their actual
values (whereas it previously still relied on the TPM 1.2 TSS not
checking the algorithm type, and the TPM 2.0 TSS only using the size
value for the TCPA log and not the actual TPM operation).
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib0b6ecb8c7e9a405ae966f1049158f1d3820f7e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Pronin <apronin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To generate a working BPM, boot policy manifest for Intel CBnT the
tool that generates it, requires ACPI base and PCH PWRM base as input.
Therefore make it a Kconfig symbol, that can be used in Makefile.inc.
Change-Id: I6f1f9b53e34114682bd3258753f2d5aada9a530d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51805
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This add an option to generate BPM using the 9elements bg-prov tool
using a json config file.
A template for the json config file can be obtained via
"bg-prov template".
Another option is to extract it from a working configuration:
"bg-prov read-config".
The option to just include a provided BPM binary is kept.
Change-Id: I38808ca56953b80bac36bd186932d6286a79bebe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50411
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is useful if you have external infrastructure to sign KM.
Change-Id: If5e9306366230b75d97e4e1fb271bcd7615abd5f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51572
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Maps the useable RAM so that it can be used for booting a payload.
TEST: Booted a simple ELF payload (that just flashes LEDs) on the
Beaglebone Black.
Change-Id: I7f657c97e4753071c90ba8ca800a96108807e6b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44388
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds initialisation of 512MB of DDR memory on the BBB to the romstage.
The parameters for the DDR peripherals are taken from U-Boot.
TEST: Booted from romstage into ramstage. Also successfully managed to
run the "ram_check" in lib.h.
Change-Id: I692bfd913c8217a78d073d19c5344c9bb40722a8
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adds code taken and (barely) adapted from U-Boot (release 2020.04,
commit 36fec02b1f90b92cf51ec531564f9284eae27ab4) for SDRAM initialization.
This should in theory work for other configurations than the Beaglebone
Black's DRAM configuration, but hasn't been tested.
Change-Id: Ib1bc2fa606f7010c8c789aa7a5c37cd41bc484b9
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44386
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds a "sd_media" boot_device to allow booting from the SD card. This
assumes that the generated "MLO" file is placed at a 128KB offset from
the start of the SD card, to allow for the MBR etc. to be at the start
of the SD card. Placing the MLO file here allows the AM335x boot ROM to
load and execute the bootblock stage as well, as 128KB is one of the
offsets the boot ROM checks when looking for the next stage to execute.
As part of this, a FMD for the Beaglebone has also been defined. It's
sized at 32M somewhat arbitrarily, as SD cards could allow for much
bigger payloads.
TEST: Beaglebone boots from bootblock into romstage. Romstage to
ramstage still doesn't work as it needs RAM initialization first.
Change-Id: I5f6901217fb974808e84aeb679af2f47eeae30fd
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44385
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds a driver for the am335x MMC peripheral. This has only been tested
with SD cards and probably needs some modification to use eMMC or MMC
cards.
It's also currently a little slow as it only supports reading a block at
a time.
Change-Id: I5c2b250782cddca17aa46cc8222b9aebef505fb2
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the format warning below by using `PRIxPTR`, which is defined as
unsigned long.
src/soc/amd/common/block/smbus/smbus.c:33:56: error: format specifies type 'size_t' (aka 'unsigned int') but the argument has type 'uintptr_t' (aka 'unsigned long') [-Werror,-Wformat]
printk(BIOS_ERR, "Invalid SMBus or ASF base %#zx\n", mmio);
~~~~ ^~~~
%#lx
src/include/console/console.h:60:61: note: expanded from macro 'printk'
#define printk(LEVEL, fmt, args...) do_printk(LEVEL, fmt, ##args)
~~~ ^~~~
1 error generated.
Change-Id: I727c490d3097dcf36cdbcd4db2852cd49d11785f
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
At the end of the built, the line below is printed.
coreboot has been built without an the Microchip EC FW.
Remove *an*, as one article is enough.
Change-Id: I28b24f0f2dade17e30e16cc6d935976e331a7a97
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1f7f5879ac318372042ff703ebbe584ce1c32c91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Move the parts of romstage.c that populate the UPD-M data structure to
the newly created fsp_m_params.c file. Since
platform_fsp_memory_init_params_cb gets called from the FSP driver and
not directly from car_stage_entry the two code parts in romstage.c
weren't directly interacting. Since soc/romstage.h only contains the
mainboard_updm_update function prototype, rename it to soc/fsp.h. This
patch also removes a few unused includes.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I52c21f13520dbdfab37587d17b3a8a3b1a780f36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This file populates the UPD-S data structure that gets passed to the
FSP-S, so add that s part to make it a bit clearer which FSP parameters
it'll set up. This is also a preparation to add a fsp_m_params.c file in
the following patches.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53786df0909055e66eac675b5580909b7960944f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Now that we have the DISABLE_KEYBOARD_RESET_PIN Kconfig option, select
it and remove the temporary workaround that was implemented in the
mainboard code in commit 39ef890336.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I634d11290dad8c93f10979f06243b1bf84737ae2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The KBRST_L pin will cause a reset when driven or pulled low even when
the GPIO mux is set to GPIO and not native function. So when you want to
use that pin as general purpose output the keyboard reset input
functionality needs to be disabled by selecting this option in the
board's Kconfig file to avoid causing a reset by writing a 0 to the
output level bit when it's configured as an output.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: I517ad551db9321f26afdba15d97ddb61be1f7d51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
TEST=Build guybrush and verified with the PPR that the register and bits
are still the same
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0619f84cf82cbb90ded9dfd58afa6acc9520fb8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TEST=Verified that this register and the defined bits exist in Cezanne,
Picasso, Stoneyridge, Bolton and SB800.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32d1d577b05edab006981516a5aefd822e7b984a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reference code does a 32-bit write, and the values don't fit in 16 bits.
Change-Id: I1195c0637b5c215a45328ebae312cf620cd4c950
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51860
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reference code uses the `0x06` as an or-mask, which makes more sense.
Change-Id: I04e5262d9ab36ae866fccd90255e4a0f85328e85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51859
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While the macro value is the same, the DMIBAR register is not HTBONUS1.
Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical.
Change-Id: I5025f115f5a55dc782092989f3d158802d1d9353
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51858
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 56823f53dc (nb/intel/ironlake:
Rewrite early QPI init) rewrote this part, but the or-value is missing
one zero. Correct this magic value to align with MRC binaries.
Change-Id: Id7a6766b3f0fe415dea70cbc54afc30f808c8b16
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51857
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was copied from Sandy Bridge and does not apply to Ironlake. These
offsets go past the MCHBAR window (MCHBAR size is 16 KiB on Ironlake).
Some of these writes would have collided with `DEFAULT_HECIBAR` if the
PCI resource had been reported as fixed. Remove the copy-pasted code.
Change-Id: I7688921ad7517cbd68a0c48262b29ecf7b4c396c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51856
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While 64-bit writes seem to work properly, there could be unknown
side-effects in some cases, e.g. when running in long mode. Since
reference code uses two 32-bit writes, follow suit.
Change-Id: I48ed3d94c7865b3a3cce52108e99cf1656b57fc2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51855
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Thermal sensor2 defined in baseboard do not exist in boten.
With the format the DPTF policies are defined in boten, all the entries
from the baseboard are included and then the overrides applied.
This causes the non-existent DPTF devices to be exported in the ACPI table
and in turn OS reading invalid temperatures. Fix the format for
DPTF passive and critical policies.
BUG=None
BRANCH=dedede
TEST=Build and boot to OS in boten. Ensure that the DPTF entries look
correct in both static.c and SSDT tables i.e. passive and critical
policies for applicable devices only are present.
Change-Id: I63c781e0a439f1e7a3525fa7cf290fa9300cb066
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:182753072
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I43c104ef912aafecadf9497f9ea20c8478c0e920
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add processor power limits control support to configure values for
alderlake soc based platforms.
BRANCH=None
BUG=None
TEST=Build and test on alderlake rvp board
Change-Id: I9dc37c7a43e6bd6f1ff5e8a97e22a0c7ac421802
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On production boards, the touchpad interrupt line was moved
from GPP_B20 to GPP_B3. Fix the GPIO pad config and devicetree entry,
and update documentation to remove touchpad config issue.
Change-Id: Iaefeba8f78c567b67e7a416c27299bff574c23ab
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51797
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gpio_get_index_in_group function returns the index of the GPIO
within its own group
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7f6b312bd1d0388ef799cd127c88b17bad6a3886
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
REG_BASE_SIZE is supposed to represent the size of the REGBAR MMIO space
in KiB. It is currently sized at 4MiB, but this is incorrect, EDS Vol. 2
indicates REGBAR is 16MiB in size, therefore update the constant to
reflect this.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0cfbe5b8bb07faa854efd4bf70640daa117f2bb2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This name isn't very meaningful, rename the config option to
ENABLE_TCSS_DISPLAY_DETECTION to make its meaning more obvious.
Change-Id: Ib21a3b5a37d25f93bd515f8c6e5ad39c9d2ea1c4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51771
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Type-C subsystem ("TCSS") IP block is similar between TGL and
ADL. For pre-boot purposes, the limited amount of functionality required
appears to be common between the two, therefore move the functionality
to intel/common/block and rename from `early_tcss to `tcss` along the way.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I1c6bb9c7098691f0c828f9d5ab4bd522515ae966
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51753
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a pin configuration macro that supports both switching a
pin to its native function and configuring it as a SCI source. This is a
preparation to remove the GPIO2 soc_gpio_hook.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If0da5c010f35fd902f6b8857368daec93c12394a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50373
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Caroline has a Wacom W9013 digitizer on I2C2, which was
incorrectly disabled in commit d957d12e6
[mb/google/glados: clean up variant devicetrees]
as part of preparation for converting to overridetree format.
Test: build/boot, verify digitizer now available under Linux
Change-Id: I234bc0126b5d13c22a663d6544382890b312ce63
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Add correct board Id for ADL-M LP5 configuration
2. Add spd hex files for LP5 Micron part
3. Update memory.c file with correct Dq-dqs and byte mapping for LP5
BUG=None
BRANCH=None
TEST=Build is successful for ADL-M RVP
Change-Id: I0bbd3f5b56bf7fbe918cc599d32a01dcae896ddd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
List of changes:
1. Add separate file for ADL-M GPIOs
2. Configure GPIOs as per the schematics of ADL-M RVP
TEST=Able to build ADL-M
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com>
Change-Id: I03a532f69f42db723b976a0f7b0acf6f4b98e354
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST=Verified build for Shadowmountain
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2ebf4da1b8c1df2e9c43b6e3bb688a9f8db652d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51496
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
During the initial phases, the development and validation teams have to
deal with both Consumer SKU and Lite SKU firmware. Having the support for
CSE Lite enabled by default in coreboot helps in integrating both the SKUs.
With this we only have to interchange the CSE region in the full BIOS image
without having to worry about Kconfigs. Eases the build and integration
flow.
TEST= Built and booted on ADL-P LP4 RVP
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ia92c7b71c69a23104ace9fc53fd39f01120fa751
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51567
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support zinitix touchpad for sasuke.
BRANCH=dedede
BUG=None
TEST=built and checked touchpad worked on sasuke
Change-Id: I85794311c49e33c4683482e125bea5ca2dbacfa8
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an option to generate the Key Manifest from Kconfig options.
Change-Id: I3a448f37c81148625c7879dcb64da4d517567067
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50410
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This add an option to generate KM using the 9elements bg-prov tool
using a json config file.
The option to just include a provided KM binary is kept.
A template for the json config file can be obtained via
"bg-prov template".
Another option is to extract it from a working configuration:
"bg-prov read-config".
Change-Id: I18bbdd13047be634b8ee280a6b902096a65836e4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50409
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Private and/or public keys will be provided as user input via Kconfig.
As a private key also contains the public key, only ask what is required.
Change-Id: I86d129bb1d13d833a26281defad2a1cb5bf86595
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
ANX7625 requires customized hs_da_trail time.
So override the data trail for ANX7625.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I620035363507daaa19e3c272a44059c17be29af1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org>
There's no need to use a fixed-width type here.
Change-Id: I727c64661990040db356c5508fecc0a65960c095
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51794
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The correct printf format specifier for an `unsigned int` is `%u`.
Change-Id: Iaf780eb366f8c3493b89beb9a5643fa285e7825d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51793
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to write the GDCRTRAININGRESULT registers after raminit.
Change-Id: If604920fe7a3bee96f72f8aff5e96f0e25548f18
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50534
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ANX7625 requires the line packets to end at the same time.
Otherwise, the display will be shifted.
BUG=b:173603645
BRANCH=kukui
TEST=Display is normal on Jacuzzi
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I5949de1a9a1947fa188233787166a478b1de68b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch allows overriding GPIO PM miscconfig register for each
GPIO community to avoid dynamic clock gating.
TEST=Dump GPIO Community MISCCFG register to ensure all Bit [7:0]
are set to '0'.
Change-Id: I9aca9cb0641e2731c028ea5ed76c563da3400b74
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Lists of changes:
1. Rename MISCCFG_ENABLE_GPIO_PM_CONFIG -> MISCCFG_GPIO_PM_CONFIG_BITS
2. Move MISCCFG_GPIO_PM_CONFIG_BITS definition from intelblock/gpio.h to
soc/gpio.h. Refer to detailed description below to understand the
motivation behind this change.
An advanced GPIO PM capabilities has been introduced since CNP PCH,
refer to 'include/intelblock/gpio.h' for detailed GPIO PM bit definitions.
Now with TGP PCH, additional bits are defined in the MISCCFG register
for GPIO PM control. This results in different SoCs supporting
different number of bits. The bits defined in earlier platforms
(CNL, CML, ICL) are present on TGL, JSL and ADL too. Hence, refactor the
common GPIO code to keep the bit definitions in intelblock/gpio.h, but
the definition of MISCCFG_GPIO_PM_CONFIG_BITS is moved to soc/gpio.h so
that each SoC can provide this as per hardware support.
TEST=On ADL, TGL and JSL platform.
Without this CL :
GPIO COMM 0 MISCCFG:0xC0 (Bit 6 and 7 enable)
With this CL :
GPIO COMM 0 MISCCFG: 0x00 (Bit 6 and 7 disable)
Change-Id: Ie027cbd7b99b39752941384339a34f8995c10c94
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
List of changes:
1. Update GPIO Group to GPE DWx assignment encoding as per MISCCFG
register per GPIO Community.
2. PMC_GPP_* macros are also updated as per GPIO_CFG register
in PMC space.
BUG=b:183464235
TEST=Able to fix the TPM IRQ issue on SM.
Change-Id: Id9f57b0b5726315f5ebba013f11d52ed3ee34484
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51789
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the PCH PCI device defines out of the SOC specific PCI defines
and into a common include. The PCH is common and doesn't need
duplicate definitions.
Change-Id: I1ca931e0f01e03c67f8f65ed7fd33c2c1d22183d
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch disables the unsued CPU PCIe RP for shadowmountain.
TEST= Boot shadowmountain and verify the device is disabled.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ide2badb06178fca8ff5cf51d8573a14635e190cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51772
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, we used to stitch extra VBT files to ADLRVP build using
Makefile. With enablement of emerge build, we should be able to
integrate more than 1 VBT binaries using ebuild.
This removing these lines to avoid compilation issues in emerge builds
BUG=None
BRANCH=None
TEST=Check if compilation passes on emerge build. Stitched additional
VBT files using emerge and checked that coreboot picks up correct VBT.
Change-Id: I69f1cc6c07415515ff85180fdd7cc5de11b4d805
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Add function to allow overriding the RcompResistor and
RcompTarget UPDs from mainboard if required.
Mainboard users can pass required rcomp from memory.c file.
Refactor ddr_config structure to take out rcomp related variable
outside for all memory type to override if required.
BUG=b:182772421
TEST=Able to override the default RcompResistor and RcompTarget
values.
Change-Id: Ie8528bbf0517728534d47f9adaabfc9a2c469609
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
List of changes:
1. Alder Lake MRC is expecting a RcompResistor value of word width.
Reference RCOMP resistors on motherboard are ~ 100 Ohms but coreboot
is passing an array of RcompResistor which is not completely in use.
Note: Rcomp resistor value represents rcomp resistor attached to
the DDR_COMP pins on the SoC.
2. Also, remove usage of '&' with memcpy the required value into
RcompTarget array.
3. Also, update RcompResistor value for ADLRVP.
BUG=b:183341229
TEST=Enable FSP debug log to verify the override value for
RcompResistor is reflecting correctly.
Change-Id: I69c7cec55b65036fc039c33374a3fd363ef7004e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
MEC1701 can be accessed by IO port 2E/2F
Change-Id: I31f1b147476ec487e64f3c30b3cf514b45ced416
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Set default USB2 HS disconnect threshold to maximum to avoid false
disconnects that eventually lock up the xHCI controller
BUG=b:174538960
TEST=suspend_stress_test -c 50 on vilboz and morphius.
Sample set of USB2 HS devices connect and disconnect
successfully
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: Ic921d850a0bdd717a2a7e50e9e6f65e39e0607bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51265
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 4f87ae1d4a introduced a regression
in the I2C initialization resulting in soc_i2c_misc_init never getting
called, since the continue statement was indented like it belonged to
the if above, but due to the missing curly braces it was outside the if
block.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Found-by: Coverity CID 1451395, 1451387
Change-Id: Id1f17ad59cba44e96881f5511df303ae90841ab3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51786
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous "PCIe port" numbering was incorrect and resulted in several
PCIe devices failing to enumerate. With lane reversal, these numbers are
all backwards. This explains the confusing mapping of Clock Source #1 to
Root Port #9 in https://review.coreboot.org/c/coreboot/+/50101. We were
confusing "Root Port" vs "PCIe Lane".
This change addresses the port vs. lane confusion in the device tree
configurations. It also adds more detailed documentation to a future
reader (i.e., me) to avoid this blunder.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I47edf0b0af1bdcf86b89f17ad2a1f128ef9e9f7a
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
After revisiting the genesis GPIO table and schematics for EVT closure,
I discovered several missing and/or incorrectly documented GPIO pin
mappings.
Now the GPIO pin names and functions should match what's written in the
latest schematics.
BUG=b:181633452,b:181635072,b:177752570
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: I73e6733bce761b00717091834c7a49e85154f80b
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51677
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both EHCI and xHCI USB controllers are inside the PCH (southbridge).
Now that mainboard USB configuration no longer depends on pei_data.h
definitions, the API declarations can be placed in southbridge code.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: Ia21991b225482b33c5bc0dc52884674d301b28ba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
With this change, only raminit.c uses pei_data.h definitions. With MRC
cornered, making it optional is just a matter of writing a replacement.
USB config definitions will be moved to Lynx Point code in a follow-up.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4bc405213e9b0828d9ced18677335533c7dd381d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/collis/memory/ src/mainboard/google/volteer/variants/collis/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:182227204
TEST=emerge-volteer coreboot
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I773c65c0b6d5e868572530305ab8a61a0dd1532d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. H9HCNNNBKMMLXR-NEE
2. MT53E512M32D2NP-046 WT:F
3. K4U6E3S4AA-MGCR
BUG=b:183057749
BRANCH=dedede
TEST=Build the cret board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iacfdd9a27f126ba4b97d1a6493bcc09bb31454a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51619
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port settings.
USB2 [0]: USB Type C Port 0
USB2 [1]: None
USB2 [2]: USB Type A Port 0
USB2 [3]: LTE
USB2 [4]: None
USB2 [5]: Camera UFC
USB2 [6]: Camera WFC
USB2 [7]: Integrated Bluetooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: None
USB3 [2]: USB Type A Port 0 (M/B side)
USB3 [3]: LTE
BUG=b:182973703
BRANCH=dedede
TEST=Build the coreboot image.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I80447d6ac3422f858a9022f550b4f42353819405
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add a helper bit mask to enable wake from either S0i3 or S3.
BUG=None
TEST=Build the Guyrbush mainboard.
Change-Id: I934abad78135260081a61aee4c496b362e483de1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The 'device pci 00.0 on end' entries are not necessary for socketed
devices unless a chip driver needs to be bound to a device, so remove
them from the devicetree. Also remove the `drivers/wifi/generic` chip
driver as it was not necessary either.
Change-Id: Id5f2e34d98b236f9cfac9f0afd8a8017e349603f
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This change allows guybrush EC communication while other patches
in the SOC code are worked on.
BUG=b:183149183
TEST=Boot guybrush with EC comunication
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: I56fb64d4c065cf0665025346218cc66d77dacb52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51665
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO129 is muxed with KBRST, so setting GPIO129 to low causes reset
when KBRSTEN is set to 1. Since reset value of KBRSTEN is 1 we need a
logic to clear it.
BUG=b:183340503
TEST=build
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I194e8432a14d6105f6bcf12111647f5aad4e2de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Modify power sequence of touchpad to meet the definition in the spec.
BUG=b:178353432
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by EE team.
Change-Id: I8b8e383223d017223c36044efdf21738fe26d2ea
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51514
Reviewed-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes an issue introduced in
commit ad0116c032
cpu/x86/smm_loaderv2: Remove unused variables
It removed one variable that was needed to set the SMM start address
that is used to set the SMM stack location.
Change-Id: Iddf9f204db54f0d97a90bb423b65db2f7625217f
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51721
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The HD Audio spec states that the STATESTS register is 16 bits wide.
Change-Id: If7859ed33e58d907a91c4ac8675892e37998cf41
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The timeout is never reached when the codec is functioning properly.
Using a small timeout value can result in spurious errors with some
codecs, e.g. a codec that is slow to respond but operates correctly.
When a codec is non-operative, the timeout is only reached once per
verb table, thus the impact on booting time is relatively small. So,
use a reasonably long enough timeout to cover all possible cases.
Remove the unconditional 25 µs delay and increase the timeout delay.
The new value of 1 ms is the maximum of all existing implementations.
Currently, the only boards using this code are AMD reference boards:
- AMD Bilby
- AMD Mandolin
- AMD Padmelon
Change-Id: Ia5e4829d404dcecdb9e7a377e896a319cb38531a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested with TianoCore payload (UefiPayloadPkg).
Working:
- PS/2 keyboard, touchpad
- Both DIMM slots
- Both NVMe ports
- SATA port
- All USB ports
- Webcam
- Ethernet
- Integrated graphics using Intel GOP driver
- Internal microphone
- Internal speakers
- S3 suspend/resume
- Flashing with flashrom
- Booting to Ubuntu Linux 20.10 and Windows 10
Not working:
- Discrete/Hybrid graphics
This requires a new driver to work correctly, which will be added and
enabled later.
Change-Id: I10667fa26ac7c4b8eb67da11f3e963062bd0db47
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47822
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables CnviBtAudioOffload. FSP is invoked to configure
BT over USB and BT I2S pins for cAVS connection.
BUG=None
TEST=Verified BT offload working on ADL RVP
Signed-off-by: Usha P <usha.p@intel.corp-partner.google.com>
Change-Id: I1185a6c2295bae7d469be4da86502506adbeb8cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51032
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use the MRC cache API for asurada, and sync dramc_param.h with dram
blob (CL:*3674585). With this change, the checksum, originally stored in
flash, is replaced with a hash in TPM. In addition, in recovery boot,
full calibration will always ne performed, and the cached calibration
data will be cleared from flash.
This change increases ROMSTAGE size from 236K to 264K. Most of the
increase is caused by TPM-related functions.
Add new API mtk_dram_init() to emi.h, so that 'dramc_parameter' can be
moved to soc folder.
With this CL, there is no significant change in boot time. Normal AP
reboot time (fast calibration) is consistently 0.98s as before, so
this change should not affect the result of platform_BootPerf.
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots with both full and fast calibration
BRANCH=none
Cq-Depend: chrome-internal:3674585, chrome-internal:3704751
Change-Id: Ief942048ce530433a57e8205d3a68ad56235b427
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Enlarge ROMSTAGE from 256K to 272K for the upcoming change of MRC cache
(CB:51620). To have more compact space usage, reduce BOOTBLOCK size from
64K to 60K (only 44K needed), and move starting address of DRAM blob
(DRAM_INIT_CODE) to 0x210000 (64K-aligned).
BUG=b:170687062
TEST=emerge-asurada coreboot
TEST=Hayato boots
BRANCH=asurada
Cq-Depend: chrome-internal:3704751
Change-Id: I7aaf9faf048e0adcb3a7d856d40891762c9a6604
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch makes all Octopus variants resume from S0ix/S3 on AC plug
and unplug.
Change-Id: Iab054d77368bf2047b6d523188b8c401a7643aaa
Signed-off-by: Derek Basehore <dbasehore@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51654
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The headers added are generated as per FSP v2081_02.
Previous FSP version was v2081_02.
Changes Include:
- Adjust UPD Offset in FspmUpd.h and FspsUpd.h
- Add UPDs in Fsps.h and Fspm.h
BUG=b:180918805
BRANCH=None
TEST=Build and boot ADLRVP
Change-Id: I69611de8286a570c59a6b4a44b9164384e9be81f
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51632
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This makes the EM100 option visible in Kconfig that makes sure that the
SPI settings that coreboot applies are valid for the EM100 that has some
limitations on the maximum SPI frequency and possibly on the supported
SPI modes. For the PSP SPI settings, the mainboard still might need to
provide EM100-specific settings for EFS_SPI_READ_MODE, EFS_SPI_SPEED and
EFS_SPI_MICRON_FLAG. Haven't checked if those PSP settings are correctly
integrated for Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5dec9ce69628ca3623b5009d47f4b3dc020a3dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add a pad configuration macro to support configuring both wake and
debounce. This support is required by Pen Detect GPIO.
BUG=b:180539900
TEST=Build Guybrush mainboard.
Change-Id: I3343a4e80fd5aa3047d76ff9f91ea57c3763bbca
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are at most 14 USB2 ports and 6 USB3 ports on LynxPoint-H, and
there are at most 10 USB2 ports and 4 USB3 ports on LynxPoint-LP. Limit
the array lengths accordingly to cause build errors on invalid configs.
Change-Id: Ieda7a1320d78dbbcb651f1715a87cd1d202a79f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51451
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For disabled USB ports, the length setting does not matter. In future
commits, disabled USB ports will end up with length field set to zero.
Change-Id: I7613e1b0c89c0b58eca790ca14fcd1633c8a93af
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
It's common to use the raw, unshifted I2C address in coreboot. Adapt
mainboards accordingly and perform the shift in MRC glue code.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I4e4978772744ea27f4c5a88def60a8ded66520e1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51458
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reorganize romstage.c to resemble sandybridge, and move everything that
needs `pei_data` into raminit.c function `perform_raminit`. Barring USB
settings, coreboot code no longer depends on pei_data.h definitions. It
still depends on MRC, though. For now.
Tested on Asrock B85M Pro4, still boots and still resumes from S3.
Change-Id: I433f88db5fe7a7533ab6837015647ec31fb45e88
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51449
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
eDP panel flicker during system idle state is observed.
Disabling USB2 SUS well power gating can remove flicker symptom.
Please refer to doc#634894 for more details.
BUG=b:182323059
BRANCH=None
TEST=Boot and confirm no display flicker.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: Icadf9c494fab82b219317c3ca3b04f633b543083
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add SPD support to eldrid for DDR4 memory part H4AAG165WB-BCWE.
Eldrid should use DRAM_ID strap ID 4 (0100) on SKUs populated
with H4AAG165WB-BCWE DDR4 memory parts.
BUG=b:181732562
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
successfully.
Change-Id: I38cfe3eb26b00563ce17df3a3ac2a0a846f2ae00
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51667
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the cret variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:181325655
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_CRET
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I700201cf81b25c6776df3ec9fc843cd9bd8c88c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
When the soc_get_mbox_address functions returns 0 after not being able
to find an initialized PSP base address MSR or in case of Stoneyridge
the PSP's BAR3, the code will print an error string. This string needs
to reference both PSP_ADDR_MSR and PSP BAR3 and not only the latter one,
since in Picasso and Cezanne only the former one is present.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I32a1e87e2a7d89c7b53f47c987e7bf0556154cf7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Matt Papageorge