Move rtc init code into common area and update the implementation for
apollolake to avoid build break.
Change-Id: I702ce0efba25cb6fde33cc15698ae44312742367
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The original purpose of adjust_cpu_apic_entry() was to set
up an APIC map. That map was effectively only used for mapping
*default* APIC id to CPU number in the SMM handler. The normal
AP startup path didn't need this mapping because it was whoever
won the race got the next cpu number. Instead of statically
calculating (and wrong) just initialize the default APIC id
map when the APs come online. Once the APs are online the SMM
handler is loaded and the mapping is utilized.
Change-Id: Idff3b8cfc17aef0729d3193b4499116a013b7930
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
- Get rid of CONFIG_ prefix from variables that don't come from Kconfig.
- Remove 2nd set of variables that are duplicates of the first set.
- Delete duplicate set of Prerequisites
Change-Id: I194b4c790b3e35353d480d34b60507a00f10ef11
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21451
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The SMU firmware used to be named *.sbin, now is named *.csbin.
Update the makefile so that the files can be named as they are
delivered and don't have to be renamed.
- Add a Kconfig option to allow the secure os binaries to be excluded.
BUG=b:64932297
TEST=Build with old and new firmware, verify file sizes.
Change-Id: I3091f8af126159488c3c398a6dc881fa05039cff
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Adapted from Chromium commit 9756af8.
Add SOC helper to identify BSW SoC stepping. Will be used to
override USB2 phy setting based on stepping in subsequent commit.
Original-Change-Id: Ic736dd945f01cf9f24af4ce3bd3f2757abfdeb2e
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Ib2371f85ea84df4b417e25ec8840d317cd918d5f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the common acpi code.ACPI code is very similar
accross different intel chipsets.This patch is an effort to
move those code in common place so that it can be shared accross
different intel platforms instead of duplicating for each platform.
We are removing the common acpi files in src/soc/intel/common.
This removes the acpi.c file which was previously in
src/soc/common/acpi. The config for common acpi is
SOC_INTEL_COMMON_BLOCK_ACPI which can be defined in SOC's
Kconfig file in order to use the common ACPI code. This patch also
includes the changes in APL platform to use the common ACPI block.
TEST= Tested the patch as below:
1.Builds and system boots up with the patch.
2.Check all the ACPI tables are present in
/sys/firmware/acpi/tables
3.Check SCI's are properly working as we are
modifying the function to override madt.
4.Extract acpi tables like DSDT,APIC, FACP, FACS
and decompile the by iasl and compare with good
known tables.
5.Execute the extracted tables in aciexec to check
acpi methods are working properly.
Change-Id: Ib6eb6fd5366e6e28fd81bc22d050b0efa05a2e5d
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch implements soc function to get previous sleep state
using chipset_power_state global structure.
acpi_get_sleep_type is needed in PRE_RAM stage when soc selects
CONFIG_EARLY_EBDA_INIT kconfig option.
Change-Id: I79acbfc09c8d255fbf9d73e49e8c7764f3f3fac6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix the warnings of klocwork scan.
e.g. "Pointer 'dev' checked for NULL at line 158 will be dereferenced at line 159"
Change-Id: I6cc9c68652b074c666c86456183460ca38a886ed
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There was already a uart.c added to bootblock. Remove the
duplicate addition.
Change-Id: I2d420ff7437d25a596ee9a120964f8d4bc413bc4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Vboot and ChromeOS support in SOC Kconfig, include a separated
verstage in Makefiles.inc as well.
Change-Id: I114a9d6e92b69199ccacc1e7e1535eccc0e2cb99
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
__packed has been introduced in commit 6a00113de8
("Rename __attribute__((packed)) --> __packed"). Use it.
Change-Id: Ie654567ebff884b911de10bd9fef605436e72af8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/21346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch fixes klocwork bug due to recent memmap.c
implementation where “Pointer 'dev' returned from call
to function 'dev_find_slot' at line 144 may be NULL.”
Change-Id: I4c74ca410d1a0ba48634ec9928a0d9d1cc20e27a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This changelist adds the capture format to be set for max98927. The
nhlt blob is the same but the format params for capture are different
from the render.
BUG=b:36724448
TEST=IV feedback data is of good quality
Change-Id: I135cf4479e89cd2046ff46027f94c0f71aed650e
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GCC_PREFIX is uncommon in the coreboot tree. If not provided, take data
from .xcompile to fill in the blanks.
Change-Id: I711a73be9d35d896198664f0ae213218653f275e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/21391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change adds support for Intel Atom C3000 SoC
("Denverton" and "Denverton-NS").
Code is partially based on Apollo Lake/Skylake code.
Change-Id: I53d69aede3b92f1fe06b74a96cc40187fb9825f1
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Move ADD_VBT_DATA_FILE to "Devices" menu and rename it to
INTEL_GMA_ADD_VBT_DATA_FILE.
Depend on Intel platforms to avoid confusing users of non-Intel platforms.
The Intel GMA driver will use the vbt.bin, if present, to fill the
ACPI OpRegion.
Change-Id: I688bac339c32e9c856642a0f4bd5929beef06409
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch defines Max PCIE Root Ports and fixes
bellow Coverity scan defect,
*** CID 1380036: Control flow issues (NO_EFFECT)
/src/soc/intel/cannonlake/romstage/romstage.c: 80 in soc_memory_init_params()
79
>>> CID 1380036: Control flow issues (NO_EFFECT)
>>> "i" is converted to an unsigned type because it's compared to an unsigned constant.
80 for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) {
81 if (config->PcieRpEnable[i])
82 mask |= (1 << i);
Change-Id: Id45ff6e96043ed71117018a4e73d08920ae9667e
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cannonlake LPSS UART port can be working on both 32 bit and 8 bit mode.
To maintian compatibilty with previous generation of SOC, select 32 bit
mode as default.
Change-Id: Iaef8bceabc1b12e054ab4a364f98b568a9efcd85
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot cannonlake RVP successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
6. Enable C6 DRAM with PRMRR size 0MB and boot to OS.
Change-Id: I0a430a24f52cdf6e2517a49910b77ab08a199ca2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses smm common library function to get tseg base
address and size. Hence removing definitions of smm_region()
from soc directory.
BRANCH=none
BUG=b:63974384
TEST=Build and boot reef successfully.
Change-Id: I091ca90cf576c0da35cf3fe010f8c22a18ef82d9
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch uses system agent common library to
know tseg region start and size. Unable to remove smm_region()
function from soc code as SMM common library
is not yet available for skylake use.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: If98b65805753db2c30d6fea29e401a17cef39799
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to avoid build bot hang issue due to no
active default value for UART_FOR_CONSOLE kconfig
option.
Change-Id: I70ca5dc6c4bde6a119ad59d8c58955c96c042198
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21287
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to add helper function to get SMM region start
and size based on systemagent common library.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: If10af4a3f6a5bd22db5a03bcd3033a01b1cce0b4
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to add helper function to get tseg memory base and
size for HW based memory layout design.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve successfully.
Change-Id: I4c8b79f047e3dc6b2deb17fdb745f004004526b6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is a bug introduced by this commit:
stoneyridge: Fix CPU ASL \_PR table [commit I870f81]
The following error is found in dmesg
ACPI Error: [\_PR_.P000] Namespace lookup failure, AE_NOT_FOUND...
ACPI Exception: AE_NOT_FOUND, During name lookup/catalog...
ACPI Exception: AE_NOT_FOUND, (SSDT:AGESA ) while loading table...
ACPI Error: 1 table load failures, 3 successful...
...
acpi-cpufreq: overriding BIOS provided _PSD data
And, "ls -la /sys/devices/system/cpu/cpufreq/" doesn't work
The cause is that the Pstate SSDT table generated by AGESA expects CPU
variables \_PR.Pxxx, not \_PR.CPxx as generated by coreboot.
Use Kconfig to set the required string.
BRANCH=none
BUG=b:64885241
TEST= Check dmeg and ls -la /sys/devices/system/cpu/cpufreq/
Change-Id: I4929f9a1c39705c6df9d965c8d030f4d1f0b5e5f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The guards in the header files were inconsistent. Some had no leading or
trailing underscores, some had one, some had both leading and trailing.
Change all to double leading & trailing underscores.
Change all comments to have a space before them instead of tabs
BUG=b:62235990
Test=Build Kahlee
Change-Id: I4466df529ab201c922096a31d7438381778b582f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Increase the default setting to add more CAR space for the early
console. This avoids truncation of the log.
BUG=b:64980233
Change-Id: Ia11d1c6c186a7025510c240206743ebe8d741461
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21186
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures skylake device using FSP1.1 can use HW based
DRAM top calculation which was broken due to skylake fsp1.1 not
honoring any UPD to know PRMMR size and default reserving 1MB for PRMRR size.
This WA is not needed for FSP2.0 implementation due to
PrmrrSize UPD is available and considering into hw based dram top
calculation.
BRANCH=none
BUG=b:63974384
TEST=Build and boot lars which is using skylake 1.1 fsp.
Change-Id: Iade0d2cb2a290fc4c9f0e6b1eaadc8afff2fa581
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This patch to ensures that coreboot is performing SPI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence SPI lock down programming has been moved
right after pci resource allocation is donei, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure SPIBAR+HSFSTS(0x04) register FLOCKDN bit and WRSDIS
bit is set. Also, Bits 8-12 of SPIBAR+DLOCK(0x0C) register is set.
Change-Id: I8f5a952656e51d3bf365917b90d3056b46f899c5
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/21064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that there is a handy macro utilize it.
Change-Id: I560bc7a591075235229952cdea63d4e667f323ee
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch to ensures that coreboot is performing DMI
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence BIOS Interface lock down through Sideband
access has been moved right after pci resource allocation is done,
so that BILD lock down is getting executed along with LPC and SPI
BIOS interface lockdown settings before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure DMI register offset 0x274c bit 0 is set.
Change-Id: Ie66701d5bd8c8f389e23fb30c8595dd83cf6b1ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit f92d7be.
This BAR is used in _PS0 and _PS3 methods and is used by kernel driver to put
SD controller in D3
Original-Change-Id: Iae4722cb222f61e96948265f57d6b522065853d9
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Change-Id: I59973226d57fe1dc3da21b2cec1c7b9a713829ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Needed for to-be-added Google Braswell boards which make use
of common GPIO library function to determine installed RAM type.
Change-Id: Ie9b0c6513f10b252bf0a5014bd038d24879421be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing PMC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence PMC register lock down has been moved
right after pci resource allocation is done, so that
PMC registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure PMC MMIO register 0xC4 bit 31 is set.
Change-Id: Ibd86a38fa78752ce007da63a9ccdd991ca21ab92
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to ensures that coreboot is performing LPC
registers lockdown after PCI enumeration is done.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence lpc register lock down has been moved
right after pci resource allocation is done, so that
lpc registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure LPC register 0xDC bit 1 and 7 is set.
Change-Id: I705a3a3c6ddc72ae7895419442d67b82f541edee
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch ensures that MRC cache data is already written
into SPI chip before SPI protected regions are getting locked
during BS_DEV_RESOURCES-BS_ON_EXIT.
This requirements are intended to support platform security
guideline where all required chipset registers are expected
to be in lock down stage before launching any 3rd party
code as in option rom etc.
coreboot has to change its execution order to meet those
requirements. Hence storing mrc cache data into SPI has
been moved right after pci enumeration is done, so that
SPI registers can be lock down before calling post pci
enumeration FSP NotifyPhase() API which is targeted to
be done in BS_DEV_ENABLE-BS_ON_ENTRY.
TEST=Ensure MRC training data is stored into SPI chip and power_
Resume autotest is passing.
Change-Id: I8ee26b5cc70433438cf4e45e707b8a54f89cf9b0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the fchec.h files, which do not seem mainboard specific, out of
the mainboard directories into the southbridge/soc directories.
Change-Id: Idd271c6ab618aa4badf81c702212e7de35317021
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is not specific to a board but the binary IMC firmware
used on the platform. Also remove unused IMSP and IMWK methods.
Change-Id: I80026bca55f5ba236c080bcd882fc374559942e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This patch ensures that entire system memory calculation is done
based on host bridge registers.
BRANCH=none
BUG=b:63974384
TEST=Build and boot eve and poppy successfully with below configurations
1. Booting to OS with no UPD change
2. Enable ProbelessTrace UPD and boot to OS.
3. Enable PRMRR with size 1MB and boot to OS.
4. Enable PRMRR with size 32MB and boot to OS.
5. Enable PRMRR with size 2MB and unable to boot to OS due to
unsupported PRMRR size.
Change-Id: I9966cc4f2caa70b9880056193d5a5631493c3f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change provides interface to override dev tree settings per
board due to many projects share same devicetree.cb.
BUG=b:64880573
TEST=Verify that dev tree settings can be overridden in mainboard
on coral
Change-Id: I349b1678d9e66022b586b6c7f344b831ed631c74
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/21142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The Sideband Acces locking code is skipped from FSP by setting an
FSP-S UPD called PchSbAccessUnlock. This locking is being done in
coreboot during finalize.c.
This is done because coreboot was failing to disable HECI1 device
using Sideband interface during finalize.c if FSP already locks
the Sideband access mechanism before that.
So, as a solution, coreboot passes an UPD to skip the locking
in FSP, and in finalize.c, after disabling HECI, it removes the
Sideband access.
BUG=b:63877089
BRANCH=none
TEST=Build and boot poppy to check lspci not showing Intel ME
controller in the PCI device list.
Change-Id: I8dba4c97480200507969b0f2873337f97bd2ff6a
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This update changes Cannonlake to use the new common PMC code. This
will help to reduce code duplication and streamline code bring up.
Change-Id: Ia69fee8985e1c39b0e4b104c51439bca1a5493ac
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Configure core PRMRR first on all the cores and then follow
the SGX init sequence. Second microcode load would run the
MCHECK. To pass MCHECK, PRMRR on all cores needs to be
configured first. Hence, PRMRR configuration would be called
from soc_core_init while MP init for each core and then from
soc_init_cpus, BSP would call sgx_configure for each core
(including for itself). This code flow satisfies the MCHECK
passing pre-conditions; and apparently this patch fixes the
behavior of calling configure_sgx() “again” for BSP. (So
removed the TODO comment also).
Change-Id: I88f330eb9757cdc3dbfc7609729c6ceb7d58a0e1
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21007
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To correct the SGX init sequence; PRMRR on all cores first
needs to be set, then follow the SGX init sequence. This
patch would refactor the common SGX code (and add needed
checks in the init sequence) so that SOC specific code can
call SGX init in correct order.
Change-Id: Ic2fb00edbf6e98de17c12145c6f38eacd99399ad
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove passing microcode patch pointer as param while calling
- soc_core_init()
- soc_init_cpus()
Also change callbacks in apollolake/geminilake and skylake/kabylake
common code to reflect the same function signature.
Change-Id: Ib03bb4a3063d243d97b132e0dc288ef3868a5a7b
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21010
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get microcode patch pointer from intel_mp_current_microcode() api
of mp_init and change sgx_configure function signature to drop
microcode_patch param.
Change-Id: I9196c30ec7ea52d7184a96b33835def197e2c799
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21009
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cannonlake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I7afa5ab2c5eb06e6df8eeb1cb1cd0de00d2b2a28
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Skylake/Kabylake SOC has two possible ways to make serial
console functional.
1. Legacy IO based access using Port 0x3F8.
2. LPSS UART PCI based access.
This patch to provide option to select index for LPSS
UART port: 0 = LPSS UART0, 1 = LPSS UART1, 2 = LPSS UART2
PCI based LPSS UART2 is by default enabled for Chrome Design.
Change-Id: I9647820fe59b5d1a1001a611b9ae3580946da0ae
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the duplicate MISCCFG_GPE0_DW* macros that are already present
in the common gpio code.
Change-Id: Iad75e5f7e276b37b5861f0c9a3bb0bb2824a638c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add mp_current_microcode() function to get the microcode patch pointer.
Use this function to avoid reading the microcode patch from the boot
media. init_cpus() would initialize microcode_patch global variable to
point to microcode patch in boot media and this function can be used
to access the pointer.
Change-Id: Ia71395f4e5b2b4fcd4e4660b66e8beb99eda65b8
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP might have done some settings for us there. Use pci_update_config32()
since the register is documented to be 32 bits wide.
Change-Id: I995e8a731a6958f10600174d031bb94f5a0a66db
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/21072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fail at build-time if one of the following happens:
Platform includes SMI handler setup function smm_init()
in the build when configuration has HAVE_SMI_HANDLER=n.
Platform does not implement smm_init_completion() when
HAVE_SMI_HANDLER=y.
Change-Id: I7d61c155d2b7c2d71987980db4c25d520452dabf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Instead of enabling power button SMI unconditionally, add a boot state
handler to enable power button SMI just before jumping to
payload. This ensures that:
1. We do not respond to power button SMI until we know that coreboot
is done.
2. On resume, there is no need to enable power button SMI. This avoids
any power button presses during resume path from triggering a
shutdown.
BUG=b:64811381
Change-Id: Icc52dc0103555602c23e09660bc38bb4bfddbc11
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Do not use the global platform_i2c_transfer() function that can only be
implemented by a single driver. Instead, make a `struct device` aware
transfer() function the only interface function for I2C controller dri-
vers to implement.
To not force the slave device drivers to be implemented either above
generic I2C or specialized SMBus operations, we support SMBus control-
lers in the slave device interface too.
We start with four simple slave functions: i2c_readb(), i2c_writeb(),
i2c_readb_at() and i2c_writeb_at(). They are all compatible to respec-
tive SMBus functions. But we keep aliases because it would be weird to
force e.g. an I2C EEPROM driver to call smbus_read_byte().
Change-Id: I98386f91bf4799ba3df84ec8bc0f64edd4142818
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds few helper functions in CPU common libraray code
which are mainly needed for ACPI module. The functions those are
moved to cpu common code is removed from common acpi files.
TEST= System boots properly and no regression observed.
Change-Id: Id34eb7e03069656238ca0cbdf6ce33f116e0e413
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/21051
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Chrome OS systems rely on the write status register to enable/disable
flash write protection and disabling this opcode breaks the ability
to enable or disable write protection with flashrom.
Add a configure option for this feature that will disable the opcode
for Write Status commands unless CONFIG_CHROMEOS is enabled.
Tested to ensure that a default build without CONFIG_CHROMEOS has this
option enabled while a build with CONFIG_CHROMEOS does not. Also
ensured that when this option is disabled (for Chrome OS) then flashrom
can be used with the --wp-enable and --wp-disable commands, depending
on the state of the external write protect pin.
Change-Id: Ia2ef3c3b1e10fba2c437e083f3537022f1fce84a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/21021
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Remove cpu.h from the cache-as-ram setup and teardown files that rely
on the FSP implementation. The struct device statement causes a
build failure and there appears to be nothing needed from cpu.h in
the two .S files.
TEST: Build Google Reef with FSP_CAR selected on Chipset menu and add
FSP binaries on the Generic Drivers menu.
Change-Id: I560b730c18d7ec73b65f2e195b790e7dcacfd6bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21057
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We do not need or use the Management Engine MBP HOB so that
step can be skipped when FSP initializes the ME.
BUG=b:64479422
TEST=boot with FSP debug enabled binary and ensure that the
output indicates this step is being skipped:
Skipping MBP data due to SkipMbpHob set!
Change-Id: I5ea22ec4b8b47fa17b1cf2bf562337bfaad5ec0d
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/20951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: Ief58fdcb8a91f9951a48c3bd7490b1c7fee17e48
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Need to perform a dummy read in order to activate LPSS UART's
16550 8-bit compatibility mode.
TEST=Able to get serial log in both 32 bit and 8 bit mode through
LPSS UART2 based on CONFIG_DRIVERS_UART_8250MEM_32 and
CONFIG_DRIVERS_UART_8250MEM selection.
Change-Id: I5f23fef4522743efd49167afb04d56032e16e417
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch fix the dependency for PMC common block code.
PMC block use SLP_TYP macros and acpi_sleep_from_pm1
function which is defined in arch/acpi.h and guarded
by CONFIG_ACPI_INTEL_HARDWARE_SLEEP_VALUES. So we need
PMC common block to depend on that config for proper
inclusion.
Change-Id: I88077626aff3efba0a95b3aaee0dbd71344ccb42
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/20964
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides the option to use the common CPU
Mp Init code by selecting a Config Token.
CONFIG_SOC_INTEL_COMMON_BLOCK_CPU_MPINIT config token can be
selected to use the Common MP Init Code, also where CPU MP Init is
done before FSP-S Init.
And if the config token is not selected, the old way of
implementation will exist, where MP Init is been done after
FSP-S.
CQ-DEPEND=CL:*397551
BUG=none
BRANCH=none
TEST=Build and boot Reef
Change-Id: I35d012785000d3f3bfcc34138cda9cd4591559f6
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20895
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
This patch was merged too early, and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20581
Change-Id: I14eeba575af1658ff8013c9a00bd71013566bcbe
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20687
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize postcar frame once finish FSP memoryinit
This patch was merged too early and reverted.
Originally reviewed on https://review.coreboot.org/#/c/20534
Change-Id: Id36aa44bb7a89303bc22e92e0313cf685351690a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20688
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The PMIO region was moved, but not updated in the ASL. Change to
generate \_PR table runtime and to report the correct PMIO region
and length.
Fix on Kahlee, where the EC overlaps the region:
[ 0.802721] cros_ec_lpcs GOOG0004:00: couldn't reserve region0
[ 0.807446] cros_ec_lpcs: probe of GOOG0004:00 failed with error -16
BUG=b:63902389
BRANCH=none
TEST=Cros_ec_lps can reserve the region. ACPI tables are correct.
Change-Id: I870f810cc5d2edc0b842478cde5b3c164ed3b47f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Our current struct for I2C segments `i2c_seg` was close to being compa-
tible to the Linux version `i2c_msg`, close to being compatible to SMBus
and close to being readable (e.g. what was `chip` supposed to mean?) but
turned out to be hard to fix.
Instead of extending it in a backwards compatible way (and not touching
current controller drivers), replace it with a Linux source compatible
`struct i2c_msg` and patch all the drivers and users with Coccinelle.
The new `struct i2c_msg` should ease porting drivers from Linux and help
to write SMBus compatible controller drivers.
Beside integer type changes, the field `read` is replaced with a generic
field `flags` and `chip` is renamed to `slave`.
Patched with Coccinelle using the clumsy spatch below and some manual
changes:
* Nested struct initializers and one field access skipped by Coccinelle.
* Removed assumption in the code that I2C_M_RD is 1.
* In `i2c.h`, changed all occurences of `chip` to `slave`.
@@ @@
-struct i2c_seg
+struct i2c_msg
@@ identifier msg; expression e; @@
(
struct i2c_msg msg = {
- .read = 0,
+ .flags = 0,
};
|
struct i2c_msg msg = {
- .read = 1,
+ .flags = I2C_M_RD,
};
|
struct i2c_msg msg = {
- .chip = e,
+ .slave = e,
};
)
@@ struct i2c_msg msg; statement S1, S2; @@
(
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1 else S2
|
-if (msg.read)
+if (msg.flags & I2C_M_RD)
S1
)
@@ struct i2c_msg *msg; statement S1, S2; @@
(
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1 else S2
|
-if (msg->read)
+if (msg->flags & I2C_M_RD)
S1
)
@@ struct i2c_msg msg; expression e; @@
(
-msg.read = 0;
+msg.flags = 0;
|
-msg.read = 1;
+msg.flags = I2C_M_RD;
|
-msg.read = e;
+msg.flags = e ? I2C_M_RD : 0;
|
-!!(msg.read)
+(msg.flags & I2C_M_RD)
|
-(msg.read)
+(msg.flags & I2C_M_RD)
)
@@ struct i2c_msg *msg; expression e; @@
(
-msg->read = 0;
+msg->flags = 0;
|
-msg->read = 1;
+msg->flags = I2C_M_RD;
|
-msg->read = e;
+msg->flags = e ? I2C_M_RD : 0;
|
-!!(msg->read)
+(msg->flags & I2C_M_RD)
|
-(msg->read)
+(msg->flags & I2C_M_RD)
)
@@ struct i2c_msg msg; @@
-msg.chip
+msg.slave
@@ struct i2c_msg *msg; expression e; @@
-msg[e].chip
+msg[e].slave
@ slave disable ptr_to_array @ struct i2c_msg *msg; @@
-msg->chip
+msg->slave
Change-Id: Ifd7cabf0a18ffd7a1def25d1d7059b713d0b7ea9
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch add new API to read LPSS CLK register. Also combine multiple
LPSS_CLOCK_CTL_REG writes into a single write inside lpss_clk_update function.
Change-Id: I420919ad9154c4cf426bc232c5eb59d95fd698d2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The minimum needed defines are included here and pm.h
will be updated when the PMC code for cannonlake is uploaded.
Change-Id: Idaf2be1258b3ec71fa449b88516bcb06c730d776
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20849
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helper functions required by intel/common UARRT driver for
enabling controller on S3 resume.
BUG=b:64030366
Change-Id: Idd17dd0bd3c644383f273b465a16add184e3b171
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20888
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Add a new variable to GNVS to store information during S3 suspend
whether UART debug port controller is enabled.
2. On resume, read stored GNVS variable to decide if UART debug port
controller needs to be initialized.
3. Provide helpers functions required by intel/common UART driver for
enabling controller on S3 resume.
BUG=b:64030366
TEST=Verified behavior with different combinations:
1. Serial console enabled in coreboot: No change in behavior.
2. Serial console enabled only in kernel: coreboot initializes debug
controller on S3 resume.
3. Serial console not enabled in coreboot and kernel: coreboot skips
initialization of debug controller on S3 resume.
Change-Id: Iad1cc974bc396ecd55b05ebb6591eec6cedfa16c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed on a number of platforms (baytrail, kaby lake)
that if serial console is not enabled in coreboot, but is enabled in
kernel (v4.4), then on resume kernel hangs. In order to fix this, add
support for enabling UART debug port controller on resume.
In order to decide whether UART debug port controller should be
enabled in ramstage, following things are checked in given order:
1. If coreboot has serial console enabled, there is no need to
re-initialize the controller.
2. This special action is taken only for UART debug port controller.
3. If boot is not S3 resume, then initialization is skipped.
4. Callback into SoC to check if it wants to initialize the
controller.
If all the above conditions are met, then UART debug port controller
is initialized and taken out of reset.
BUG=b:64030366
TEST=Verified with the entire patchset series that:
1. If coreboot does not have serial console enabled, but Linux kernel
has console enabled, then on resume, coreboot initializes UART debug
port controller.
2. If coreboot and Linux do not have serial console enabled, then
coreboot does not initialize UART debug port controller.
3. If coreboot has serial console enabled, there is no change in
behavior.
Change-Id: Ic936ac2a787fdc83935103c3ce4ed8f124a97a89
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20835
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add new API function lpss_is_controller_in_reset that returns whether
the LPSS controller is in reset. Also, add lpss.c to smm stage so that
lpss_is_controller_in_reset can be used in smihandler.
BUG=b:64030366
Change-Id: I0fe5c2890ee799b08482e487296a483fa8d42461
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Create a new function uart_lpss_init which takes the UART LPSS
controller out of reset and initializes and enables clock.
2. Instead of passing in m/n clock divider values as parameters to
uart_common_init, introduce Kconfig variables so that uart_lpss_init
can use the values directly without having to query the SoC.
BUG=b:64030366
TEST=Verified that UART still works on APL and KBL boards.
Change-Id: I74d01b0037d8c38fe6480c38ff2283d76097282a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Cannon lake, Apollo Lake and GLK CPU device IDs in
common Mp Init code.
BUG=none
BRANCH=none
TEST=Build and boot reef
Change-Id: I22694ced0cf900a55a28d1ecaa177cab2ea9a90c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20896
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The device_t type is used in smihandler.h, but the header
is not including a header which provides that type. Fix
that by #includeing <device/device.h>
Change-Id: I89af949b088bf569d330f2ea74b1b8ae97e1ed52
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20933
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add smm common code for io trap handling. This feature is
mainly used by big core intel platforms. Commonizing io trap
handling will make bring up of big core platforms more
seamless.
Change-Id: I83bcf22107291ea181b347fac40d57d7ea138de1
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20848
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In _FSL ACPI notification 0x83 was incorrectly being sent to DPTF.
When there should be no notification on fan speed change.
Change-Id: I66efa7a7feb911a458829a54dbd0afefabd42394
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20875
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With this patch apollolake uses the common PMC util
code.No regression observed on a APL platform.
Change-Id: I322a25a8b608d7fe98bec626c6696e723357a9d2
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19375
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
PMC util code is very similar accross different intel SOC's.
This patch is an effort to move those code in common place
so that it can be shared accross different intel platforms
instead of duplicating for each platform. This patch adds
pmclib.c file which contains the pmc utility functions
common accross SOC's. The config for common PMC is
SOC_INTEL_COMMON_BLOCK_PMC which can be defined in SOC's
Kconfig file in order to use the common PMC util code.
Change-Id: Ic3d96fc23a98c30e8ea0969a7be09d217eeaa889
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/19349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Internal PME is detected when bit PME_B0_STS is set. Following devices
causes internal PME.
- Integrated LAN
- HD Audio/Audio DSP
- SATA
- XHCI ('USB3')
- ME Maskable Host Wake
In SPT, PCIEXPWAK_STS bit isn't getting set due to known bug.
So scan all PCIe RP for PME status bit & update event log accordingly.
BUG=b:36992859
TEST=Build for Soraka, Verify resume due to PME on root port is logged
in elog.
Change-Id: I879a7c332e62ab598942b29d31bad84619b35ea7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The SPI controller initialization in finalize_chipset was failing
because FSP was setting FLOCKDN before finalize_chipset was called.
Hence move finalize_chipset to get called from BS_POST_DEVICE so that it is
called before FSP notify function-Ready To Boot state.
TEST: run flashrom with -VVV and observe supported opcodes and SPI
flash chip are reported correctly, and write/erase operations succeeed.
Original-Change-Id: I3c0297f3f2258cf77cf00db367f11ff4d1d9dc77
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I690fb4bf9e78bb58811c704179ba8b8f25ce95cc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Always sanity check for EHCI class device and move
PCI function power enablement up.
Change-Id: I1eebe813fbb420738af2d572178213fc660f392a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is assumption of static EHCI_BAR_INDEX, try to
clean it up by bringing BAR programming at one spot.
Change-Id: Ie16090536ac5470c24720a54813015250ae2d0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Starting with RK3399, PMUGPIO pull registers use the same write mask
format as normal GRF registers, so they need to use RK_CLRSETBITS()
rather than clrsetbits_le32().
BRANCH=None
BUG=None
TEST=boot from scarlet
Change-Id: Ibe391273d58ab35df993e149187d67497fcf2acc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add Cannonlake pci device ids for all the merged intel common code. As
of now only have CNL-U and CNL-Y pci ids.
Change-Id: Iee5087cdeba53919d83ff665d0c417075279294c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ied677e8c77fa7b166b016da458caad0e4702b5d8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If IGD PCI device is disabled:
1. BAR for the device will be 0.
2. There is no need to allocate framebuffer for this device.
Some early SOCs don't have GFX model fuse by default hence
we need to add a check to ensure PCI device is enable. This
code to avoid die inside coreboot for missing resources.
Change-Id: Ic31d3e57ba730f6b569bf2cc3bdc54cb369b8caf
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Without RELOCATABLE_RAMSTAGE selected, S3 resume will hang under
Linux and Windows. All other Intel SoCs have this selected by
default, so this change simply corrects an omission on Braswell.
TEST: boot Linux on google/cyan with and without RELOCATABLE_RAMSTAGE
selected; observe that S3 resume fails without and succeeds with.
Change-Id: I9071d9b4e3e3a156281d95fae059947c4c26f744
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code doesn't include much, but when compiled outside the coreboot
build (what the shipped Makefile is made for), we want to make sure that
the few files it includes are controlled by us.
TEST=`cd src/soc/nvidia/tegra124/lp0; make CC=arm-eabi-gcc` works
Change-Id: Ic2f1e4aa4047617b048ef7ef98d71f9d540ccd74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20860
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The array of CMOS values that was passed into the read routine was
never getting updated. GCC 7.1 gives a warning on this:
error: may be used uninitialized in this function
Change-Id: I2f7c9b6455761a38598467b001efb0603fd14c32
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A mainboard may access GPIO in romstage.
Change-Id: Id380c6570943ce2a0bf6112d62cc91aeae283fcf
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI asl for global non-volatile storage (GNVS).
Change-Id: I9ecab92181bfe60e7b6c6e91ffb9fa843345352f
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20275
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As per discussion with CSME team, ME is NOT using PCI Config
Space register HFSTS2 Bit 10 to update ME power-gated status.
ME goes to CM0-PG state after ME device becomes idle after
Bit 2 of MMIO register offset 0x800 (D0i3 Control - HECI1_D0I3C)
is being set.
And to retrieve the PG status of ME, one should read from the
PWRMBASE+offset 0x590 (which should give the value 0xF9) and
PWRMBASE+offset 0x594 (which should give the value 0xFF).
But, also it needs some time for the ME FW to go to idle state
and reflect these values in PWRMBASE registers after D0i3 bit
is being set. This does not happen instantly.
So, in coreboot, if we read the ME PG state in finalize.c, which
happens just after FSP Notify phase, where actually ME D0i3 bit
is set, we do not read the correct PG state values (i.e, 0xF9
and 0xFF).
But, once it boots to Kernel, if we read those same registers
through iotool mmio_read32 command, we get correct values.
So, removing the ME PG state prints from coreboot, since it is
actually showing wrong information, although ME Power Gating is
successful.
Change-Id: Idd31a9803b4c9db7d4bb8bbec5374583a8df0c41
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the unused support code from the old multi-device hudson
SD controller. The binaryPI blob contains the correct steps
for setting up SD and the public BKDG doesn't completely document
the controller.
The sd.c file was using device IDs not associated with the Stoney
Ridge APU. The hudson_enable() code removed was also looking for
incorrect device IDs and the PM_MANUAL_RESET register doesn't
behave as the source indicates.
The SD default settings may be overridden. Future improvements
may include a few Kconfig options and a weak call to the mainboard
for overriding additional defaults.
BUG=chrome-os-partner:62580062
Change-Id: I7dbd70320740e8a05e6bf16af125d67012f20674
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Kconfig selects for vboot and update the makefile to pick up
files to be used in verstage.
Change-Id: If5c439a330d687156006aec2ebaea18ff2c96b3e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19756
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The format of the D14F3xA0 SPI Base_Addr register is different
than a traditional BAR. Change the function to preserve any
enables already in place. Change the AND mask to remove the
reserved field and the enables.
Change-Id: I9a43c029a2e1576703ce9cdc787d18658e9190a5
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The following changes have been applied for GPIO:
1. Correct port id using by GPIO community 3 for CNL-LP.
2. Correct number of doubleword for each pad from 2 to 4.
Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Apollo Lake SoC supports configuration of Running Average Power Limits
(RAPL) for package domain. This feature is not required for all APL
mainboards. According to the APL SoC EDS Vol 4 chapter 18.4 Power
Limiting Control it is not necessary to enable the RAPL algorithm per
default. For that reason make the RAPL configuration selectable.
Change-Id: Ib737b162f72b76c15e5768859f9099e2e7ef6426
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
init_igd_opregion itself is supposed to return cb_err so this adds
error handling, just like other implentations of write_acpi_tables do it.
this had been found by coverity:
*** CID 1378270: Error handling issues (CHECKED_RETURN)
/src/soc/intel/skylake/igd.c: 147 in write_acpi_igd_opregion()
141 /* If IGD is disabled, exit here */
142 if (pci_read_config16(device, PCI_VENDOR_ID) == 0xFFFF)
143 return current;
144
145 printk(BIOS_DEBUG, "ACPI: * IGD OpRegion\n");
146 opregion = (igd_opregion_t *)current;
CID 1378270: Error handling issues (CHECKED_RETURN)
Calling "init_igd_opregion" without checking return value
(as is done elsewhere 5 out of 6 times).
147 init_igd_opregion(opregion);
148 update_igd_opregion(opregion);
149 current += sizeof(igd_opregion_t);
150 current = acpi_align_current(current);
TEST=Built
Change-Id: If6f5d53037f093607d89cfe8faf193d55de7f6c4
Found-by: Coverity (CID 1378270: Error handling issues (CHECKED_RETURN))
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The values were verified to be correct with the KabylakeFsp0001 from
github. Skylake FSP documentation disagrees so YMMV.
Change-Id: I1ee04dbbed48d5376dbc24ae70753b059f2646eb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20765
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SMBIOS memory HOB produced by glk FSP v52_27 has new structure
members, which are not available in current apl FSP. New FSP-m
header file in https://review.coreboot.org/#/c/20673/ lists new
SMBIOS structure members.
Break memory HOB save routine into different functions for glk
and apl to accomodate new changes.
Change-Id: I33c6e4f2842cebbb326b6a05436fa69e3836ffc6
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20674
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current implementation of itss_irq_init() uses 8 bit write access to
IRQ routing registers which is not supported on Apollo Lake.
This commit moves the register access from 8 bit to 32 bit so that this
function can be used with every platform.
Change-Id: I15c3c33a16329fd57f0ad7f99d720adbf300d094
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
coreboot was setting SPI FPR register to protect the
mrc_cache data range stored in flash. This programming was being done
after FSP Notify 1.
But, FSP was locking the SPI by setting FLOCKDN Bit during Notify
phase 1, due to which coreboot was unable to protect that range.
As solution, FSP introduced a new UPD SpiFlashCfgLockDown to skip
the lockdown of flash on interest of bootloader. Set that UPD to 0
to skip the lockdown of FAST_SPI flash from FSP.
The same is being done from coreboot after end of Post at finalize.c
file.
BUG=b:63049493
BRANCH=none
TEST=FPR can be set properly to protect the mrc_cache range. The
issue reported in the bug doesn't come when both software and
hardware WP is enabled with this patch.
Change-Id: I3ffca2f1b05ab2e4ef631275ef7c3a6e23e393aa
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use 16bit write to avoid touching the upper two bytes that may cause
write cycle to fail in case a prior transaction has not completed.
This function sets the WRSDIS(Bit 11) and FLOCKDN (Bit 15) of the
SPIBAR + BIOS_HSFSTS_CTL. While WRSDIS is lockable with FLOCKDN,
writing both in the same cycle is guaranteed to work by design.
Avoid read->modify->write operation not to clear the RW1C bits
unintentionally.
Change-Id: Ia7880aaca0ed64150c994d49786a0a008bbaa98b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Earlier 15ms time-out was kept for SPI transactions which was not
enough for SPI Erase transactions.
Increase the max time-out time to 5 secs which was present in SKL
before common code.
This increase in time-out won't disturb other SPI transactions like
Read, Write or Read Status, since, for those it will come out of
the loop once FDONE bit or FCERR bit is set.
BUG=b:63959637
BRANCH=none
TEST=Built and booted poppy and all SPI transactions succeeded.
Change-Id: I1c015d80b33677de11755fb2097373631d1fa8c4
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions.
Allows to get rid of opregion.c, as it's no longer needed.
Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
The variable p was going out of scope while still being pointed to by
*cpu_name.
Fix coverity ID 1378215 (Pointer to local outside scope)
Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This reverts commit 399c022a8c.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit dbe7f893c0.
This was merged too early. I'll repost it.
Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The gpio numbers are global, but they have their respective place
within each community and the group within their community. For
all the calculations open coding this calculation convert them to
use the helpers.
Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A pad number is passed into gpi_status_get() to determine if its
associated bit is set from a generated event. However, the
implementation wasn't taking into account the gpi_status_offset
which dictates the starting offset for each community. Additionally,
the max_pads_per_group field is per community as well -- not global.
Fix the code to properly take into account the community's
gpi_status_offset as well as the max_pads_per_group.
Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in
`igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`.
Nobody missed it for nearly a year, plus, it's not applied on the GOP
path, let's drop it.
Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This quirk was superseded a view lines above. Also the whole path is
guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for
nearly a year now.
Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.
Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency
was I2C_SPEED_FAST.
This was due to incorrect register programming.
TEST= Build for Soraka, I2C frequency during firmware execution was
I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS.
Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The _PIC method is called by the OS to choose between interrupt routing
via the i8259 interrupt controller or the APIC.
Change-Id: I2bc16f9c096c095c02de3692e76c0906cec54cb5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
HECI2 and HECI3 devices are “function disable” during FSP
Silicon Init phase. Device will not be visible over PCI bus
hence removing these devices from wake source list.
Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Explicitly add LOGICAL to the reset macro name to make it explicit
that the values are logical.
2. Reword some of the comments and combine them into single comment
instead of scattering the comments throughout.
3. Use c99 struct initializers for the reset mapping array.
4. For the chipset specific values use literals that match the hardware.
5. Use 'U' suffixes on the literals so we don't trip up compiler being
over zealous on undefined behavior.
6. Use unsigned and fixed-width types for the reset mapping structure
since the code is reliant on matching up with a register definition.
7. Fix formatting that can fit < 80 cols.
Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sadly, small core and big core are not aligned with the OS driver's
expectation on the number of ACPI devices used for each community.
Big core uses a single device while small cores use one ACPI device
per community. Allow for this distinction within the common gpio
implementation and ensure apollolake is utilizing the new option
to retain the correct behavior.
Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It should never be globally exposed. Remove the global symbol
and make it static.
Change-Id: I3b85f3bbf6a73d480cdefdcdec26e137e3a3f75f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It should never be globally exposed. Remove it.
Change-Id: I90e201ddd4df2cda89e7d3e4cb81bdc2a81cac83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
