USB type-A port with same PLD.token information as USB type-C port,
causes conflict while generating ACPI code for the EC CONN device.
Use a different PLD.token number for type-A port to fix the issue.
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
before patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS01
},
after patch:
Package (0x02)
{
"usb2-port",
\_SB.PCI0.XHCI.RHUB.HS01
},
Package (0x02)
{
"usb3-port",
\_SB.PCI0.TXHC.RHUB.SS03
},
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: If3e76c11dd6808eee4c9c2f3f71604a60379b5a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This patch renames config `SOC_INTEL_METEORLAKE_U_P` to
`SOC_INTEL_METEORLAKE_U_H` as per Intel Meteor Lake Processor EDS
version 1.3.1 (doc number: 640228).
With new branding, the MTL-U/H-Processor Line offered in a 1-chip platform that includes the Compute, SOC, GT, and IOE tile on the
same package.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I032be650bbfef0bf0ef86bb37417b1d854303501
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75931
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
get_usb_port_references refer the PLD group. If the port assign cross
ports like mux[0] use USB3 and mux[1] use USB1, then we need set USB3
to group 1. Update the PLD panel to back as well.
BUG=b:286328285
TEST=check ACPI can have right USB port in EC CON.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97517ecd4f8615af749fb6d007ded8e171796f7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75912
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Using the boolean type and the true/false macros give the reader a
better understanding about the option. Thus, use the bool type for the
attribute and use the macros for assignments.
Skylake mainboards which use that option were changed by the following
command ran from the root directory.
socs="SOC_INTEL_(SKYLAKE|KABYLAKE|SKYLAKE_LGA1151_V2)" && \
option="s0ix_enable" && \
grep -Er "${socs}" src/mainboard | \
cut -d ':' -f 1 | \
awk -F '[/]' '{print $1"/"$2"/"$3"/"$4}' | \
xargs grep -r "${option}" | \
cut -d ':' -f 1 | \
xargs sed -i'' -e "s/${option}\".*\=.*\"1\"/${option}\" \= true/g"
Change-Id: I372dfb65e6bbfc79c3f036ce34bc399875d5ff16
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75871
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Update overridetree to support ELAN and G2_G7500 touchscreen.
BUG=b:285477026
TEST=emerge-nissa coreboot and check touchscreen function
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I236a2815f956929c6cd84c981cb15e9ab0f657b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75762
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableSataSalpSupport'.
Change-Id: I4a68ffd2b68c92434da681b5e5567329c8784c72
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75858
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'ModPhyIfValue'.
Change-Id: I4cdf68e65cea4ab316af969cd6a8d096b456518d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75855
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'DisableComplianceMode'.
Change-Id: I9d5605134a753f161a66857c7f78844ae7490cd6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'PmicPmcIpcCtrl'.
Change-Id: I3632d1e83108221d3487b4f175133ad347238bc5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75853
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures the SoC to flip the orientation of the AUX pins to
follow the orientation of the cable when using the anx7452 retimer. This
is necessary when there is no external retimer/mux or the retimer/mux
does not implement the flip. The anx7452 retimer does not appear to
support this feature, so let the SoC do the flip.
BUG=b:267589042,b:281006910
TEST=verified DP-ALT mode works on rex using both cable orientations
Change-Id: Ibb9f442d2afd81fb5dde4bca97c15457837f9f4a
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75827
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
USB3 is used for both typeA and WWAN based on different DB.
BUG=b:287159026
TEST=change FW config and check typeA and WWAN can work.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I5ad3973a9519350794a661ad00f71c0eb34edfba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75819
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the support RAM parts for gothrax.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
H58G56AK6BX069 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:284388714
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: Ib16846f7b2061ee254db674ac7bac66c9b9f4e70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75834
Reviewed-by: Henry Sun <henrysun@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
TCSS and TBT use the same lane on schematic. Update the port start
from 0 to match the Intel schematic. You can better follow the it
without convert the port number.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ic6631dcbbd9f6c79c756b015425e2da778eb395e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
- Disable devices in variant.c instead of adding probe statements to
devicetree because storage devices need to be enabled when fw_config is
unprovisioned, and devicetree does not currently support this. (it
disables all probed devices when fw_config is unprovisioned.).
- Removed `bootblock-y += variant.c` from Makefile.inc based on
CL:3841120.(The infrastructure for selecting an appropriate firmware
image to use the right descriptor is now ready so runtime descriptor
updates are no longer necessary.).
BUG=b:285477026
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I6920d88dfec86676ff6733146f748e06d4085c49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75743
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
There are two baseboards within the set of mainboards built
here, with baseboard name appended in the filenames.
Take the style and variable BASEBOARD_DIR from google/brya,
then move and rename the supporting files under separate
directories.
Change-Id: I2046b6f82519540b8596ce925203bd60d1870c1c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74471
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the initial USB PHY tuning values that were a copy of the ones
from the Chausie mainboard to the values used in the Birman UEFI
firmware reference implementation. The USB3 PHY tuning values are still
the same while some of the USB2 PHY tuning values are different. The
last two USB2 PHYs that are used by the USB4 controllers have a
different parameter set compared to the other USB2 PHYs.
TEST=All USB ports on Birman function as expected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0ddfa2594d66b21582282ab8509c921a6e81a93f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75823
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for Micron MT53E2G32D4NQ-046 WT:C LP4x DRAM.
BUG=b:216393391
TEST=build pass
Change-Id: I3797de01629fdb5ace4c610943d88db525da112b
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75826
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This patch enables BT offload feature on Rex over SSP1.
BT mode is selected via FW_CONFIG and corresponding VGPIOs are
programmed.
BUG=b:275538390
TEST=Verified audio playback using BT speaker/headset in I2S mode on google/rex.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I46e9702add37464122ffc78826ebf8a6c5b5b07c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72881
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pujjo does not support GPIO based D-SAR,
so set GPP_D15 and GPP_H23 to NC.
BUG=b:275264095
TEST=boot on pujjo and no impact WWAN dynamic SAR function
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I4fe40b32a572a8d914e01e5cd7927766ccf17c02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75403
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's been decided not to use the USB 3.0 port 1 on this board anymore,
so disable it also with the corresponding USB 2.0 lane.
BUG=none
TEST=USB 3.0 port 1 not functional anymore after boot, while others
continue working.
Change-Id: I2799e3d9d7232743c9480dd9611d94ed3249f53b
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch renames `SOC_INTEL_STORE_CSE_FPT_PARTITION_VERSION` config
to `SOC_INTEL_STORE_ISH_FW_VERSION` to ensure the usage of this config
is clear.
Any platform would like to fetch the currently running ISH firmware
version should select this configuration.
TEST=Able to build and boot google/marasov.
Change-Id: Ie503d6a5bf5bd0d3d561355b592e75b22c910bf5
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75767
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Boxy audio codec chip uses ALC5682I-VD, not ALC5682I-VS.
It needs to modify codec HID to "10EC5682" in coreboot to fix audio no
output sound issue.
BUG=b:286970886
BRANCH=dedede
TEST=confirm audio soundcard can be list by command "aplay -l"
Change-Id: Icd69a9d757ba817b586a703a17375682db684224
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
This patch enables adding variant specific ASL code
TEST=Kernel driver is able to communicate with device
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I231482d56dd4afa150766c07cfde105158e5e124
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add driver to support ELAN touchscreen using SPI for rex
* See "HID Over SPI Protocol Specification" section 5.2 - ACPI enum
* https://www.microsoft.com/en-us/download/details.aspx?id=103325
BUG=b:278783755
TEST=Kernel driver is able to communicate with device. Also tested
S0ix, ran 'suspend_stress_test -c 1' - no issues in suspend/resume.
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Id51d385ce350cef23da4184b044c74569f4dd3f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74885
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
One specific Hynix LPDDR5x DRAM part requires an ABL workaround to
eliminate DRAM-related failures during a FAFT test, but due to the
use of generic/common SPDs, there is no way for the ABL to determine
the DRAM part # itself.
Consequently, we will have coreboot check the DRAM part #, and set/clear
a CMOS bit as appropriate, which the ABL will check in order to apply
(or not apply) the workaround.
The ABL already uses byte 0xD of the extended CMOS ports 72/73 for
memory context related toggles, so we will use a spare bit there.
BUG=b:270499009, b:281614369, b:286338775
BRANCH=skyrim
TEST=run FAFT bios tests on frostflow, markarth, and whiterun without
any failures.
Change-Id: Ibb6e145f6cdba7270e0a322ef414bf1cb09c5eaa
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75698
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
On nissa, the ISH is running closed source firmware, so the ChromeOS
security requirements specify it must be behind an IOMMU. Add
DmaProperty to the ISH _DSD on joxer.
BUG=b:285477026
TEST=Kernel marks ISH (PCI device 12.0) as untrusted, and changes the
IOMMU group type to "DMA". Also, device still goes to S0i3.
Before:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
0
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA-FQ
After:
$ cat /sys/devices/pci0000\:00/0000\:00\:12.0/untrusted
1
$ ls /sys/kernel/iommu_groups/5/devices
0000:00:12.0
0000:00:12.7
$ cat /sys/kernel/iommu_groups/5/type
DMA
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I69b00f0281f4493db157783840d9cdcbb138017f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75758
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When fw_config is unprovisioned, devicetree will disable all probed
devices. However, boot-critical devices such as storage devices need to
be enabled.
As a temporary workaround while adding devicetree support for this,
remove the fw_config probe for storage devices so that all storage
devices are always enabled. On eMMC SKUs, UFS and ISH will be disabled
by the PCI scan anyway. On UFS SKUs, eMMC is not disabled by the PCI
scan, but keeping it enabled should have no functional impact, only a
possible power impact.
BUG=b:285477026
TEST=On joxer eMMC and UFS SKUs, boot to OS and
`suspend_stress_test -c 10`
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I834bd81ce636a6f32d50434cbf07b1d572620492
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75757
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PCIE_RST_L is attached to a pull down, change the init to NC.
BUG=None
TEST=Boot to OS
Change-Id: I3f7a548a33eb18327139f033d7c0d6a1843f1639
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75700
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update PCIe GPIOs during rom stage to properly initialize the
PCIe devices and allow the NVMe/eMMC to be properly detected.
BUG=b:284213391
TEST=Boot to OS
Change-Id: I24ad6c1addedb414afade2512b6628022d000a47
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Move the WP signal to GPP_E12 from the current GPP_E15 to
match the design.
BUG=b:285084125
TEST=WP signal reports as we expect
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I8772173fcdcabf78b0c7d605cd495ebe04b63242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Define a CMOS layout for Librem Mini v1/v2 spanning both banks. The
only setting provided is the automatic power-on setting, which is
implemented by the EC. This can now be configured in a firmware image
by replacing cmos.default in CBFS.
Since cmos.default is applied early in bootblock, the EC BRAM interface
must now be configured in bootblock, including opening the LPC I/O
range.
Change-Id: Ib0a4ea02d71f6f99e344484726a629e0552e4941
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74363
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support of variant_devtree_update() function to override
devtree settings for variant boards. Also, add CPU power limit
values for mtlrvp baseboard.
BRANCH=None
BUG=None
TEST=Built the changes
Change-Id: I11bc17f25d4880562d016e29f81e37e068bb6757
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Currently if a rails PG fails to assert, the power on sequence
continue after the 20ms timeout. Instead, we should abort
and enter a power down.
BUG=b:285980464
TEST=sequence now aborts and powers down on failure
Change-Id: Id0865e6bdb5db1815ad5509306637308e98c15d7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch configures external V1p05/Vnn/VnnSx rails for Joxer
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
Kit: 646929 - ADL N Platform Design Guide
BUG=b:285477026
TEST=Verified all the UPD values are updated with these configs.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I78d2a885d577f6c1a89ab74c0da7b6544322c0d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Properly shutdown NV12 rail in the off sequence (current
implementation leaves it asserted).
BUG=b:286287940
TEST=NV12 now shuts down on GCOFF entry
Change-Id: I7d338fc4a96f119617aff558413a5a9ac44c27d7
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75533
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add pen detect support on the SOC pen detect GPIO.
BUG=b:286296762
TEST=Verify pen detect works on Myst
Change-Id: I922d643a83c5cd8ea0ab9fe6733f7aa05d935802
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Follow spec[1] to modify WWAN power sequence. The WWAN power sequence
of warm reset is fail. The correct sequence is WWAN_EN should keep high when doing warm reset. Set GPP_D6 to PWROK which is not to do PAD
reset when warm reset.
[1]:
[JDB10] FC ADL-N_WWAN sequence_FM101-GL SDX12 Power Timing
Review_V1.6_20230602.xlsx
BUG=b:285065375
BRANCH=firmware-nissa-15217.B
TEST=1. emerge-nissa coreboot chromeos-bootimage
2. power sequence meets spec.
Change-Id: If59630dbd10e971c91e01f33a657c01d857bc0b9
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75690
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable wifi sar function for yavilla/yavilly/yavijo.
Use the fw_config to separate SAR setting for different wifi card.
BUG=b:286141046
BRANCH=firmware-nissa-15217.B
TEST=build, enabled iwlwifi debug, and check dmesg
Change-Id: I1bd111a734a250df49535a07ef056d5b68fccb33
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add new memory parts
DRAM Part Name ID to assign
Hynix H58G66AK6BX070 3 (0011)
Hynix H9JCNNNFA5MLYR-N6E 4 (0100)
Micron MT62F2G32D8DR-031 WT:B 4 (0100)
BUG=b:279325772
BRANCH=firmware-brya-14505.B
TEST=run part_id_gen to generate SPD id
Change-Id: I2e6a916de08e7c05e95909d2b69bc839d13192d9
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74713
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
The memory parts being added are:
1. K4U6E3S4AB-MGCL
2. K4UBE3D4AB-MGCL
BUG=b:285504022
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I87a4dcdb6196c3ca7bed4b5c1bc654297339c16d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75605
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of adding the new PCI IDs of the XHCI controllers in every new
chip generation to the pci_xhci driver, bind the driver to the internal
PCI devices of the XHCI controllers via the device ops statement in the
chipset devicetree. The PCI device function of the XHCI2 controller in
Mendocino can be either a dummy device or the XHCI controller, so the
device ops are attached to that device in the mainboard devicetree
instead. The Glinda code is right now just a copy of the Mendocino code,
so it'll change in the future, but for consistency the equivalent
changes to those in Mendocino are applied there too.
Since the device ops are now attached to the devices via the static
devicetree entry, also remove both the xhci_pci_driver struct and the
amd_pci_device_ids array from drivers/usb/pci_xhci/pci_xhci.c.
TEST=SSDT entries for the XHCI controllers are still generated on
Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9c455002c6d2aac576fe24eee0c31744b4507bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Initialize the SPI Flash in bootblock to ensure that
CONFIG_SPI_FLASH_EXIT_4_BYTE_ADDR_MODE will exit 4-byte addressing mode.
BUG=b:285110121
TEST=boot myst and verify flash operations work correctly
Change-Id: Ia88d2b46884b096b4c558bc86513159ec6d35eb5
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75588
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Include the GPU ACPI methods for all of Hades baseboard.
BUG=b:285981616
TEST=built for Hades and verify shutdown works
Change-Id: Iec3c4b59a9e7a9d4a902db51d40b60e114521774
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
HW has invert the signal, set it to active high.
BUG=b:285964562
TEST=check crossystem wpsw_cur change as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I54c578e5df5f1b24743cc9506e1e31b0b18bfb25
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75628
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Add usb wwan device tree entry. Also set wwan_rst to high due to
HW design active high.
BUG=b:285792436
TEST=check FM101 is detected by Linux kernel.
Bus 002 Device 002: ID 2cb7:01a2 Fibocom Wireless Inc.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0aa60cb284d4b7f99e16643a92ee58467a355026
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75660
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Board IDs are now filled in as part of the signing process, so we don't
need to set them in coreboot.
BUG=b:240620735
TEST=Build and check VBOOT_GSC_BOARD_ID is set to ZZCR.
Change-Id: I7dda8ad59046a1dd9a28595e037eda86e91c98df
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75641
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new GFX devices for DDI and TCP with custom _PLD to describe the
corresponding ports.
BUG=b:277629750
TEST=emerge-rex coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I193b95e8bd8ae538c4f25fbe772b174ef455d744
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
All the DRAM module for Juniper/Willow can reuse the RAM ID in
offset 0x30 table, so change Juniper/Willow RAM table offset to 0x30
for introducing more DRAM modules.
BUG=b:284423187
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I92740275dcc27061a94b7db7ce095655c0bd7cf5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The K&D-ILI9882T panel and STA-ILI9882T share all DCS commands and EDID
information except for the manufacturer_name which has no effect to the
function of panel. Let's reuse the STA_ILI9882T struct in this case.
BUG=None
TEST=emerge-staryu coreboot chromeos-bootimage and boot the panel
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I510462a49d273f3d25158b25906d4c514f855cdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Based on the power sequence of the panel [1], the power on T2 sequence
VSP to VSN should be larger than 1ms, and the power off T2 sequence VSP
to VSN should be larger than 0ms. We modify the power sequence to meet
the datasheet requirement.
[1] B5 TV110C9M-LL0 Product Specification Rev.P0
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I4ccb5be04062a0516f84a054ff3f40afbf5279be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Touchscreen may either use I2C1 or SPI0.
FW_CONFIG.TOUCHSCREEN is set to determine which is used.
This CL adds a probe to enable I2C1.
BUG=b:278783755
TEST=Tested on rex, confimed i2c1 is disabled when
TOUCHSCREEN != TOUCHSCREEN_I2C
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I0bee176298fddd2aee35cf084db037a3ce7672f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Follow 57263_FP8_MBDG_rev_0_92 Table.57 to update the alias. We
can match the schematic for now.
BUG=b:285793461
TEST=USB still works.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Id1058279fe5b0e3131608a0b9bbd708dbbde7e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add Makefile.inc to include four LPDDR5x SPDs for the following
parts for Joxer:
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 3 (0011)
H58G56BK7BX068 4 (0100)
MT62F1G32D2DS-026 WT:B 4 (0100)
K3KL8L80CM-MGCT 4 (0100)
BUG=b:236576115
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ibdc89c882581cfe4e5978faf4c6f70d653e0813d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75610
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: I5c0395d33ee47ab1c7d45f33d6afb063b8263836
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75572
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: I51ff0991565d60807c100b33fb66ab10cc48b8e1
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Ensure USB-C ports' _PLD group numbers appear in order.
get_usb_port_references in src/ec/google/chromeec/ec_acpi.c uses group
token to match with the Type-C port number.
BUG=b:216490477
TEST=build coreboot and system boot into OS.
BRANCH=firmware-brya-14505.B
Change-Id: Ib564ffe272e73f46ec6608420dc431c8b017fb65
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Select SOC_INTEL_RAPTORLAKE for kuldax so that it will use the RPL
FSP headers for kuldax.
BUG=b:285406822
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=kuldax emerge-brask
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"
Cq-Depend: chromium:4583807, chrome-internal:6003096
Change-Id: Icbf8b26bc2bfee2559cce236bde80a99f8bff859
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75599
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP
threshold.
BUG=b:285406822
BRANCH=firmware-brya-14505.B
TEST=Verify that the feature is enabled by reading from fsp log
Change-Id: I9ae58d704cba8124c6cb9865431aff84c9d154f7
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75600
Reviewed-by: Bob Moragues <moragues@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add the phoenix usb config struct for Myst since the FSP has been
updated to accept the config from coreboot and the default values
do not work.
BUG=None
TEST=Boot to OS on Myst, verify devices are seen with lsusb
Change-Id: I329aba80f3003a3a5f343b8dcc3efa8502b98e24
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Enable ISH based on FW_CONFIG obtained from EC CBI. This is useful in
case device is a tablet and motion sensors are handled by ISH instead
of EC.
BUG=b:280329972,b:283023296
TEST= Set bit 21 of FW_CONFIG with CBI
Boot rex board
Check that ISH is enabled and loaded
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ibe0e1b8ce2c9b08ac6b1e6fef9bd19afc9b4f59f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75039
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix for the "Onboard Keyboard and Type-C ports are not working after
resuming from powerd_dbus_suspend" issue. This issue was caused since
FSP 3165 FSP was fixed and started skipping GpioConfigureIoStandbyState
programming when GpioOverride UPD is enabled.
This patch moves the IO Standby State programming that FSP was doing to
coreboot.
BUG=b:284264580
TEST=Boot to OS, compare gpio pins, verify keyboard / Type-C
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: If96c1e71fdde784a55fe079875915ffa5a4f548a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75555
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Myst, the FSP is shutting down the PCIe lanes that the SSD is
on. Enable hotplug to force the FSP to keep the lanes active.
BUG=b:284213391
TEST=Boot to OS
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: Iaf0aca329f05f15a3ce9edfa6a0e782c2edccabe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Intel/MTLRVP is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot intel/mtlrvp.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8b1dec47ef9d12ac50317b86c4f0bc5fbe4e4dc3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75607
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Google/Rex is built with Intel Meteor Lake-U SoC, so select it.
Currently, there is no functional difference, but in the future FSP
UPD parameters can be overridden properly.
BUG=b:276697173
TEST=Able to build and boot google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4c233e0a8ce58998dc1a0379662e386f9b3d0073
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75612
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Create the karis variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:285195072
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KARIS
Change-Id: I16d8b43390401789b87a6233238e37f32a17b46b
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL
DRAM Part Name ID to assign
K4UCE3Q4AB-MGCL 3 (0011)
BUG=b:281950933
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I75818b8a34d010fc0efe90c7625162e40e3b0dca
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Generate RAM ID for Samsung K4UCE3Q4AB-MGCL
DRAM Part Name ID to assign
K4UCE3Q4AB-MGCL 3 (0011)
BUG=b:281943392
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: I79b29b1195468272c7f64a0eeb15d032eff8c1d3
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The ramtop entry has to be 10 bytes long, and it was incorrectly set
to 10 bits, instead of 10 bytes. Change this to 80.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I506f9d98a389dd859038fd270c5e344b65f514f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75420
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For a unification of the naming convension, change from pascal case to
snake case style for parameter 'SataPortsEnable'.
Change-Id: I0df35125360eb42a03d5445011d72842cb2b8d7e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75553
Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Follow the eKTH7B18U_Product_Spec_V1.1 to add the device.
BUG=b:284381267
TEST=Check touch screen can detect in coreboot.
[INFO ] \_SB.I2C1.H010: ELAN Touchscreen at I2C: 02:10
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I4bd521410953892a477020a872de0d882001b178
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75480
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Follow the data sheet SA577C-12C0, Rev. 1.1 to add the device.
BUG=b:284381266
TEST=check touch pad can detect in coreboot.
[INFO ] \_SB.I2C0.D015: ELAN Touchpad at I2C: 01:15
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I0eb0ee1e6cb9c15bfe3964af6ce2ed02eee370a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Follow the schematic_0502 to add the audio codec and amp.
BUG=b:270109435
TEST=Check device can detect in coreboot.
[INFO ] \_SB.I2C3.RT58: Realtek RT5682 at I2C: 04:1a
[INFO ] \_SB.I2C3.D029: Realtek SPK AMP R at I2C: 04:29
[INFO ] \_SB.I2C3.D02A: Realtek SPK AMP L at I2C: 04:2a
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Icfec8d99be8fde986c5516e0c4cd50dae1edfa98
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75477
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I2c2b0548865e87859a1d742295e09a731bfb3f76
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Due to mainboard restrictions a SATA link at Gen 3 can cause issues as
the margin is not big enough. Limit SATA speed to Gen 2 to achieve a
more robust SATA connection.
Change-Id: Ifdea4542836b9c75b5507324fbb06b9566a6fe1d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75365
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the power sequence of the panel [1] and PMIC datasheet [2],
the power on T2 sequence VSP to VSN should be large than 1ms, but it's
-159us now, and the power off T2 sequence VSP to VSN should be large
than 0ms, but it's less than 0 now. Let's modify the power sequence
to meet the datasheet requirement.
[1] HX83102-J02_Datasheet_v03.pdf
[2] TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:282902297
TEST=power sequence T2 pass
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: Ib1625c6a211f849071393f69eaf5c649a8e7f72e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75298
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DPTF parameters were verified by the thermal team.
BUG=b:282598257
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I1f38ef52d3906960f8b692595fcc3b39bc000243
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit
(TCC) activation feature for proto phase.
BUG=b:282865187
BRANCH=None
TEST=Build FW and test on Screebo board
Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Incorrect filename "MakeFile.inc" cause gpio.c can not be complied.
Rename to "Makefile.inc" and confirm gpio.c can load correctly.
BUG=b:281620454
BRANCH=dedede
TEST=build and confirm gpio.c can be loaded
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I39947c66de04695e5242ab1affc328894f34f9f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75520
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable drivers for SoundWire codecs and define the topology in
the devicetree for the rex0 variant with the SoundWire daughter
board connected.
+------------------+ +--------------------+
| | | Headphone Codec |
| Intel Meteor Lake| +--->|Cirrus Logic CS42L42|
| SoundWire | | | ID 0 |
| Controller | | +--------------------+
| | |
| Link 0 +----+ +-------------------+
| | | Left Speaker Amp |
| Link 1 | +--->| Maxim MAX98363 |
| | | | ID 0 |
| Link 2 +----| +-------------------+
| | |
| Link 3 | | +-------------------+
| | | | Right Speaker Amp |
+------------------+ +--->| Maxim MAX98363 |
| ID 1 |
+-------------------+
This was tested by booting the firmware and dumping the SSDT table
to ensure that all SoundWire ACPI devices are created as expected with
the properties that are defined in coreboot under \_SB.PCI0:
HDAS - Intel Meteor Lake HDA PCI device
HDAS.SNDW - Intel Meteor Lake SoundWire Controller
HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec
HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp
HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp
BUG=b:269497731
TEST=Verified SSDT for SNDW in the OS. Playback and recording are also
validated on google/rex.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FBVDD_PWR_EN signal should be inverted in its control level
on Agah v.s. Hades. The original change covered the Hades
implementation, but needs to be updated to invert for Agah. This
change can be removed once we drop support for Agah.
BUG=b:280467267
TEST=built for Hades and Agah
Change-Id: I7f90c03b8d9b859004e5c124bf0a1f7b59921c3d
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75530
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually
ended up by adding DMA property _DSD which is similar to what
`add_acpi_dma_property` does for WWAN drivers, hence it makes sense to
have a unified name across different device drivers.
BUG=b:279676191
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add 'common_config.acp_config' to the device tree, so we have the
correct pin configuration.
BUG=b:225320579
TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in
depthcharge console
TEST=Boot into ChromeOS, verify YouTube sound works with internal
speakers and headphone jack
TEST=Boot into ChromeOS, verify microphone with Google Meet
Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Incorrect memory part was used in CB:74745 to generate the DRAM Strap
ID. Amend the memory_parts_used.txt and regenerate the DRAM Strap ID.
BUG=b:272746814
TEST=Generate the DRAM Strap ID.
Change-Id: I0668d7e02345610a11f9113d8bbe99a474f33f1a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
The IBM SBP1 is an evaluation platform.
It's utilising:
- 4 SPR sockets, having 16 DIMMs each
- 240C/480T at maximum
- 32x CPU PCIe slots
- 2x M.2 PCH PCIe slots
- Dual 200Gbit/s NIC
- SPI TPM
It has an AST2600 BMC for remote management.
It doesn't have:
- External facing USB ports
- Video outputs
- Audio codec
Test:
The board boots to Linux 5.15 with all 480 cores available.
All PCIe devices are working and no errors in ACPI.
All 64 memory DIMMS are working and M.2 devices can be used.
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds two new chromeos_*.fmd files for release and debug FSP
builds targeting rex_ec_ish.
`rex_ec_ish` variant would pack ISH firmware into the CSE boot partition
hence, the blob size is expected to increase. Creates separate flash map
layout to ensure ISH work is not impacting on the regular `rex0` project
SPI flash usage.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a new variant to support the ISH enablement using
Rex platform.The idea here is to leverage the `rex0` code as much as
possible and add specific support for ISH enablement as per the hardware
schematic differences.
BUG=b:284254353
TEST=Able to build google/rex_ish_ec board and boot on target hardware.
Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Add support of variant_devtree_update() function to override
devtree settings for variant boards. Also, add CPU power limit
values for rex baseboard.
BRANCH=None
BUG=b:270664854
TEST=Built and verified power limit values as below log message
for 15W SKU on Rex board.
Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW)
(57000, 57000) PL4 (W) (114)
Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Use verbs enabling jack detect if the EC firmware has been updated
with fixed jack detection.
Test: Build Librem 14 and boot with latest EC, test headset jack
detection.
Change-Id: I57a27b1d51e4f6c7c712bcb2823d21692b9c5ce6
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74364
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on the schematic and vendor ASL code, PCI interrupt lines ABC of
the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC.
From lspci and the schematic this chip is PCI device 1. The original
config copied from the T400 was routed ABCD->BCDA, causing Linux to
issue an "irq 18: nobody cared" message when inserting an SD card.
This is fixed by this patch and the SD card now works properly.
Change-Id: Iede1de72d5369f1aebbac170792733739add3431
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot winterhold, dump ACPI, verify unchanged
Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot markarth, dump ACPI, verify unchanged
Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI
generation") fixed the USB-A ports being double-nested, but neglected
to move the chip driver registers up into the correct scope. While the
generated ACPI is still correct, fix the register scope anyway to
avoid confusion.
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, dump ACPI, verify unchanged
Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be
able to train memory (DIMM) at different frequencies.
On all latest Intel based platforms SaGv is expected to be enabled
to support dynamic switching of memory operating frequency.
BUG=b:267879107
TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2)
and MRC retraining takes around ~20ms extra compared to SaGv being
disabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SKU1A C0 has no redriver, so enable SBU muxing in the SoC.
BUG=b:283044004
BRANCH=none
TEST=Voltages are correct on the C0 and C1 AUX bias pins
Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba
Signed-off-by: mike <mike5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Hades uses the SODIMM, enable the smbus to see the SPD address for the
memory.
BUG=b:283138024
TEST=i2cdetect -l can see the smubs adapter.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add devicetree and Kconfig entries to enable additional configuration
of the Pericom PI7C9X2G608GP PCIe switch on this board variant.
The amplitude is being adjusted to 425 mV and de-emphasis level to
6.0 mV.
BUG=none
TEST=Read out the PCIe config space values of the switch and check if
they match with the ones configured over SMBus.
Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and
root port #3 (00:1c.2) set the max payload size to 256 bytes for both
root ports.
Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Override the weak function mainboard_ewl_check() and select OCP_EWL.
Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are
needed for OCP EWL driver, but they are Meta-specific BMC commands
and don't really work for AC, this change is just for a demonstration
with AC.
Note that FSP UPD promoteWarnings needs to be disabled so that
FSP won't block and can return to coreboot for EWL processing
when memory EWL type 3 error occurs.
Tested=On Intel AC, connected with a faulty DIMM can see
EWL type 3 error being generated and halted with coreboot log:
[DEBUG] Number of EWL entries 3
[ERROR] EWL type: 3 size:32 severity level:1
[ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04,
[ERROR] Major Checkpoint: 0xb7
[ERROR] Minor Checkpoint: 0x74
[ERROR] Socket 0
[ERROR] Channel 4
[ERROR] Dimm 0
[ERROR] Rank 0
[ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1)
[DEBUG] ipmi send memory training error
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e978: 00 00 00
[DEBUG] EWL type: 1 size:19 severity level:1
[DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04
[DEBUG] 0x6392e98b: 00 00 01
[EMERG] Memory Training Error!
Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=untested, but same error/fix as frostflow variant.
Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The overridetree definitions for the USB ports wrongly double-nested
the ports, causing the generated SSDT to be incorrect, leading to
an error in dmesg:
ACPI BIOS error (bug): Could not resolve symbol \
[\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND
BUG=b:283778468
BRANCH=skyrim
TEST=build/boot frostflow, verify error no longer present in dmesg.
Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Generate the RAM ID for Samsung K3KL6L60GM-MGCT.
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 6 (0110)
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP
can be used.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
BUG=b:282912666
TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0)
is enabled when bit20 is set, and disabled when cleared
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
According to Thermal table 0518, adjust DPTC and STT settings.
BRANCH=none
BUG=b:273636128
TEST=emerge-skyrim coreboot chromeos-bootimage
Then the thermal team has verified.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
The board needs this setting to boot.
Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Pujjoteen5 support WWAN 5G device, use variant.c to handle the
power on sequence.
BUG=b:279835626
TEST=Build and check WWAN 5G power on sequence.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the DmaProperty in the device's _DSD so that the OS can treat the
device as untrusted.
BUG=b:278310256
TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1
iperf3 -c <iperf3-server> -t 60 (No performance regressions seen)
Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36
Signed-off-by: Mark Hasemeyer <markhas@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Set all GPIOs to their target functions and do not depend on FSP to
configure them. The board support has stabilized and was tested with
many PCIe devices. There is no need to detect CLKREQ signals so we may
hardcode them.
TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock
PM features' state on PCIe root ports are the same before and after
the change.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I01dc83ce23ca27525b8905665da942510f249824
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Disable backlight before turning on bridge, otherwise the bridge will
initialize failed.
Fixes: d5c1e1(mb/google/corsola: Add support for MIPI panel)
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I7d10bf9e8675b2fb03bfd1e294af66207b9b0620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75354
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
The upstream kernel privacy screen driver uses HID GOOG0010 to look for
firmware node to use. This method is used on other boards, e.g. redrix.
See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources.
Update jinlon gfx ACPI node to work with that.
BUG=b:279092050
TEST=privacy protection screen works with 5.15 and 4.19 kernels
Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7
Signed-off-by: Kornel Dulęba <korneld@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
The support for the board has stabilized and PCIe ports have been
tested with many devices. Although hotplug is not commonly used
and it seems pointless to keep it enabled, so disable it.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I338c55cb57d971badd08235b71626a710fafb829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board
has two specific VBT files that are hard-coded in the Makefile. Hence
set an empty INTEL_GMA_VBT_FILE string.
Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
There is only a single place where we need the LVDS EDID string. Let's
call gm45_get_lvds_edid_str() right there. This simplifies the API and
helps to follow the execution flow.
The function is moved to avoid a forward declaration.
Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
The PCI resource should only be probed as part of the device
.init process. We can simply do that first and know that we
can use the global `gtt_res` from then on.
This simplifies the signature of gm45_get_lvds_edid_str(), and
makes changes to the API user (lenovo/x200) necessary.
Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
As announced in the 4.20 release notes, support for the Intel Galileo
mainboard is moved to the 4.20 branch and dropped from master.
Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Generate the RAM ID for Samsung K3KL6L60GM-MGCT.
DRAM Part Name ID to assign
K3KL6L60GM-MGCT 6 (0110)
BUG=b:281928906
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: Ia5193d3ab3d654f25d519ad9a954f2ca8a15a978
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75152
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@google.com>
GC6 - Low power mode for system idle on Nvidia GPU
In GC6I Before ramp of PEXVDD:
Deassert FBVDDQ Enable, no delay is needed before or after.
In GC6O After ramp of PEXVDD:
Assert FBVDDQ Enable, no delay is needed before or after.
BUG=b:280467267
TEST=built for Hades and Agah, tested on Agah
Signed-off-by: Eran Mitrani <mitrani@google.com>
Change-Id: I0277772b1d2f6f4e6a3f74b92035e8b36f2670ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75302
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables stylus support by configuring the "GPP_D08" irqs for
rex SoC. This allows the SoC to detect a stylus device, when in use.
However stylus is not a wake up source for the rex.
BUG=b:282256460
Test=Stylus is detected on proto1 device.
Signed-off-by: Dinesh Gehlot <digehlot@google.com>
Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Phoenix has one more Type C port and two more USB2 ports which are used
as the legacy USB part of the two USB4 ports. The USB struct version
numbers have also changed, since it's a newer and incompatible version
of that struct.
TEST=After changing FSP to not hard-code the USB PHY config, but use the
configuration provided by coreboot, and applying this patch, the USB
connector on the USB2 port 4 lines works.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If52934595dd612154b97e7b90dbd96243146017a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Things with prompts should not use selects, but should instead default
to y. If there's a reason they need to be selected, they should be able
to be hidden when they're selected.
This isn't one of those cases where a select is needed, so set the
default to y instead.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6de339c3a1ceb3cd71008402bba49b5efc4af3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
The SPD format in the APCB has changed for Phoenix, and the injection
tool 'apcbtool' needs to be updated to match. Until this happens, the
APCB will be built containing the correct SPD.
BUG=b:281983434
TEST=Build
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This hook is specifically for asus/p3b-f so its mainboard code has
a chance to put SPD away after RAM init completes. What it intends
to do is done when GPO gets programmed in ramstage (and it's safe
to do so), and no other board needs this hook, so drop it.
Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use AUDIO PROBE to determine speaker amp config, set SOF driver
profile accordingly.
TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile
selected, drivers loaded and functional.
Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Taniks uses a 4-channel output config, rather than 2-channel.
Update the SOF speaker topology accordingly.
TEST=build/boot Win11 on taniks, verify speaker output functional.
Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
By moving certain FW UI assets from RO to RW sections, 4 MiB is
sufficient for RO section. Split the resultant available 4 MiB equally
between 2 RW sections. This will help in getting to 16 MiB SPI flash for
the mainboard.
BUG=b:281567816
TEST=Build Myst BIOS image with the updated layout.
Cq-Depend: chromium:4519688
Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Update USB port macros:
- change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1,
HUB to USB 2.0 headers, HUB to rear USB 2.0
- change USB type C header to LONG which caused hard lockups on the
port making it unable to enumerate in UEFI Payload and Linux
- add empty definitions for USBr ports
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
copy from dibbi since taranza base on dibbi,this is only for first
initial configuration, will update the more setting afterward.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the parts.
BUG=b:277664211
BRANCH=dedede
TEST=build
Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The detachable Starmie will use MIPI panels, which require reading
serializable data from the CBFS. So we add MIPI panel support to the
display configuration and align the configuration sequence with the
panels that use MIPI bridges.
The PMIC Datasheet:
TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf
BUG=b:275470328
BRANCH=corsola
TEST=emerge-corsola coreboot chromeos-bootimage and display normally
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Error message ´Cannot map compressed file config without cbfs_cache' is reported.
Compressed parts of CBFS can not be used during bootblock stage.
Remove config from mb_log_list.
Will be added to verified items by CB:74752.
BUG=NA
TEST=booting and verify log on facebook FBG1701
Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte
addressing mode, so ensure the driver exits that mode for regular
operation.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
TPM IRQ should be A20 not A13. RAM table is correct.
BUG=b:282164589
TEST=able to boot up
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to correct I2C bus.
BUG=b:282164589
TEST=able to boot up
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot samsung/lumpy, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach.
TEST=build/boot google/parrot, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad
Windows drivers to properly attach. Change the interrupt type
from EDGE to LEVEL.
TEST=build/boot google/butterfly, verify touchpad functional under
both Windows 10/11 and Linux, verify Windows overlay driver
correctly remaps top row keys.
Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO
default, so that Windows installs a multitouch-capable driver rather
than the standard PS2 mouse driver.
TEST=build/boot Win11 on google/stout, verify trackpad is multitouch
capable.
Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can
be locked. The MSR remains locked after a non-power cycle reset, though.
If the MSR is locked, coreboot bails out and leaves VMX in the state it
was found. Because of this, changes to the VMX enable option in the BMC
only take effect after the system is power cycled.
This behaviour is highly undesirable because users are likely not aware
that a power cycle is required for changes to VMX state to take effect.
So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the
current VMX state does not match the requested state, then issue a full
reset. This will power cycle the system and unlock the MSR, so that the
desired VMX state can be programmed into the MSR. This is checked early
to avoid needlessly doing time-consuming operations (running FSP) twice
if we know we will need to power cycle the system anyway.
Note that a user may change the VMX setting after the newly-added check
but before the setting is read in ramstage to program the MSR, but this
is a non-issue as firmware settings need a reset to take effect anyway.
TEST: Toggle VMX setting in BMC and reboot without power cycle, observe
coreboot automatically issues a power cycle reset because the MSR
is locked and the VMX state differs. Verify that the system boots
properly with VMX in the correct state after having power cycled.
Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Instead of having the maximum number of possible CPU objects defined in
the DSDT, dynamically generate the number of needed CPU devices in the
SSDT like it's done on all other x86 platforms in coreboot.
TEST=APU2 still boots and Linux doesn't show any ACPI errors with this
patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states".
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The `get_board_settings()` function always returns non-NULL, so there is
no need for NULL checks. When only one member is accessed, also drop the
local variable and directly dereference the function's return value.
Change-Id: I4fc62ca2454f4da7c8ade506064a7b0e6ba48749
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75140
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This mainboard contains in addition to its base variant, mc_ehl2, an LCD
panel driven through the PTN3460 eDP-to-LVDS bridge.
This patch enables the PTN3460 support by adding the device to
devicetree.cb and board-specific configuration parameters in
lcd_panel.c.
BUG=none
TEST=Boot with the LCD panel attached and observe whether the picture is
stable and free of artifacts coming from wrong resolution and timing.
Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard is based on mc_ehl2. In a first step, it contains a copy
of mc_ehl2 directory with minimum changes. Special adaptations for
mc_ehl5 mainboard will follow in separate commits.
Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Based on touchscreen product spec.
For uldren variants with a touchscreen, drive the enable GPIO high
starting in romstage while holding in reset, then disable the reset
GPIO in ramstage (done in the baseboard).
BUG=b:279989974
TEST=Build and boot to OS in uldren. Touch screen is workable.
Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity.
Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
This signal isn't functionally being used and is causing leakage
during suspend. Set it to NC.
BUG=b:279762779
TEST=builds. WWAN functional.
Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
If reading the serial/part number fails, returning an empty string is
very confusing. Instead, return "INVALID" to make problems obvious.
Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
The Realtek RTL8111F NIC is currently not defined at all, nor as a child
device, resulting in the on_board flag not being set to 1. This means
that Linux / udev will call the device enp3s0 rather than eno0, as it's
appropriate for on-board ethernet devices.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
This board has a TPM connector, enable support for it.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Small typo in brask/gma-mainboards-ads
Should be brask/gma-mainboards.ads
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds
Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052
Reviewed-by: Eran Mitrani <mitrani@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Create the gothrax variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.).
BUG=279614675
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_GOTHRAX
Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com>
Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
The boxy removed the APW8738BQBI-TRG and
"disable_external_bypass_vr" should be set to "1" to disable
BUG=b:271407334
TEST=emerge-dedede coreboot
Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the sequenced controlled shutdown path, there's a 10ms delay
after the PEXVDD rail is disabled to permit discharge needed on
Agah/Proxima.
This can be dropped to 3ms for Hades designs Proto0 and forward.
Once Agah board is dropped, "if CONFIG" can be cleaned up/removed.
BUG=b:271167335
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I8a0d62ec76caff861adce2d6c0ba2d4e4064affa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75051
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.
Change-Id: Ia8b7f997ca6234add569da751e1070144790e258
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
An underscore has crept into the mainboard model option for mc_ehl3 and
mc_ehl4 by mistake. This patch fixes the incorrect entry.
Change-Id: Ie59619877fb6341a5bbfe91c13e7692943480ad0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75040
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are only SSD connected to SATA ports on this mainboard. To prevent
misbehavior, set the correct hard drive type for enabled SATA ports.
BUG=none
TEST=Boot into OS and check the stability of the SSD
Change-Id: I116b1e36f0582956604c3c2508961ffb3de0898a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74947
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Selects should be done in the Kconfig file instead of Kconfig.name.
Change-Id: I2ae03a3ac548674b8c5e7dfaff47d6c536b452f1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75013
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The STA_HIMAX83102_J02 and STA_ILI9882T panel will be used for Starmie,
enable these two panels config for it.
BUG=b:272425116
BRANCH=corsola
TEST=build starmie and check the cbfs include the panels
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I1dd696dd6a84d9606e4b9a2d4884dd70a6df9161
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74200
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Librem Mini v1/v2 has an automatic power-on setting provided by the EC
in BRAM bank 1. Use this bank as the high bank of CMOS memory so that
setting can be described in cmos.layout.
Change-Id: Icb87bc521f71aa4350c8f5a64fc2cbe7a7a8c808
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Add FW_CONFIG item for FP sensor init and conditionally init
the GPIOs based on whether we're using a SPI or UART FP sensor.
BUG=b:276939271
TEST=builds
Change-Id: I9815bd17df1d15f73529beb15d08cde1ef90efad
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add FW_CONFIG item for eMMC/NVMe support and address the init
of the lanes based on said config.
BUG=b:278877257
TEST=builds
Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Mark Hasemeyer <markhas@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Allow different gma-mainboards configs for different baseboards
as they support varying display interfaces. Set Brya to eDP only
and Brask to HDMI only.
BUG=b:277861633
BRANCH=firmware-brya-14505.B
TEST=Builds and SoL functions on both brya and brask varaints
Change-Id: Iaf3f35b009d53e50723e4aa82c0f4932783f9bb9
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Update devicetree to support G7500 touchscreen.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot and check touchscreen function
Change-Id: I3b63b1bb45275ad7eef8799dcff27f264739c258
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Id5b0fa96ca8d86ddf20d808f5107a43ad2d0a1e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add variant makefile to support including the memory folder for Myst.
BUG=b:273383819
TEST=Builds in chromium with blobs
Change-Id: I03b0cd91dd66f357b15522da36f5118867b6b14c
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74964
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the OEM ID from CBI to determine the correct OEM board name.
ID mapping taken from ChromeEC source, branch firmware-fizz-10139.B.
TEST=build/boot multiple fizz variants, check that board name reported
correctly in SMBIOS tables.
Change-Id: I06251974ac73570b911920ed566a175e8e733710
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
DSM (Dynamic Speaker Management) uses calibration parameters stored in
a VPD (Vital Product Data) FMAP region to configure the audio output
via an ACPI _DSD table. This has no dependency on a ChromeOS, and can
be used by Linux/Windows drivers if appropriately configured.
Remove the dependency of DSM_CALIB (and the calibration file) on
CHROMEOS and replace it with VPD, so that non-CHROMEOS builds
can utilize this feature as well. Move files from underneath
vc/google/chromeos to underscore the point.
TEST=build/boot google/nightfury, dump ACPI, verify DSM calibraton
parameters present in _DSD table.
Change-Id: I643b3581bcc662befc9e30736dae806f94b055af
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The patch disables Tccold Handshake to prevent possible display
flicker issue for marasov board. Please refer to Intel doc#723158
for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Boot to OS on marasov.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I286e88e5bec240d64e6c801648f6483ad2b0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74931
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Configure the SuperIO and logical devices in the device tree. This
overrides the power-on default state.
UART1 was already enabled, and if ENABLE_EC_UART1 was selected in
Kconfig, the LPC UART1 I/O range was also already enabled.
The RTC/BRAM interface was enabled (and the BRAM1 base was 0x360 by
default), but the LPC I/O range was not opened previously. Now it is
open and BRAM bank 1 is accessible.
Mouse/Keyboard are not wired to anything on this board and are now
disabled.
UART2, SMFI, power channel 1, and power channel 2 were enabled
previously, but their LPC I/O ranges were not opened and they were not
accessible to the OS. Fan control is performed by the EC on this board
so there is no change.
SWUC and power channels 3-5 were disabled by default, no change.
Change-Id: I58a5a427737f4a2caa64326c110eb53ec00b347d
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
variant_board_sku() is missing dependences in order to work correctly
in romstage. Rather than more intrusive rework as its use is limited,
move the FPMCU early GPIO init back to ramstage. We still meet
sufficient power off time to fully power cycle the MCU.
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and FP tests all pass
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ia428ec5aec1a0438e91bc48903bda043046b740e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74695
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The image processing unit/GMM and xDCI are not used on octopus boards;
additionally, enabling xDCI can cause some problems with USB ports in
both booting from the payload and in the OS.
Change-Id: I1ee99b5c45881a4cf3624bf487bc9d83fb3d07a1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74893
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on wyvern variant, verify headphone output
and microphone functional under Windows using coolstar's SOF drivers.
Change-Id: I421c070eac321c2fc160b8f26868bcb1ec13001e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74815
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on several volteer variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I62a96149cec9eeb7b2da8a2337083969a1b0fce0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74816
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on banshee and osiris variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I12614b85f9779cc40d83a9c868cc46b110f26af6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74817
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Add all SOF chip drivers to baseboard and use FW_CONFIG to determine
the correct option, to ensure the correct audio config is passed to the
SOF OS drivers.
TEST=build, boot Windows on several dedede variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: I9452b11af614d8727aa8dd448e37f7a06faa450d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74818
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Since commit 833bb448c5 ("mb/siemens/mc_ehl: Remove spd.bin from
CBFS"), the subdir 'spd' is no longer necessary.
Change-Id: Ibaf44e3181b2167aa83cffcc59835196e4cb5cdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Remove explicit PNP 6e.1 configuration for UART. This had no effect,
the SuperIO is actually on I/O port 2e. Enabling the 8250IO driver is
sufficient to use the UART, the UART device is enabled by default.
Test: Build Mini v2 with and without CONFIG_ENABLE_EC_UART1, boot and
check output on serial.
Change-Id: Idbb39c81cadd633f4718f0682d231dc578d20325
Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74362
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have largely dropped from filling in mainboard_ops.name
as unnecessary. A common place should be decided where or if
this information is added in the console log.
Change-Id: I917222922560c6273b4be91cd7d99ce2ff8e4231
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Add SOF chip driver entries for all variants, so that the correct audio
config is passed to the OS drivers.
TEST=build, boot Windows on several hatch variants, verify audio
functional under Windows using coolstar's SOF drivers.
Change-Id: Ie791fa873fc7bbab84644f5ea5743bdcdc124908
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The image processing unit (Iunit) and SoC UARTS are not used on any
reef boards.
Change-Id: Iacdf93b4952cbc63fc465f07d440463106527b8d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It's not particularly useful to end users, and shows up as an unknown
PCI device under Windows Device Manager.
TEST=build reef, boot Windows, verify unknown PCI device no longer
present in Device Manager.
Change-Id: Ie8ec46e2e07b6635bfe9766812ce08b866c71d66
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add rules to inject the variant specific SPD binaries into APCB.
BUG=b:273383819
TEST=Build Myst BIOS image. Currently no APCB is present. So no SPD is
injected into APCB.
Change-Id: Ic511cdc4fe0989c9abc0cd0531cc0cae40f8dc34
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74746
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Generate the RAM Strap IDs based on the initial memory configuration.
BUG=b:272746814
TEST=Build Myst BIOS image.
Change-Id: I8a4fe9a41f101ac10391756f1b815220c8b98612
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
There is no platform-level implementation for USB port power management
in various sleepstates. This mainboard never evaluates the set GNVS
variables S3U0, S3U1, S5U0 and S5U1 in ASL or in its SMI handlers.
Change-Id: Ic7af2d608d95c6691f31ef1b8af72f96da20787c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There is no platform-level implementation for USB port power management
in various sleepstates. The mainboards changed here never evaluate the
set GNVS variables S3U0, S3U1, S5U0 and S5U1 in ASL or in their SMI
handlers.
Change-Id: Ia1bc5969804a7346caac4ae93336efd9f0240c87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Add data.vbt files for all variants supported by current volteer
recovery image. Several boards use the same VBT, so place the "common"
VBT under the baseboard directory and set it as the default.
For variants with a unique VBT, override the default and use the file in
their respective variant directory. Select INTEL_GMA_HAVE_VBT for all
variants which have a VBT file.
TEST=build/boot various volteer variants
Change-Id: I728ab81938c78f600ff8931a8073d1f7de152c09
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74852
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Camera LED will blink several times as sensor is being probed during kernel boot.
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips
initial probe during kernel boot and prevent privacy LED blink.
BUG=b:274634319
TEST=Build and boot on Craask. Verify & observe Camera LED blinking behavior.
Change-Id: I78ed5efe1e2c071d817c1e0455271886e89e63c7
Signed-off-by: Jimmy Su <jimmy.su@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74728
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The support for a spd.bin from CBFS was removed for all mc_ehl boards in
commit 833bb448c5 (mb/siemens/mc_ehl: Remove spd.bin from CBFS).
There is still a remaining comment in romstage_fsp_params.c referring to
the removed capability. This fix removes the spd.bin related part of the
comment to stay consistent with the code.
Change-Id: I669ee1c33d1d1c47764640982f71129195e63f14
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74801
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
With the profile ATLAS_PROF_REALTIME_PERFORMANCE it is desired to not
have the option to be able to enter sleep. The reason is that Microsoft
Windows goes to sleep after 30min of inactivity by default.
TEST: See that Microsoft Windows 11 has no 'Sleep' option in the start
menu.
Change-Id: I424db7e712a705c628aa3a10a486d3313404987a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74421
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
FSP is fractionally faster at configuring ASPM (1,118,688 vs 1,122,205)
but coreboot's configuration results in lower power consumption of
approximately 0.5W when idling - the reason why is unknown.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ib15eaede956f0aa55118d093fdff0fd9487df250
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74520
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functionality to ensure that the FPMCU is power cycled long enough
on boot to ensure proper reset.
This solution relies solely on coreboot to sequence the power and reset
signals appropriately (150ms on boot).
-Confirmed power is off for 150ms on boot.
-Confirmed RCC_CSR of FPMCU indicates power cycle occurred.
-Confirmed reset is de-asserted approx 3ms after power application
(target >2.5ms)
BUG=b:245954151
TEST=Confirmed FPMCU is still functional on Nami and timings are
as expected.
Change-Id: I0a23bda96bc2ea90be81a2310605f75c55c0a839
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add functionality that allows a variant SKU to have a specific set of
GPIO configs in romstage (modeled after the existing one in
ramstage)
BUG=b:245954151
TEST=builds
Change-Id: I593a23951306908fadc00e6bc8d9d310f09c5e4b
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The number of NID entries was too high for the Realtek
and Intel sound cards, preventing the verb table from
loading. Now the values are correct; it loads as intended.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I79825313a4801c120a0a2a321cbabab7c728aa71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Commit 5103b87a4d ("mb/starlabs/starbook/adl: Add an option to
enable Hot Plug") introduced an option to enable Hot Plug for the
SSD. The port was set to 4 (RP5) which is the wireless card. Change
this to 8 (RP9) which is the SSD.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I884f4997d73e31bd422477952466f168afad66a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74738
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Because SPL fuse needs to be set before the FW lock. So enable
Markarth project to send the fuse SPL (security patch level)
command to the PSP.
BUG=b:279499511
BRANCH=none
TEST=FW_NAME="Markarth" emerge-skyrim coreboot chromeos-bootimage
Then get "PSP: SPL Fusing Update Requested." in the firmware log.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I8fbbd89d11b1bdb2c95c761955c10bedb366fd70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74753
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds new USB_DB FW_CONFIG to enable support for USB4 ANX7452
Rev 2.
BUG=b:279647370
TEST=Able to build and boot google/rex with Proto 2 SKU
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I878b591e5919d05d3c5fc2eefdeb492e95d4f7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Set edp_panel_t9_ms to 8ms which means it will delay 8ms
between backlight off and vary backlight off.
BUG=b:271704149
BRANCH=Skyrim
TEST=Build; Verify the UPD was passed to system integrated table;
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I952d05b18e29cf30256f43562a5052007c5c6268
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74790
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rename the UPD pwr_on_vary_bl_to_blon to edp_panel_t8_ms to
match the eDP sequence timing in milliseconds.
BUG=b:271704149
BRANCH=Skyrim
Test=Build/Boot to ChromeOS
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Iecdfe47cd9142d8a1ddeee0ec988d37b2a11028e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74787
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The MIPI panels will be used on the detachable variant starmie, and
there will be different MIPI panels used on starmie. In order to make
the different panels functional on unprovisioned devices, it needs
to pass the SKU ID and panel ID to the payload to load the matched
device tree for kernel. From the schematic, the starmie variant
will read the LCM ID from ADC channel 5.
BRANCH=corsola
BUG=b:275470328
TEST=boot starmie and see FW screen display
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: I6339dc3c177fb8982f77fb3bd32dc00da735fce4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
The signals for the NV33 regulator were swapped (enable and power
good). Switch these back to the way they should be:
GPIO_NV33_PWR_EN GPP_E1
GPIO_NV33_PG GPP_E2
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Ic2a53103e1feadd7ecebd4bed02dcc34410b8e3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:274377518
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Change-Id: I1329386631dc54209db54ac146e4aafe95b6a3ac
Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74599
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
By default, coreboot includes support for all the different types of SPI
ROMs. Excluding the unused ROM types shrinks ramstage by almost 4k.
BUG=b:267735039
TEST=Build & Boot ROM
BRANCH=Skyrim
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6e402269d1f2cac8256d478eb36743441497bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72769
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Remove rtd3 for emmc device on taeko
BUG=b:271003060
TEST= emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I21191c9762a00ba137892e680d533f7dc3b53e86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Remove rtd3 for emmc device on taniks
BUG=b:271003060
TEST=emerge-brya coreboot, flash to DUT and can boot to OS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I03168ecbf4611f05acd8c6c722b6a5037a8cc31d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This will fix:
> [INFO ] Probing TPM I2C: tis_plat_irq_status() not implemented,
wasting 20ms to wait on Cr50!
BUG=b:277297687
TEST=builds
Change-Id: I611a2855d94167748d0f82a478687fe2cdf5846a
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74286
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Ensure that DXIO descriptors are updated using info from AMD and Myst
board schematics.
BUG=b:275960920,b:276744321
TEST=builds
Change-Id: Icdad785bcb90de036095bcc4219c15f55f4277fe
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74112
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This mainboard has SD slot available and therefore it should be enabled.
Use the same SD card configuration as for mc_ehl2 mainboard.
Change-Id: Icd9b25301311679cf93b05ba83a24e551261a020
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This mainboard has the RTC RV-3028-C7 connected to the I2C1.
TEST:
- Console Log shows no errors for RV-3028-C7 during I2C1 init
- Finalize device for I2C 00:52 shows correct date and time
Change-Id: I1b4115d7844a0c218fdf92cb1af2da5a95eb4337
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74652
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the USB settings, suitable for this mainboard.
Change-Id: I943eb891e2f2d967acfd441c085063dbad49e993
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74651
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the default
value of the Kconfig switch EARLY_PCI_BRIDGE_FUNCTION must be set to
'0'. On this mainboard NC FPGA is connected to PCIe root port #1
(00:1c.0).
Change-Id: I15035523d8575d486c3f2d0ffe3916712ee89d7d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since mc_ehl4 was only a copy of mc_ehl1 in a first step, the GPIOs must
be adjust according to the circuit diagram for this mainboard.
Change-Id: I66bfbb380e9a05b3a2c08d5d1980e9749b46ee43
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The patch disables Tccold Handshake to prevent possible display
flicker issue for Omnigul board. Please refer to Intel doc#723158
for more information.
BUG=b:279539826
BRANCH=firmware-brya-14505.B
TEST=Verify the build for Omnigul board
Change-Id: I04e54df5afe09c12e1cf774445d57e13ffd8819e
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74737
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
For uni-processor platforms, with SMP=n or MAX_CPUS=1,
neither the LAPIC or IOAPIC MADT entries are added.
Change-Id: I8777f4e3b37fe7b564189c6bf48e3988026b2361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add Kconfig COMMON_ACPI_MADT_IOAPIC to replace platforms'
implementations of adding IOAPIC and IRQ override entries
for ACPI MADT tables.
Platforms that have a more complex MADT may continue to
add custom entries using CUSTOM_ACPI_MADT.
Change-Id: I0b77769f89cc319ad228eb37bc341e2150b8a892
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74348
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
USB port 6 connects to a USB front camera, it should always probe.
Remove probe by rear camera fw_config.
BUG=b:273791621
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot
Change-Id: I554046718f6e0eb7197970f9a3808b3e1ea7f99c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Implement `smm_mainboard_pci_resource_store_init` to store the
resources for XHCI devices. These stored resources are later used by
the elog code to log XHCI wake events.
BUG=b:277273428
TEST=builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I608d51f438681ac529323c23cc707845a3d609d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74281
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the crypto device to the devicetree.
BUG=b:277214359
TEST=builds
Change-Id: I5394c5f9df64642d8633af84cf662652bd1a5cb2
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74275
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix after 'commit 69a13964ea ("sb,soc/amd,intel: Add and use
ACPI_COMMON_MADT_LAPIC")' broke interrupt delivery in kernel.
Apparently combination of LAPIC without IOAPIC is too rare
to be well supported.
Change-Id: I5e2fbf358cf644665b897afb0a9404abb5ca1df2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74472
Reviewed-by: Branden Waldner <scruffy99@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Mendocino and Rembrandt don't have an eMMC controller and also don't
have GPIO pins that eMMC signals can be multiplexed on, so drop the eMMC
related code from Mendocino.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib8ec49a7084bdd62e480baee75a280fde8b13d01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:268342532
BRANCH=firmware-octopus-11297.B
TEST=Observe kernel ec panic handler run when ec panics
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I37e566e459f39f8bc2dafc3c3915260259730ca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74622
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add boxy supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
2. Hynix H54G46CYRBX267
3. Micron MT53E512M32D1NP-046 WT:B
BUG=b:278983561
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I317f2b31774627706babdea10776af05ab692d1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
To aid in layout, the PCI ports for LAN and SD card were swapped.
SD Card is now on RP3 (clksrc 4)
LAN is now on RP8 (clksrc 3)
BUG=b:269371363
TEST=builds
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: If59849c13e4c42f00e3571c0385994ade5931adb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The patch disables PCH USB2 PHY power gating to prevent possible
display flicker issue. Please refer Intel doc#723158 for more information.
BUG=b:279117758
BRANCH=firmware-brya-14505.B
TEST=Verify the build for marasov board
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a5199be768fc59e2f053f8c50a49247145e7e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74627
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The STARYU is the mt8186 detachable reference design, and the STARMIE
is a variant of STARYU. Let's rename the common config from STARMIE
to STARYU, and we can select the STARYU config for the follow up
mt8186 detachable variant.
BRANCH=corsola
BUG=b:275470328
TEST=./utils/abuild/abuild -t google/corsola -a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Change-Id: If75e94e86420b0a216fe7a1a9dee9cb42bbd985c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74654
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post
right after PCI enumeration and handle the command response at
`BS_PAYLOAD_BOOT'.
With these settings we have observed a boot time reduction of about
100ms on google/rex.
TEST=Tests on google/rex with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show
End-Of-Post after PCI initialization and EOP message received at
`BS_PAYLOAD_BOOT'.
Change-Id: I27b540eeddcada521eba91fcc51504831d6dc855
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Select EC_GOOGLE_CHROMEEC_SKUID and EC_GOOGLE_CHROMEEC_BOARDID to
provide common routine for reading skudid and boardid from Chrome EC.
BUG=b:277293398
TEST=builds
Change-Id: I8e42ba23dada9771f335df34275e44e51d645596
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74283
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I5b53765453bac0fc96e9651ab347069c7c8bf058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73384
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN. The purpose of using this mutex is to prevent OSPM from
calling _ON and _OFF methods while WWAN kernel driver is calling _RST,
which accesses the GPIO pins.
BUG=NA
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: I809eb84cb1a09deb168040e83041b65237a1b576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73383
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This adds RTD3 RPMX mutex to the root port. It is shared between RTD3
and WWAN.
BRANCH=firmware-brya-14505.B
TEST=boot to OS and check the generated SSDT table for the root port.
The RPMX mutex should be generated under the root port.
Signed-off-by: Cliff Huang <cliff.huang@intel.com>
Change-Id: Ia87b5f9d8300d6263c84a586256424799d3a45b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73382
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
The mp2 PCI device is still present when no mp2 firmware is loaded. When
this device isn't explicitly enabled in the mainboard's devicetree, the
chipset devicetree default of the device being disabled is used. This
results in coreboot's resource allocator not allocating resources to
the device and since the bridge doesn't have enough MMIO space reserved,
the Linux kernel can't assign resources to it. Enable the mp2 device in
the mainboard's devicetree so that it gets its resources assigned by
coreboot.
BUG=b:277217097
TEST=builds
Change-Id: I21885c51ff08846b456675090946f381843ef5e6
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74277
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because WD SSD drive isn't holding the clock low for some reason.
So we change to read eMMC clkreq signal instead.
BRANCH=none
BUG=b:278495684
TEST=emerge-skyrim coreboot chromeos-bootimage and verify ok.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I3a9225473a6ae1ba01dc8e5d982c4999f073267e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74583
Reviewed-by: Chao Gui <chaogui@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Configure GSC I2C and Interrupt GPIOs during the early initialization.
Add devicetree configuration for GSC device and enable the required
config items.
BUG=b:275959717
TEST=builds
Change-Id: I6e235356b252a7b68a42da128ffd3189a829f117
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74111
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
`is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers,
hence it makes sense to have a unified name across different device drivers.
BUG=b:278310435
BRANCH=firmware-brya-14505.B
TEST=Verified that the _DSD object is still present in the SSDT.
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: I5a69a47e67f6acaad5a5d1b67e437c5a41bebf3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74499
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the boxy variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:277529068
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BOXY
Change-ID: Ief22eb000421c23abf6de3f99eb860bdae1e7919
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add eSPI configuration for myst. Ensure the additional windows are used
and remove unnecessary addresses from the range used on skyrim.
BUG=b:275953893
TEST=builds
Change-Id: I7b40adec78d4e0b596596fa6e2951c79bd3bd8c7
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74110
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the `TcssD3ColdDisable` option in devicetree, as it exists
in Kconfig. The setting is only used on `starlabs/starbook` which
selects D3COLD_SUPPORT so the UPDs will not change.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I50e49e900c96748edd5b678765e47cc0e0d9b280
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74476
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kconfig option SOC_INTEL_TIGERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.
Remove it, and instead use D3COLD_SUPPORT so it's clear what the
option is doing.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id43f3e5c8620d474831cc02fcecebd8aac961687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74405
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PCIe RTD3 support so the NVMe gets placed into D3 when entering s0i3
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I5eac65125c11dd04c5dbb5996c947ad734acdae3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update DXIO descriptors for birman-phoenix per schematic 105-D67000-00B
v0.7
Update devicetree to reference the updated DXIO descriptors.
TEST=boot birman and note the devices show up in the logs correctly
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I76cf6715b60a1857bf58349d70a623bf043594fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Update the EC GPIO values for Birman, per schematic # 105-D67000-00B
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Icd9df120f555eb06f920f6263a8d2ab45c05baec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73971
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Skyrim variants, the eMMC reset GPIO should be SSD_AUX_RST_L (GPIO6).
Update the port_descriptors to link the correct reset GPIO. Data
is from the skyrim variant schematics and go/skyrim-gpios.
BUG=b:278759559
TEST=reboot: 5 iterations
suspend_stress_test: 10 iterations
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I4713b3af23bb7684c9e2e81cf9c8d8a560b41a79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74512
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as crota is using a converged firmware image.
BUG=b:267249674
BRANCH=firmware-brya-14505.B
TEST="FW_NAME=crota emerge-brya
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage"
Cq-Depend: chromium:4430832
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I448c58f93fddc44904c1f5ef3f8939618eff536f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The Kconfig option SOC_INTEL_ALDERLAKE_S3 suggests that it's doing
something with S3, but it's actually disabling D3Cold support.
Rename it to D3COLD_SUPPORT to make it clear what it's doing.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ifc3f19912ac7ee55be8ec7a491598140f9532675
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add supported memory part in mem_parts_used.txt, then generate.
K4UBE3D4AB-MGCL
BUG=b:267539938
TEST=run part_id_gen to generate SPD id
Change-Id: Iee41bb4511f2d77e5ddc2798f9d4db6137ed818d
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74497
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Add boten supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K4U6E3S4AB-MGCL
BUG=b:278138388
TEST=Use part_id_gen to generate related settings
Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com>
Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This patch enables all DDI ports on Rex board to support display port
tunneling and dual display on TBT dock.
BUG=b:273901499
TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality.
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add G2 touchscreen GTCH7503 for craaskino.
Use SSFC to separate touchscreen settings.
Bit 38-41 for TS_SOURCE:
(1) TS_UNPROVISIONED --> 0
(2) TS_GTCH7503 --> 1
BUG=b:277979947
TEST=(1) emerge-nissa coreboot
(2) Test on craaskino with G2 touchscreen
(3) Test on craaskino with elan touchscreen
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I636f21be39f26a617653e134129a11479e801ea2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Create the screebo variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:276814951
BRANCH=None
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_SCREEBO
Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9
Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have
special handling for the time being.
Change of aopen/dxplplusu is coupled with sb/intel/i82801dx.
Change of emulation/qemu-i440fx is coupled with intel/i82371eb.
For asus/p2b, this adds MADT LAPIC entries, even though platform
has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates
the MADT, including an entry for LAPIC address.
Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The 'Starmie' is a mt8186 detachable reference design that will share
most of Corsola design. For AP firmware, there will be a few changes,
mostly in display (MIPI interface and w/o bridge), so we create it
as a variant in Corsola.
BUG=b:275470328
BRANCH=corsola
TEST=./util/abuild/abuild -t google/corsola -b starmie -a
Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a
Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add G2touch touchscreen support for kracko.
BOE NV116WHM-T04 V8.0 with G7500 touch panel sensor IC
BUG=b:277852921
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot & test on DUT
Change-Id: Ic065d5dc2900c6ccfee09031f7a80cefc391f5dd
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74307
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All the variant will use the same dGPU, so make PCIEXP_SUPPORT_RESIZABLE_BARS common.
BUG=b:277974986
TEST=abuild -a -x -c max -p none -t google/brya -b hades
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74371
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The keyboard reset is not being used on this board, so disable the
functionality.
BUG=b:277294460
TEST=None
Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74285
Reviewed-by: Tim Van Patten <timvp@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the GPS_REQUESTDXSTATE function which forces the
current D notifier state to re-report.
TEST=verified that notifications are forced out when invoked using
acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I6dab9b793fe1d0b1c875eddbe6ae324d2894efe6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently the DNOT function first checks to see if the current DNOT
value has already been reported. Add support to allow forcing regardless
if it had been sent already.
TEST=confirmed that when enabled, all events notify. When disabled, only
events on value change are notified.
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I7a93cca6a8f922574dd46b46572b230755db9aa7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Currently the value was being truncated to 4 bytes. Change so that
the full 8 byte value is passed.
TEST=verified function returns expected value using acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: Icfc775de680e328a2b240595223d7098fee3dc3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This function adds support to convert a integer into a 8 byte buffer
TEST=verified returned buffer is as expected using acpiexec
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I89eb50f1452657c26b97eb5609ed956fa8ee8117
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The logic was not equals, rather than the intended greater than or
equal to for checking the minimum GPS revision.
TEST=version check passes as expected now
BUG=b:271938907
Signed-off-by: Tarun Tuli <taruntuli@google.com>
Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73897
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Create the taranza variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:277664211
BRANCH=dedede
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_TARANZA
Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74295
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
