Fixing documentation of PAD_INT macro and replacing spaces with a tab to
match the rest of the documentation.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I72a2578ce21dd10b3beb65c706440c3379f216d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70281
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
The DSI CMDQ offset of MT8186 is different from previous SoCs.
Therefore, we define two versions for DSI register header files. The v1
is for MT8173/MT8183/MT8192 and the v2 is for MT8186/MT8188.
BUG=b:244208960
TEST=build pass
BRANCH=corsola
Change-Id: I3d13ca03b72554ab7be2b194db32a4f961f38dad
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70183
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For geralt project, we also support MIPI panel as our firmware display.
So add this patch to configure ddp to choose eDP display or MIPI panel
display.
BUG=b:244208960
TEST=test firmware display pass for both eDP and MIPI panel on MT8188
EVB.
Change-Id: I06f38b1889811274588c26e9284da4d502acf38b
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70181
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will avoid clearing the other bits in fifo_status.
Change-Id: I7917b3f8d9af6056ed872b7e48cef9c3deba5119
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The devices in the list that was introduced in commit c66ea98577
("soc/intel/alderlake: provide a list of D-states to enter
LPM") are all internal. This CL skips the external buses (which caused
the addition of packages to non-existant paths such as
"_SB.PCI0.RP1.MCHC", and warnings from the kernel)
BUG=b:231582182
TEST=Built and tested on anahera by verifying SSDT contents
Change-Id: I3785b2b2af85d96e2e1296b6cfdefcd72080b5fe
Signed-off-by: Eran Mitrani <mitrani@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70163
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch selects SOC_INTEL_CSE_SEND_EOP_LATE config to let IA
common code to skip sending CSE EOP cmd during finalize operation
rather uses boot state machine (either payload load or payload boot)
to delay in sending EOP cmd to CSE.
BUG=b:260041679
TEST=Able to boot to Google/Rex with this patch and observed ~150ms
savings in boot time
Without this patch:
942:before sending EOP to ME 1,795,702 (354)
943:after sending EOP to ME 1,950,526 (154,824)
With this patch:
942:before sending EOP to ME 2,051,406 (35,484)
943:after sending EOP to ME 2,057,583 (6,177)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7d44d5eff890ac78e3075d49cc249f740686dd0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69999
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch allows to send late EOP cmd to CSE (after CSE .final)
using boot state machine (either BS_PAYLOAD_BOOT or BS_PAYLOAD_LOAD)
if the SoC user selects SOC_INTEL_CSE_SEND_EOP_LATE config.
Rename `set_cse_end_of_post()` to `send_cse_eop_with_late_finalize()`
to make the function name more meaningful with its operation.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If4c4564befcd38732368b21f1ca3e24b68c30e0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch creates an API that can perform essential CSE operation
after sending the late EOP command to the CSE and prior booting to OS.
Lists of operation are
- Perform global reset lock
- Put HECI1 to D0i3 and disable the HECI1 if the user selects
- Set D0I3 for all HECI devices.
BUG=b:260041679
TEST=Able to boot Google/Rex after sending CSE EOP late.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I10131ea9b553a62f0d632783c4dbad96d35d6563
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69977
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors common code to allow cse_final() function to send
EOP cmd if the SoC user selects `SOC_INTEL_CSE_SET_EOP` kconfig.
This patch helps cse_final_ready_to_boot() and
cse_final_end_of_firmware() function for being meaningful with its
operation and let cse_final() being that outer layer to perform three
operations based on the selected kconfig.
1. send cse eop command
2. perform cse_final_ready_to_boot() operations
3. perform cse_final_end_of_firmware() operations
Additionally, ensures the platform that choose to send EOP late
(like JSL and TGL) is not being impacted due to this code refactoring
hence, skip calling into CSE.final if SoC selects
`SOC_INTEL_CSE_SEND_EOP_LATE` config.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I412291c9378011509d3825f9b01e81bfced53303
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69975
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Presently, coreboot supports two instances of sending EOP cmd to
the Intel CSE.
1. Sending EOP cmd to CSE during `.final` operation from cse pci driver.
2. Starting with Alder Lake, the recommendation was to send EOP to CSE
earlier than CSE `.final` operation. Since then it's referred to as
`Sending EOP Early`. This method helped to save the CSE EOP
response time significantly.
During Meteor Lake platform, CSE EOP response time has become
non-deterministic and we have figured that sending EOP command later
than CSE .final operation is actually helping to optimize the boot time
significantly (around ~150ms savings compared to sending from `.final`
ops and ~5sec compared to sending CSE early).
Hence, this patch intended to create yet another kconfig for sending
CSE late (specifically after `.final` operation). The idea for this
newer config is to use the boot state machine for sending CSE EOP cmd.
The patch train in this series would add the specific changes to allow
sending EOP late and perform other essential operations required prior
booting to OS as coreboot decided to skip calling into FSP Notify phase.
Starting with Jasper Lake, coreboot sends EOP before loading payload
hence, this config is applicable for those platforms.
The current plan is that Intel Jasper Lake, Tiger Lake and Meteor Lake
platform will select this newer config from SoC code.
BUG=b:260041679
TEST=Able to send EOP command successfully for Google/Taeko.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iea512cd5b79d61dd5d5a962079baf525027c831f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69976
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures dropping of the duplicate macro introduced with
'commit 9e4488ab06 ("soc/intel/{adl,cmn}: Add/Remove LTR
disqualification for UFS")'
`PCH_PWRM_BASE_SIZE` macro represents the size of the PMC MMIO range
which can be used as is even in ufs.asl file.
BUG=b:252975357
TEST=Build and boot nirwen and see no issues in PLT runs.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic967c609e1330eca1b9e1143e7efd78db011f317
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70180
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The patch logs CSE RO's write protection information for Meteor Lake
platform. As part of write protection information, coreboot logs status
on CSE RO write protection and range. Also, logs error message if EOM
is disabled, and write protection for CSE RO is not enabled.
Port of commit abe0d810f0 ("soc/intel/alderlake: Log CSE RO write
protection info for ADL").
BUG=none
TEST=Verify the write protection details on google/rex.
Excerpt from google/rex coreboot log:
[DEBUG] ME: WP for RO is enabled : YES
[DEBUG] ME: RO write protection scope - Start=0x4000, End=0x396FFF
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Idb072a873a8b8323532799f5fc64f995c9f0a604
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This reverts commit 095c931cf1.
Previously cpu_info() was implemented with a struct on top of an
aligned stack. As FSP changed the stack value cpu_info() could not be
used in FSP context (which PPI is). Now cpu_info() uses GDT segments,
which FSP does not touch so it can be used.
This also exports cpu_infos from cpu.c as it's a convenient way to get
the struct device * for a certain index.
TESTED on aldrvp: FSP-S works and is able to run code on APs.
Change-Id: I3a40156ba275b572d7d1913d8c17c24b4c8f6d78
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The coreboot CPU index for a lapic is arbitrary: it depends on which
CPU obtains a spinlock first. Simply using an increasing index will
result in consistent ACPI tables across each boot.
Change-Id: Iaaaef213b32b33e3ec9f4874d576896c2335211c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69510
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Name a variable based on its utility. `is_external` variable adds
`ExternalFacingPort` _DSD property to an ACPI device hence
rename it to `add_acpi_external_facing_port`.
BUG=b:259716145
TEST=Build google/rex with this flag and verify it in SSDT at
runtime.
SSDT snippet:
Name (_DSD, Package (0x04) // _DSD: Device-Specific Data
{
ToUUID ("6211e2c0-58a3-4af3-90e1-927a4e0c55a4"),
Package (0x01)
{
Package (0x02)
{
"HotPlugSupportInD3",
One
}
},
ToUUID ("efcc06cc-73ac-4bc3-bff0-76143807c389"),
Package (0x01)
{
Package (0x02)
{
"ExternalFacingPort",
One
}
}
})
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I65100283ed9b65037c9890f28ecab41fcfa25d83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69970
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The message only makes sense if ACPI PM base address is
allowed to be dynamic. If requested, it can be logged
in common code.
Change-Id: Iad7a60098c0391cc23384035af49e373dad90233
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Later soc/intel/common/smbus addresses TCO2_STS as a separate
16-bit register, while baytrail and braswell assumes 32-bit
wide TCO1_STS to extend as TCO2_STS.
In src/soc/intel/denverton_ns:
#define TCO2_STS_SECOND_TO 0x02
In soc/intel/baytrail,braswell:
#define SECOND_TO_STS (1 << 17)
Elsewehere
#define SECOND_TO_STS (1 << 1)
It's expected that we remove the first (1 << 17) case and only
access TCO2_STS as a separate 16-bit register. For now, use
unique names to avoid confusion.
Change-Id: I07cc46a9d600b2bf2f23588b26891268e9ce4de0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tree is inconsistent with the use of TCO register space offsets and
related preprocessor defines. The legacy space was offset from ACPI
PM base by 0x60, but this changed with later platforms. The convenient
way is to define the TCO registers relative to its base address and
subtract 0x60 here, but this change cannot be easily done tree-wide or
in one go.
For the transient period, apply TCO_SPACE_NOT_YET_SPLIT flag until
all platforms use a clean style of tco_{read,write} accessor functions
instead of {read,write}_pmbase16(), or worse, inw/outl().
Change-Id: I16213cdb13f98fccb261004b31e81a9a44cb6e3b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch drops the local implementation
`log_me_ro_write_protection_info` and adopts the API from IA common
code (cse_lite.c).
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I087ffb8ac94f14a6bd7f2bf6bb907c4047dc9899
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69969
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch creates an API for CSE-Lite specific SKU to retrieve the
Write Protect (WP) information (`cse_log_ro_write_protection_info`)
like WP range and limit, if the region is write-protected or not etc.
BUG=none
TEST=Able to compile the cse_lite.c file for google/kano without
any error.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8f4b7880534ded5401b6f8d601ded88019c636c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69968
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
These boards do no fill MADT with useful information.
Change-Id: Ie61e4e4b03c9b7fcd70aba7a2bd71eadd6f4dab1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The cpu cluster is always present and it's the proper device to contain
the settings that need to be applied to all cpus. This makes it possible
to remove the fake lapic from devicetrees.
Change-Id: Ic449b2df8036e8c02b5559cca6b2e7479a70a786
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59314
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Set of boards and platforms did not have LINT1 configured
as NMI source.
Change-Id: I65044125562bda363b3a0d92da6137c77a28b587
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69528
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the broadcast ID to deliver LINT1 as NMI to all CPUs,
instead of listing individual LAPIC IDs.
Change-Id: Iaf714d8c2aabd16c59c3bcebc4a207406fc85ca9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A previous CL ("Add missing ACPI device path names",
commit d22500f0c61f8c8e10d8f4a24e3e2bf031163c07) caused some errors
from the Kernel on Brya devices (see Tim's comment on patchset 8):
> ACPI Error: AE_NOT_FOUND, While resolving a named reference
> package element - \_SB_.PCI0.FSPI
FSPI is defined in src/soc/intel/alderlake/chipset.cb:
device pci 1f.5 alias fast_spi on end
This CL adds the corresponding FSPI device to the DSDT to prevent
the error mentioned above.
TEST=Built and tested on brya by verifying the error is gone.
BUG=b:231582182
Change-Id: I11e89ad2a5d47f6b579f755b0a41399ee3cb856c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69920
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this doesn't change any post codes, simply making the
existing post-codes into macros.
picasso/romstage.c did get a couple of post codes removed to match the
other files.
The POST_ROMSTAGE and POST_BOOTBLOCK codes are intended to become global
at some point, while the POST_AGESA and POST_PSP codes would stay AMD
specific.
Change-Id: I007a09b6a3ed3280bac674cd74e298ec5c408ab7
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69867
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.
BUG=b:260183610
TEST=Able to build google/rex.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3c9c5a73028cde90af3553093a13d0c05b831bae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69930
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch refactors the MDIO access for the TSN GbE device by placing
the MDIO read and write functions into mdio_bus_operations struct which
is assigned to the .ops_mdio member of the PCI device struct. In this
way the MDIO interface of the TSN GbE device is exposed and can be used
by other drivers if needed.
Change-Id: I5d1b9dd2f2ba8c18291fff314c13f0c3851784aa
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch skips setting D0I3 bit for all HECI devices by FSP.
The learning being made from Alder Lake platform showed that the CSE
EOP cmd response time is highly nondeterministic and letting the EOP
cmd issued by FSP makes the response time even worse.
The idea being pursued during Alder Lake platform is to let FSP skip sending the EOP cmd and coreboot sends it at the last minute
(late sending of EOP) to ensure there is ample time for CSE to come
to a state where the response to the EOP is almost immediate.
There were a number of refactoring being done to ensure the EOP cmd
can be sent at the later stage.
#1: Ensure FSP is not putting those HECI devices into the D0i3. (SoC specific change)
#2: Modify the CSE related boot state based operation to allow a
proper window for sending late EOP cmd. (Common Code Specific change)
The entire refactoring helps us to save ~60ms of boot time.
Without those code change EOP sending timestamp as below:
943:after sending EOP to ME 1,248,328(61,954))
With those code change EOP sending timestamp as below:
943:after sending EOP to ME 1,231,660 (2,754)
Port of commit d6da4ef69e ("soc/intel/alderlake: Skip setting D0I3
bit for HECI devices") to incorporate the #1 which is a SoC specific
code change.
BUG=none
TEST=FSP-S UPD dump suggested `DisableD0I3SettingForHeci` UPD is
set to `1`.
Excerpt from google/rex coreboot log:
[SPEW ] DisableD0I3SettingForHeci : 0x1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I1c3765ce41f192ab5f5ff176e0a2b49b312d18d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Update the fields that need to be updated directly in the local static
usb_phy_config struct instead of dereferencing the pointer written to
the corresponding UPD field. This will allow updating the type of UPD
field in a follow-up commit to enable 64 bit coreboot builds.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I44a9fe719e6803fc957fee3db13b261489ed313d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69896
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This ports forward part of commit df09680626 ("soc/amd/picasso: Add
support for 64bit builds") to the newer AMD SoCs.
Use -Wl instead of -l to get the output format that the commands in the
Makefile expect to extract the value for PSP_BIOSBIN_SIZE. Without this
change, readelf will split the output into two lines in case of a 64 bit
coreboot build. This results in invalid amdcompress and amdfwtool
command lines which will cause the amdfwtool call to fail with
Error: BIOS binary destination and uncompressed size are required
With the old readelf -l command we get this output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr
FileSiz MemSiz Flags Align
LOAD 0x0000000000000080 0x0000000002030000 0x0000000002030000
0x0000000000010000 0x0000000000010000 RWE 0x10
while we get the correct output in a 32 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000060 0x02030000 0x02030000 0x10000 0x10000 RWE 0x20
With readelf -Wl we also get the expected output in a 64 bit build:
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x000080 0x0000000002030000 0x0000000002030000 0x010000 0x010000 RWE 0x10
TEST=This fixes the 64 bit build on Cezanne with some follow-up patches
applied.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I35f9feda4d0da3546592dfac233ca66732bd5464
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69895
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Skip eDP initialization when we failed to get EDID. This prevents the
PLL assertion in dp_intf_config() if the display could not be
initialized properly.
BUG=b:233720142
TEST=boot to depthcharge on MT8188 EVB.
Change-Id: I0fd672b175feb9b813c1d9ec4140e4273079ff07
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69858
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.
Port the Alder Lake 'commit 6526e78967 ("soc/intel/alderlake: Select X86_INIT_NEED_1_SIPI Kconfig for RPL")' also to Meteor Lake.
Additionally, no performance degradation is observed while running
benchmarks.
BUG=b:211770003
TEST=Able to boot Google, Rex to ChromeOS with all cores enabled.
Without this patch:
30:device enumeration 1,480,217 (28,232)
With this patch:
30:device enumeration 1,472,466 (18,334)
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iec21470b9b34514169789c39bdc3be4e4ff6c7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69851
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For the most part, this just moves the existing post codes into macros
so that they're not just bare numbers.
cache_as_ram.S:
Post code 0x28 was previously pointless with just a single jump between
it and post code 0x29, car_init_done. This code was removed, and the
0x28 value was used to differentiate the car_nem_enhanced subroutine
from the other 0x26 post codes used before calling the clear_car
subroutine.
All other post codes remain identical.
POST_BOOTBLOCK and POST_CODE_ZERO are expected to become global, whereas
the POST_SOC codes are expected to be Intel only.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I82a34960ae73fc263359e4519234ee78e7e3daab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69865
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CBFS_MCACHE is currently experiencing overflow with CBFS verification
enabled. Reduce the pre-x86 cbmem console size from ~5.5 KiB to 4 KiB.
This reduction along with the available free space in PSP shared buffer
(32 KiB) helps to increase the CBFS_MCACHE size from 8 KiB to required
14 KiB.
BUG=b:259342909
TEST=Build and boot to OS in Skyrim. Ensure that there are no CBFS
mcache overflows.
FMAP: area COREBOOT found @ 80a000 (8347648 bytes)
VB2:vb2_digest_init() 0 bytes, hash algo 2, HW acceleration unsupported
CBFS: mcache @0x00019a40 built for 67 files, used 0x19a0 of 0x1c00 bytes
CBFS: Found 'apu/amdfw_a' @0x0 size 0x3ff80 in mcache @0x0001b640
VB2:vb2_digest_init() 262016 bytes, hash algo 2, HW acceleration enabled
Ensure that firmware_CbfsMcache FAFT test is successful.
Change-Id: I35e1a8c6d73e0870b6a43aac604f83a0b6c3aabe
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69827
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The patch parses CPU and PCH Trace Hub modes from the debug area in the
Descriptor Region. The modes can be updated in the debug area in order
to configure the CPU and PCH Trace Hub modes. The debug area's offset
starts from the SPI Flash offset:0xf00.
For runtime debugging, the OEM Section in the Descriptor Region is being
used as debug area. The OEM Section details are documented in the SPI
Programmer Guide of CSE Lite kit.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I61241c5c1981ddc4b21581bb3ed9f531da5f41b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
After DisplayPort is plugged into type-C port, its hpd signal
instantly presents and EC has mux_info for dp and hpd. This change
fixes the DP detection flow to avoid the 1 second delay while no DP
is connected. If DP is present, there will be requests towards PMC
through the sequence of connect, safe mode, dp and hpd mode.
BUG=b:247670186
TEST=Built image and validated the DisplayPort preboot feature on Rex.
Change-Id: I7cb95ec7fcc7e1a86e86466e6d45390eedcc4531
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Set `EnableTcoTimer=1` in order to keep FSP from
1) enabling ACPI Timer emulation in uCode.
2) disabling the PM ACPI Timer.
Both actions are now done in coreboot.
`EnableTcoTimer=1` makes FSP skip these steps in any possible case
including `SkipMpInit=0`, `SkipMpInit=1`, use of the MP PPI or FSP
Multiphase Init. This way full control is left to coreboot.
Port of commit 0e905801f8 ("soc/intel: transition full control over PM
Timer from FSP to coreboot").
NOTE: This will have a huge power impact when it's enabled. If TCO timer
is disabled, uCode ACPI timer emulation must be enabled, and WDAT table
must not be exposed to the OS.
BUG=none
TEST=Boot to OS on google/rex.
Excerpt from google/rex coreboot log:
[SPEW ] EnableTcoTimer = 1
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: I2693f0390e6c9fa92fec366ab87589c3bcea9027
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Get rid of a lot of casts.
Change-Id: I93645ef5dd270905ce421e68e342aff4c331eae6
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Update acpigen_write_alib_dptc() to support extra 5 thermal profiles.
User can use these profiles for dynamic thermal table switching support.
BUG=b:232946420
TEST=emerge-skyrim coreboot
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Change-Id: I9e6d5c0fc6f492340c935899920d9ee7c9396256
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68470
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Issue:
Device can't wake up using power key.
Root cause and solution:
EINT event mask register is used to mask EINT wakeup sources. All
wakeup sources are masked by default. So we add a driver here to unmask
all wakeup sources.
BUG=none
TEST=wake the device up by power key on MT8188 EVB.
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Change-Id: I94b20909b0b8d77f75c41bc745f892baded7a54b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69688
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
On Herobrine, we will determine if we have an NVMe device based on SKU
id. Basically, if bit 0 is 2 (or Z), then we know that we have an
NVMe device and thus will need to go through PCIe initialization.
Otherwise, we know that we are booting an eMMC device.
BUG=b:254281839
BRANCH=None
TEST=build firmware image and boot and make sure we can boot up Tested
on villager, which does not have NVMe and made sure that it boots
still. Check cbmem dump to make sure that device configuration
entry is still low since it's not initializing PCIe devices:
40:device configuration 730,203 (1,295)
Change-Id: I1fa0ad392ba6320fdbab54b3b5dc83ac28cd20ba
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69690
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement mainboard_needs_pcie_init() for herobrine in order to
determine if we need to initialize the pcie links. When the SKU id is
unknown or unprovisioned (for example at the beginning of the factory
flow), we should still initialize PCIe. Otherwise the devices with
NVMe will fail to boot.
BUG=b:254281839
BRANCH=None
TEST=emerge-herobrine coreboot
Change-Id: I8972424f0c5d082165c185ab52a638e8b134064c
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The dimm_info structure (defined in src/include/memory_info.h)
currently does not hold information about the DIMM's
node/controller ID.
This patch extends the dimm_info structure by adding a new field for
the node ID, called node_num. Also, adapt the dimm_info_fill()
function accordingly to populate the newly-added field.
Background: These changes are necessary for the Atlas mainboard, where
we are currently experiencing issues with the DIMMs device/bank
locator. Our 2 DIMMs share the same CHANNEL and DIMM ID but have a
distinct NODE ID. By looking at the smbios table we see
Channel-0-DIMM-0 for both DIMMs. Thus, we need their NODE IDs in order
to distinguish them.
This patch was tested by building and booting for the Alderlake-P
RVP board, which has the same DIMM slot configuration as the
Prodrive Atlas mainboard.
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Change-Id: I6ffa5bdff0ba0e3c4a4a51f2419291fd1278cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68525
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
default SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE value is missing by
accident for SOC_INTEL_COMMON_BLOCK_SGX_PRMRR_SIZE_32MB.
Change-Id: Ib3af0a1c509ab2e2eccf3e36ff604a1040995af4
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69332
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
It is no longer necessary to explicitly add "Warning" in front of
BIOS_WARNING message.
Change-Id: If1645180dd98ff5a1661fd568554de5831ef237e
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69623
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per Intel doc #627331 Section 3.6.1 "Intel CSME Production Machine
Determination", from ADL onwards there are three criteria which
determine whether a device is in production mode:
1. Fuses are programmed
2. SPI descriptor is locked
3. Manufacturing variables are locked
When logging whether the device is in manufacturing mode, 1 and 2 are
already checked. Add a check for 3 as well.
Also add logs for each individual criteria so it's easy to tell why the
overall Manufacturing Mode is set or not.
BUG=b:255462682
TEST=On a nivviks which has not gone through EOM:
Before:
[DEBUG] ME: Manufacturing Mode : YES
[DEBUG] ME: SPI Protection Mode Enabled : NO
After:
[DEBUG] ME: Manufacturing Mode : YES
[DEBUG] ME: SPI Protection Mode Enabled : NO
[DEBUG] ME: FPFs Committed : NO
[DEBUG] ME: Manufacturing Vars Locked : NO
On an anahera which has gone through EOM:
Before:
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: SPI Protection Mode Enabled : YES
After:
[DEBUG] ME: Manufacturing Mode : NO
[DEBUG] ME: SPI Protection Mode Enabled : YES
[DEBUG] ME: FPFs Committed : YES
[DEBUG] ME: Manufacturing Vars Locked : YES
Change-Id: Iac605baa291ab5cc5f28464006f4828c12c748fe
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69324
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update Alder Lake CSME HFSTS registers definitions as per Intel
doc #627331 revision 1.0.0, section 3.4.8.
Follow up CLs will use the bit definitions for performing
various checks.
TEST=build and boot nivviks platform
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Change-Id: I9aeee7a3b41ad59c03391207930a253ffff19ae5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69286
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 1b07797a7b.
Reason for revert: Herobrine program decided that we wanted
to be able to boot from NVMe if one exists.
Change-Id: If675947026095d16b72bdb0f3ec790e583523465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69719
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per Intel doc #729124 Section 3.6.1 "Intel CSME Production Machine
Determination", from ADL onwards there are three criteria which
determine whether a device is in production mode:
1. Fuses are programmed
2. SPI descriptor is locked
3. Manufacturing variables are locked
When logging whether the device is in manufacturing mode, #1 and #2 are
already checked. Add a check for #3 as well.
TEST=Build and boot MTL RVP
Snippet from coreboot log:
[DEBUG] ME: Manufacturing Mode : YES
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I495a7d8730716fc92e8c57b2caef73e8bb44d30b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
The patch updates HFSTS4, HFSTS5 & HFSTS6 register definitions as per
MTL Intel CSME BIOS Specification (doc# 729124). Also, the patch logs
the firmware status details as per the new register definition.
TEST=Build and boot the coreboot on Rex
Snippet from coreboot log with the patch:
[DEBUG] ME: CPU Debug Disabled : NO
[DEBUG] ME: TXT Support : NO
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ibee9a0955efc22ea0d9fdbba2d09e57d8851e22e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69577
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hide these ACPI device so Windows does not warn about missing device
drivers.
Port of commit 907c85ad48 ("soc/intel/alderlake: Hide PMC and IOM
devices").
BUG=none
TEST=Verified _STA method from ACPI tables in OS. USB-C drive is
detected in OS.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Ic62172bee9120d260a3cd60770ef780cb7dce860
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69576
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update header files for FSP for Meteor Lake platform to
version 2404_00, previous version being 2364_00.
FSPM:
1. Address offset changes
2. Rename `PlatformDebugConsent` to `PlatformDebugOption`
FSPS:
1. Address offset changes
Additionally, incorporate the UPD name change for MTL romstage.
BUG=b:255481471
TEST=Able to build and boot Google, Rex to ChromeOS.
Signed-off-by: vjadeja-intel <vikrant.l.jadeja@intel.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I63ef4ecb6569141542a3b9bf4ee8cbcd2946582e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Remove TODO comments after reviwing against morgana ppr #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I598daf40a774ec81a956ce8c1aeb1cbbf4b475f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69275
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Not all functions that call fsp_print_guid print their output with the
BIOS_SPEW log level, so introduce a new log level parameter so that the
caller of fsp_print_guid can specify which log level fsp_print_guid
should use for printing the GUID.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3b37afe703f506d4913f95a954368c0eec0f862d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69599
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clang doesn't understand the -Wstack-usage=40960 option. Replace it
with -Wframe-larger-than=40960.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I7d8b9c26d3fc861615a8553332ed1070974b751b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch uses index 0x10 for IOE P2SB memory resource allocation
instead of static 0.
Additionally, switches to `mmio_resource` from `mmio_resource_kb`.
TEST=Able to build and boot Google/Rex and observed log as below.
Without the code change:
[SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
gran 0 limit 0 flags f0000200 index 0
With the code change:
[SPEW ] PCI: 00:13.0 resource base 3fff0aa0000 size 1400 align 0
gran 0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I44caac73e245f536f3a22baafa1a6a0370e1dd37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested on google/vilboz (running the PCI rom with yabel).
Change-Id: Icd72c4eef7805aacba6378632cbac7de9527673b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Now that we have a common init_tables in all mainboards using AMD SoCs,
both the population of the fch_pic_routing and fch_apic_routing arrays
and the definition of those arrays can be moved to the common AMD SoC
code to not have the code duplicated in all mainboards.
BUG=b:182782749
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Change-Id: I8c65eca258272f0ef7dec3ece6236f5d00954c66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68853
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Explicitly cast integers to fix building for long mode.
Change-Id: I9f56e183563c943d1c2bd0478c41a80512b47c5e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use the newly added functions to iterate over the FSP HOBs to report the
resources used by FSP to the resource allocator instead of open coding
the iteration over the HOBs in the SoC code.
TEST=Patch doesn't change reported resources on Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67ca346345c1fa08b008caa885d0a00d2d5afb12
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use VBOOT_STARTS_BEFORE_BOOTBLOCK to determine whether the VERSTAGE
needs to be build as x86 stage.
Change-Id: I126801a1f6f523435935bb300f3e2807db347f63
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
On newer AMD platforms, mb_pre_fspm() is used to set GPIOs in romstage
for PCIe reset (currently set in bootblock) and touchscreen power
sequencing (not yet implemented, but will be later in the patch train).
Change-Id: Ia422aaa9e80355f9a9f8f850368441e5c8ff6598
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69452
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For extern ethernet PHY access it is necessary to enable the 'scan_bus'
functionality.
Change-Id: I88050df2059ec7e0b27a132bca626eaef3d5dfb0
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69385
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This replaces 'SPDX-License-Identifier' tags in all the files under
soc/mediatek/mt8195 for better code re-use in other open source
software stack.
These files were originally from MediaTek and follow coreboot's main
license: "GPL-2.0-only". Now MediaTek replaces these files to
"GPL-2.0-only OR MIT" license.
Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com>
Change-Id: I79a585c2a611dbfd294c1c94f998d972118b5c52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66625
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This makes it easier to get the content of an msr into a full 64bit
variable.
Change-Id: I1b026cd3807fd68d805051a74b3d31fcde1c5626
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68572
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When no HOB list is found, not only adding the resources reported by the
FSP were skipped, but also adding the GNB IOAPIC resource was skipped.
Fix this bug by moving the reporting of the GNB IOAPIC resource before
the resources reported in the FSP HOBs to not skip the IOAPIC resource
when there's no HOB list.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9174c8d7e5e94144187d27210e12f2dca3a6010f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69460
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is no longer necessary to explicitly add "ERROR: "/"WARNING: " in
front of every BIOS_ERR/BIOS_WARN message.
Change-Id: I22ee6ae15c3d3a848853c5460b3b3c1795adf2f5
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
to soc
Move SMBIOS type 4 override functions from mainboard to soc so that all
xeon family cpus share same functions without implementing again.
Tested=On OCP Deltalake, dmidecode -t 4 shows expected info.
Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com>
Change-Id: I17df8de67bc2f5e89ea04da36efb2480a7e73174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This kind of allocation without '=' is not working with clang.
Change-Id: I2d3e9eb44c3e0e25e5a67c5386e5ddde1487cc74
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63063
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It looks like this code was not finished so it's left commented out
for now.
Change-Id: I442a42e297f2968dd2c824a93a9a1e2bc74ea2f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63074
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit factors out `struct xhci_usb_info` from intel specific code
as it will be useful on other platforms.
BUG=b:186792595
TEST=Builds for volteer
Change-Id: I5b4cc6268f072c6948f11c7498a564d7a5c0a190
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This commit factors out some code for XHCI port status values.
BUG=b:186792595
TEST=Built coreboot for volteer device
Change-Id: I045405ed224aa8f48f6f628b7d49ec6bafb450d7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the \_SB scope, but those
are defined inside the \_SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.
TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the \_SB scope
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
This aligns Picasso more with the newer AMD SoCs and also makes it a bit
clearer what this file does. Also remove the unneeded tabs at the
beginning of each line.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie6e5ee815e4346004bc864a6111a255dc689eae8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
According to measurements Elkhart Lake seems to drive the internal I2C
controllers with 100 MHz instead of the common 133 MHz. The datasheet
itself is quite vague on this definition, just one place mentions that
it is 100 MHz (register description for offset 0x94).
This patch changes the I2C controller base frequency to 100 MHz. The
verification was done by measuring the set up resulting I2C clock for
both 100 and 400 kHz.
Change-Id: I7c826bbb01b53e3661746e49f25441565068d1c2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
On certain mainboards due to hardware design limitations, certain SPI
Read Modes eg. (Dual I/O 1-2-2) cannot be supported. Add ability to
override SPI read modes in boards which do not have hardware
limitations. Currently there is an API to override SPI fast speeds.
Update this API for mainboards to override SPI read mode as well.
BUG=b:225213679
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~25 ms with 100 MHz SPI speeds.
Before:
11:start of bootblock 688,046
14:finished loading romstage 30,865
16:FSP-M finished LZMA decompress (ignore for x86) 91,049
Total Time: 1,972,625
After:
11:start of bootblock 667,642
14:finished loading romstage 29,798
16:FSP-M finished LZMA decompress (ignore for x86) 87,743
Total Time: 1,943,924
Change-Id: I160b56f6201a798ce59e977ca40301e23ab63805
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
This patch introduces support signing and verification of firmware
slots using CBFS metadata hash verification method for faster initial
verification. To have complete verification, CBFS_VERIFICATION should
also be enabled, as metadata hash covers only files metadata, not their
contents.
This patch also adapts mainboards and SoCs to new vboot reset
requirements.
TEST=Google Volteer/Voxel boots with VBOOT_CBFS_INTEGRATION enabled
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: I40ae01c477c4e4f7a1c90e4026a8a868ae64b5ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66909
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel FSPs of XEON server platforms define FSPX_CONFIG
instead of FSP_X_CONFIG, which is expected by coreboot.
Re-define in the common code.
Update coreboot code to use FSP_X_CONFIG consistently.
Tested=On OCP Delta Lake, boot up OS successfully.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ifa0e1efa1618fbec84f1e1f23d9e49f3b1057b32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch groups vboot context, recovery reason and subcode saving, and
reboot calls into two handy functions:
- vboot_save_and_reboot() - save context and reboot
- vboot_fail_and_reboot() - store recovery reason and call function
above
Signed-off-by: Jakub Czapiga <jacz@semihalf.com>
Change-Id: Ie29410e8985e7cf19bd8d4cccc393b050ca1f1c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69208
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Disable Pch PM Energy Report WA was added to enhance boot time
with HFPGA only. SoC needs reporting enabled.
BUG=None
TEST=Build and Boot Google, Rex and Intel, MTLRVP without any boot time regression..
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: If5f1f9c6ab31652977d436a49a3531edffbd60c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69042
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
This patch replaces static index 0 for PMC read resources with PCI
configuration offset 0x10 (PWRMBASE).
TEST=Able to build and boot Google, Rex to OS.
Without this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 0
With this change:
[SPEW ] PCI: 00:1f.2 resource base fe000000 size 10000 align 0 gran
0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iee2523876a8045e70effd5824afc327d1113038b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable x86 SHA accelerator for use by VBOOT library. This is useful when
CBFS verification verifies the hash of the file being loaded in x86.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim. Observe a boot time improvement of
~10 ms with CBFS verification enabled.
Change-Id: I14efe7be66f28f348330580d2e5733e11603a023
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68954
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
RTD3,_ON method sometimes can create delays during system boot.
Even when the power is already up, kernel still tries to call _ON
method to power up device, but it's unnecessary.
RTD3._STA returns device power, so _ON method can check _STA and see
if the power on process can be skipped
BUG=b:249931687
TEST=system can boot to OS with RTD3 pcie storage and save ~80 ms on
Crota. Suspend stress test passes 100 cycles
Change-Id: I296ce1b85417a5dbaca558511cd7fc51a3a38c84
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO debounce timebase bit 4 is only 183uS on Picasso. On the other
SoCs it is 244uS. This affects the 1mS and 2mS actual debounce times
slightly.
Time PCO Others
1mS 0.915mS 1.220mS
2mS 2.013mS 2.684mS
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Id84bef75e6ab134778721ca269d763a4bb2ddde5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69209
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to document 337348-001 (Intel® 300 Series and Intel® C240
Series Chipset Family Platform Controller Hub Datasheet - Volume 2
of 2), the only GPIOs that support PWROK reset are those in the GPD
group. The mappings themselves are correct, but they're assigned to
the wrong communities.
Change-Id: Ib586c987f768ddff31b053f4c108a8526326a7dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69214
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
In function 'set_power_limits' there is a path to bail out early if the
Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS is selected. In this case
reading the MSR PLATFORM_INFO is useless and can be avoided. So read it
right before the value is needed.
This was found by the scanbuild.
In addition, fix an unnecessary line break to increase code readability.
Change-Id: Ibdededdfd56287fb9b9223e78033a3cd6425e1a2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
When using site-local we need to have ability to override
MAINBOARD_BLOBS_DIR with a different location (presumably somewhere in
site-local). site-local Makefiles.inc should be pulled in first
(different CL) allowing MAINBOARD_BLOBS_DIR to be overwritten.
Change-Id: I028042b947887d1182642ad4482dd1bba7ad8e23
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Use the common device ops instead of an soc-specific device ops.
TEST=builds for each soc
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I1804200c3c3f5ab492d237f4b03484c383862caf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add the generic data_fabric_acpi_name function and device ops to common
code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I12053389a12081ddd81912a647bb532b31062093
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Make the data_fabric_acpi_name function more generic, in preparation to
move it to common.
TEST=build chausie, dump ACPI tables, and inspect DFD0 to DFD7
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I77140d8d0d6bf3e048b737de03d18142a6e23c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Morgana/Glinda have a different register mapping for data fabric access,
although the registers themselves are mostly compatible. The register
layouts defined by each soc capture the differences and the common code
can use those.
Move the register offsets to soc headers and update the offsets for
morgana/glinda per morgana ppr #57396, rev 1.52 and glinda ppr #57254,
rev 1.51
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I9e5e7c85f99a9afa873764ade9734831fb5cfe69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Now that the socs have defined the DF FICAA and MMIO Control registers,
update the common code to use them.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia5566f7af6cf5444fc8c627e004dd08185468c77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69073
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The DDR RFIM is a frequency shifting RFI mitigation feature required by
the Intel integrated Wi-Fi firmware(CNVi) for Meteor Lake. Please refer
to Intel technical white paper 640438_Intel_DDR_Mem_RFIM_Policy_Enable
once it is externally available. This change has backport changes from
commit hash 6f73a20 (soc/intel/alderlake: Move CnviDdrRfim property to
drivers) and provides the CNVi RFIM support for Meteor Lake.
BUG=b:248391777
TEST=Booted to OS on Rex. Looked the DDR_DVFS_RFI_CONFIG_PCU_REG
register at the offset 0x5A40 of Mchbar and verified the BIT0
(RFI_DISABLE bit) is 0.
Change-Id: I87110bc10b98a27a8f274680597b15a1df488824
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67789
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Instead of having callbacks into serial console code to set up the
coreboot table have the coreboot table code call IP specific code to get
serial information. This makes it easier to reuse the information as the
return value can be used in a different context (e.g. when filling in a
FDT).
This also removes boilerplate code to set up lb_console entries by
setting entry based on the type in struct lb_uart.
Change-Id: I6c08a88fb5fc035eb28d0becf19471c709c8043d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This reverts commit 3bc9fbb496.
The patch that added hob_enhancedwarningloglib.h was marked as private
after the Jenkins run, so I didn't see and submit it before submitting
the patch that gets reverted by this commit. Temporary revert this patch
to fix the coreboot tree until the issue with the missing patch is
sorted out.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If56609dd2d91a70fe7e99ce86e0341f2b3fee3d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69229
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Patrick Georgi <patrick@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add In Band Error Correction Code to Alderlake SOC's.
It's currently needed and tested for the Prodrive Atlas mainboard.
After enabling it in the UPD, FSP-M takes care of enabling IBECC.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I9cc2ed6defa1223aa422b9b0d8145f8f8b3dd12e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68756
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EWL (Enhanced Warning Log) is a FSP HOB generated by FSP-M that may
contain several warnings/errors related to core, uncore and memory, etc.
mainboard can override it in its romstage.c for its own
Enhanced Warning Log check.
Change-Id: I6f542e71d20307397c398fd757d9408438f681ed
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69143
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The input-gating is an experimental feature (but unfortunately default
enabled) and would lead to crash on MT8188, so we have to disable it
in the firmware stage.
BUG=b:233720142
TEST=CPUfreq in kernel test pass.
Change-Id: Ifd68fe9362587955cdb8598c4cc5c2d0eefe53ca
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69089
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When enabling cpufreq-hw driver, it is required for MCUPM to access
secure registers. Therefore, we enable side-band to allow MCUPM to
access the secure registers.
BUG=b:236331463
TEST=It works well after boot to login shell.
Change-Id: I67b08c38a31a7eae1bc59543a5148a78b61456d6
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69088
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
This reverts commit a8172c329f.
In the aforementioned patch, we allowed MCUPM to access secure
registers and set the domain to DOMAIN_2.
Additional attribute settings are also required when a hardware is
set to a specific domain. Otherwise, there would be violation between
hardware. Since MT8188 is in bring-up stage, we simply enable access
register permission for the DOMAIN_0 by default. So remove the wrong
setting for MCUPM, SCP and SSPM.
We will complete DEVAPC setting when the settings are confirmed.
Change-Id: I5d9809f6e84b8d10bc2e6f2ea5a442e676ad3bf9
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69139
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This change disables support for memory types not used by each of the
chips. This will in turn remove the files for those memory types from
the platform builds.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8c7f47b43d8d4a89630fbd645a725e61d74bc2a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Don't call into disabled memory type code, it won't work.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ie239039b3dd2b5d0a6f8e9230fd3466bb8309761
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields, updated per
glinda ppr #57254, rev 1.51
Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I509eaf5910d8d65ce0956200d7c00451ff9ce864
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields, updated per
morgana ppr #57396, rev 1.52
Update IOMS0_FABRIC_ID and DF_MMIO_NP per referenced ppr.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If64c875026b643c584975f7abffad9b35f1a7b44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I01dcea783542ecc0a761191907c1273016f854c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add structs to define the data_fabric register bitfields.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If7cc94681cd5e282e09455c0ac7d3675884c3cf9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The data_fabric_set_mmio_np function is effectively identical, so move
it to common code.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I58e524a34a20e1c6f088feaf39d592b8d5efab58
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add function needed to generate ACPI backlight control SSDT, along with
Kconfig values for accessing the registers.
Tested by adding gfx register on system76/lemp11. Backlight controls
work on Windows 10 and Linux 6.1.
Change-Id: I1cc33bf0121ff44aea68a7e3615c5e58e2ab6ce2
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69076
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Provide PTS/WAK hooks for ECs like we do for mainboards.
Change-Id: I687254362a896baa590959bd01ae49579ec12c94
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68788
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Don't set bit 2 in _STA in order for Windows not to show a warning about
an unknown device in the device manager for this device. Since the _STA
object just returns a constant, a name definition can be used instead of
a method definition.
TEST=The unknown device with device instance path ACPI\AAHB0000\0
disappeared from the device manager in Windows 10 build 19045 on a
Mandolin board with a Picasso APU.
Just shutting down and then booting it again won't clear some internal
state in Windows, so a reboot is needed instead for the change to become
visible.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cb1712756c3623cc3ea16210af69cde0fa18f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch ensures the P2SB PCI device resource is getting reserved
so that the resource allocator is not assigning this resource to any
other PCI device during the PCI enumeration.
BUG=b:254207628
TEST=Able to ensure on the Google/Rex device, the PCI enumeration
is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3.
Instead the 0xE000_0000 address is being assigned to the P2SB
PCI device.
Without this patch:
[SPEW ] PCI: 00:07.3 resource base e0000000 size c200000 align
20 gran 20 limit ec1fffff flags 60080202 index 20
[DEBUG] GENERIC: 1.0
[DEBUG] NONE
[SPEW ] NONE resource base e0000000 size c200000 align 12 gran
12 limit ec1fffff flags 40000200 index 10
With this patch:
[SPEW ] PCI: 00:07.3 resource base e1000000 size c200000 align
20 gran 20 limit ed1fffff flags 60080202 index 20
[DEBUG] GENERIC: 1.0
[DEBUG] NONE
[SPEW ] NONE resource base e1000000 size c200000 align 12 gran
12 limit ed1fffff flags 40000200 index 10
......
[DEBUG] PCI: 00:1f.1
[SPEW ] PCI: 00:1f.1 resource base e0000000 size 1000000 align
0 gran 0 limit 0 flags f0000200 index 10
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
CB:66943 - commit 8d66fb1a70 (soc/amd: Add amdfw.rom in coreboot.pre)
changed the build flow for the amd firmware binary after glinda was
branched from morgana. Update glinda to match the other SoCs.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I5b0ccaa8c33e59f7146edd6a86f107480c152008
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Adding coreboot's postcodes to the smart trace buffer lets us see the
entire boot flow in one place.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8eb9f777b303622c144203eb53e2e1bf3314afaa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This adds the mendocino specific code for printing the STB data to the
boot log. It still needs to be enabled in the mainboard to be used.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I249507a97ed6c44805e9e66a6ea23f200d62cf66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This allows platforms that support AMD's STB (Smart Trace Buffer) to
print the buffer at various points in the boot process.
The STB is roughly a hardware assisted postcode that captures the
time stamp of when the postcode was added to the buffer. Reading
from the STB clears the data.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8d78c0e86b244f3bd16248edf3850447fb0a9e2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This patch helps to save 10.200ms of booting time without any issue
seen during MP Init. All cores are out from reset and alive.
Additionally, no performance degradation is observed while running
benchmarks.
Refer to Intel Technical White Paper number:751003 for more details.
BUG=b:211770003
TEST=Able to boot to ChromeOS with all cores are enabled.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1886bc5e60c2f6bc1e2f9d3c8d9c11799d2b53c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
This reverts commit 9c2f3cc9d9.
This broke the smihandler for no clear reason on some platforms.
Change-Id: I72da99c019241b627ce8b543937364a53a5fe97b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
a) Add LTR disqualification in D3 to ensure PMC ignores LTR
from UFS IP as it is infinite.
b) Remove LTR disqualification in _PS0 to ensure PMC stops
ignoring LTR from UFS IP during D3 exit.
c) Add Kconfig (SOC_INTEL_UFS_LTR_DISQUALIFY) check to apply
this LTR WA.
BUG=b:252975357
TEST=build and boot nirwen and see no issues in PLT runs
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I88772b0b7dde1fca0130472a38628e72dfd6c26c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch introduces a config option for SoC code to choose
the applicable SoC workaround.
For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE`
to apply UFS OCP timeout disable workaround.
At present ADL SoC only selects so, and in future MTL and others
should check with Intel prior selecting this kconfig.
It's the placeholder to add more workaround in required going forward.
BUG=none
TEST=Able to build and boot Google/Brya.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Enable GPP clk req disabling for disabled PCIe devices. If a clk req
line is enabled for a PCIe device that is not actually present and
enabled then the L1SS could get confused and cause issues with
suspending the SoC.
BUG=b:250009974
TEST=Ran on skyrim proto device, verified that clk reqs are set
appropriately
Change-Id: I6c840f2fa3f9358f58c0386134d23511ff880248
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68139
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently the GPP clk req configuration code assumes that the size of
the config array is `GPP_CLK_OUTPUT_COUNT`. This commit changes that
code to use the `ARRAY_SIZE` macro instead.
BRANCH=guybrush
BUG=b:250009974
TEST=Ran on nipperkin device, verified that clk req settings are
correct.
Change-Id: I3ff555843c6f5aa38acd8300e0dc2da4e33fb4b7
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Factor out the `gpp_dxio_update_clk_req_config` function as it will be
useful for other AMD SoCs.
BUG=b:250009974
TEST=Ran on nipperkin device, verified clk req settings match enabled
devices
Change-Id: I9a4c72d8e980993c76a1b128f17b65b0db972a03
Signed-off-by: Robert Zieba <robertzieba@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68138
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Instead of using magic constants for the fch_pic_routing and
fch_apic_routing array sizes, define FCH_IRQ_ROUTING_ENTRIES in the
common code headers and use this definition. This also allows to drop
the static assert for the array sizes. In the Stoneyridge mainboard code
the equivalent arrays are named mainboard_picr_data and
mainboard_intr_data; also use FCH_IRQ_ROUTING_ENTRIES as fixed array
size there.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d7ee46bd013ce413189398a144e46ceac0c2a10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68818
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define the fch_irq_routing struct once in a common header file instead
of in every mainboard's code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I11d9000b6ed7529e4afd7f6e8a7332c390da6dab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68817
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Crypto engine prefers the buffer from SRAM. CBFS verification may pass
the mapped address of a CBFS file from SPI flash. This causes PSP crypto
engine to return invalid address. Hence if the buffer is from SRAM, pass
it directly to crypto engine. Else copy into a temporary buffer before
passing it to crypto engine.
BUG=b🅱️227809919
TEST=Build and boot to OS in skyrim with CBFS verification enabled using
both x86 verstage and PSP verstage.
Change-Id: Ie9bc9e786f302e7938969c8093d5405b5a85b711
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add region/range of SPI ROM to be verified by Google Security Chip
(GSC).
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.
Change-Id: If8a766d9a7ef26f94e3ab002a9384ba9d444dd1f
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Do not compress PSP BIOS image when CBFS verification is enabled.
Otherwise when a file is added to CBFS, cbfstool is not able to find the
metadata hash anchor magic in the compressed PSP BIOS image.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled for
both x86 and PSP verstage.
Change-Id: Iaed888b81d14ede77132ff48abcfbeb138c01ce4
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
With CBFS verification enabled, CBFS file header + file name + metadata
consumes more than 64 bytes. Hence reserve additional space aligned to
the next 64 bytes.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.
Change-Id: I2b7346e2150835443425179048415f3b27d89d89
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66944
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change ensures that amdfw.rom binary containing metadata hash
anchor is added before any file is added to CBFS. This will allow to
verify all the CBFS files that are not excluded from verification.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled using
x86 and PSP verstages.
Change-Id: Id4d1a2d8b145cbbbf2da27aa73b296c9c8a65209
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
To enable RO CBFS verification in AMD platforms with PSP verstage,
metadata hash for RO CBFS is kept as part of verstage. This means any
updates to RO CBFS, before WP is enabled, requires updating the
metadata hash in the verstage. Hence keep the metadata hash outside the
signed range of PSP verstage. This means the metadata hash gets loaded
as part of loading PSP verstage while still being excluded from the
verification of PSP verstage.
This change keeps the metadata hash outside the PSP footer data. This
will help to keep it outside the signed range of PSP verstage & aligned
to 64 bytes.
BUG=b:227809919
TEST=Build and boot to OS in Skyrim with CBFS verification enabled with
both x86 and PSP verstage.
Change-Id: I308223be8fbca1c0bec8c2e1c86ed65d9f91b966
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68135
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add build rules to build amdfwread tool. Also mark this as a dependency
either while building tools or amdfw.rom.
BUG=None
TEST=Build and boot to OS in Skyrim with CBFS verification enabled.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I3fee4e4c77f62bb2840270b3eaaa58b894780d75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66939
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only edk2 used this to fill in a different struct but even there the
entries go unused, so removing this struct element from coreboot has
no side effects.
Change-Id: Iadd2678c4e01d30471eac43017392d256adda341
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This patch moves DRIVERS_INTEL_USB4_RETIMER config from Meteor Lake
SoC to Rex mainboard to maintain the symmetry with previous
generation ChromeOS devices (Brya and Volteer).
BUG=none
TEST=Able to build and boot to Google/Rex with USB4 functionality
remaining intact.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I38360f6f1f2fcb4b0315de93c68f00d77e63003c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This adds the initial framework for the Glinda SoC, based on what's been
done for Morgana already.
I believe that there's more that can be made common, but that work will
continue as both platforms are developed.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: I43d0fdb711c441dc410a14f6bb04b808abefe920
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Add system agent ID for RPL QDF# Q271
TEST=Tested by ODM and "MCH: device id a71b (rev 01) is Unknown" msg is
gone
Signed-off-by: Lawrence Chang <lawrence.chang@intel.corp-partner.google.com>
Change-Id: I6fd51d9915aa59d012c73abc2477531643655e54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
When CONFIG_DEBUG_SMI is enabled SMM handler performs console hardware
initialization that may interfere with OS. Here we store the state
before console initialization and restore state before SMM exit.
Tested=On not public yet system, after exiting smm, uart console can
still work well.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa5042c24f0e3217a75971d9e6067b1d1f56a484
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
After some measurements it turned out that Elkhart Lake uses a higher
CSR clock internally from which the MDIO clock is derived. In order to
stay compliant with the specification, the MDIO clock needs to be lower
than 2.5 MHz. Therefore, the divider needs to be 102 and not 62.
This patch changes the define to match the new divider value and uses
this new define at the appropriate place.
Test=Measure the MDIO clock rate on mc_ehl2 which results in 2 MHz.
Change-Id: Idf498c3547530dfa395f54488ef244e787062e34
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Depending on the real workload that is executed on the system the L1
prefetcher might be too aggressive and will populate the L1 cache ahead
with data that is not really needed. In the end, this will result in a
higher cache miss rate thus slowing down the real application.
This patch provides a devicetree option to disable the L1 prefetcher if
needed. This can be requested on mainboard level if needed.
Change-Id: I3fc8fb79c42c298a20928ae4912ee23916463038
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68667
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8188, the SPDX identifiers are all GPL-2.0-only OR MIT, so
replace "GPL-2.0-only" with "GPL-2.0-only OR MIT".
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5ef6c488b7ef937f6e298670ea75d306b9fe7491
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68759
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- For display, only vdosys0_pwr_con and edp_tx_pwr_con settings are
required.
- For audio, it requires powering on adsp_ao_pwr_con,
adsp_infra_pwr_con and audio_pwr_con.
- Add new power domain data `ext_buck_iso_bits` for buck isolation
control.
BUG=b:244208960
TEST=access display registers successfully.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I7f00bda0cc5c7f8dea55a564a0ff10ae601115b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The SPM register at offset 0x0 is often named as poweron_config_set in
previous MediaTek SoCs. To use common driver, we rename it from
poweron_config_en to poweron_config_set.
BUG=none
TEST=emerge-geralt coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I31dbf09d668844d3ee74790c657a2ab076e8cdf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68486
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8195 supports 2P mode and MT8188 supports 1P mode. A new struct
member `input_mode` is added to `struct mtk_dpintf` for
differentiation. We also move SoC-specific data `dpintf_data` to soc
folder.
BUG=b:244208960
TEST=emerge-cherry coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I6d138b0ff75e005518bc8fcce06df20924b2a6ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
DP drivers can be shared for both MT8195 and MT8188, so move them to
common folder.
BUG=b:244208960
TEST=emerge-cherry coreboot.
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Ic80c03aa6b13e6c9c39fd63b5c1c1cbdbe93a7c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This is the enum value to initialize the Smart Trace Buffer's
Spill-to-DRAM feature. More information on how this is used is
available in the STB Linux kernel driver.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Iab2e5fb121902959ddd0e7c8cca930a327b69291
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Update the MCA bank names for morgana per PPR #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: If0082bd5362bdead3f9dc693d1e338e8cda224f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For recent X86 CPUs, the 0x15 CPUID instruction will return Time Stamp
Counter Frequence. For CPUs that do not support this instruction, EDK2
must include a different library which is the reason why this must be
configured at build time.
If this is enabled, and the CPU doesn't support 0x15, it will fail to
boot. If is not enabled, and the CPU does support 0x15, it will still
boot but without support for the leaf. Consequently, disabled it by
default.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I4f0f43ce50c4f6f7eb03063fff34d015468f6daa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Working with resources in KB is tedious and the base_k / size_k variable
naming was simply wrong in one case.
Change-Id: Ic5df054e714d06c9003752ed49dc704554e7b904
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68406
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TOLUD stands for top of lower usable dram. Memory between cbmem_top and
TOLUD, even if stolen for another device/purpose can still be marked WB
cacheable. This will result in a cleaner MTRR setup.
Change-Id: Ic3d6f589c60e44a3dce9122d206397cac968647f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68405
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.
BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Make GPIO_I2C_MASK macro more accurate by using the GPIO_I2Cx_SCL
definitions instead of BIT(x).
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I13fc376552068a64768fe1cf9f1c09cca1768aed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
On nissa, the pre-x86 time is not part of the 1s firmware boot time
target. Including the pre-x86 timestamps causes confusion since the boot
time appears to be greater than 1s, so disable the Kconfig on nissa.
We're not doing any analysis or optimisation of the pre-x86 time on
nissa anyway, this work will start from MTL onwards. Also, the Kconfig
is already disabled on the brya firmware branch, so this will result in
the same behaviour as brya.
Before:
Total Time: 1,205,840
After:
Total Time: 995,300
BUG=b:239769532
TEST=Boot nivviks, check "1st timestamp" is the first timestamp.
Change-Id: I885071c9e0ff9c8fac9444b382567d38a19c3c15
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68553
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On MT8186T, the big cores are powered on by MT6315 via PMIF. This
patch adds the following changes.
- Add MT6315 settings.
- Configure PMIC PMIF for MT6315.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: Id01931e564b0b5002b8d6b9d13d4f32cdf0ae708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68620
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPMI interface configuration is SoC-dependent.
- MT8192 and MT8195 are the same.
- MT8186 does not need to implement this.
- MT8188 is different from MT8195, and we will submit another patch to
fix this.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I4cf508a0690995a7fe7b7316269d07cb7a799191
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68619
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For MT8186, PMIF_SPMI mode is the hardware default setting, so we don't
need to configure PMIF SPMI IO pins. Add a config to control that.
BUG=b:249436110
TEST=build pass.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I92b54e8379a5dec55ef95cbd72ce03abd3a4954b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68578
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8186 has two slightly different versions: MT8186G and MT8186T
(turbo version). Add get_cpu_id() to identify different CPUs.
BUG=b:249436110
TEST=cpu id is correct.
BRANCH=corsola
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I0612dd589e11853dbddc1d99526e9c9bf170acec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68576
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update the SMI definitions for morgana per PPR #57396, rev 1.52
Remove references to dropped SMITYPE_XHC2_PME in xhci.c to fix compile
errors.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6a9f05bcc6a6e4c94114ccbd07628629bdfabcba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows us to see which of the common code blocks have been verified
and which have not.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Icb9eba5838013de75c408c28a4a7d3afacdf0674
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch adds the support to enable/disable skipping MBP HOB
from the devicetree based on mainboard requirement.
Porting the feature from commit 2bc54e7c00
("soc/intel/alderlake: Add support to skip the MBP HOB")
TEST=Build and boot to verify that the right value has been passed to
the FSP.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: I360d33617b9d2626fce5600e861214b0747f57b4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Now that the SoC-specific UART controller data and the common code part
are cleanly separated, move the code to the common AMD UART support
block folder. The code is identical to the UART code in Cezanne,
Mendocino, Morgana and Picasso while Stoneyridge doesn't use the parts
related to the MMIO device driver.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id9429dac44bc02147a839db89d06e8eded7f1af2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I813483bc0421043dc67c523f0ea2016a16a29f60
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I80278f1a098b389d78f8e9a9fb875c4e466dc5db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8cfea274f4c9e908c11429199479aec037a00097
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iab1aec44c55570aa8085aeaf68ec69fe6de0f2ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use soc_get_uart_ctrlr_info to access the uart_info array
to further decouple uart_info from the code as preparation to factor out
most of the code to a common implementation. In order to slightly reduce
the number of function calls, pass the size of and pointer to uart_info
to get_uart_idx as a parameter instead of calling again
soc_get_uart_ctrlr_info in get_uart_idx despite all callers already
having the information form the soc_get_uart_ctrlr_info call.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I474e47059eaebcf0b9b77f66ee993f1963ebee77
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Initialize the two GPIOs of the SoC UART if it's used for serial console
to be sure that the I/O mux is configured correctly without having to
rely on the bootblock_mainboard_early_init call to do this. This brings
Stoneyridge more in line with the other AMD SoCs. Since this code will
be factored out to the common AMD SoC code in a follow-up patch, the
function prototype is added to southbridge.h instead of creating a new
uart.h header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id4aa6734e63dad204d22ce962b983cde6e3abd62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
soc/iomap.h provides the UART base address information used in the
uart_info struct.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7defd135dc888cfc7d6e1c106d72116425560576
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Introduce and use an array of soc_uart_ctrlr_info to align Stoneyridge
with the other AMD SoCs in order to allow commonization of the AMD SoC
UART code. Since the current Stoneyridge code doesn't provide or use
UART MMIO device operations, only the base addresses of the UART
controllers from this array are used for now.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie868cd3e2f77b0f7253c9f6d91dd3bbc3e4b6b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The SoC's uart_info structs all use the same anonymous uart_info struct
definition, so create a named struct for this in the common AMD SoC UART
header and use it in the SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id183a3c838c6ad26e264c2a29f3c20b00f10d9be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib893720911114d61ee6b3fbbf1a2a3594500bcfc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5077681b64dd68351340bd179838a174d8df1701
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0e585370a0de56787340788acfecc7931820566d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The goal of this is to be able to move most of the code over to the
common AMD blocks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia496a4b29b25d4438ed8fc09bfe6f83e3fb768d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
We are required to boot with eMMC enabled in the BIOS to store modem
calibration data. Thus, it doesn't make sense to enable NVMe at boot
time since we will never boot from NVMe w/o eMMC. We may as well take
the boot time reduction (~100ms) by eliminating NVMe initialization.
BUG=b:185426670, b:254281839
BRANCH=None
TEST=Boot after disabling NVMe and make sure that it still boots
Note that we are able to see a little over 100ms in boot time
savings with this change.
Before: 40:device configuration 824,021 (102,701)
After: 40:device configuration 717,402 (44)
Cq-Depend: chromium:3964185
Change-Id: I94f614ba0369c073617949285c0781aef5c6263f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch drops `ufs.asl` from the local SoC directory.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I84e0b51e74e2d6a7120f1d990152bc27e37a501f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68302
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
This patch includes UFS ASL entry from common block ACPI code.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia77ea1c915d0dec991afa5b977af78487ae6a8b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68301
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
This patch migrates UFS ASL entry from Alder Lake SoC to common
block ACPI code to be able to be utilized across different IA SoCs.
Additionally, migrate to ASL2.0.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2e803138a20fd1fc3cdcd5c0fbbb1254663bb8dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68300
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I59985f283f1694beeacb0999340111146fa3f39b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Move i2c SoC related code from early_fch.c to i2c.c
TEST=build boards for each SoC
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I69d4b32cf95ce74586bd8971c7ee4b56c1c2fc04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Update the GPIO definitions for morgana per PPR #57396, rev 1.52
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I7fa4aaf81b5487f7548f430cb35630aca8be732f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This code is identical for all non-CAR AMD SoCs, so factor it out to
soc/amd/common/block/cpu/noncar/bootblock.c to avoid code duplication.
Also integrate the bootblock.c improvement to include cpu/cpu.h which
provides cpuid_eax from commit 68eb439d80 ("soc/amd/picasso: Clean up
includes").
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I42e4aa85efd6312a3ab37f0323a35f6dd7acd8e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Rename soc/amd/common/block/cpu/smm/smi_ampc_helper.c to smi_apmc.c and
add the fch_apmc_smi_handler function.
Remove the duplicated function from picasso, cezanne, mendocino, and
morgana SoC.
The stoneyridge soc does not implement the APM_CNT_SMMINFO handler, so
give the handler a unique name that does not conflict with the common
handler name.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I2e6fb59a1ee15b075ee3bbb5f95debe884b66789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68441
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9377c3b65aa342f754c303148b0b8d826d05bb94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67662
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1f6e5344cab2af7aa6001b9ec0f07b043a9caa8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Cezanne has two SATA controllers, but doesn't select
SOC_AMD_COMMON_BLOCK_SATA, so it's not added to the SATA devices in the
Cezanne chipset devicetree.
Change-Id: If7f0a9638151cf981d891464a2c3a0ec5fc9c780
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This removed the need to maintain a PCI driver.
Change-Id: I43def81d615749008fcc9de8734fa2aca752aa9d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This removes the need for a PCI driver.
Change-Id: I6674d13f434cfa27fa6514623ba305af6681f70d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This removes the need for a PCI driver.
Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
This patch creates helper header file (ufs.h) for UFS to keep
required registers details and ACPI device id for UFS.
BUG=none
TEST=Able to build and boot Google/Kano.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: If08c54eb706876a4255542a708aa5fcd8bf43c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68299
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add DEVAPC permission settings for ADSP and set its domain number to 6.
TEST=SOF driver is functional.
BUG=b:204229221
Change-Id: I37bfea70386af953e89f3c38ac51e41af6aafa6e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68290
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To use SOF correctly, we need to initialize ADSP in coreboot stage.
TEST=SOF driver is functional.
BUG=b:204229221
Change-Id: I45db587252ccdcdf75e0be2029743034a79925c5
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68289
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To use SOF correctly, we need to enable power domain of ADSP.
TEST=SOF driver is functional.
BUG=b:204229221
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: I39d1357af5f901a91379fdf7e595f16952b962de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68288
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To use SOF correctly, we need to enable ADSP clock.
TEST=SOF driver is functional.
BUG=b:204229221
Signed-off-by: Mandy Liu <mandyjh.liu@mediatek.com>
Change-Id: Ia17db889829df2668cf2af1b71c6468230de68e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68287
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current SMBIOS for coreboot is missing processor info for Alder Lake and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements voltage function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS processor voltage value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I77712b72fa47bdcb56ffddeff15cff9f3b3bbe86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68023
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current SMBIOS for coreboot is missing processor info for Alder Lake
and Raptor Lake SoC, specifically, voltage, max speed,
and upgrade (socket type). This patch implements max speed function.
Refer to SMBIOS spec sheet for documentation:
https://web.archive.org/web/20221012222420/https://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.6.0.pdf
BUG=NONE
BRANCH=firmware-brya-14505.B
TEST=Boot and verified that SMBIOS max speed value is correct.
Signed-off-by: Zhixing Ma <zhixing.ma@intel.com>
Change-Id: I09bcccc6f97238f7328224af8b852751114896fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67913
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The northbridge ops should be added to the actual northbridge and not
the first HT device. Neither of the devices has BARs on it, so
read_resources implementation will still work correctly.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2e5f21bfe5fff043d7d9afafa360764203dd61f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68409
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stoneyridge is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime. In contrast to the other AMD
SoCs in the coreboot tree the PC driver used the PCI ID of the first HT
PCI device function, so add the ops to the device 0x18 function 0
devicetree entry in this patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I500521701479aa271ebd61e22a1494c8bfaf87fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id668587e1b747c28207b213b985204b7a961a631
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68410
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add chipset devicetrees for Stoneyridge and Carrizo, which is also
supported by the Stoneyridge code, but has more external PCIe ports and
devices. The mainboard's devicetrees will be changed to use the aliases
defined in the chipset devicetree in follow-up patches. This is a
preparation to statically assign the ops for the internal devices
statically in the SoC devicetree instead of dynamically adding them in
ramstage.
BKDG #55072 Rev 3.04 was used to check the PCI devices and functions and
the MMIO addresses.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia45260b1168ed1d99993adfb98475da5b5c90d11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68316
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need for a PCI driver.
Change-Id: I4b499013a80f5c1bd6ac265a5ae8e635598d9e6c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This removes the need for a PCI driver.
Change-Id: I8e235d25622d0bd3f1bb3f18ec0400a02f674a6d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This removes the need for a PCI driver.
Change-Id: Id25016703d1716930d9b6c6d1dab5481b10aca17
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68145
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Morgana is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I67362ae4a32bc9b1dd19ee5e4caf42db8f5dd1bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68311
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Mendocino is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: I5619c8ad42cdeb019cb7294da884909df64a2211
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Cezanne is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: If535221335217cee53bca956747e7f17f0a5fd8d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Picasso is a SoC so it makes sense to statically use ops instead of
matching them to PCI DID/VID at runtime.
Change-Id: Ide747c9d386731af89b27630b200676c6e439910
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67743
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This removes the need for a lot of boilerplate code in the soc code to
hook up device_operations to devices.
Change-Id: I2afc1855407910f1faa9bdd4e9416dd46474658e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67738
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This allows for reduced use of chip_operations in the followup patch and
allows the allocator to skip over the used mmio.
Change-Id: I4052438185e7861792733b96a1298201c73fc3ff
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
The psp_verstage/svc.h SVC_CALLx macros are virtually
identical between picasso/cezanne/mendocino, so move
to common.
TEST=timeless builds are identical
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I86a8d9b043f68c01ee487f2cdbf7f61934b4a520
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This reverts commit 4b5ba94363.
Reason for revert: This optimization is causing the non-serial enabled
tot BIOS to not boot. To get tot back into good shape, will revert
for now and reevalute this fix and resubmit at a later time.
BUG=b:218406702
BRANCH=None
TEST=reboot from AP console (on herobrine) after flashing
image-herobrine.bin.
prior to fix the device would never boot to login prompt.
after rever the device would boot to login prompt again.
Change-Id: Iaac5f2fb2120f6aa41a0ce9a763d50fd7b9a3ec7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Function 'setbits16' performs an 'OR' operation with the new data and
the origin register entry. This can lead to an incorrect value in the
register which can then lead to issues.
Change-Id: I0212420be770e2ffdabebbfaf5dfbf8d99d25915
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Makes it possible to configure the maximum allowed/supported DDR memory
frequency on a per mainboard basis.
Test
- Define maximum memory frequency in mainboard devicetree.cb
- Boot into Linux and run 'sudo dmidecode --type 17' to check memory
speed
- Boot into Linux and run 'phoronix-test-suite benchmark ramspeed'
Change-Id: I9e0c7225e2141e675a20b8e3f0dbe8c0b3a29b28
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68097
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
This is not critical functionality and doesn't need a build-time error.
Having it as a build time error causes a chicken & egg issue where
the chipset needs to be added before it can be added to this file, but
the header file fails the build because the chipset is unknown.
It's not practical to exclude these files from the new platform builds
because the PSP functionality is thoroughly embedded into the coreboot
structure.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: Ib02bbe1f9ffb343e1ff7c2bfdc45e7edffe7aaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
This is an initial framework for the Morgana SoC.
TODOs have been added to the files for both customization and
commonization.
Signed-off-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Change-Id: If92e129db10d41595e1dc18a7c1dfe99d57790cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68195
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel document number 336561, GLK has UFS (0x1d),
so add the PCI interrupt.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I68bac590bd1a9a0b8213440e882c8f431f06c95f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67680
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel document number 336561, G, SD Card (0x1b)
does not exist on GLK, so remove it.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6921fc3db430c76ec54cf832ce51c627a507385c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67679
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To be able to change the MAC addresses, it is necessary that the
controllers are in D0 power state. As of FSP MR3, Intel has set the
controllers to D3 power state at the end of FSP-S TSN GbE
initialization. This patch sets the state back to D0 before the
programming of the MAC addresses.
Test:
- Build coreboot with FSP MR4 for mc_ehl2 mainboard
- Boot into Linux and check MAC addr via 'ip a'
Change-Id: I4002d58eb4332ba45c35d07820900dfd2c637f21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
apu/amdfw_a was only getting added to CBFS when VBOOT_SLOTS_RW_AB was
selected, but needs to be added in the RW_A only case as well
(VBOOT_SLOTS_RW_A). Since VBOOT_SLOTS_RW_AB selects VBOOT_SLOTS_RW_A,
we can guard amdfw_a and _b separately and both will be added in the
RW_AB case.
TEST=build google/zork with VBOOT_SLOTS_RW_A or VBOOT_SLOTS_RW_AB
selected, ensure amdfw_a and amdfw_b are added to correct CBFS regions
as appropriate.
Change-Id: Ic8048e869d7449eeb1ac10bfec4a5646b848d6a8
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68126
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
apu/amdfw should be restricted to the RO region only when building with
VBOOT + any RW region (RW_A or RW_A + RW_B); it is not tied to ChromeOS
in any way. Fix guarding to match newer AMD platforms (eg, CZN/MDN).
TEST=build google/zork without CHROMEOS, with VBOOT_SLOTS_RW_A
Change-Id: I32d7fa7a4b3d41107cfdba96128a4a75f7066c6f
Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68125
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
RaptorLake introduces the support of the Voltage Regulator Fast Vmode
feature. When enabled, it makes the SoC throttle when the current
exceeds the I_TRIP threshold. This threshold should be between
Iccmax.app and Iccmax and take into account the specification of the
Voltage Regulator of the system.
This change provides a mean to:
1. Enable the feature via the `vr_config->enable_fast_vmode'. If no
I_TRIP value is supplied FSPs picks an adapted I_TRIP value for
the current SoC assuming a Voltage Regulator error accuracy of
6.5%.
2. Set the I_TRIP threshold via the `vr_config->fast_vmode_i_trip'
field.
These new fields are considered independent from the other `vr_config'
fields so that the board configuration does not have to unnecessarily
supply other VR settings to enable Fast VMode.
Information about the Fast VMode Feature can be found in the following
Intel documents:
- 627270 ADL and RPL Processor Family Core and Uncore BIOS
Specification
- 724220 RaptorLake Platform Fast V-Mode
- 686872 RaptorLake Lake U P H Platform
BUG=b:243120082
BRANCH=firmware-brya-14505.B
TEST=Read I_TRIP from the Pcode and verify consistency with
a few `enable_fast_vmode' and `fast_vmode_i_trip' settings.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I313acf01c534d0d32620a9dedba7cf3b304ed2ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I14c5933b9022703c8951da7c6a26eb703258ec37
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, after the PCIe link is initialized, we wait 100ms every
time the link is not up anymore. However, this causes significant
delay. Assuming the first check is false, we'd like to increase the
frequency of checks for the link to be up. Changing to check every
10ms instead. This seems to save about 90ms in the device
configuration stage of bootup on herobrine.
BUG=b:218406702
BRANCH=None
TEST=reboot from AP console (on herobrine)
prior to fix (from cbmem dump):
40:device configuration 919,391 (202,861)
after fix (from cbmem dump):
40:device configuration 826,294 (112,729)
Change-Id: Ic67e7207c1e9f589b34705dc24f5d1ea423e2d56
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Reviewed-by: mturney mturney <quic_mturney@quicinc.com>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Intel Core i5-10210U can have the following IGD Device IDs
0x9B21/0x9B41/0x9BAC/0x9BCA/0x9BCC according to Intel ARK. Some of
these IDs were not present in coreboot source nor hooked to the
common graphics driver. Add the missing IDs so that the graphics
driver will probe on the mentioned processor and detect the
framebuffer.
TEST=Boot Protectli VP4650 with i5-10210U and see framebuffer is
detected when using FSP GOP and libgfxinit.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Iee720a272367aead31c8c8fa712bade1b6e53948
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67975
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The delayed return of certain fetch instruction from memory to
the UFS causes the OCP fabric to timeout on the transaction
and become non-responsive.
As recommended by the SoC and IP teams,program the
OCP fabric register to avoid the timeout in the OCP fabric.
This patch adds the following changes
1. Program the OCP fabric registers in the PS0 routine.
2. Move the ssdt contents of UFS to dsdt asl code to avoid
duplication of UFS device creation
BUG=b:240222922
TEST=Build and boot Nirwen UFS board, observe no system hang
during Chrome PLT test.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I949a4538ea5c5c378a4e8ff7bb88546db1412df2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Copy AMD PSP fw hash table into memory, then pass it to the PSP.
The PSP will use this hash to verify it's the correct firmware bundled
with coreboot build and not replaced.
BUG=b:203597980
TEST=Build Skyrim BIOS image with the hash table and boot to OS after
PSP verified the binaries against the hash table.
Change-Id: I84bea97c89620d0388b27891a898ffde77052239
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60291
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add build rules to separate signed PSP/AMDFW. Also add build rules to
add the generated hash table containing SHA digest of individual PSP FW
components into CBFS. This will allow verified boot to load and verify
less components from SPI rom which means faster boot time.
BUG=b:206909680
TEST=Build Skyrim with modified fmap and Kconfig
Change-Id: If54504add72b30805b6874bee562e0b9482782b9
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67260
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling this config will put signed amd firmwares into
SIGNED_AMDFW_[AB] region which is outside FW_MAIN_[AB]. Vboot only
verifies FW_MAIN_[AB] so these regions will not be verified by vboot,
instead the PSP will verify them.
As a result we have less to load and verify from SPI rom which means
faster boot time.
BUG=b:206909680
TEST=Build Skyrim with modified fmap and Kconfig.
Change-Id: If4fd3cff11a38d82afb8c5ce379f1d1b5b9adfbf
Signed-off-by: Kangheui Won <khwon@chromium.org>
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59867
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id8573217d3db5c9d9b042bf1a015366713d508c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67981
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Also include arch/mmio via device/mmio.h and not directly to have the
[read,write][8,16,32]p helper functions available.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I51c6f5c73b41546b304f16994d517ed15dbb555f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67980
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
use is_enabled_cpu() on cycles over device list to check
whether the current device is enabled cpu.
TEST: compile test and qemu run successfully with coreinfo
payload
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: If64bd18f006b6f5fecef4f606c1df7d3a4d42883
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67797
Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Use just one function to get the chipset powerstate and add an argument
to specify the powerstate claimer {RTC,ELOG,WAKE} and adjust the
failure log accordingly.
TEST: compile tested and qemu emulation successfully run
Signed-off-by: Fabio Aiuto <fabioaiuto83@gmail.com>
Change-Id: I8addc0b05f9e360afc52091c4bb731341d7213cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Issue:
Camera APP is not functional after CB:67434 applied.
Root cause and solution:
SCP hardware needs to access H264 encoder registers, so we need to
remove the DEVAPC protection of H264 encoder for SCP.
BUG=b:247743696
TEST=camera APP is functional.
Signed-off-by: Runyang Chen <runyang.chen@mediatek.corp-partner.google.com>
Change-Id: I95946346018bff6a8f2dc02b1ff3e24ad079fc90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67787
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add new PSP svc call to pass psp firmware hash table to the PSP.
psp_verstage will verify hash table and then pass them to the PSP.
The PSP will check if signed firmware contents match these hashes.
This will prevent anyone replacing signed firmware in the RW region.
BUG=b:203597980
TEST=Build and boot to OS in Skyrim.
Change-Id: I512d359967eae925098973e90250111d6f59dd39
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67259
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Guard sa_lock_pam with PAM0_REGISTER so it doesn't run on platforms
that don't select this.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I5055d09c634851e9f869ab0b67a7bcab130f928c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66492
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add SOC_INTEL_COMMON_PCH_CLIENT which is specific to Apollo
Lake. This is used to select the options that Apollo Lake
requires, without the ones specific to a PCH as Apollo Lake
doesn't have a PCH.
This change also enables SOC_INTEL_COMMON_PCH_LOCKDOWN for
Apollo Lake.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I084a05f904a19f3b7e9a071636659670aa45bf3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The fast SPI driver reports the BIOS window as reserved so that the OS
is aware of this region. Now that platforms which supports an extended
BIOS window are added to this driver, add the extended range as reserved
as well if it is enabled. And since this is now handled in the SPI
driver itself, remove the extended BIOS region reporting from
common systemagent code.
Change-Id: Ib5c735bffcb389be07c876d7b5b2d88c545a0b03
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
There are two classes of SPI controllers on Intel chipsets:
* generic usable SPI controllers
* SPI controller hosting the BIOS flash (fast SPI controller)
While the first class can be used for generic peripheral attachment the
second class mostly controls the BIOS flash and a TPM device (if
enabled). The generic SPI driver is not fully applicable to the fast SPI
controller. In addition, the fast SPI controller reports the reserved
MMIO range used for the BIOS flash mapping so that the OS is aware of
this range.
This patch moves the fast SPI controller of all known SoCs to the
fast SPI driver in common code. In addition, the PCI device for the
fast SPI controller is removed from the function 'spi_soc_devfn_to_bus'
as this is a callback of the generic SPI driver.
Change-Id: Ia881c1d274acdcf7f042dd8284048a7dd018a84b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch fixes AP hanging issue caused by the handshaking between
MCUPM and CPUfreq driver.
CPUfreq hardware failed to read MCUPM registers due to DEVAPC
permission. Therefore, update the DEVAPC settings to fix this issue.
BUG=none
TEST=CPUfreq in kernel test pass.
Change-Id: I6b30b01fc0be052182599709cbcc9139e6d09742
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67724
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides a workaround which skips requesting IOM for D3 cold
entry sequence.
BUG=b:244082753
TEST=Verified MUX configuration after hot plugging Type-C devices on
Rex and MTL RVP boards.
Change-Id: I17bcde75360c4b2b40885d355702e3e5f45d770a
Signed-off-by: zhaojohn <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This reverts commit 7ef5376123.
Reason for revert: It was merged before its dependencies so now master is broken.
Change-Id: Ia270efaed4f5c9d0c7b9761ae22dec55f57f74cf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67285
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP silicon 3347 changed the default value of the EnergyEfficientTurbo
Updateable Product Data (UPD), enabling the Energy Efficient Turbo
feature by default. This feature prevents the cores from entering
Turbo frequency under heavy load.
As a result of this FSP change, coreboot explicitly disables this
feature to stay consistent with commit `caa5f59279e Revert
"soc/intel/alderlake: Enable energy efficiency turbo mode"'.
BRANCH=firmware-brya-14505.B
BUG=b:246831841
TEST=verify that bit 19 of MSR 0x1fc is set. 'iotools rdmsr 0 0x1fc'
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Change-Id: I7498f87eb4be666b34cfccd0449a2b67a92eb9db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Coverity is throwing a bunch of "maybe uninitialized" errors for tu
struct. Initialize the tu struct with zero.
BUG=b:182963902,b:216687885
TEST=Validated on qualcomm sc7280 development board.
Monitor name: LQ140M1JW49
Change-Id: Ie249ad4f53abc91376445420712364a28618a15a
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
This patch adds power state 1/2/3 threshold setting interfaces
and pass the settings to FSP.
BUG=b:229803757
BRANCH=None
TEST=Add psi1threshold and psi2threshold to overridetree.cb and
enable FSP log to ensure the settings are incorrect.
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Change-Id: I0330ede4394ebc2d3d32e4b78297c3cb328660d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
FSP-M is not run XIP so it can be compressed. This more than halves
the binary size. 364544 bytes -> 168616 bytes.
On the up/squared this also results in a 83ms speedup.
TESTED: up/squared boots.
Change-Id: Ic76b51f0f3007b59ccb9f76b6a57bb9265dab833
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure FSP S UPDs to allow coreboot to handle the lockdown.
The main change here is setting `Write Protection Support` to 0,
as the default is Enabled, which shouldn't allow writes (even though
it seems to).
The UPDs are identical on APL and GLK, but all ones configured
in this patch have been there since their initial releases.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I35185b498315511f3236758caebfe2f9c28fd04a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65039
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use dynamic power and thermal configuration (DPTC) via ACPI ALIB calls
to throttle the SOC when there is no battery or critically low battery,
to enable the SOC to boot without overwhelming the AC charger and
browning out.
DPTC is not enabled for low/no battery mode with this CL. It will be
enabled for Skyrim in a following CL.
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifeddb99e97af93b40a5aad960d760e4c101cf086
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67189
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for DPTC by calling SB.DPTC() as part of PNOT().
BRANCH=none
BUG=b:217911928
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ifc332bfc4d273031c93b77673224b4f3c2871fb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67694
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add VRM DPTC limit registers. These are required when throttling the SOC
for low/no battery mode to prevent the SOC from overwhelming the
charger.
b/245942343 is tracking passing these additional fields to the FSP and
having the FSP configure them.
BRANCH=none
BUG=b:217911928
TEST=Build skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ie62129d967192f9a9cf654b1854d7dbe4324802a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67378
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update acpigen_write_alib_dptc() to support "low/no battery mode",
which throttles the SOC when there is no battery connected or the
battery charge is critically low.
This is in preparation for enabling this functionality for Mendocino.
BUG=b:217911928
TEST=Build zork
TEST=Boot nipperkin
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Icea10a3876a29744ad8485be1557e184bcbfa397
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66804
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are platforms equipped with AMD SoC where I2C3 controller
connected to TPM device is shared between X86 and PSP. In order to
handle this, PSP acts as an I2C-arbitrator, where x86 (kernel) sends
acquire and release requests to be accepted by PSP.
Introduce new CONFIG for Mendocino SoCs similar to what we have for
Cezanne.
BUG=b:241878652
BRANCH=none
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I015a24715271d2b26c0bd3c9425e20fb2987a954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Q0 stepping has a different ID than P1.
Reference: CML EDS Volume 1 (Intel doc #606599)
Change-Id: Id1da42aa93ab3440ae743d943a00713b7df3f453
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The patch updates comment on HFSTS1.spi_protection_mode.
The spi_protection_mode indicates SPI protection status as well as EOM
status (in a single staged EOM flow). Starting from TGL platform, staged
EOM flow is introduced. In this flow, spi_protection_mode alone doesn't
indicate the EOM status.
For information on EOM status, please refer secton# 3.6.1 in doc#
612229.
TEST=Build code for Gimble
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I19df5cfaa6d49963bbfb3f8bc692d847e58c4420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
skyrim boards, similar to mainboard/google/zork/Kconfig. This makes the
value dptc_tablet_mode_enable redundant.
This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.
BRANCH=none
BUG=b:217911928
TEST=emerge-skyrim coreboot
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I73fca5a16826313219247f452d37fb526ad4f4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
guybrush boards, similar to .mainboard/google/zork/Kconfig This makes
the value dptc_tablet_mode_enable redundant.
This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.
BRANCH=none
BUG=b:217911928
TEST=emerge-guybrush coreboot
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Moving the config value SOC_AMD_COMMON_BLOCK_ACPI_DPTC to
soc/amd/picasso/Kconfig and conditionally enabling it for only Morphius
boards makes the value dptc_tablet_mode_enable redundant.
This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.
BRANCH=none
BUG=b:217911928
TEST=Build zork
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ic54a9bb491234088be8184bec8b09e2e31ffa298
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD CPUs have a convenient MSR that allows to set the SMBASE in the save
state without ever entering SMM (e.g. at the default 0x30000 address).
This has been a feature in all AMD CPUs since at least AMD K8. This
allows to do relocation in parallel in ramstage and without setting up a
relocation handler, which likely results in a speedup. The more cores
the higher the speedup as relocation was happening sequentially. On a 4
core AMD picasso system this results in 33ms boot speedup.
TESTED on google/vilboz (Picasso) with CONFIG_SMI_DEBUG: verify that SMM
is correctly relocated with the BSP correctly entering the smihandler.
Change-Id: I9729fb94ed5c18cfd57b8098c838c08a04490e4b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Some PCI IDs were missing, and at least one (SPT's fast SPI
device in a generic SPI driver) was wrong. Hence, this patch
actually changes behavior depending on the devices actually
present in a machine.
In this patch the Skylake devicetree is written in a single-line
style. Alternative, the device operations could be put on a separate
line, e.g.
device pci 00.0 alias system_agent on
ops systemagent_ops
end
Tested on Kontron/bSL6. Notable in the log diff is that the
CSE and SATA drivers are hooked up now.
Change-Id: I8635fc53ca617b029d6fe1845eaef6c5c749db82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move enabling SOC_AMD_COMMON_BLOCK_ACPI_DPTC from
soc/amd/picasso/Kconfig to mainboard/google/zork/Kconfig and
conditionally enable it only for Morphius boards.
This reduces which boards/variants have DPTC enabled to only those that
actually use it.
BRANCH=none
BUG=b:217911928
TEST=Build zork
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Iddebcf5dbadae135c8110e2afd9ad76ef7dcc09d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67637
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Conditionally include dptc.asl based on the Kconfig value
SOC_AMD_COMMON_BLOCK_ACPI_DPTC.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build guybrush
TEST=Build skyrim
TEST=Build majolica
Change-Id: Idd94af8e8b2d7973abc0fb939e4600189e21656a
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67620
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the FSP binary check logic is fixed to only check the FSP files
if ADD_FSP_BINARIES is selected, the default paths for the not yet
published Cezanne FSP binaries can be added without breaking abuild.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9950a1fe7bd1b21109cca9631de1a8f1d265d9b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Only check if the FSP_M size is small enough to fit inside the memory
region reserved for it if ADD_FSP_BINARIES selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: I6a115412c113eb0d02b8d4dfc2bb347305f97809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Locking SMM as part of the AP init avoids the need for
CONFIG_PARALLEL_MP_AP_WORK to lock it down.
Change-Id: Ibcdfc0f9ae211644cf0911790b0b0c5d1b0b7dc9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64871
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is the same for all supported AMD hardware.
Change-Id: Ic6b954308dbb4c5a2050f1eb8f15acb41d0b81bd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67617
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Being divided by 1000 causes data loss and the loss is expand by
muliplication.
So we just set a lower divisor before muliplication.
BUG=b:185922528
Change-Id: Ib43103cc62c18debea3fd2c23d9c30fb0ecd781b
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for having different Security Patch Level (SPL) table files
in the read-only and the read-write A/B partitions. This allows the SPL
table file in the main or RO FMAP partition to only cover the embedded
firmware binaries in that partition and have a separate SPL file in the
RW A and B partitions that covers the embedded firmware binaries in the
RW partitions.
BUG=b:243470283
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ba8c370ce14f7ec88e7ef2f9d0b64d6bb4fa176
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67555
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
Some PLLs are not used in firmware, so we should keep them as hardware
default values. If their modules want to set them, the corresponding
drivers should set them in the kernel stage.
BUG=b:233720142
TEST=build pass.
Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I9bee18005ffed7fc1785c7fd3c0370c8293064ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67547
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
vpp_sel and ethdr_sel are vdosys clock source select mux.
Steps to change to support 4K source:
1. Change vpp_sel source to mainpll_d6 to run at 416MHz.
2. Change ethdr_sel source to univpll_d6 to run at 416MHz.
BUG=b:233720142
TEST=build pass.
Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I24f133b9b383fd019983cb29a213b47717148e97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67545
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The observed CPU big core frequency is double compared with the current
PLL setting. Therefore fix the wrong setting for PLL register
APMIXED_ARMPLL_BL.
Moreover, we also fix some wrong settings for other PLLs.
TEST=CPU frequency of big core CPU is correct and bootup correctly.
BUG=b:244215537
Signed-off-by: Garmin Chang <Garmin.Chang@mediatek.com>
Change-Id: I9126f439d7a5136b2fb8d66f103ef427a0b08a99
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67543
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since mono_time is now 64-bit, the utility functions interfacing with
mono_time should also be 64-bit so precision isn't lost.
Fixed build errors related to printing the now int64_t result of
stopwatch_duration_[m|u]secs in various places.
BUG=b:237082996
BRANCH=All
TEST=Boot dewatt
Change-Id: I169588f5e14285557f2d03270f58f4c07c0154d5
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This patch fixes MeteorLake GPIO PINCTRL entries as per 5.15
kernel pintrl driver:
https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/v5.15/drivers/pinctrl/intel/pinctrl-meteorlake.c
In order to support using ACPI GPIOs it is necessary for coreboot
to be compatible with this implementation. The GPIO groups that
are usable by the OS are declared with a pad base which is then
used to compute the number for ACPI GPIOs.
BUG=b:232573696
TEST=Tested on Google Rex board. After this change, driver rt5682s
is able to claim pinctrl IRQ 358 corresponding to GPP_B06.
Signed-off-by: Kapil Porwal <kapilporwal@google.com>
Change-Id: Icabbe9e125ee9efaf0eef4c4cdc8be9f734aa703
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67565
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
This message is not really an error message, so BIOS_ERR is
inappropriate. Since the message is informational, switch to
BIOS_INFO instead.
BUG=b:244687646
TEST=emerge-rex coreboot
before
[ERROR] USB Type-C 0 mapped to EC port 0
after
[INFO] USB Type-C 0 mapped to EC port 0
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Ia08fd45dd484c79d81527ea46cfaaa5a01a410c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67536
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Problem: OTA is triggering warmboot, where DDR is
in self-refresh mode. Due to which DDR training
is not going well.
Change: Verify reboot type in case of OTA. If it is warmboot, will
force for cold boot inorder to trigger DDR training
BUG=b:236990316
TEST=Validated on qualcomm sc7180 development board.
Test observation: Cold boot is triggered forcefully,
if current reboot is warmboot in case of OTA
Signed-off-by: Venkat Thogaru <quic_thogaru@quicinc.com>
Change-Id: I908370662292d9f768d1ac89452775178e07fc78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67406
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The following boards are setting DTPC tablet mode values without
corresponding device tree values, meaning they are effectively setting
"random" values for tablet mode:
1. Cezanne
2. Mendocino
The device tree has tablet mode disabled, so the code should never be
exercised, but this CL removes it entirely to cleanup "dead" code.
BRANCH=none
BUG=b:217911928
TEST=Build nipperkin
TEST=Boot skyrim
Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: Ide96f255b69670d1b4c37ca2f94cc3504a958b57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change removes all references to HybridStorageMode
UPD since it has been deprecated starting from FSP v2344_00
BUG=b:245167089
TEST=build coreboot mtlrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I16eb33cb1260484b0651d40211323c6ae986a546
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Instead of just printing the fatal errors, do early return so that
boot up time will be reduced during display init failure. Remove malloc
allocation and make tu a local variable.
Change-Id: I51f7a86d143128d2c426fb8940ff34a66152b426
Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66975
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor AMD DPTC tablet mode in preparation for adding low/no battery
DPTC settings.
1. Refactor and simplify acpigen_write_alib_dptc() into the following
functions:
- acpigen_write_alib_dptc_default()
- acpigen_write_alib_dptc_tablet()
2. Add device tree register value dptc_tablet_mode_enable to control
whether DPTC tablet mode is enabled for a variant.
3. Add dptc.asl to perform the necessary ACPI checking before modifying
the DPTC settings.
BRANCH=none
BUG=b:217911928
TEST=Build zork
TEST=Build nipperkin
TEST=Boot skyrim
Change-Id: I2518fdd526868c9d5668a6018fd3570392e809c0
Signed-off-by: Tim Van Patten <timvp@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Thermal configuration registers are now located behind PMC PWRMBASE
for MeteorLake as well (same as ADL). Hence, using thermal common code
to sets the thermal low threshold as per mainboard provided
`pch_thermal_trip`.
Note: These thermal configuration registers are RW/O hence, setting
those early prior to FSP-S helps coreboot to set the desired low
thermal threshold for the platform.
TEST=Dump thermal configuration registers PWRMBASE+0x150c etc on
Google/rex prior to FSP-S shows that registers are now programmed
based on 'pch_thermal_trip' and lock register BIT31 is set.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I1d6b179a1ed43f00416d90490e0a91710648655e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67462
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch updates `pch_thermal_trip` as per Intel MTL vol1
chapter 14.
Additionally, dropped the `FIXME` tag for `pch_thermal_trip`.
TEST=Able to boot the Google/rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I86f97c9245fe953832d3b408aa902d6a41e55651
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67461
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This patch drops redundant MCHBAR programming in romstage as bootblock
already done with MCHBAR setting up.
TEST=Able to boot Google/Rex to ChromeOS and MCHBAR is set to correct
value as per iomap.h
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic2c05f47ab22dc7fe087782a1ce9b7b692ea157e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Lastbus is a bus debug tool. When the bus hangs, the bus transmission
information before resetting will be recorded.
The watchdog cannot clear it and it will be printed out for bus hanging
analysis.
TEST=build pass.
BUG=none
Signed-off-by: ot_zhenguo.li <ot_zhenguo.li@mediatek.corp-partner.google.com>
Change-Id: Iff39486dfad556a3104b2f2b6811c34c2ded6954
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
1. There are two power sources for CPU:
- Logic power (VPROC).
- SRAM power (VSRAM_PROC).
2. There is a constraint between VPROC and VSRAM_PROC:
- 0mV <= VSRAM_PROC - VPROC <= 250mV.
With software control, the constraint might not always hold. Therefore,
we enable hardware tracking from PMIC MT6366 to ensure the constraint
is met automatically.
BUG=b:236353282, b:241615706
TEST=meet the constrain correctly when adjusting the voltage.
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Change-Id: I6012c57e60c009f1d599b57aab1c2526ee789208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67436
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Expose configuration of Intel PAVP (Protected Audio-Video Path, a
digital rights protection/management (DRM) technology for multimedia
content) to Kconfig.
TEST=Able to boot Google/rex to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I416346995d744990054c8e0c839ada82c84b7550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67423
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Missing power limit setting for Alder-Lake-N 7W soc.
Document reference: 645548 and 646929
BUG=b:245440443
BRANCH=None
TEST=Build FW and test on nivviks board and there is no error
message "unknown SA ID: 0x4617, skipped power limits configuration."
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Change-Id: Iefe17f5b574cc319fe9aad3850401a8aa8e31270
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Change the name of the CALIBRATION_REGION definitions used in two
separate locations. This conflict was causing an error for the
lint-001-no-global-config-in-romstage test.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: If6734f2a7d9be669586ea350fb9979fcd422b591
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
