Add the missing macro for ACPI_IRQ_LEVEL_HIGH so it can get
used by devicetree when necessary.
BUG=b:35585307
BRANCH=none
TEST=Add rt5514 SPI device with active high level IRQ on Eve board
and check that it is enumerated in the kernel
Change-Id: I25c7b035a198efb218f0f6b4ba3f4a1bf532bcea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18815
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch make some general adaptations in relation to commit 6a489237
(mainboard/intel/leafhill: Clean up).
- add necessary defaults to Kconfig
- remove irrelevant entries from FMD file
- include romstage file for better understanding
Change-Id: I190d648a7ffeca11acc6560db85ff03c78e85b21
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18808
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Always read the rmu.bin file from the read-only section of the SPI
flash. Without this change vboot attempts to read this file from the
A or B section of the flash.
TEST=Build and run on Galileo Gen2
Change-Id: Ied8eaa2cd37645bf401aa957936943946bfd6182
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18803
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: Bad function definition - void init_timer() should probably be void init_timer(void)
ERROR: Prefixing 0x with decimal output is defective
WARNING: Comparisons should place the constant on the right side of the test
WARNING: char * array declaration might be better as static const
TEST=Build and run on Galileo Gen2
Change-Id: I9f618eea95e1f92fa34f4f89da27c0b16ae7f4ee
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18763
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error detected by checkpatch:
ERROR: do not use assignment in if condition
TEST=Build and run on Galileo Gen2
Change-Id: I5a08d1647db66bd5d480f81e90d473999c222acf
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18761
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: Ief4b96073b3df30e45bf5d802ca3b190e7f431a7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since asking CSE to read FPF status turned out to be slow in some
cases, cache and save returned value on first boot only. Value is
read from flash on consequent boots.
BUG=b:35586975
BRANCH=reef
TEST=boot twice, make sure cached FPF status is loaded from
flash the second time.
Change-Id: I6e56a35407c9097616ccb05a557fded7b639c88a
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18774
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add FPF_STATUS region under MISC_RW. The purpose of the region is to
store FPF status.
Change-Id: I2997b3d39a94bf444df51068f254edcf49c47afd
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18773
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
#!/bin/sh
#
# The necessary tools were built and installed using the following
commands:
#
# pushd 3rdparty/vboot
# make
# sudo make install
# popd
#
# The keys were made using the following command
#
# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
# --4k --4k-root --output $PWD/keys
#
#
# Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
#
# Add the empty GBB to the coreboot.rom image
#
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
#
# Add the keys and HWID to the GBB
#
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
#
# Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix build error with FSP 1.1. Pass the S3 wake status to
fsp_silicon_init.
TEST=Build and run on Galileo Gen2
Change-Id: I78150f737321db5b1b4d63b411fa6432ac30d080
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18805
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Return NULL for top_of_memory when the register has not been set.
TEST=Build and run on Galileo Gen2
Change-Id: If79cac68c2a64aa9bf3be72d3cfc4c73fceef12b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18802
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a Kconfig value to enable other platforms to use the soft reboot
workaround.
TEST=Build and run on Galileo Gen2
Change-Id: I5a7ebd200229654128d367ecb50647ff69bb5258
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18798
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disable the display of the MMCONF_BASE_ADDRESS if it is not supported.
TEST=Build and run on Galileo Gen2
Change-Id: Ie4f0fbf264662b5bc12ca923f25395e5e91defea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18801
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The user has to know in which stage gdb is waiting to be able to
use symbolic debugging.
Change-Id: Ia992e7a2077b92c45546ae56c5fb648775f8f63b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12709
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Extract SMBIOS memory information from FSP SMBIOS_MEM_INFO_HOB
and save it in CBMEM.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: I593d4ccb0d4866e99913a73c49b2f000b51827d1
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18275
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sand is not convertible and no EC sensor sends event from EC to AP.
That event default is tablet mode, we don't have to enable tablet event.
Modify the ec.h, is based on <baseboard/ec.h>
BUG=b:36108742
BRANCH=reef
TEST=emerge-sand coreboot, boot to OS and touchpad and keyboard can work.
Change-Id: I6b6b45b5b4daf2c430ed18130f39eab0bd9a9812
Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com>
Reviewed-on: https://review.coreboot.org/18737
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the files to support verstage for vboot.
TEST=Build and run on Galileo Gen2
Change-Id: Icf87075012c08cf581c17d579e0763888c707265
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18040
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: macros should not use a trailing semicolon
TEST=Build and run on Galileo Gen2
Change-Id: Ie1d966b0f1f8fff401d6314fd2ef005ab6ac69db
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18764
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warnings detected by checkpatch.pl:
WARNING: break is not useful after a goto or return
WARNING: Statements terminations use 1 semicolon
WARNING: else is not generally useful after a break or return
WARNING: void function return statements are not generally useful
TEST=Build and run on Galileo Gen2
Change-Id: I6f095c4e9cb1ee4ff2ebdf095ef612e1a8393231
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warning detected by checkpatch.pl:
TEST=Build and run on Galileo Gen2
Change-Id: I811763c6de57dfdf5456579f63e83dca29d37d61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18751
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build for reef
Change-Id: I4fbe95037ca4b52e64ba37e5c739af4a03f64feb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18728
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
ERROR: do not use assignment in if condition
WARNING: Statements terminations use 1 semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: else is not generally useful after a break or return
TEST=Build for reef
Change-Id: I5486936dbf19b066c76179d929660affa1da5f16
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18727
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error and warning detected by checkpatch.pl:
ERROR: inline keyword should sit between storage class and type
WARNING: storage class should be at the beginning of the declaration
TEST=Build for reef
Change-Id: I2ed418cc3b4a989eb1101013944169429bf147c2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18726
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following errors and warning detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
ERROR: return is not a function, parentheses are not required
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build for reef
Change-Id: I31f854adf3269ba6f77c4044fb3748bb1957841c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18725
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build for reef
Change-Id: Ifc45ce90d466d087cd20af72ddfc8486d2f1492c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18724
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warnings detected by checkpatch.pl:
WARNING: braces {} are not necessary for any arm of this statement
WARNING: braces {} are not necessary for single statement blocks
TEST=Build for reef
Change-Id: Ifab09c023faa7da215945f1aedd391f4b2a1a04c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18723
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
TEST=Build for reef
Change-Id: Id7a758463b95274c5e8bbdd67da0955f1ae78aac
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18721
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following errors detected by checkpatch.pl:
ERROR: spaces required around that '==' (ctx:VxO)
ERROR: space required before that '-' (ctx:OxV)
ERROR: spaces required around that '=' (ctx:VxW)
ERROR: spaces required around that '=' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: need consistent spacing around '+' (ctx:VxW)
ERROR: space prohibited before that '++' (ctx:WxB)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space required after that ',' (ctx:VxV)
TEST=Build for reef
Change-Id: I37265a69fcb14fbf7c182ef29d823f70a5748ad8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following errors detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
TEST=Build for reef
Change-Id: I4a762d8fa762057a06e601dfed10538adc5d8bc8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18719
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: open brace '{' following function declarations go on the next line
TEST=Build for reef
Change-Id: Icb92dc49c6e7b8dfea60bc0395f3db7316c4e34c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18722
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18687
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: need consistent spacing around '-' (ctx:WxV)
TEST=Build and run on Galileo Gen2
Change-Id: Ib4c2c0c19dee842b7cd4da11a47215dc2f124374
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18686
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: Avoid gcc v4.3+ binary constant extension: <...>
TEST=Build and run on Galileo Gen2
Change-Id: Iab29c494060df3f60eff5317259e0fdbfea06f27
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18685
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: spaces required around that ':' (ctx:ExV)
TEST=Build and run on Galileo Gen2
Change-Id: Idb2ea29a6c7277b319e6600e8a9d7cb8285ae5df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18684
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: switch and case should be at the same indent
TEST=Build and run on Galileo Gen2
Change-Id: I92f00254c7fcb79a5ecd4ba5e19a757cfe5c11fa
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18683
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: Comparisons should place the constant on the right side of the test
TEST=Build and run on Galileo Gen2
Change-Id: Id790e0034ea5c926fcaef95486319d6c0c936f28
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18682
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: storage class should be at the beginning of the declaration
TEST=Build and run on Galileo Gen2
Change-Id: I7d3135466634a4bb84dcef16dbd68754f8d8d6c2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18760
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors detected by checkpatch.pl:
ERROR: open brace '{' following function declarations go on the next
line
ERROR: that open brace { should be on the previous line
ERROR: open brace '{' following struct go on the same line
ERROR: else should follow close brace '}'
TEST=Build and run on Galileo Gen2
Change-Id: I971ada9ba9ba7ce5d8029323710fee1a6166570b
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18759
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warning detected by checkpatch.pl:
WARNING: Unnecessary space before function pointer arguments
TEST=Build and run on Galileo Gen2
Change-Id: I2b56af20d5f74cc2625d3cb357fbb137bd440af0
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18660
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I5fa3f8e950e2f0c60bd0e8f030342dc8c0469299
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18758
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: do not use assignment in if condition
TEST=Build and run on Galileo Gen2
Change-Id: I911d528bd85afcd9f3837241494f13d1f9f283ab
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18659
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: Unnecessary typecast of c90 int constant
TEST=Build and run on Galileo Gen2
Change-Id: I137efa55e945d1315322df2a38d70716a3807a1e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: storage class should be at the beginning of the declaration
The following storage class attribute is not detected by checkpatch.py:
static cbmem_init_hook_t init_fn_ ## _ptr_ __attribute__((used,
\
section(".rodata.cbmem_init_hooks"))) = init_fn_;
The following lines generates a false positive:
(pound)define STATIC static
src/include/cpu/amd/common/cbtypes.h:60: WARNING: storage class should
be at the beginning of the declaration
typedef asmlinkage void (*smm_handler_t)(void *);
src/include/cpu/x86/smm.h:514: WARNING: storage class should be at the
beginning of the declaration
(pound)define MAYBE_STATIC static
src/include/stddef.h:34: WARNING: storage class should be at the
beginning of the declaration
TEST=Build and run on Galileo Gen2
Change-Id: Ie087d38e6171b549b90e0b831050ac44746a1e14
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18657
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I0ac30b32bab895ca72f91720eeae5a5067327247
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18656
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following errors detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
ERROR: "foo* bar" should be "foo *bar"
ERROR: "foo*bar" should be "foo *bar"
TEST=Build and run on Galileo Gen2
Change-Id: I5a3ff8b92e3ceecb4ddf45d8840454d5310fc6b3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18655
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: spaces required around that '?' (ctx:WxV)
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that '<' (ctx:VxV)
ERROR: spaces required around that '+=' (ctx:VxV)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open brace '{'
ERROR: space required after that close brace '}'
ERROR: need consistent spacing around '+' (ctx:WxV)
ERROR: need consistent spacing around '*' (ctx:WxV)
ERROR: need consistent spacing around '&' (ctx:VxW)
ERROR: spaces required around that '?' (ctx:VxW)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: trailing whitespace
ERROR: space prohibited before that '++' (ctx:WxO)
ERROR: space prohibited before that ',' (ctx:WxW)
ERROR: space prohibited after that '!' (ctx:BxW)
ERROR: spaces prohibited around that '->' (ctx:VxW)
ERROR: space prohibited after that '-' (ctx:WxW)
WARNING: space prohibited before semicolon
WARNING: unnecessary whitespace before a quoted newline
WARNING: missing space after return type
Note that lib/libgcov.c and lib/lzmadecode.c are providing false
positives for ERROR: need consistent spacing around '*' (ctx:WxV)
An example is:
void __gcov_merge_add(gcov_type *counters __attribute__ ((unused)),
unsigned int n_counters __attribute__ ((unused))) {}
TEST=Build and run on Galileo Gen2
Change-Id: I0016327a5754018eaeb25bedf42338291632c7c1
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18733
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: return is not a function, parentheses are not required
TEST=Build and run on Galileo Gen2
Change-Id: Idf7723d4fd48124a26bbb626afc310820f859f66
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18757
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the following warning detected by checkpatach.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
TEST=Build and run on Galileo Gen2
Change-Id: Ic266c077eb115e0c7d934c15bcc4cc9b9e530a39
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18756
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the following errors detected by checkpatch.pl:
ERROR: spaces required around that '=' (ctx:VxV)
ERROR: spaces required around that ':' (ctx:VxW)
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required before the open parenthesis '('
ERROR: switch and case should be at the same indent
ERROR: "foo ** bar" should be "foo **bar"
TEST=Build and run on Galileo Gen2
Change-Id: I52ba2a3c1e0fffad7145eecd878aba8dc450ac0b
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18755
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: I61c4f01216cb6c788cf6da988c414bbb9648d502
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18754
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
ERROR: switch and case should be at the same indent
WARNING: Statements should start on a tabstop
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
WARNING: suspect code indent for conditional statements
WARNING: labels should not be indented
TEST=Build and run on Galileo Gen2
Change-Id: Iebcff26ad41ab6eb0027b871a1c06f3b52dd207c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable an internal pull-up on the power button input as short
press is resulting in power button override being asserted.
BUG=b:36111214
BRANCH=none
TEST=tested on poppy board to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I3a25b78562e2302b6f7575e64c87ae8142690701
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/18734
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: space prohibited between function name and open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I8f3c79302dc5eb1861ffb245617a27addf8653ef
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18731
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: trailing statements should be on next line
The remaining error is a false positive in libgcov.c where the if
statement spans several lines with conditional compilation directives
intertwined.
TEST=Build and run on Galileo Gen2
Change-Id: I37fcef78e9323340bac1367ae1c5fde334f5ce10
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18730
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: I00b59f6a27c3acb393deaa763596363b7e958efd
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18654
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix the following errors and warning detected by checkpatch.pl:
ERROR: open brace '{' following enum go on the same line
ERROR: open brace '{' following struct go on the same line
ERROR: that open brace { should be on the previous line
WARNING: missing space after struct definition
TEST=Build and run on Galileo Gen2
Change-Id: I856235d0cc3a3e59376df52561b17b872b3416b2
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18653
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix the following warning detected by checkpatch.pl:
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: If60a58021d595289722d1d6064bea37b0b0bc039
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18652
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error messages found by checkpatch.pl:
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
TEST=Build and run on Galileo Gen2
Change-Id: I2a9a0df640c51ff3efa83dde852dd6ff37ac3c06
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18651
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Old dock.c copied from x201 was incorrect. Do a rewrite of t60 dock
code as pnp devices.
Fixes USB and serial on the dock, if it is already connected when
computer is powered on. DVI and ethernet worked without this patch.
Hot-plug is yet to be fixed.
Change-Id: Ib20a0eff10d0cde92dd089baf4fca28b117dc999
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18054
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fix the following error detected by checkpatch.pl:
ERROR: need consistent spacing around '+' (ctx:WxV)
Test: Build and run on Galileo Gen2
Change-Id: Idd5f2a6d8a3c8db9c1a127ed75cec589929832e3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18650
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error found by checkpatch.pl:
ERROR: Macros with complex values should be enclosed in parentheses
False positives are detected for attribute macros. An example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define BOOT_STATE_INIT_ATTR __attribute__ ((used, section
(".bs_init")))
False positive also generated for macros for linker script files. An
example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define CBFS_CACHE(addr, size) \
+ REGION(cbfs_cache, addr, size, 4) \
+ ALIAS_REGION(cbfs_cache, preram_cbfs_cache) \
+ ALIAS_REGION(cbfs_cache, postram_cbfs_cache)
False positives generated for assembly code macros. An example is:
ERROR: Macros with complex values should be enclosed in parentheses
+#define DECLARE_OPTIONAL_REGION(name) asm (".weak _" #name ", _e" #name
)
False positive detected when macro includes multiple comma separated
values. The following code is from src/include/device/azalia_device.h:
#define AZALIA_SUBVENDOR(codec, val) \
(((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \
(((codec) << 28) | (0x01721 << 8) | (((val) >> 8) & 0xff)), \
(((codec) << 28) | (0x01722 << 8) | (((val) >> 16) & 0xff)), \
(((codec) << 28) | (0x01723 << 8) | (((val) >> 24) & 0xff))
TEST=Build and run on Galileo Gen2
Change-Id: I6e3b6950738e6906851a172ba3a22e3d5af1e35d
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18649
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error detected by checkpatch.py:
ERROR: space required before the open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I6969e63f750f327afff1a0efa1aab56d477af0df
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18645
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error detected by checkpatch.pl:
ERROR: "foo * bar" should be "foo *bar"
TEST=Build and run on Galileo Gen2
Change-Id: If68dfa2b49c61d574f35192f94d1a6642069fa7f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18752
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following errors and warning detected by checkpatch.pl:
ERROR: open brace '{' following struct go on the same line
ERROR: else should follow close brace '}'
WARNING: else is not generally useful after a break or return
False positives are detected for the following checkpatch.pl error.
ERROR: that open brace { should be on the previous line
These false positives are in cbfs.c for two function definitions.
TEST=Build and run Galileo Gen2
Change-Id: Ic679ff3a2e1cfc0ed52073c20165e05bf21d76f3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following error detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
TEST=Build and run on Galileo Gen2
Change-Id: I3a44a02d4cd1be6b2bb2f52fc832e673a580e562
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18749
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following errors and warnings detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
ERROR: space required after that ';' (ctx:VxV)
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
WARNING: please, no spaces at the start of a line
WARNING: please, no space before tabs
TEST=Build and run on Galileo Gen2
Change-Id: I54877f60eb5fdf3f6d8729711c55ff5a284d22cf
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
TEST=Build and run on Galileo Gen2
Change-Id: I0e5acef53d558948b7713cfe608cd346ddc5e9fe
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18746
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: Ibd351703e60acebbacd6ae5b1a2fa1cb34fd3ff9
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18745
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following errors detected by checkpatch.pl:
ERROR: space prohibited before that close parenthesis ')'
ERROR: space required before the open parenthesis '('
ERROR: space prohibited before open square bracket '['
ERROR: spaces required around that ':' (ctx:VxE)
TEST=Build and run on Galileo Gen2
Change-Id: I085aaaa9e276c60eded6edf3be0325ed2402702a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18744
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following error detected by checkpatch.pl:
ERROR: "(foo*)" should be "(foo *)"
False positives are generated by checkpatch for the following condition
which is not properly detecting the variable type:
ERROR: need consistent spacing around '*' (ctx:WxV)
The false positives are found in debug.h and upd_display.c
TEST=Build and run on Galileo Gen2
Change-Id: I0e871d64544ebf5eacbae46466cf7aefbfa701eb
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18743
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the following warning detected by checkpatch.pl:
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: I7cb35c8b5d7ff97849e666ce7f75d4e4763bb2a7
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18742
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In strncpy() function of dimm_info_fill(), the minimum possible size
of Module Part Number of DIMM is passed as argument.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS Table from Kernel command "dmidecode".
Change-Id: Icc7667149eae9705b91e271628af1b443eb8556e
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18617
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
CDClk selection was wrong in some corner cases (e.g. ULX SKUs) and,
for Broadwell, never took the devicetree config into account.
Rewrite the selection with the following in mind:
o cpu_is_ult() might return `true` for ULX SKUs, too,
o ULX and Broadwell-ULT SKUs can be `overclocked` with additional
cooling, so leave that as devicetree option.
For Haswell, the following frequency selections are valid:
o ULX: 337.5MHz by default, 450MHz optional
o ULT: 450MHz only (maybe 337.5MHz too, documentation varies,
it wasn't selectable before either)
o others: 540MHz by default, 450MHz optional
For Broadwell:
o ULX: 450MHz by default, 337.5MHz / 540MHz optional
o ULT: 540MHz by default, 337.5MHz / 450MHz / 675MHz optional
o others: 667MHz by default, 337.5MHz / 450MHz / 540MHz optional
Side effects: A too high setting in the devicetree results in the
highest possible frequency now, Haswell non-ULT/ULX defaults to 540MHz
instead of 450MHz.
Change-Id: Iec12752f2a47bf4a5ae6077c75790eae9378c1b2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17768
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
eMMC Controller is taking over 100ms to resume during runtime which
results in I/O latency issues on the Skylake systems like Cave and Caroline.
This patch adds _DSM method for eMMC comtroller for specifying the
device readiness durations. Function index 9 returns package of five
integers to set D3 cold delay to zero and ACPI constant Ones for the
elements where overriding the default values is not desired.
BUG=b:35774937
BRANCH=none
TEST=update caroline coreboot and test i/o latency is under 100ms
Change-Id: Iacc8aa8560897da8770fe559ca8cd17aaf6ebeba
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/18532
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.
Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.
Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18273
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
This configures GPIO_177 as an input pin for SDCARD card
detect. This also changes the ownership of the pin from ACPI
to GPIO driver.
Assign the sdcard card detect pin in devicetree for reef variants.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=None
Change-Id: Ia8aef60bd7d0ea36afb39f76fab051aa46a2ed64
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18497
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This implements dynamic generation of sdcard GpioInt in SSDT.
GpioInt in SSDT generation is based on the card detect GPIO if
it is provided by the mainboard in devicetree.
This implements GNVS variable to store the address of sdcard cd pin.
GNVS used to store rxstate of the sdcard cd pin to get card presence.
Add _PS0/_PS3 methods to power gate the sd card controller in
S0ix and runtime PM.
CQ-DEPEND=448173
BUG=chrome-os-partner:63070
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should enter S0ix and resume with no issue.
Change-Id: Id2c42fc66062f0431385607cff1a83563eaeef87
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/18496
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Address the iasl 20160108-64 (Ubuntu 16.04) warnings below.
```
Intel ACPI Component Architecture
ASL+ Optimizing Compiler version 20160108-64
Copyright (c) 2000 - 2016 Intel Corporation
dsdt.aml 245: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 262: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 277: Method (_CRS, 0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
dsdt.aml 295: Method(_CRS, 0) {
Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within)
```
Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18323
Tested-by: build bot (Jenkins)
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The init files for the AMD families using the AGESA platform
initialization code are quite similar. So reduce the differences, by
using the same comments, variable names, console messages, and blank
lines.
Change-Id: Id4a3a5c3812a34627d726cdcbe8f4781a14be724
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18507
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
cr50 by default delays nvmem commits internally from the point of
reset to accumulate change state. However, the factory process can
put a board into dev mode through the recovery screen. This state
is stored in the TPM's nvmem space. When the factory process is
complete a disable_dev_request and battery_cutoff_request is performed.
This leads to disabling the dev mode in TPM, but the battery is
subsequently cut off so the nvmem contents never stick. Therefore,
whenever antirollback_write_space_firmware() is called we know there
was a change in secdata so request cr50 to immediately enable nvmem
commits going forward. This allows state changes to happen immediately.
The fallout from this is that when secdata is changed that current
boot will take longer because every transaction that writes to TPM
nvmem space will perform a write synchronously. All subsequent boots
do not have that effect.
It should also be noted that this approach to the implementation is
a pretty severe layering violation. However, the current TPM APIs
don't lend themselves well to extending commands or re-using code
outside of the current routines which inherently assume all knowledge
of every command (in conflict with vendor commands since those are
vendor-specific by definition).
BUG=b:35775104
BRANCH=reef
TEST=Confirmed disablement of dev mode sticks in the presence of:
crossystem disable_dev_request=1; crossystem
battery_cutoff_request=1; reboot;
Change-Id: I3395db9cbdfea45da1f5cb994c6570978593b944
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18681
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Going forward it's important to note when a CR50 is expected
to be present in the system. Additionally, this Kconfig addition
provides symmetry with the equivalent i2c Kconfig option.
BUG=b:35775104
Change-Id: Ifbd42b8a22f407534b23459713558c77cde6935d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18680
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
verstage can be pretty chatty so bump the pre cbmem console size
when building for Chrome OS so that all messages can be observed.
BUG=b:35775104
BRANCH=reef
TEST=Booted and noted no cutoff of console when sec data being saved.
Change-Id: I0ce2976572dedf976f051c74a3014d282c3c5f4c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18679
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
marshal_blob() was setting an unsigned size (size_t) to a value
of -1 when an error is determined. This is wrong for the current
implementation of the code because the code assumes the buffer
space gets set to 0. Setting an unsigned value to -1 effectively
tells the library the buffer has unlimited amount of space.
BUG=b:35775104
Change-Id: I677a1fd7528bef3ea7420d0a8d0a290e9b15cea3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18678
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Fix the following error detected by checkpatch.pl:
ERROR: space required before the open parenthesis '('
TEST=Build and run on Galileo Gen2
Change-Id: I8953fecbe75136ff989c9e3cf6c5e155dcee3c3b
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18698
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the following warning detected by checkpatch.pl:
WARNING: braces {} are not necessary for single statement blocks
TEST=Build and run on Galileo Gen2
Change-Id: Ie4b41f6fb75142ddd75103a55e0347ed85e7e873
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18697
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Fix the following errors detected by checkpatch.pl:
ERROR: "foo* bar" should be "foo *bar"
ERROR: "(foo*)" should be "(foo *)"
ERROR: "foo * const * bar" should be "foo * const *bar"
TEST=Build and run on Galileo Gen2
Change-Id: I0d20ca360d8829f7d7670bacf0da4a0300bfb0c1
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18696
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the following warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
The remaining 37 warnings in gcov-io.c and libgcov.c are all false
positives generated by checkpatch detecting a symbol or function name
ending in _unsigned.
TEST=Build and run on Galileo Gen2
Change-Id: I9f1b71993caca8b3eb3f643525534a937d365ab3
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18695
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Fix the following error detected by checkpatch.pl:
ERROR: space prohibited after that '&' (ctx:ExW)
TEST=Build and run on Galileo Gen2
Change-Id: Ied8b4c00fc57a35ed4d649264a5ff1b8dcc6a1cd
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18648
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: space required after that ',' (ctx:VxV)
TEST=Build and run on Galileo Gen2
Change-Id: I297bfc3d03dc95b471d3bb4b13803e81963841b5
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18647
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error and warning detected by checkpatch.pl:
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
TEST=Build and run on Galileo Gen2
Change-Id: I487771b8f4d7e104457116b772cd32df5cd721a6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18646
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.py:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
False positives are generated when assembly code is used in a macro. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define post_code(value) \
+ movb $value, %al; \
+ outb %al, $CONFIG_POST_IO_PORT
False positives are also generated for linker script include files. An
example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define SET_COUNTER(name, addr) \
+ _ = ASSERT(. <= addr, STR(name overlaps the previous region!));
\
+ . = addr;
False positives are also generated for attribute macros. An example is:
ERROR: Macros with multiple statements should be enclosed in a do - while loop
+#define DISABLE_TRACE_ON_FUNCTION __attribute__
((no_instrument_function));
TEST=Build and run on Galileo Gen2
Change-Id: I88abf96579e906f6962d558a3d09907f07d00b1c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18644
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following error detected by checkpatch.pl:
ERROR: trailing statements should be on next line
TEST=Build and run on Galileo Gen2
Change-Id: I169f520db6f62dfea50d2bb8fb69a8e8257f86c7
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18643
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix warning detected by checkpatch.pl:
WARNING: Prefer 'unsigned int' to bare use of 'unsigned'
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: I23d9b4b715aa74acc387db8fb8d3c73bd5cabfaa
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18607
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add two GPIO macros:
1. PAD_CFG_GPI_APIC_EDGE allows a pin to be route to the
APIC with input assuming the events are edge triggered.
2. PAD_CFG_GPI_ACPI_SCI_LEVEL to route the general purpose
input to SCI assuming the events are level triggered.
Change-Id: I944a9abac66b7780b2336148ae8c7fa3a8410f3f
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Reviewed-on: https://review.coreboot.org/18533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add SKL/KBL PCH-H GPIO settings referring from SKL PCH-H
specifications to support sklrvp11.
Split the gpio_defs.h into headers gpio_pch_h_defs.h and
gpio_soc_defs.h for PCH-H specific and SOC specific GPIO
defs respectively.
Change-Id: I5eaf8d809a1244a56038cbfc29502910eb90f9f2
Signed-off-by: Li Cheng Sooi <li.cheng.sooi@intel.com>
Signed-off-by: Rahul Kumar Gupta <rahul.kumarxx.gupta@intel.com>
Reviewed-on: https://review.coreboot.org/18027
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In all simplicity, with board/OptionsIds.h file having:
IDSOPT_IDS_ENABLED TRUE
IDSOPT_TRACING_ENABLED TRUE
And src/Kconfig modified to:
config WARNINGS_ARE_ERRORS
default n
With these settings AGESA outputs complete debugging log
where-ever you have your coreboot console configured.
Change-Id: Ie5c0de6358b294160f9bf0a202161722f88059c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15320
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins)
We build with WARNINGS_ARE_ERRORS, while IDS tracing will
raise various (non-fatal) printk() format warnings.
Change-Id: I9dc81c89ee60d17a6556a412380fed1413af66bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18560
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
We have been forced to build AGESA with ASSERT() as non-fatal
for some board, as hitting those errors is not uncommon.
For the cases touched here, abort eventlog operations early
to avoid further errors and dereference of null pointers.
Change-Id: I1a09ad55d998502ad19273cfcd8d6588d85d5e0c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18543
Tested-by: build bot (Jenkins)
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Implement threshold as described in AMD.h, and do not add
entries below STATUS_LOG_LEVEL in the eventlog.
Change-Id: Ic9e45b1473b4fee46a1ad52d439e8682d961dc03
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This is useful for debugging S3 issues and in general
to understand AGESA memory allocator behaviour.
Change-Id: I422f2620ed0023f3920b8d2949ee1c33a6c227e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18535
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
A problem around CAR teardown time may result with missing
training results at the time we want to save them.
Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.
Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18534
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
When allowing use of SSE instructions, stack must be
aligned to 16 bytes. Adjust x86 entry to C accordingly,
by pushing values to maintain the alignment.
Fixes regression with new toolchain using GCC-6.3 and
ec0a393 console: Enable printk for ENV_LIBAGESA
For some builds, the above-mentioned commit emitted
SSE instruction 'andps (%esp),%xmm0' with incorrectly
aligned esp, raising exception and thus preventing boot.
Change-Id: Ief57a2ea053c7497d50903838310b7f7800bff26
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The init files for the Core Duo and Core 2 Duo are very similar. Reduce
the differences, by using the same order for the include statements, the
same blank lines, and the same comments.
Change-Id: I0de060222a61a482377c760c6031d73c7e318edf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18506
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This is required to transmit button information from EC to kernel.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I8f380f935c2945de9d8e72eafc877562987d02db
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18642
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is required to pass button information from EC to kernel without
using 8042 keyboard driver.
1. Define EC buttons device using GOOG0007 ACPI ID.
2. Guard enabling of this device using EC_ENABLE_MKBP_DEVICE.
BUG=b:35774934
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I4578f16648305350d36fb50f2a5d2285514daed4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18641
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Apollolake platform comes with FPF (field-programmable-fuses). FPF can
be blown only once, typically at the end of the manufacturing process.
This patch adds code that sends a request to CSE to figure out if FPFs
have already been blown.
Change-Id: I9e768a8b95a3cb48adf66e1f17803c720908802d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18604
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add common driver that can send/receive HECI messages. This driver is
inspired by Linux kernel mei driver and somewhat based on Skylake's.
Currently it has been only tested on Apollolake.
BUG=b:35586975
BRANCH=reef
TEST=tested on Apollolake to send single messages and receive both
fragmented and non-fragmented versions.
Change-Id: Ie3772700270f4f333292b80d59f79555851780f7
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fix the following errors detected by checkpatch.pl:
ERROR: space prohibited after that open parenthesis '('
ERROR: space prohibited before that close parenthesis ')'
TEST=Build and run on Galileo Gen2
Change-Id: I586c5731c080282080fe5ddf3ac82252cb35bdd4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18636
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The event log entry indicating developer mode is useful for the
boot path, but is not really useful on the resume path and removing
it makes the event log easier to read when developer mode is enabled.
To make this work I have to use #ifdef around the ACPI code since
this is shared with ARM which does not have acpi.h.
BUG=b:36042662
BRANCH=none
TEST=perform suspend/resume on Eve and check that the event log
does not have an entry for Chrome OS Developer Mode.
Change-Id: I1a9d775d18e794b41c3d701e5211c238a888501a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18665
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
If Deep Sx is enabled the event log will get entries added on every
power sequence transition indicating that the suspend well has failed.
When a board is using Deep Sx by design this is intended behavior and
just fills the logs with extraneous events.
To make this work the device init state has to be executed first so it
actually enables the Deep Sx policies in the SOC since this code does
not have any hooks back into the devicetree to read the intended setting
from there.
BUG=b:36042662
BRANCH=none
TEST=Perform suspend/resume on Eve device with Deep S3 enabled, and
then check the event log to be sure that it does not contain the
"SUS Power Fail" event.
Change-Id: I3c8242baa63685232025e1dfef5595ec0ec6d14a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18664
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a function to read the current state of Deep S5 configuration
and indicate if it is enabled (for AC and/or DC) or disabled.
This is similar to the existing function that checks Deep S3
enable state.
BUG=b:36042662
BRANCH=none
TEST=tested with subsequent commits to check Deep S5 state at boot
and filter event log messages if it is enabled.
Change-Id: I4b60fb99a99952cb3ca6be29f257bb5894ff5a52
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18663
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add options to the skylake chip config that will allow tuning the
various settings that can affect acoustics with the CPU and its VRs.
These settings are applied inside FSP, and they can adjust the slew
slew rate when changing voltages or disable fast C-state ramping on
the various CPU VR rails.
BUG=b:35581264
BRANCH=none
TEST=these are currently unused, but I verified that enabling the
options can affect the acoustics of a system at runtime.
Change-Id: I6a8ec0b8d3bd38b330cb4836bfa5bbbfc87dc3fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18662
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
A new board revision is making use of two previously unused GPIOs
to drive BOOT/RESET pins to an on-board MCU.
The reset pin is open drain so it is set as input by default, and
the boot pin is driven low by default.
Since these are UART0 pins they also need to be set up again after
executing FSP-S as it will change them back to native mode pins.
BUG=b:36025702
BRANCH=none
TEST=manual testing on reworked board, toggling GPIOs to put
the MCU into programming mode.
Change-Id: Id6f0ef2f863bc1e873b58e344446038786b59d25
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Fine tune USB2, need to override the following registers.
port#1:
PERPORTPETXISET=7
PERPORTTXISET=0
BUG=b:35858164
BRANCH=reef
TEST=built, measured eye diagram on snappy, and reviewed by intel
Change-Id: I461cf8f032b4e70abc9707e6cd3603a62cee448f
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18590
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.
Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.
Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.
Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18501
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
None of the boards currently have HAVE_ACPI_RESUME and
and ACPI S3 support calls should not appear under board
directories anyways.
Change-Id: I1abd40ddba64be25b823abf801988863950c1eb5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18500
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The file is used for fam15.
Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Definitions are not part of ACPI S3 feature, nor do
they require any AGESA headers so move them to a
better location.
Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Declaration of main in cpu/amd/car.h conflicts with the
definition of main required for x86/postcar.c in main_decl.h.
Change-Id: I19507b89a1e2ecf88ca574c560d4a9e9a3756f37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18615
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Note that M and M_PRO had same DefaultPlatformMemoryConfiguration
defined, use one for both.
Change-Id: Ia1925957800a7fe6ef511b2d041f7a863c8fc931
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18606
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Relocate the enabling of the LAPIC out of the southbridge source and
surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD
systems). The LAPIC is now enabled for all cores; not only the BSP,
and not only when the UART is used.
This solves the problem of APs not having their APICs enabled when
the timer is expected to be functional, e.g. verstage often uses
do_printk_va_list() instead of do_printk() which exits early for
APs when CONFIG_SQUELCH_EARLY_SMP=y.
The changes were tested with two Gardenia builds, one using verstage
and another with CONFIG_SQUELCH_EARLY_SMP=n.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad)
Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18436
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Only declare S3 support in ACPI if CONFIG_HAVE_ACPI_RESUME
is set.
Change-Id: I6f8f62a92478f3db5de6feaa9822baad3f8e147e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18493
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add some generic functions that can configure the SPI interface to
have faster performance.
Given that the hudson files are used across many generations of FCHs,
make sure to refer to the appropriate BKDG or RRG before using the
functions. Notable differences:
* Hudson 1 defines read mode in CNTRL0 differently than later gens
* Hudson 1 supports setting NormSpeed in Cntr1 but Hudson3 allows
setting FastSpeed as well
* Kabini, Mullins, Carrizo and Stoney Ridge contain a "new" SPI100
controller
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1922d6f424dcf1f42e2f21fb7c6d53d7bcc247d0)
Change-Id: Id12440e67bc575dbe4b980ef1da931d7bfae188d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18442
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add defines that will be used later for setting the fastest settings
in the SPI controller.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 0d2c28b8156dcc1f3dc925b3c3ba15b6b07f202c)
Change-Id: I660cc9ed6910c33042321c80453c7f74912455d9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18441
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove unused definitions from a .c file and use the BIT(n) macro
found in types.h instead. Convert existing definitions to BIT(n).
Orignial-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit f403d12b49985ee9d9b339a6659b60ef1560519c)
Change-Id: I24105bf75263236dbdbc2666f03033069d1d36d2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/18440
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix the error detected by checkpatch and update the copyright date.
TEST=Build and run on Galileo Gen2
Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18591
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Gru/Kevin use 933 MHz (actually 928 MHz for better jitter) as max sdram
frequency, while bob uses 800 MHz.
It's normal some variants can't meet 928 MHz SI requirement and hence
have to use a lower freq as spec.
BUG=chrome-os-partner:61001
BRANCH=gru
TEST=check dpll is 800 MHz on bob
Change-Id: I6d19a351f25d1f48547715ce57c3a87d9505f6f1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8176bfea52422c713f144ffec419752aeca66db2
Original-Change-Id: I46afba8d091f1489feeb20cafc44decaa81601fc
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/420208
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-(cherry picked from commit eba5dff79eeedae5ff608d2d8d297ccf9c13cb55)
Original-Reviewed-on: https://chromium-review.googlesource.com/448277
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18581
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The K4B4G1646E-BYK0 shares sdram config with K4B4G1646D-BYK0.
For clarity, sdram-ddr3-samsung-2GB now is used by
- K4B4G1646D-BYK0
- K4B4G1646E-BYK0
- K4B4G1646Q-HYK0
BUG=chrome-os-partner:62131
BRANCH=veyron
TEST=emerge
Change-Id: Ie43f23bf8f5f5b1acbb74c85cac17fe181c841c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 46d62d87101e0ee1050b00db02b3ecaa4587e9f4
Original-Change-Id: I461c6f36c28ea0eeaf7d64292c9c87ab0c9de443
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/446197
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-(cherry picked from commit f98251a4a4fe4d49721a936a684f6ac80f3f6405)
Original-Reviewed-on: https://chromium-review.googlesource.com/446300
Reviewed-on: https://review.coreboot.org/18519
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This adds SDRAM entries for the following modules:
- Micron: DDMT52L256M64D2PP-107
- Hynix: H9CCNNNBKTALBR-NUD
They are compatible with Samsung K4E8E324EB-EGCF, so this just
copies sdram-lpddr3-samsung-2GB-24EB.inc and changes the name used
in the comment near the top.
Notes on our "special snowflake" boards:
- veyron_danger's RAM ID is hard-coded to zero, so I skipped changes
involving the binary first numbering scheme.
- Rialto's SDRAM mapping is different, so I padded its SDRAM entries
to 24 to match other boards.
- veyron_mickey requires different MR3 and ODT settings than other
boards due to its unique PCB (chrome-os-partner:43626).
BUG=chrome-os-partner:59997
BRANCH=none
TEST=Booted new modules on Mickey (see BUG)
Change-Id: If2e22c83f4a08743f12bbc49b3fabcbf1d7d07dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35cac483e86e57899dbb0898dad3510f4c2ab2d3
Original-Change-Id: I22386a25b965a4b96194d053b97e3269dbdea8c7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/412328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: Jiazi Yang <Tomato_Yang@asus.com>
Original-Tested-by: Jiazi Yang <Tomato_Yang@asus.com>
Original-(cherry picked from commit bd5aa1a5488b99f2edc3e79951064a1f824062f6)
Original-Reviewed-on: https://chromium-review.googlesource.com/446299
Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18518
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix the following issues:
* A raw read is described by a single read segment, don't assert.
* Support reads longer than the FIFO size.
* Support writes longer than the FIFO size.
* Use the 400 KHz clock by default.
* Remove the error displays since vboot device polling generates
errors.
TEST=Build and run on Galileo Gen2
Change-Id: I421ebb23989aa283b5182dcae4f8099c9ec16eee
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18029
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configure the right GPIOs for finger print sensor interrupt and reset
lines.
As per the schematics GPP_C8 is for sensor interrupt and GPP_C9
is for sensor reset.
Change-Id: Ib25c68ec2fe20b1302b6170d67ceab7e8cca1a83
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18389
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
One very long line has to be wrapped to be shorter than 80 characters to
satisfy the lint scripts.
Note, that this gets rid of the brackets ().
Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18556
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Status:
- The primary PCIe 16x slot works:
It was tested with a GPU compatible with nouveau
- USB and audio are not very reliable
- The ethernet card is not seen with lspci
- The secondary pcie16x slot isn't working:
When plugging a GPU inside, it's not seen with lspci
- SATA works: The board fully boots GNU/Linux
- Serial doesn't work
- Populating the RAM slots might have to follow
the recommended memory configuration that is described
in the mainboard manual in order to be able to boot.
Note that when running the shutdown command, the default
boot firmware will rewrite part of the boot flash before
powering off the machine.
Flashing coreboot internally from the default boot fimrware can
still work, if the power plug is removed after running flashrom.
Change-Id: I934de521d0acceb7770f23b2ae15c31a67ae73eb
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/16931
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The size of the array did not match that of the actual
allocation. Furthermore, the tables are written as
part of set_pci_irqs() in hudson/pci.c.
Also the removed code was never reached runtime, as it is
only executed on ACPI S3 resume path that is currently
disabled.
Change-Id: If1c47d53a7656bdff40d93fc132c8c057184ae46
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18587
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This file is only static defines.
Change-Id: Id50a0eba1ce240df36da9bd6b2f39a263fa613df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18585
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
The current elog implementation has two event types defined for 0xa7,
apparently the result of divergent coreboot trees on chromium where
some events were added to ARM systems but not upstreamed until later.
Fix this by moving ELOG_TYPE_THERM_TRIP to be 0xab, since the current
elog parsing code in chromium is using ELOG_TYPE_SLEEP for 0xa7.
BUG=b:35977516
TEST=check for proper "CPU Thermal Trip" event when investigating a
device that is unexpectedly powering down.
Change-Id: Idfa9b2322527803097f4f19f7930ccbdf2eccf35
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18579
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move all common MSRs as per IA SDM into a common location
to avoid duplication.
Change-Id: I06d609e722f4285c39ae4fd4ca6e1c562dd6f901
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Select all Kconfig belongs into Intel SoC Family block/ips common
code model and include required header.h file.
Change-Id: Idbce59a57533dbeb9ccfadca966c3d7560537fa0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18377
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, when using `iasl` 20140926-32 [Oct 1 2014] from Debian 8
(Jessie/stable), the build of the Lenovo X60 fails due to syntax errors.
ASL 2.0 supports `<<`. For consistency, right now, coreboot still uses
the old syntax. So use `ShiftLeft` instead, which also fixes the build
issue with older ASL compilers.
Change-Id: Id7e309c31612387da3920cf7d846b358ac2bdc71
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18520
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Support for voltage margining is dependent on the platform.
Enabling voltage margining puts additional constraints for
the SLP_S0# to be asserted and hence moving to S0ix state.
If the platform PMIC/VR supports PCH voltage reduction,
voltage marigining can be enabled.
Use the UPD provided by FSP to enable/disable voltage margining.
Change-Id: Iea214e9d7d6126e8367426485c6446ced63caa66
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18469
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is selected by default and not overwritten anywhere else for this
board.
Change-Id: I0f803e130366ee322163f7bb6fa16cac75f5416e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18541
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
As we drive both channels with the same speed,
chan0dll and chan1dll are the same.
Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18472
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
AGESA AmdInitEarly() reconfigures the lapic timer in a way that
conflicts with lapic/apic_timer.
This results in an endless loop when printk() is called after
AmdInitEarly() and before the apic_timer is initialized.
This patch forces a reconfiguration of the timer after
AmdInitEarly() is called.
Codepath of the endless loop:
printk()->
(...)->
uart_tx_byte->
uart8250_mem_tx_byte->
udelay()->
start = lapic_read(LAPIC_TMCCT);
do {
value = lapic_read(LAPIC_TMCCT);
} while ((start - value) < ticks);
[lapic_read returns the same value after AmdInitEarly()]
Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/17924
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit fec8872c9d.
The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Reviewed-on: https://review.coreboot.org/18369
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
The newly assigned ACPI ID for coreboot is 'BOOT'
http://www.uefi.org/acpi_id_list
Use this new range of ACPI IDs of "BOOTxxxx" for coreboot specific
ACPI objects instead of the placeholder range of "GOOGCBxx".
Change-Id: I10b30b5a35be055c220c85b14a06b88939739a31
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18521
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix a typo that was introduce in commit 696ebc2d (Broadwell/Sata:
Add support for setting IOBP registers for Ports 2 and 3.) [1].
Setting one of the SATA port 3 IOBP setting was using the value from
the port 2 register.
On the purism/librem13 (on which SATA port 3 is tested), this change
doesn't seem to affect anything, as that typo wasn't exhibiting any
visible problems anyways.
[1] https://review.coreboot.org/18408
Change-Id: I3948def5c0588791009c4b24cbc061552d9d1d48
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18514
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Follow commit 7676730 (mb/lenovo/x60: Remove PCI reset code from
romstage). The PCI reset was copied from code specific for Roda
RK886EX and Kontron 986LCD-M. It is not needed on the MacBook.
Change-Id: I22dac962e8079732591f9bc134c1433f5c29ff4e
Signed-off-by: Axel Holewa <mono-for-coreboot@donderklumpen.de>
Reviewed-on: https://review.coreboot.org/18502
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
struct dimm_info has all the parameter types defined in stdint.h
file. So including it.
BUG=none
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: I707523749ecf415e993b460f9613eae7be859c34
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18471
Tested-by: build bot (Jenkins)
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Save SMBIOS memory information from FSP MEM_INFO_DATA_HOB in CBMEM.
Add function dimm_info_fill() which populates SMBIOS memory
information from FSP MEM_INFO_DATA_HOB data.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP to verify the type 17 DIMM info coming in
SMBIOS table from Kernel command "dmidecode".
Change-Id: I0fd7c9887076d3fdd320fcbdcc873cb1965b950c
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add the MemInfoHob.h provided by FSP v1.6.0 for aid in parsing the
MEM_INFO_DATA_HOB.
BUG=chrome-os-partner:61729
BRANCH=none
TEST=Build and boot KBLRVP
Change-Id: Ia2b528ba4d9f093006cc12ee317d02e7f3e83166
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18326
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
thinkpad_acpi expects a SSMS method to turn on/off the mute LED
and a MMTS method to turn on/off the microphone mute LED. With
these methods implemented the driver can correctly sync the LEDs
with the corresponding statuses.
There seems to be two different bits to mute the audio in the
Lenovo H8 EC:
* AMUT, used internally (for example to disable the audio before
entering S3).
* ALMT, controllable by the OS, which also toggles the mute LED
(if present).
Tested on a X220T and on a X201.
Change-Id: I578f95f9619a53fd35f8a8bfe5564aeb6c789212
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18329
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Tested-by: build bot (Jenkins)
Currently, the USB ports are still powered during S3, so turning
them off may reduce the power consumption.
Note that, when the USB Always on feature is enabled, the USB
ports are always powered, regardless of the USBP state.
This patch also disables the audio, as it might consume some
power or generate some noise.
Both the USB power and the audio are reenabled by coreboot during
the poweron.
Change-Id: If0431b1315fffef2e372e7023f830a66bb7fddae
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18464
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
On the models that support it (like the X220) the LED pulses, on
the others (like the X201) the LED powers off.
Change-Id: I2ac7dbc30609179e4ca5fc0a7b06763431fe3344
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
thinkpad_acpi expects a MHKG method which returns the current
state of the tablet mode switch shifted left by 3. If such
method is not found, subsequent laptop/tablet mode events are
ignored.
Tested on a X220T.
Change-Id: Ic9ffea2ffe507b3692d1dd7411c52b813ec32146
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This timeout is probably needed on all devices with Lenovo H8 embedded
controllers so set the default there.
Change-Id: I830ab1894f7c0f10f55c82e398becf44d810852d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18274
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The cr50 part on reef is connected to the SoC's UART lines. However,
when the tx signal is low it causes an interrupt to fire on cr50.
Therefore, keep the tx signal high in suspend state so that it doesn't
cause an interrupt storm on cr50 which prevents cr50 from sleeping.
BUG=chrome-os-partner:63283
BRANCH=reef
TEST=s0ix no longer causes interrupt storm on cr50. Power consumption
normal.
Change-Id: Idaeb8e4427c1cec651122de76a43daa15dc54d0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18491
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Apply tuning for the PCH I2C buses on Eve based on rise/fall time
measurements that were done with a scope.
BUG=chrome-os-partner:59686
BRANCH=none
TEST=Manual testing on Eve P1 to verify that all devices on I2C
buses are still functional. Post-tuning measurement will be done
once a new firmware is released.
Change-Id: I3d70ff455a20ecda374d7e7fa6cd3ab15e7f2621
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18487
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18479
Tested-by: build bot (Jenkins)
This fixes a warning that the new toolchain generates.
Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=chrome-os-partner:62967
BRANCH=None
TEST=Verified that touchscreen works on power-on and after
suspend-resume as well.
Change-Id: Id674cbcc2d524a6ed2883bf9f0e9e076890f9a85
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18466
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ie0d35c693ed5cc3e890279eda289bd6d4416d9e6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18376
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On my Thinkpad with an H8-compatible ENE KB9012 EC (GDHT92WW 1.52), when
the battery is nearly full and we switch from battery to AC by plugging
in the cable, the current rate will not drop to 0 immediately, but the
discharging state is cleared immediately.
This leads to the code trying to process an invalid rate value >0x8000,
leading to a displayed rate of >1000W.
This patch changes the logic to deal with these corner cases.
Change-Id: Ideb588d00757f259792e5ae97729e371b63a096c
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18349
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
- Remove warnings about code using deprecated declarations such as:
plat/mediatek/mt8173/bl31_plat_setup.c: In function 'bl31_platform_setup':
plat/mediatek/mt8173/bl31_plat_setup.c:175:2: warning:
'arm_gic_setup' is deprecated [-Wdeprecated-declarations]
include/drivers/arm/arm_gic.h:44:6: note: declared here:
void arm_gic_setup(void) __deprecated;
- Disable pedantic warnings to get rid of these warnings:
In file included from plat/mediatek/mt8173/bl31_plat_setup.c:36:0:
plat/mediatek/mt8173/include/mcucfg.h:134:21: error:
enumerator value for 'MP1_CPUCFG_64BIT' is not an integer constant
expression [-Werror=pedantic]
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
Change-Id: Ibf2c4972232b2ad743ba689825cfe8440d63e828
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17995
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fixes warnings that the new toolchain generates.
Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Follow up to https://review.coreboot.org/#/c/18460/
Change-Id: Ic3aada2acf3051622698e10d2e764050e16480d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
According to USB 2.0 Spec Table 7-7, the High-speed squelch
detection threshold Min 100mV and Max 150mV, and we set USB
2.0 PHY0 and PHY1 squelch detection threshold to 150mV by
default, so if the amplitude of differential voltage envelope
is < 150 mV, the USB 2.0 PHYs envelope detector will indicate
it as squelch.
On Kevin board, if we connect usb device with Samsung U2 cable,
we can see that the impedance of U2 cable is too big according
to the eye-diagram test report, and this cause serious signal
attenuation at the end of receiver, the amplitude of differential
voltage falls below 150mV.
This patch aims to reduce the PHY0 and PHY1 otg-ports squelch
detection threshold to 125mV (host-ports still use 150mV by
default), this is helpful to increase USB 2.0 PHY compatibility.
BRANCH=gru
BUG=chrome-os-partner:62320
TEST=Plug Samsung U2 cable + SEC P3 HDD 500GB/Galaxy S3 into
Type-C port, check if the USB device can be detected.
Change-Id: Ia0a2d354781c2ac757938409490f7c4eecdffe61
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d74311c25762668386061234df0562f84b7203e
Original-Change-Id: Ib20772f8fc2484d34c69f5938818aaa81ded7ed8
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/431015
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Inno Park <ih.yoo.park@samsung.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18462
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
As David commented the "Bob and other follow-ons match Gru, Kevin should
be the special case here", and update the calculations value for gru/bob
board.
From the actual tests, some regulator voltage than the actual set of less
than 20mv on bob board. (e.g: little-cpus and Center-logic) Update the
{min, max} regulator voltage for Bob board. Make sure we get the accurate
voltage.
BUG=chrome-os-partner:61497
BRANCH=none
TEST=boot up Bob, measure the voltage for little cpu and C-logic.
Change-Id: Iad881b41d67708776bfb681487cf8cec8518064e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 25e133815f49018e7496c75077b8559c207350a4
Original-Change-Id: I3098c742c7ec355c88f45bd1d93f878a7976a6b4
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/424523
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Original-Reviewed-by: Brian Norris <briannorris@chromium.org>
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/430403
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18460
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for poppy.
It enables the DPTF flag in the device tree for poppy. It also includes
the DPTF specific ASL file in the main DSDT definition.
BUG=None
BRANCH=None
TEST=Built for poppy.
Change-Id: If44b01dd3c17fea06681ccf50e8e9f406e642e36
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17926
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Once the PCI command register is written the bridge forwards
future IO and memory regions, as programmed in the respective base
and limit registers, to the secondary PCI bus.
It was previously argumented this is copy-paste and never known
to be required for these more recent platforms:
https://review.coreboot.org/#/c/2706/
Change-Id: Ic8911500a30bc83587af8d4b393b66783fa52e18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18330
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18476
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
The children of Gru should share the benefits. In the real world, Bob can't
pass the eye diagram tests.
BUG=chrome-os-partner:62714
BRANCH=firmware-gru-8785.B
TEST=build coreboot
Change-Id: I2470bbc81acdaf2458d660dca5dc307cc3038f83
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0cb3e718a7571f602a00c08a42019851634e7fd
Original-Change-Id: I0ccb48bb52eb770ccc9c8c265b07df46b0308dd3
Original-Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/440745
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/441468
Reviewed-on: https://review.coreboot.org/18461
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Camera and Imaging device should be enabled for camera usecase,
FSP provides a UPD to enable/disable the SA IMGU (Imaging Unit)
expose the same as a config option in devicetree.cb
Also remove a redundant assignment for PchCio2Enable.
BUG=None
BRANCH=None
TEST=lspci should list 00:05:00
Change-Id: I4cf7daf41bfaf4dcba414921cac2e7e12bf89f37
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18365
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This enables some required Kconfig options when CONFIG_CHROMEOS is set.
Change-Id: I290902746c1ea19c8bcb69540e34fde09abb9adf
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/18448
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
These parameters are probably the result of copying from the Thinkpad
X60 code.
Change-Id: I29763b38618d4b306c37424c5c4b57dfcf69424b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18374
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This file reportedly didn't compile on SUSE Linux with gcc 4.3.4:
[...]
> HOSTCC cbfstool/fsp_relocate.o
> In file included from coreboot/src/commonlib/fsp_relocate.c:18:
> coreboot/src/commonlib/include/commonlib/fsp.h:26: error:
> expected '=', ',', ';', 'asm' or '__attribute__' before
> 'fsp_component_relocate'
[...]
According to POSIX-2008[1], sys/types.h defines ssize_t, so include it.
This should not break coreboot code (as opposed to utils code), as we
have a sys/types.h in src/include.
[1]: http://pubs.opengroup.org/onlinepubs/9699919799/basedefs/sys_types.h.html
Change-Id: Id3694dc76c41d800ba09183e4b039b0719ac3d93
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18417
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
This is more consistent with newer Intel targets.
Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18371
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There was a 'typo' where the subsystem id was set instead of the codec
vendor id. This caused the lynxpoint HDA codecs init to fail to find
the proper codecid verbs so codecs were never initialized. That caused
the headphones jack to not work.
Change-Id: I975031643fc42937ecaea2300639b90632543f67
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18411
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
The M.2 SSD is on the SATA port 3, which also required the DTLE setting
to be set.
This fixes issues with the M.2 SSD not being detected/stable.
Change-Id: Id39d9ec395a2d9d32be4c079678d0708f08b3935
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18409
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Broadwell SATA controller supports IOBP registers on ports 0 and 1 but
Browell supports up to 4 ports, so we need to support setting IOBP for
ports 2 and 3 as well.
The magic numbers (IOBP SECRT88 and DTLE) for ports 2 and 3 were only
guessed by looking at ports 0 and 1 and extrapolating from there.
Port 3 has been tested (DTLE setting on Librem 13) and confirmed to work
so we can assume that port 2 and 3 magic numbers are valid, but having
someone confirm them (through non-public documents?) would be great.
Change-Id: I59911cfa677749ceea9a544a99b444722392e72d
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/18408
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
In order to allow GPIOs to be set/clear according to their polarity,
provide helper functions that check for polarity and call set/clear
SoC functions for generating ACPI code.
BUG=None
BRANCH=None
TEST=Verified that the ACPI code generated remains the same as before
for reef.
Change-Id: Ie8bdb9dc18e61a4a658f1447d6f1db0b166d9c12
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18427
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I538c28fb1bc412947ef9df947fa3f6a3312aeb4b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18322
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Adding spi_xfer_two_vectors as .xfer_vector for ipq40xx spi_ctrlr.
Commit c2973d196d ("UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING")
has added a new driver method xfer_vector to support combined write-read
operation within a single CS cycle. The method is wrapped in the
spi_xfer_vector() API. When spi_ctrlr structure does not have
xfer_vector method, API calls write and read operations sequentially.
However the QCA40xx SPI driver has "forced" CS activation-inactivation
in xfer method, so individual operation will break CS after write
operation, making combined write-read cycle broken.
Adding xfer_vector method to spi_ctrlr is a simple fix to prevent this.
BUG=None
BRANCH=none
TEST=built and run on Gale
Change-Id: I2258e563d0793bcacd626f78b8e96b3649a8e4a4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 88a8824951cef4fe293dfa6e3a1a837ae07b6156
Original-Change-Id: I031e85ce5b847353cb1084f6f68b2af8c6f702e1
Original-Signed-off-by: Yuji Sasaki <sasakiy@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/433439
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Kan Yan <kyan@google.com>
Reviewed-on: https://review.coreboot.org/18297
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family14 northbridge with an SB800 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
(_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c
(_SB.PCI0.LPCB).
Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18402
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
With recent change (a4b11e5c90: soc/intel/skylake: Perform CPU MP Init
before FSP-S Init) to perform CPU MP init before FSP-S init, suspend
resume is currently broken for all skylake/kabylake boards. All the
skylake/kabylake boards store external stage cache in TSEG, which is
relocated post MP-init. Thus, if FSP loading and initialization is
done after MP-init, then ramstage is not able to:
1. Save FSP component in external stage cache during normal boot, and
2. Load FSP component from external stage cache during resume
In order to fix this, ensure that FSP loading happens separately from
FSP initialization. Add fsp_load callback for pre_mp_init which ensures
that the required FSP component is loaded/saved from/to external stage
cache.
BUG=chrome-os-partner:63114
BRANCH=None
TEST=Verified that 100 cycles of suspend/resume worked fine on poppy.
Change-Id: I5b4deaf936a05b9bccf2f30b949674e2ba993488
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18414
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a function to allow FSP component loading separately from silicon
initialization. This enables SoCs that might not have stage cache
available during silicon initialization to load/save components from/to
stage cache before it is relocated or destroyed.
BUG=chrome-os-partner:63114
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae77e20568418c29df9f69bd54aa571e153740c9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18413
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
poppy board uses Maxim 98927 speaker codec and Realtek RT5663
for headset. Select the apropriate NHLT blobs to be packaged in CBFS.
Also, generate the required ACPI NHLT table for codec and the supported
topology in poppy.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=With the required driver support in kernel verify that
the Audio plays on on-board speakers and headset, recording
works from on-board mics and headset mics.
Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed
Signed-off-by: M Naveen <naveen.m@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18214
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18397
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add the audio devices to Eve mainboard:
- Describe Maxim 98927 speaker amps and RT5663 headphone codec
in ACPI so they can be enumerated by the OS.
- Supply NHLT binaries for MAX98927, RT5663, and DMIC_4CH.
BUG=chrome-os-partner:61009
TEST=manual testing on Eve P1 with updated kernel to ensure that
both speakers and headset are functional. DMIC support is
is still being worked on and is not yet functional.
Change-Id: I5243e35d159a0ed15c6004e94ba5a50b28cff0a9
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18398
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Created using autoport plus some manual work and copying from G505S to
account for the non-H8 EC.
This model uses the same ENE KB9012 EC as the G505S.
Tested:
- Mainboard variant with 8GB Elpida DDR3
- SeaBIOS payload
- Booting into Linux 4.9.6 with Debian/unstable installed on the
internal HDD/SDD slot
- Native raminit
- Both native VGA init and option rom VGA init
- Basic TPM functionality (auto-detection and RNG)
- Battery status readout
- Basic ACPI functions (power button event; power-off; reboot)
- thinkpad-acpi hotkey functions
- thinkpad-acpi LED control (red thinkpad LED)
- Suspend to RAM and resume works
- Mini displayport output works
Known issues:
- Patches needed for EC battery support
https://review.coreboot.org/#/c/18348/https://review.coreboot.org/#/c/18349/
- No thermal zone since temperature sensing is not H8-compatible
and needs to be reverse engineered.
Not tested:
- msata/wwan (probably works)
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Change-Id: I52bc4515277e5c18afbb14a80a9ac788049f485c
Reviewed-on: https://review.coreboot.org/18351
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18399
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.
Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18380
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Not selecting the Kconfig option `GENERATE_SMBIOS_TABLES` the build
fails with the error below.
```
CC ramstage/ec/lenovo/h8/h8.o
src/ec/lenovo/h8/h8.c:201:2: error: unknown field 'get_smbios_strings' specified in initializer
.get_smbios_strings = h8_smbios_strings,
^
src/ec/lenovo/h8/h8.c:201:2: error: initialization from incompatible pointer type [-Werror]
src/ec/lenovo/h8/h8.c:201:2: error: (near initialization for 'h8_dev_ops.read_resources') [-Werror]
cc1: all warnings being treated as errors
```
So add the appropriate preprocessor guards to fix the build error.
Change-Id: I3baed452d422539a805c628a8c4a6a8c2a809317
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17770
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.
Changes is being verified and booted to Yocto with Saddle Brook.
Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/18364
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0f.
Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18368
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a test in case we have a DIMM2 not populated but DIMM3 is.
Change-Id: I14f82afe03884740570838e7b2771233356c518d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18386
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Coverity is detecting 'sp' as a variable which has not been initialized.
This is obviously not correct, so this patch *TRIES* to mark it as false
I'm not positive that this will work because the annotation needs to go
on the line above the error, but this error is inside of a # define.
Does the whole #define count as one line? Can it go on the line
above the #define in the .h file? Does it have to precede every line
where the #define is used? The documentation doesn't make this clear.
Should suppress coverity issues: 1368525 & 1368527
uninit_use: Using uninitialized value sp.
Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18247
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18396
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18395
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:
- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP
BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10
Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for more ACPI features in the generic SPI ACPI
driver so it can be flexible enough to support more devices,
or devices in different configurations.
- add a wake pin
- add support for using IRQ GPIO instead of PIRQ
- add power resource support with enable and reset gpios
BUG=chrome-os-partner:61233
TEST=ensure existing SSDT generation is unchanged,
and test that new features generate expected code
Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18393
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add individual macros for the various interrupt types so
they can be used in devicetree.
BUG=chrome-os-partner:58666
TEST=nothing uses this yet, will be used in an upcoming commit
Change-Id: I2a569f60fcc0815835615656b09670987036b848
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18392
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move the function that adds a power resource block from
i2c/generic to the acpi device code at src/arch/x86/acpi_device.c
so it can be used by more drivers.
BUG=chrome-os-partner:61233
TEST=verify SSDT table generation is unchanged
Change-Id: I0ffb61a4f46028cbe912e85c0124d9f5200b9c76
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18391
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The hybrid driver select by DRIVERS_LENOVO_HYBRID_GRAPHICS doesn't work
for t400/t500.
Replace it with a custom romstage implementation.
Tested on Lenovo T500 with dual graphics:
* Intel Native GFX init
* AMD VBios
* GNU Linux 4.8.13
* SeaBios as payload
* Discrete is working (44 W)
* Integrated is working (24 W)
* Switchable is working (34 W)
** Both GPUs are enabled, with Intel being connected to the panel
** DRI_PRIME allows to use AMD GPU
** ACPI doesn't seem to work (no vgaswitcheroo)
Depends on Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Depends on Change-Id: If389016f3bb0c4c2fd0b826914997a87a9137201
Change-Id: I7496876e9b434d4a2388e1ede27ac604670339b7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18010
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: M Naveen <naveen.m@intel.com>
Signed-off-by: Dylan Reid <dgreid@chromium.org>
Reviewed-on: https://review.coreboot.org/18211
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18312
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: https://review.coreboot.org/18366
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for generating digitizer node in SSDT using wacom i2c
driver.
BUG=None
BRANCH=None
TEST=Verified that the node shows up in SSDT.
Change-Id: If7e1e2463778c2ff7263eff995def149457edcde
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Similar to I2C driver, add support for generating SPI device and
required properties in SSDT for ACPI.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles succesfully. Verified SPI device generated in SSDT on
poppy.
Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18342
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
scan_smbus routine does not perform any smbus specific operation. Thus,
rename the routine to scan_generic_bus so that it can be used by other
buses like SPI. Add a wrapper scan_smbus to allow other users of smbus
scan to continue working as before.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I8ca1a2b7f2906d186ec39e9223ce18b8a1f27196
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18363
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18340
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Add a new callback to spi_ctrlr structure - get_config - to obtain
configuration of SPI bus from the controller driver. Also, move common
config definitions from acpi_device.h to spi-generic.h
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I412c8c70167d18058a32041c2310bc1c884043ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18292
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/18287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17909
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit 32997fb0bc.
This change is breaking I2S audio on Kabylake platforms so
revert the change to fix audio.
BUG=chrome-os-partner:61548,chrome-os-partner:61009
TEST=manual testing on Eve P1 system
Change-Id: I3212c8be83078ed57e38501386605e67b87d5bd0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18360
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Some variants need the internal pull resistor on GPIO_SSUS_40
set explicitly to pull down rather than disabling the pull,
in order for the ram-id to be read correctly via GPIO.
Correct this by adding a function to enable and set the internal pull
and define its use as needed in the board's variant.h.
Chromium source:
branch: firmware-gnawty-5216.239.B
/src/soc/intel/baytrail/baytrail/gpio.h#418
/src/mainboard/google/gnawty/romstage.c#60
Test: boot 4GB Candy board and observe correct RAM id, amount detected
Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18309
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18294
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Poppy doesn't support 8042 keyboard. Select
NO_FADT_8042 to disable 8042 in FADT header.
Kernel will not try to access 8042 region
if 8042.FADT=0
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/18311
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Kernel relies on FADT 8042 flag to enable/disable
8042 interface. If FADT reports 8042 capability and
8042 (/PS2) capability is actually disabled by coreboot,
kernel would assume the presence of 8042 based on the
FADT flag. This results in undesired system power off when
kernel tries to access the 8042 memory region. To address
this, CONFIG_NO_FADT_8042 was added to selectively
disable 8042 on FADT.
BUG=chrome-os-partner:61858
TEST=Boot OS and verify FADT 8042 flag
Change-Id: Ic80b3835cb5cccdde1203e24a58e28746b0196fc
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/18307
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update DPTF parameters based on thermal team test result.
1. Update TSR2 trigger points.
TSR2 passive point: 70, critical point: 90
2. Set PL2 Max to 15W.
BUG=chrome-os-partner:61383
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team
Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/18318
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Void pointer arithmetics are forbidden in standard C but GCC has
an extension that allows it.
Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18293
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Performance degradation seen with current PL1 throttling rate as 8
seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1
throttling rate to 15 seconds, fps score improved.
BUG=chrome-os-partner:60038
BRANCH=reef
TEST=Built and tested on electro system
Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/18317
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
There will be more follow-up changes.
BUG=chrome-os-partner:62377
BRANCH=None
TEST=emerge-scarlet coreboot libpayload
Change-Id: I9ca45598ff0ab12bf8063d16a86be564cf509390
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a020a9ba1228b15599e202972df0096f58b1b31c
Original-Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a
Original-Signed-off-by: philipchen <philipchen@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/433039
Original-Commit-Ready: Philip Chen <philipchen@chromium.org>
Original-Tested-by: Philip Chen <philipchen@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18296
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18265
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18264
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Also make sure that no board changes behaviour because of that by adding
a static assert.
TEST=abuild over all builds still succeeds (where it doesn't if
DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the
device/dram code).
Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18254
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Shorten field names of struct cbmem_console since saying "buffer_" in
front of everything is redundant and we can use the gained space to save
some line breaks in the code later. This also aligns the definition with
the version in libpayload.
Change-Id: I160ad1f39b719ac7e912d0466c82a58013cca0f9
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The FSP UPD offsets and the corresponding structure size do not match,
CpuConfigData.h needs an update to align the same. Hence update the
header file based on FSP version 1.4.0.
BUG=chrome-os-partner:61548
BRANCH=none
TEST=Built and booted KBLRVP and verify that all UPDs are in sync in
both coreboot and FSP.
Change-Id: I5ef7cbb569c3d1a44e7846717201952a0acf12ab
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/18285
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The apollolake boards don't have an me.bin proper, but they still have
descriptor regions which need to be locked down. Therefore, remove the
restriction of HAVE_ME_BIN from LOCK_MANAGEMENT_ENGINE.
BUG=chrome-os-partner:62177
TEST=For apollolake one can select LOCK_MANAGEMENT_ENGINE.
Change-Id: I73aab3a604ec25cd56d760bf76cc21c5a298799e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18304
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Dump the CSE status registers for potential debugging purposes.
Explicitly call out manufacturing mode of the part since it's
important shipping devices ensure manufacturing mode is locked
down. Intel is planning on writing a common driver so a complete
status -> string dumps was not done because (surprise surprise)
not all the fields are equal with previous implementations.
BUG=chrome-os-partner:62177
BRANCH=reef
TEST=Booted and noted dump of CSE status registers.
Change-Id: I71d15722bb193877f1569c1d3e7f441302f5bd14
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18303
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fixes an issue on systems where the S3 state in the pm1 control
registers are not cleared when vboot determines recovery mode is
required on an S3 resume. The EC code will reboot the system knowing
that the EC was in RW. However, on subsequent entry into romstage the
S3 path will be taken and fails to recover cbmem -- forcing another
reboot. To work around that, signal to the platform a reboot is
happening and let the platform perform the necessary fix ups to the
register state.
BUG=chrome-os-partner:62627
Change-Id: Ic144b11b4968c92a1273b8d9eb9dc10f0056bf3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/18295
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Eve is a convertible add support for sending Tablet mode switch
changes from EC to AP.
Change-Id: I35133ebc1439852d0ceb88d7d679b37356b0869d
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/18276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add a new driver GOOG0006 to report tablet switch
to user space.
On glados based convertible, check that with a new kernel driver
(cros_ec_tbmc) that evtest collects tablet switch changes.
Change-Id: I6821eaac1feb6c182bc973aaa2f747e687715afb
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/430951
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/18173
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Options with no prompt can go anywhere in the tree with the same
dependencies and they have the same effect. Moving them lower in
the tree allows the default values to be overridden by other Kconfig
files.
This patch just moves options with default values that aren't 'n'. The
'n' options are just removed in the next patch, since they aren't needed.
Verified that this makes no significant changes to any config file.
Change-Id: I46175756b937a241edba87dbf70ce1be851fa89d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17907
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The WAK_STS bit is not set in a wake from G3, so the check for this
bit needs to only be done when checking for a wake from S3.
This change correctly enables the keyboard backlight in wake from G3
and only does not enable it during a wake from S3.
BUG=chrome-os-partner:58666
TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard
backlight turns on like it does when waking from S5. Also force enter
hibernate with Alt+VolumeUp+H and then power back up and ensure that
the keyboard backlight is enabled when booting.
Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18280
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Kconfig options that we might want to override the default,
move the fallback default to the bottom of the file. This allows
the default to be set anywhere else, without requiring a select.
This is especially important for non-boolean symbols, which can't
have their defaults overridden in the Kconfig. Those can only be
updated in a saved config file.
Verified that this makes no significant changes to any config file.
Change-Id: I66034f356428f4ccd191d7420baf888edd5216dc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17906
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When guado/rikku/tidus were rolled into jecht, an error was
made in set_power_led() as guado/rikku set the polarity
differently than tidus. Fix the power LED for guado/rikku
by setting the polarity correctly.
Test: boot guado/rikku and observe proper function of power LED
under S0, S3, and S5 power states.
Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18249
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Bit 16 in BLC_PWM_CTL enables brightness controls, but the
current value is generic. Use the proper value, obtained
by reading BLC_PWM_CTL while running the VBIOS.
Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f
Signed-off-by: Francis Rowe <info@gluglug.org.uk>
Reviewed-on: https://review.coreboot.org/10624
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reason for revert:
Pyro has two touchscreen sources: WACOM/ELAN.
It will not have both touchscreen IC in one system at the same time.
So the "probed" property of WACOM i2c device is mandatory to set for kernel
to know whether it exists before driver initializes it.
Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF
will be invoked to set GPIO#152 low to cut off power.
BUG=chrome-os-partner:62371
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This also selects RELOCATABLE_RAMSTAGE and
CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell.
Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change fixes the two sets of pins that were swapped in the
map of DQS signals from CPU to DRAM for channel 1.
Although this does not appear to have any impact to the system it
does result in different register values for DQS pin mapping that
are programmed inside FSP.
BUG=chrome-os-partner:58666
TEST=This fix was verified against the current schematic and using
FSP debug output.
Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18279
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74
this is required for poppy board as well.
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=None
BRANCH=None
TEST=play test sound in OS over internal speaker
Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/18282
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals
when doing GPIO-driven I2S. This needs to be high by default so
the DSP can drive these signals, instead of low where it is enabled
for GPIO-driven I2S and the DSP cannot drive these signals.
BUG=chrome-os-partner:58666
TEST=play test sound in OS over internal speaker
Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18281
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The me_cleaner option is available on multiple platforms:
* Sandy and Ivy Bridge (well tested by multiple users).
* Skylake and Braswell (tested).
* Haswell, Broadwell and Bay Trail (untested).
The untested platforms have been included anyways because all the
firmwares are very similar and Intel ME/TXE probably behaves in the
same way.
Change-Id: I46f461a1a7e058d57259f313142b00146f0196aa
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/18206
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add VFCT table to provide PCI Optiom Rom for
AMD graphic devices.
Useful for GNU Linux payloads and embedded dual GPU systems.
Tested on Lenovo T500 with AMD RV635 as secondary gpu.
Original Change-Id: I3b4a587c71e7165338cad3aca77ed5afa085a63c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: I4dc00005270240c048272b2e4f52ae46ba1c9422
Reviewed-on: https://review.coreboot.org/18192
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:62110
BRANCH=reef
TEST=Apply new firmware to evaluate Octane benchmark score.
Change-Id: I51734051586753677129314b5273fb275c74f5d2
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/18283
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This allows for defaults to be applied to CMOS parameters
when cmos checksum is incorrect.
This probably results in changed cmos settings for current users of
these targets.
Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17041
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Activate the IOMMU for the ASUS F2A85-M LE board.
Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by
enabling the option in `buildOpts.c`.
ACPI and MPTABLES interrupt routers are already present since they are
syminks to the F2A85-M version.
```
$ uname -a
Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux
$ lspci -s 0.2
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit
$ dmesg | grep -i IOMMU
ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD AMDIOMMU 00000001 AMD 00000000)
AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2
iommu: Adding device 0000:00:01.0 to group 0
[...]
iommu: Adding device 0000:00:18.5 to group 9
iommu: Adding device 0000:03:00.0 to group 8
AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40
AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de>
```
Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18259
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with minimum changes. Special adaptations for MC APL1
mainboard will follow in separate commits.
Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/18272
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty,
heli, kip, orco, quawks, squawks, sumo, swanky, and winky using
their common reference board (rambi) as a base.
Chromium sources used:
firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...]
firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...]
firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...]
firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...]
firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...]
firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...]
firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*]
firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.]
firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data]
firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data]
firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...]
firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table]
firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...]
The same basic cleanup/changes are made here as with the initial BYT
variant commit:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
- Micron 2GB SPD file for kip with updated values renamed to distinguish
from same file used by other boards
Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18164
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
That status isn't needed and making it non-static helps gcc 4.9.2 (or
any compiler that insists on "standard C" behaviour with global const
initializers)
Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/18266
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We rely on gnu make, so we can expect the jobserver to be around in
parallel builds, too. Avoids some make warnings and slightly speeds up
the build if those sub-makes are executed (eg for arm-trusted-firmware
and vboot).
Change-Id: I0e6a77f2813f7453d53e88e0214ad8c1b8689042
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/18263
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reorder the items to minimize the differences.
Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17438
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The rule to make spd.bin that's in src/lib is for the 'generic_spd_bin'
implementation. It wasn't guarded though, so it was generating a build
warning for any other platform that generated an spd.bin file.
Sample warning that this fixes:
src/mainboard/gizmosphere/gizmo/Makefile.inc:42:
warning: overriding recipe for target 'build/spd.bin'
src/lib/Makefile.inc:298: warning: ignoring old recipe for target
'build/spd.bin'
Change-Id: Iadd6743f8ae476969bf36f99b918f04c04172d1d
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/18261
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Apollolake boards should use DMIC-4ch configuration in Kernel side and
use CaptureChannelMap in userspace to distinguish boards with different
number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will
not be required and hence removed.
BUG=chrome-os-partner:60827
TEST=Verify internal mic capture
TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works
Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/18252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
EC sets the logic level based on outstanding wake events. When GPIO_22
is configured as a level triggered interrupt, the events are not
cleared from the interrupt handler. Hence, we'd just be re-signalling
over and over causing an interrupt storm upon lid open. So, GPIO_22
needs to be configured as EDGE_SINGLE instead of LEVEL.
BUG=chrome-os-partner:62458
TEST=Lid close/open. check CPU usage using top. It should
not show 70% CPU usage.
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a
Reviewed-on: https://review.coreboot.org/18267
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For the boards that intend to use mock tpm and have recovery mrc cache
support enabled, provide mock functions to read and write mrc hash
space.
Reading MRC hash space returns TPM_SUCCESS as later checks take care of
comparing the hash value and retraining if hash comparison fails. Thus,
in case of mock tpm, device would always end up doing the memory
retraining in recovery mode.
BUG=chrome-os-partner:62413
BRANCH=None
TEST=Verified that eve builds with mock tpm selected.
Change-Id: I7817cda7821fadeea0e887cb9860804256dabfd9
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18248
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
1. For ELAN, export reset GPIO as well as PowerResource
2. For WCOM, export PowerResource
BUG=chrome-os-partner:62311, chrome-os-partner:60194,
chrome-os-partner:62371
BRANCH=reef
TEST=Verified that touchscreen works on pyro with WCOM device on
power-on as well as after suspend/resume.
Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18239
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18238
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during
standby states S3/S0ix. This causes leakage of power. To reduce the
leakage, we have to pull these lines high during S3/S0ix. This is
done by programming the IOSSTATE to HIz. Also note that we are using
the internal pull ups to keep at SOC at 1.8V and the I2C lines are
not floating.
BUG=chrome-os-partner:62428,chrome-os-partner:61651
TEST=Enter S3/S0ix. Measure trackpad power. It should be less
than 4mW. Also I2c lines should be pulled high in S3/S0ix.
Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/18251
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
If cmos is invalid, it doesn't make sense to read the value before
finding that out.
Change-Id: Ieb4661aad7e4d640772325c3c6b184de1947edc3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18236
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Wacom touchscreen is i2c hid device and it's the device that always
exists.
So no need to set "probed" property for it.
BUG=chrome-os-partner:61513
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18227
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The default macaddress in rt8168.c can be changed with a cbfsfile
called macaddress. This patch makes it possible to add such a file
using Kconfig at build time.
This also changes the name of the cbfsfile from "macaddress" to
"rt8168-macaddress" to avoid confusion.
Change-Id: I24674d8df11845167b837b79344427ce0c67f4fb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18088
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat
-Wformat-security`, causing errors similar like the one below.
```
CC romstage/northbridge/amd/amdht/ht_wrapper.o
src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify':
src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security]
printk(log_level, event_class_string_decodes[evtClass]);
^
[…]
```
Fix that, by explicitly using a format string.
TEST=Built and booted on ASUS KGPE-D16.
[1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for
"fprintf, error: format not a string literal and no format arguments [-Werror=format-security"
[2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609.
Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18208
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This fixes building coreboot with -std=gnu11 on gcc 4.9.x
Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing
type.
Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18220
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This reverts commit 580db7fd90.
There's a (parallel) mechanism more closely aligned with how the values
are filled in (fixed device part + version string) that landed from
Chrome OS downstream (see commit 4399b85fdd).
Change-Id: I5ccd06eadabb396452cc9d1d4dff780ea0720523
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18205
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
In order for PD charge events to properly notify the OS when a charger is
attached we need to enable the PD MCU device and event source from the EC.
Without this change the charging still happens, but the OS does not notice
and update the charge state icon in the Chrome OS UI.
BUG=chrome-os-partner:62206
BRANCH=none
TEST=plug in a charger to either port and see charge status updated to
indicate charging in the power_supply_info tool and the Chrome OS UI.
Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18209
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add support for Lenovo Thinkpad L520.
The files are generated by autoport,
and are successfully tested on the board.
L520 has got 4MiB flash chip, that contains a "slim" ME
with 1.2MiB only. The flash IC has to be desoldered, as
it won't be accessible in circuit. It is located on top
of the mainboard right under the touchpad.
Test-setup:
Extract the following blobs from vendor BIOS:
* Intel Flash Descriptor
* Intel Management Engine
* Intel VBios
The laptop has been externaly flashed. It was able to
turn on the display and load SeaBIOS.
Latest debian has been booted from harddisk.
Latest fedora has been booted from USB flash drive.
The following hardware has been tested and is working:
* Display using Option Rom
* PCIe wifi
* Ethernet
* Keyboard, trackpoint and touchpad
* Some Fn functions keys
* Volume Keys (except mic mute)
* Status LEDs
* Audio (headphone jack only)
* USB ports
* Native raminit dual channel (2 DDR3-1333 DIMMs tested)
* SATA cdrom
* SATA harddrive
Broken:
* Some Fn functions keys
* Microphone mute button
* Speakers (but headphone jack gives sound)
Untested:
* Expansion slot
* SD card slot
* Docking station
* Native gfx init
The EHCI debug port is the first one on the right side.
Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18003
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18039
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
o Fix indentation and other whitespace issues,
o Use `const` where applicable,
o Avoid retyping the same constant literals,
o Actually read PCI revision from the device (instead of using the
lowest class byte).
Change-Id: I2c64153c61a51a6a87848360d22f981225812a3b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18185
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18038
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently, it will print the function name as a prefix to the debug
output. Make it so that a null function name won't get printed, so
that it's possible to print little bits of debug output.
BUG=chromium:683391
BRANCH=none
TEST=build_packages --board=reef chromeos-firmware
Change-Id: I046fa766773fc08a29460db1f884d7902692d182
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 853ff7176e97e5e1ab664d094e1914c9c94510aa
Original-Change-Id: I1dff38e4d8ab03118e5f8832a16d82c2d2116ec9
Original-Signed-off-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/431111
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18204
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Duncan Laurie