This patch uses the fill_processor_name function in order
to fetch the CPU Name.
TEST = Successfully able to build boot Waddledoo and verify the
cpu_name from CPU log "CPU: Genuine Intel(R) CPU 0000 @ 1.10GHz".
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I532e05d9bb71fdff24e086e81ec72ffe8dc2c22d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43480
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Strip manufacturer information from SPDs before injecting into APCB.
This allows more flexibility around changing DRAM modules in the future.
BUG=b:162098961
TEST=Boot, dump memory info
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I1bbc81a858f381f62dbd38bb57b3df0e6707d647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is already defined in <commonlib/helpers.h> and it gets included
implicitly by some other header. Fixes building with code coverage.
Change-Id: Id2dc6cc34b6f1d351d8e1b52d8cc4ada8666c673
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add interrupts for all enabled superio devices to quiet the warning
about missing interrupts in devicetree.
Vendor uses interrupt 0x00 for all devices except SUART* and KBC, so
let's do that, too. This also changes SWC from 0x0b to 0x00.
Verified with superiotool on X11SSM-F.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I7a6dc7345f020e53415a7d0d104ce93ab4b194fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonas Löffelholz
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add VPD variables for enabling/disabling FRB2 watchdog timer and setting
the timer countdown value in romstage. By default it would start the timer
and trigger hard reset when it's expired. The timer is expected to be
stopped later by payload or OS.
Add RO_VPD and RW_VPD sections.
Tested on OCP Tioga Pass.
Change-Id: I53b69c3c5d22c022130fd812ef26097898d913d0
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
When emitting a fan's _FPS (Fan Performance States) table, the revision
field was missing. According to ACPI spec 6.3, the current revision is
zero, so add that Package entry before the others.
BUG=b:149722146
TEST=verified first element of \_SB.DPTF.TFN1._FPS is 0
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If16d4751f1d924807f5087d93b348e58d5265197
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43978
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the Kconfig flag VBOOT_VBNV_CMOS_BACKUP_TO_FLASH for psp_verstage
to save the vbnv data to the SPI rom.
BUG=b:161366241
TEST=Boot Morphius, Read rom from SPI and extract the RW_NVRAM region.
See that it's getting updated.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0d4b92fa321a8409468b8d8fc40be0d4b57b664b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43487
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SPI needs to be initialized to save VBNV (Vboot Non-Volatile memory)
to flash.
BUG=b:159811539
TEST=Build & boot.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iebf3ed3f5d6be0dda717d91d5b2fbcf2a1cc43cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Two usb Type-C ports under the actual mux device. Each port has its own
ACPI device entry. These nodes are the ones that the USB Type-C
port/connector device will refer to in order to configure the mux.
TEST=Built image-tglrvp-up4.bin successfully.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8423ddbb5bc189899a9e19e7da6e2ee7b7fecc18
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Currently, if PSPBTLDR_FILE is empty, the md5sum will hang forever on
stdin, leading to the appearance of a hung script. This is
confusing.
There's no option to md5sum to say "you must use this file", so instead,
use dd with if to ensure we at least get an error if the file is not found.
Not optimal, but better than what we have now.
Change-Id: Ia13035bc592bdf2a515dfd2e052ae9135e218612
Signed-off-by: Ronald G Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Fill in the new fields introduced with version 3.0 and install the new
entry point structure identified by _SM3_.
Tested on Linux 5.6 using tianocore as payload:
Still able to decode the tables without errors.
Change-Id: Iba7a54e9de0b315f8072e6fd2880582355132a81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rearrange code to unify with the rest of xx20/xx30 boards. No functional
changes - just smaller diff output.
Change-Id: I5867b2a90b2e53a3a9dd919701f1e185cb39cf78
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace functionally identical files with t440p/acpi/superio.asl which
is licensed under more flexible terms (GPL-2.0-only or no licensing
terms vs. GPL-2.0-or-later). Apart from licensing terms these files are
identical.
This makes diff between boards smaller.
Change-Id: I1cd4a85b65ceaa0a383416e7276ad41a41783cb7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43685
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
BUG=b:161215903
BRANCH=NONE
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib61af2399541c4caf4a310a34e778e0ba1cbd3ab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43802
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow schematic to modify USB port setting and clean up I2C clock tuning.
USB2 [0]: USB Type C Port 0
USB2 [1]: USB Type C Port 1
USB2 [2]: None
USB2 [3]: USB Type A Port 1
USB2 [4]: None
USB2 [5]: Camera
USB2 [6]: None
USB2 [7]: WLAN module - BlueTooth
USB3 [0]: USB Type C Port 0 (M/B side)
USB3 [1]: USB Type C Port 1 (Sub/B side)
USB3 [2]: None
USB3 [3]: USB Type A Port 1
USB3 [4]: None
USB3 [5]: None
BUG=b:161407664
BRANCH=NONE
TEST=Build the coreboot image on madoo board.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ia73593f52adee3806e725127891f084a08bf1360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43750
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:153588771
TEST=Verified that I2C5 frequency is between 389-396kHz.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: If59502aec7c3ab55864a518d626cde52aee18373
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43746
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a missing newline to a printk in the max98373 driver.
BUG=none
TEST=verified BIOS boot log is properly formatted on volteer.
Change-Id: I1c989729bdc71736975901566023e0057a6d0556
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This adds the PCI ID of the realtek 5261 PCIe to SD Express card
reader.
BUG=b:161774205
TEST=none
Change-Id: I4d5e6cfca59b02adc74a0c148281a92421fe209d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This copies over the USB daughterboard device tree config from volteer
to volteer2. These two boards are basically identical in this area so
the config should also be identical.
BUG=b:158673460
TEST=none
Change-Id: If8a82bc18b36d92a1c851b49612edfbefa18ec54
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Re-organize the existing generic wifi driver into a generic wifi chip
driver. This allows generic wifi chip information to be added to the
devicetree.
BUG=None
TEST=./util/abuild/abuild
Change-Id: I63f957a008ecf4a6a810c2a135ed62ea81a79fe0
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43768
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:161734657
TEST=Ensure that the discrete WiFi information is built into ACPI table.
Scope (\_SB.PCI0.RP01)
{
Device (WF00)
{
Name (_UID, 0x923ACF1C) // _UID: Unique ID
Name (_DDN, "WIFI Device") // _DDN: DOS Device Name
Name (_ADR, 0x00000000) // _ADR: Address
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x43,
0x03
})
}
}
Change-Id: I9a9259e167fc213291b89e151729553ec4649eaf
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43769
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop a leading blank line in the license header comment.
Change-Id: Ic3d7568303f9d816a8727a2960270e7667d41104
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
On Haswell platforms, the processor and the PCH are two separate dies,
and communicate through a high-speed bus. This is DMI (Direct Media
Interface) on traditional two-package platforms, but single-package
Haswell LP variants use OPI (On-Package Interconnect) instead.
Since OPI is not routed through the mainboard, most link parameters are
static and cannot be changed. OPI self-initializes on boot, anyway.
However, DMI needs to be initialized in firmware. On Haswell, the MRC
initializes the physical DMI link, but things like topology and power
management need to be configured as well. And we don't do that properly.
We enable ASPM on the PCH side of the DMI link, but not on the SA side.
Both sides need to use the same settings, so enable DMI ASPM on the SA.
Clearing the error status bits needs to be done on all Haswell variants.
Tested on Asrock B85M Pro4, still boots.
Change-Id: Ie97ff56eec9f928cfd2d5d43a287f3e0d2fbf3cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Looks like no one really knows what this bit would be useful for, nor
when it would need to be set. Especially if coreboot is setting it even
on PCI *Express* bridges. Digging through git history, nearly all
instances of setting it on PCIe bridges comes from i82801gx, for which
no reason was given as to why this would be needed. The other instances
in Intel code seem to have been, unsurprisingly, copy-pasted.
Drop all uses of this definition and rename it to avoid confusion. The
negation in the name could trick people into setting this bit again.
Tested on Asrock B85M Pro4, no visible difference.
Change-Id: Ifaff29561769c111fb7897e95dbea842faec5df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove the obscure path in source code, where ACPI S3 resume
was prohibited and acpi_resume() would return and continue
to BS_WRITE_TABLES.
The condition when ACPI S3 would be prohibited needs to be
checked early in romstage already. For the time being, there
has been little interest to have CMOS option to disable
ACPI S3 resume feature.
Change-Id: If5105912759427f94f84d46d1a3141aa75cbd6ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This applies what commit 79572e4f32 does
to the devicetree settings of amd/mandolin.
Change-Id: I6cc0a2b60b13a809016225caf3c89f730deb4ce0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Since there aren't any other variants, we can move things between the
devicetree and the overridetree.
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I54aac67237a3850dbf11f58bd41aba87505214f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43927
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Built with BUILD_TIMELESS=1, resulting coreboot.rom does not change.
Change-Id: I655bc7576e8ff48258a2a19387e01372f4bbea3d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Todor is created to take the place of terrador therefore
copying terrador content into todor's setup.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I63151728a04f2252ca8a77158a2656ad8b1e1b51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Create the todor variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
In addition,
* sort the variant names in alphabetical order.
* todor uses the same config options as terrador.
BUG=b:162110806
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_TODOR
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I7aa7acf1f3c3cc14b92ded05d5868818a627a432
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Use the common driver to configure the GPIOs on the Delta Lake
platform as done for Tioga Pass in commit 89d2aa0. The GPIO
settings are dumped by inteltool with original UEFI firmware,
then use intelp2m to generate header file.
TEST=Dump GPIO settings by Intel ITP and check if match gpio.h.
Change-Id: I8005d4caa2d87b6831099bfec3a40246224f3cb5
Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All boards disable PIRQs, except purism/librem_bdw. Since IRQ0 is
invalid and modern OSes don't use PIRQ routing, disable the PIRQs.
Change-Id: I93b074474c3c6d4329903cab928dc41e1d3a3fb3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
All boards disable PIRQs. They aren't used on modern OSes anyway.
Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I744939bee3d51ac25c1cc2dcd3359fe571c9e408
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43898
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Simplify if-statements and use is_dev_enabled() where possible.
Change-Id: I791273e5dd633cd1d6218b322106e2f62a393259
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43897
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the eldrid variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:162115131
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_ELDRID
Signed-off-by: MiceLin <mice_lin@wistron.corp-partner.google.com>
Change-Id: I1cd07ee7a87335e1e0b51d65c26bffc3bc46037c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Because there was a lot of discussion about the size increase,
I also looked at the impact of calling the get_spi_bar() function
vs reading spi_base directly and just not worring about whether
or not spi_base was already set.
Using the spi_base variable directly is 77 bytes bytes for all 6
functions. it's roughly double the size to call the function at
153 bytes. This was almost entirely due to setting up a call stack.
If we add an assert into each function to make sure that the spi_base
variable is set, it doubles from the size of the function call to
333 bytes.
For my money, the function call is the best bet, because it not only
protects us from using spi_base before it's set, it also gets the
value for us (at least on x86, on the PSP, it still just dies.)
BUG=b:161366241
TEST: Build
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I0b0d005426ef90f09bf090789acb9d6383f17bd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Mark that psp_verstage is running in userspace so that it won't run
the code in dcache_clean_all() and hang the system.
BUG=b:161554141
TEST=Run board through a bunch of recovery cycles.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I936dcec18a2be9ec8636ce77bb0954f4fc58153e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make an empty macro for dcache_apply_all for code running in userspace
so that we don't hang the system.
BUG=b:161554141
TEST=Run board through a bunch of recovery cycles.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I3dc0f40dfe4d4a699528068154eee2d3c23d3d74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This lets code that run in userspace notify coreboot of that fact so
things that can't run in userspace can be excluded.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I4da414bc96cfcf0464125eddc6b3f3a7b4506fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43784
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Neither the family 17h model 10-1Fh PPR nor the internal FSP source
seems to have the mapping of the USB OC pins to the four bit values, so
this is based on the information from the family 15h model 70-7Fh BKDG
which also corresponds to what I'd have expected here.
BUG=b:162010077
Change-Id: I581ef1d730e9d729d9849d7e73ef1c1b67b2c4cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some smart battery patches have been backported to the ChromeOS 4.19 kernel,
and userspace can now access smart battery data from sysfs instead of using
the hacky ectool instead.
Also change all space indents into tab indents while we're here.
BUG=chromium:1047277
TEST=confirmed a /sys/class/power_supply/sbs-i2c device shows up
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I43687e63e4c1a7756c117129ced20749afc1b9e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Invoke PCIe root port devicetree update to swap the enabled root port
devices with the disabled devices.
BUG=b:162046161
TEST=Ensure that the PCIe device 1c.7 corresponding to Root port 8 is
swapped with the PCIe device 1c.0 corresponding to Root port 1.
Change-Id: I7d422014a2f5cafc41296ce0a2c116c82aefb0d7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43835
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use gpio_keys driver to add ACPI node for pen eject event. Also
setting gpio wake pin for wake events.
Removal and insertion (both edges) triggers IRQ and only removal is a
wake event (rising edge).
Adding for both Volteer and Volteer2 variants.
BUG=b:146083964
BRANCH=None
TEST=tested on a Volteer
Change-Id: Ida3217a5b156320856ce3302c2623eba2230f28d
Signed-off-by: Alex Levin <levinale@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43764
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MRC automatically detects the DDR type and sets Rcomp resistor
and target values for JSL and does not require explicit programming.
Change-Id: Ia130765e2cb91d6a39ad00ebbab20e7e87fa42d1
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create the magolor variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:58540772
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MAGOLOR
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3e39e650b82a0aa629a48a00227700b058effb34
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Fixes a bug in Makefile.inc, which did not allow building ROM image
with ramstage.c from motherboard configuration.
Change-Id: I70d8a2e1f53e2fa56d514361116a55f175407753
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43457
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In TGL SoC we have PCH and CPU side PCIe support. This patch
skips CPU side PCIe enablement in FSP if device is disabled in
devicetree. Disabling the initialization of CPU PCIe saves ~30ms
in FspSiliconInit!
BUG=b:158573805
BRANCH=None
TEST=Build and boot volteer and TGL RVP. Using cbmem tool measure the
boot time. FspSilicontInit time is reduced by ~30ms with this patch.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I7e8512d22b1463bc4207f80b16dcfb5d00ef4b46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42557
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If bit 7 of a PIRQ route is set, it is disabled. Modern OSes don't use
PIRQ routing, so we might as well zero the other bits for consistency.
Tested on Asrock B85M Pro4 with SeaBIOS 1.13.0, still boots.
Change-Id: I78980b9ea5e878a6200df0f6c18c5e7d06a7950a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43861
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enabling VT-d on pre-QS silicon may have issues like rendering the
Thunderbolt driver useless. This change will ensure that VT-d is
disabled for pre-QS silicon and enabled for QS.
BUG=b:152242800,161215918,158519322
TEST=Validated VT-d is disabled for pre-QS (cpu:0x806c0) and enabled for
QS (cpu:0x806c1). Kernel walks through ACPI tables. If VT-d is disabled
and no DMAR table exists, IOMMU will not be enabled.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I98a9f6df185002a4e68eaa910f867acd0b96ec2b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The following changes are done in this patch:
1. Get the CSE partition info containing version of CSE RW using
GET_BOOT_PARTITION_INFO HECI command
2. Get the me_rw.version from the currently selected RW slot.
3. If the versions from the above 2 locations don't match start the update
- If CSE's current boot partition is not RO, then
* Set the CSE's next boot partition to RO using SET_BOOT_PARTITION
HECI command.
* Send global reset command to reset the system.
- Enable HMRFPO (Host ME Region Flash Protection Override) operation
mode using HMRFPO_ENABLE HECI command
- Erase and Copy the CBFS CSE RW to CSE RW partition
- Set the CSE's next boot partition to RW using
SET_BOOT_PARTITION HECI command
- Trigger global reset
- The system should boot with the updated CSE RW partition.
TEST=Verified basic update flows on hatch and helios.
BUG=b:111330995
Change-Id: I12f6bba3324069d65edabaccd234006b0840e700
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The prompts for the DPTF Kconfig options were not necessary, they should
be selected based on what DPTF implementation is being used, ASL files
or generated at runtime. It's not really meant to be fiddled with at
build-time. Also rewrite the help text for the _HID selection, to try
and make it more clear when to use y or n.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6edcabd28426916d9586d501b95b510dfc163fc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43830
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This macro is not correct because the RX Level/Edge Configuration
(trig) and the GPIO Tx/Rx Buffer Disable (bufdis) fields in DW0
register do not affect on the pad in the native function mode.
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ic0416e3f67016c648f0886df73f585e8a08d4e92
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao
Reviewed-by: Michael Niewöhner
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: I6a6b745bdaacb1c4fbf032e4ce54cb25a72d790a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43561
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set these fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Icdb6cb39934548e125461929701b33477a74f2a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43454
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This effectively reverts commit 5086ccef
(mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe).
Some Librem 15v3/v4 boards are showing issues with NVMe detection or
booting via SeaBIOS, so revert this until a proper fix can be found.
Test: build / successfully boot Librem 15v4 with problematic NVMe drive.
Change-Id: I0659f77bbe693f3d3b192a28ff3ef013658930cc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For devices sharing same firmware, there may be few customization based
on SKU ID - for example being clamshell or form factor. On Kukui and
Jacuzzi platforms the SKU ID is defined on AP SOC, so we have to send
the information to EC.
BUG=b:161767717
TEST=make -j # builds and boots on Juniper
BRANCH=kukui
Change-Id: I8ffdd9fd1e609c1dd4b0e22dc7aab560ccdc842e
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43788
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, audio is not working on Boten, caused by the coreboot
HDA driver not being run as the Jasper Lake PCI ID is missing.
So, add the Jasper Lake ID.
BUG=b:160651126
BRANCH=NONE
TEST=Connect speaker to audio jack, and verify sound is played.
Signed-off-by: Yan Liu <yan.liu@bitland.corp-partner.google.com>
Change-Id: Ib62c332d8d87201b3e6903251d824e1c3e06cd68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43441
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HDMI DDC GPIOs were configured as NC till now in waddledoo.
This may cause HDMI i2c transfer to break and EDID read will
fail due to wrong configuration
Configuring these GPIOs as NF in coreboot to fix the issue.
BUG=b:160324327
BRANCH=None
TEST=HDMI works on DDI2 onn Type-C port
Change-Id: If02f062132d7c3b01b07ea9401e81f451df35c3c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43294
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C bus3 frequency and insure it meets I2C spec.
BUG=b:161650117
TEST=flash coreboot to the DUT and actual measured I2C bus3
make sure it meet Spec.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ifa9f0bce723f55a12fd2313788c995f8326e3e7d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43661
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the scan-build warning below:
CC romstage/drivers/mrc_cache/mrc_cache.o
src/drivers/mrc_cache/mrc_cache.c:450:26: warning: Value stored to 'flash' during its initialization is never read
const struct spi_flash *flash = boot_device_spi_flash();
^~~~~ ~~~~~~~~~~~~~~~~~~~~~~~
1 warning generated.
The function can return early before the value is read. Fix this, by
getting rid of the variable, as the value is only read once.
Change-Id: I3c94b123f4994eed9d7568b63971fd5b1d94bc09
Found-by: scan-build (clang-tools-9 1:9.0.1-12)
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=Able to build and boot Waddledoo successfully.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Iaa0a41f3b5972251d6cd9359bbb46d392196b2e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The outb() call is replaced with the post_code()
The post_codes.h is replaced with console.h since console.h
includes both the post_code definition and post_codes.h
Change-Id: I21345260e86de30614c416e2f509bd77b9e00cb7
Signed-off-by: Sindhoor Tilak <sindhoor@sin9yt.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Kconfig lint tool checks for cases of the code using BOOL type
Kconfig options directly instead of with CONFIG() and will print out
warnings about it. It gets confused by these references in comments
and strings. To fix it so that it can find the real issues, just
update these as we would with real issues.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I5c37f0ee103721c97483d07a368c0b813e3f25c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We have definitions for the bits in the PCI COMMAND register. Use them.
Also add spaces around bitwise operators, to comply with the code style.
Change-Id: Icc9c06597b340fc63fa583dd935e42e61ad9fbe5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Mark the CPU as enabled and the socket as populated.
EDK2 tests these flags before further reading this structure.
Change-Id: Ic545bb47c502cb9d2352ba6d43eaed8c97229c02
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43703
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement type 19 by accumulating the DRAM dimm size found in cbmem's
CBMEM_ID_MEMINFO structure. This seems common on x86 where the
address space always starts at 0.
At least EDK2 uses this table in the UI and shows 0 MB DRAM if not
present.
Change-Id: Idee8b8cd0b155e14d62d4c12893ff01878ef3f1c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
- Update MAINBOARD_PART_NUMBER for TGL variants
- MAINBOARD_PART_NUMBER is reported as FRID on acpi
- This is required for cros_config to differentiate
across TGL variants.
- Mosys uses cros_config to identify TGL variants using
data read from FRID
Bug=none
Test=build and boot coreboot on TGLRVP UP3 hardware
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Change-Id: I11d4ab2a5b6ade6c50988a9fec4d9866fe79d7b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43620
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Set up a 8-byte I/O range at 0x290-0x297 as PIIX4's generic device 9,
which activates a chip select when this range is accessed.
On the P2B family it connects to the W83781D hardware monitor,
allowing access to it over the ISA bus, just like vendor firmware.
Apparently this does not work on p3b-f, but no ill effects observed
either.
TEST=On p2b-ls lm-sensors can detect chip and get readings over ISA.
Change-Id: Iaed1df7230359e94c580c305f4769c8bb4f5fce0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These will be put to use in a follow-up.
Change-Id: Id13dde5ce2239064b9b18de7ca516525158ae268
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Remove EIO define. It is unused and means something else,
elsewhere in the tree.
Move PMIOSE bit definition next to PMREGMISC, where it actually
belongs.
Correct a number of bit defines with glaring errors.
Clarify in comments which PM register defines are in PCI config
space are which are in I/O space.
Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects dereferencing pointers that might be "NULL" when
calling acpigen_write_scope and acpigen_write_device. Add sanity
check for both of scope and name to prevent NULL pointer dereference.
Found-by: Coverity CID 1430454
TEST=Built and boot up to kernel on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I8ece3831bbd2641ceafbd71b9dc3db7e04a8eae4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43449
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously, the spi base address code was using a number of different
functions in a way that didn't work for use on the PSP.
This patch consolidates all of that to a single saved value that gets
the LPC SPI base address by default on X86, and allows the PSP to set
it to a different value.
BUG=b:159811539
TEST=Build with following patch to set the SPI speed in psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I50d9de269bcb88fbf510056a6216e22a050cae6b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43307
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The while loop in \_SB.DPTF._OSC accidentally used <= instead of <, so
there was an error indexing into IDSP.
BUG=b:162043345
TEST=verify disassembled ASL, as well as no BIOS bug mentioned in
/var/log/messages
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I08c4152c59cc9eb13386c825aab983681cfa88ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
I accidentally had the same value for two different postcode
entries. Fix that.
BUG=None
TEST=Watch postcodes in psp_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Id0bf18efc7e79278a21683c11a1084d2a7d97e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The only reason to use a named choice statement is if you plan on
having the choice statement in multiple places. Since none of these
are used in multiple places, we can get rid of the names.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie5f84e9dc38050234976bd193ac5fbf649e564f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Missed one other scope operator in the DPTF cleanup. This one is for the
fan device, and without this fix, the kernel isn't able to properly
control the fan (it gets confused about whether it's ACPI 4+ compatible
or not).
BUG=b:149722146
TEST=verify /sys/class/thermal/cooling_zone0/max_state returns > 1,
and /sys/class/thermal/cooling_zone0/cur_state is writable, and writing
the value of `max_state` causes the fan to spin faster.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7bd83967ace761ddd17eaeae9c25abb0b2cbe413
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Variants that select BASE_ASUS_P2B_D will also get
MAX_CPUS==2 below, so this was redundant.
Change-Id: I9048a4821f19d90e1489b09e294d2551941abf10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43809
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not stricly related to spinlocks. If defined, a better
location should be found and the name collisions with other
barrier() defined in nb/intel solved.
Change-Id: Iae187b5bcc249c2a4bc7bee80d37e34c13d9e63d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43810
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's not related to spinlocks and the actual implementation
was also guarded by CONFIG(SMP).
With a single call-site in x86-specific code, empty stubs
for other arch are currently not necessary.
Also drop an unused included on a nearby line.
Change-Id: I00439e9c1d10c943ab5e404f5d687d316768fa16
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43808
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's a `GPL-2.0-or-later` version of this file in volteer2, so use it
in place of these weirdly-licensed files.
Change-Id: Icde2f6539d9c726d6967350f74e7bc015e01e7b5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Put them in common code just in case something depends on the values.
Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are many places where we do this. Put it inside an inline function
for convenience reasons.
Change-Id: I5515a52458b6c78c1a723cb08e6471eb9bac9cd6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43871
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This applies what commit 79572e4f32 does
to the devicetree settings of the zork devices.
Change-Id: Ife94818d771f137e56c51ad1598148f60fcf5345
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43820
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since FSP pre-populates the UPD struct with the non-zero default values,
coreboot shouldn't set them to zero in the case that they aren't
configured in the board's devicetree. Since all parameters being zero is
a valid case, this patch adds another devicetree option that applying
the devicetree settings for the USB2 PHY tuning depends on being set.
BUG=b:161923068
Change-Id: I66e5811ce64298b0644d2881420634a8ce1379d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43781
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I49e9cef1dfaa62dcfbd1260cec459ff5910ad5da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and avoids
unlikely but potential bugs regarding missing braces in macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ic341fe70e7d6fb4751f2fefbdedbee5c90dd8d1f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43201
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I90632909cd7d632d80739b3762e4ccba51624b75
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43200
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaf557caac16b36e356a4fb1b05416718d86093bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43199
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Iaa6d5d72cd0368342205a9b98552c1e0762abbce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I9d9edd774143b0a98773b6d5de630d116cb6f0b1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43197
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I08ccbc70744a17d589450e321a3ed77d9a56492f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43196
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I98d17fc470149b181e8d92b8bcc5d99c68299212
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43195
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: If75b4299918f5bee3cc68bc662d03f1a819aef68
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43194
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the documentation [1], RX Level/Edge Configuration (trig)
and GPIO Tx/Rx Buffer Disable (bufdis) [2] settings are not applicable
in native mode and BIOS does not need to configure them. Therefore,
there is no need to configure this in gpio.h using PAD_CFG_NF_BUF_TRIG
macros. Use PAD_CFG_NF instead and set this fields to 0.
[1] Intel document #549921
[2] Intel document #336067-007US
This is part of the patch set
"src/mb/*, src/soc/intel/common/gpio: Remove PAD_CFG_NF_BUF_TRIG ":
CB:43455 - cedarisland: undo set trig and bufdis for NF pads
CB:43454 - tiogapass: undo set trig and bufdis for NF pads
CB:43561 - h110m: undo set trig and bufdis for NF pads
CB:43569 - soc/intel/common/gpio_defs: Remove PAD_CFG_NF_BUF_TRIG
Change-Id: Ie3ee2eadc08826d49e8517c83ab6831398e3aa93
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43455
Reviewed-by: Michael Niewöhner
Reviewed-by: Lance Zhao
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no reason to return the result of a void function.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I677dec1622768874a51effd6d73f0b2329f27aed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43193
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell, and
prevents possible bugs when using these macros.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I18e9a750901f1bf8d3b61f4b64bbed907bc1fa15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43192
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ifd71881e3924dca3add1e788852e7eb078405d00
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43191
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I52d58c6b77cd870b5d3f5892521e4c82027c4cac
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43190
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I0b07f8d52203c0a6d20b747f36d4d22cf53c791c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I34079985e165ce8d10c7a2b4f0dde15060132208
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43188
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Ia21b588a3ce07e33a7a8d36e1464c0ff5e456c3e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43187
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This to silent a bug found using gcc-10.
src/northbridge/intel/ironlake/raminit.c: In function 'setup_heci_uma':
src/northbridge/intel/ironlake/raminit.c:1805:11: error: 'reply.command' may be used uninitialized in this function [-Werror=maybe-uninitialized]
1805 | if (reply.command != (MKHI_SET_UMA | (1 << 7)))
| ~~~~~^~~~~~~~
cc1: all warnings being treated as errors
Change-Id: I0d13de549b6d428ac3675ee3f91eb5e42aeb25e8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add missing registers and sort them by ascending offsets.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 does not change.
Change-Id: I98f836668144032d920b56afff878acc0a58ed82
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Both files are identical, so we only need one copy in the tree.
Change-Id: I07d7429caca7f6211a186b770c3608f642d4f269
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43159
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set power limits in devicetree for Tiger Lake Y-SKU based volteer
variant boards.
BUG=b:152639350
BRANCH=None
TEST=Built and tested power limits on volteer variant board.
Change-Id: If4f1226473b48365e5962df9fff29910c99007fc
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43607
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates Tiger Lake SA DID and report platform. According to
doc #613584, remove PCI_DEVICE_ID_INTEL_TGL_ID_U_1 and add below
definitions of SA ID for TGL-UP4 skus:
TGL-UP4(Y) (4+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_4_2 0x9A12h
TGL-UP4(Y) (2+2): PCI_DEVICE_ID_INTEL_TGL_ID_Y_2_2 0x9A02h
Change-Id: Id9d9c9ac3bf39582b0da610e6ef912031939c763
Signed-off-by: Derek Huang <derek.huang@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43061
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the binary layout of this struct matters, it should be marked as
packed. Since all struct elements are uint8_t, this shouldn't result in
a different layout though.
BUG=b:161923068
Change-Id: I6a390c3a3f35eaf8a72928b4cef0e9f405770619
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43780
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- remove comments (except the GPIO group), because it does not contain
useful information that helps to understand the circuit, which we do
not have;
- remove empty lines between macros;
- use a shorter PAD_CFG_GPI_INT() macro instead of
PAD_CFG_GPI_TRIG_OWN() to set DRIVER mode.
Change-Id: Ia7111341aab6f400da70d936849e4d4c9406905b
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Converts bit field macros to target PAD_CFG_*() macros, which were
hidden in the comments. To do this, the following command was used:
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -n -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: Idad7536854d4b1ae7dcf7934e81de438478fe059
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35679
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes some bit fields to convert to target macros PAD_CFG_*() macros.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: I291f5f0f34505c466b610aa4049c8cc35937d140
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42918
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch excludes bit fields that should be ignored [1] in order
to convert current macros to target PAD_CFG_*() macros. The following
commands were used for this:
./intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
/intelp2m -ii -fld cb -ign -t 1 -p snr -file ../../src/mainboard/
supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] ignore RX Level/Edge Configuration (bit 26:25) and RX/TX Buffer
Disable (bit 9:8) for the native function, because it does not
affect the pad in this mode.
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Change-Id: Icdf366a8d416598cec5afcb9a0fae6bf7ecd7ba0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42917
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the middle of the Great DPTF Refactor of 2020, new volteer variants
were added, but their dptf.asl files are no longer used, so delete them.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I52f2042aa870a29026eb9fe122340ad07654e706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
When refactoring, one can move code around quite a bit while preserving
reproducibility, unless there is an assert-style macro somewhere... As
these macros use __FILE__ and __LINE__, just moving them is enough to
change the resulting binary, making timeless builds rather useless.
To improve reproducibility, do not use __FILE__ nor __LINE__ inside the
assert-style macros. Instead, use hardcoded values. Plus, mention that
timeless builds lack such information in place of the file name, so that
grepping for the printed string directs one towards this commit. And for
the immutable line number, we can use 404: line number not found :-)
Change-Id: Id42d7121b6864759c042f8e4e438ee77a8ac0b41
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
One would expect disabled devices to not be present. So, don't print
misleading warnings about it, because it only confuses people.
Change-Id: I0f14174a1d460a479dc9f15b63486f4f27b8f67c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the intelp2m utility [1,2] with -fld=cb options to convert the pad
configuration format with the raw values of the DW0 and DW1 registers
to the format with the bit fields macros: PAD_FUNC(), PAD_RESET(),
PAD_TRIG(), PAD_BUF(), PAD_PULL(), etc... Also use the -ii options to
generate the target macro in the comments, so that it is easier to
understand what result we should get:
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h
./intelp2m -ii -fld cb -t 1 -p snr -file ../../src/mainboard/supermicro/
x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h
[1] https://github.com/maxpoliak/pch-pads-parser
[2] https://review.coreboot.org/c/coreboot/+/35643
This is part of the patch set
"mb/supermicro/x11-lga1151: Rewrite pad config using intelp2m":
CB:42916 - 1/4 Decode raw register values
CB:42917 - 2/4 Exclude fields for PAD_CFG
CB:42918 - 3/4 Fixes some field macro
CB:35679 - 4/4 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Supermicro X11SSH-TF and X11SSM-F,
remains identical.
Change-Id: I209ecdca75a0e62233d3726942c75ea06acc40a2
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42916
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the bufdis parameter (bit 9:8 in Pad Configuration DW0 register)
does not affect the pad in native function mode,
PAD_CFG_NF_BUF_IOSSTATE_IOSTERM() macro is not required to configure
the pad. This macro has not been used, so deleting it will not affect
anything.
Change-Id: Icce6f130308dbe7032b99539f73688bae8ac17e0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42913
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IO Standby State can use various settings independently of
PAD_CFG_GPI_TRIG_OWN (). Instead, use other existing macros to set this
parameter:
- PAD_CFG_GPI_IOSSTATE_TRIG_OWN()
- PAD_CFG_GPI_TRIG_IOS_OWN()
Change-Id: I0f5fbd79f892981eb4534f50ac96a7d0c190f59e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42912
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch updates existing macros for the GPI:
- PAD_CFG_GPI_IOSSTATE_IOSTERM()
- PAD_CFG_GPI_IOSSTATE()
to allow the user to set the RX Level/Edge Configuration (trig) and
the Host Software Ownership (own) fields in addition to IO Standby State
(iosstate) and IO Standby Termination (iosterm) in the pad configuration
using these macros.
Change-Id: I8a70a366e816d31720d341a5d26880dc32ff9b8d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Gate the A-Link to AHB Bridge clocks to save power. These
are internal clocks and are unneeded for Raven/Picasso.
This was previously performed within the AGESA FSP but this
change relocates it into coreboot.
BUG=b:154144239
TEST=Check AL2AHB clock gate bits at the end of POST before and
after change with HDT.
Change-Id: Ifcbc144a8769f8ea440cdd560bab146bf5058cf9
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42829
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Coverity detects dereferencing a pointer that might be "NULL" when
calling report_resource_stored. Add sanity check for dev to prevent
NULL pointer dereference.
Found-by: Coverity CID 1419488
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I03efad87ba761e914b47e3294c646335cfbaed24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
With the updated FSP UPD headers there are enough DXIO descriptor slots
in the UPD, so we can now add asserts to make sure that the mainboard
doesn't pass more DXIO/DDI descriptors than the UPD has slots for. This
is part of the DXIO/DDI descriptor handling cleanup.
BUG=b:158695393
Change-Id: Ia220d5a9d4ff11707b795b04662ff7eead4e2888
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43435
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A new version of UPD headers generated from the FSP tree. This adds UPDs
for downcoring and increases the number of DXIO descriptor slots.
BUG=b:161152720
TEST=SATA on Mandolin works now.
Cq-Depend: chrome-internal:3175393
Change-Id: I1e27597e22af4df65d206a38b67c4920298b30b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43659
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use macros to configure each of the IIO ports instead of an array
of some unknown parameters. This will clean up the code and make
it easier to read.
Tested with BUILD_TIMELESS=1, Tioga Pass, remains identical.
Change-Id: I2911992435a6c93624525426d56212f821abb866
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43502
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was only used in one function, but its value was never read. Drop it.
Change-Id: Ib511352d51d4452d666640d0f52810b06c8d61ce
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There's no need to set up the southbridge in the northbridge code.
Change-Id: I0f80c92aca885812c27a8803c2745844d8dfb939
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Looks like these comments were moved without checking them. They are no
longer correct nor useful, so kill them with fire.
Change-Id: I3de04b8c03f7c511376dec922a60958ffc3bf6a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When RTC failure is detected, send IPMI OEM command to issue CMOS clear.
This is to let the payload (LinuxBoot) handle the IPMI OEM CMOS
clear command by resetting RTC data, erasing RW_VPD (TODO) and add a
SEL, then reboot the system.
Tested=on OCP Delta Lake, after removing RTC battery we can see the above
flow can be executed correctly.
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Change-Id: I27428c02e99040754e15e07782ec1ad8524def2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43005
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Populate SMBIOS data from OCP_DMI driver read from FRU
2. Set the read PPIN MSR for CPU0 and CPU1 to BMC, selecting
PARALLEL_MP_AP_WORK to enable OCP DMI driver to read remote socket PPIN.
Tested on OCP Tioga Pass.
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Change-Id: Ie11ab68267438ea9c669c809985c0c2d7578280e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40524
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Raydium ACPI entry currently provides a reset GPIO and an _ON/_OFF
method to the kernel. These are contradictory. The ownership of the GPIO
should be mutually exclusive between either the OS or the FW. Since we
have two methods exposed this causes the OS to reset the TS twice. Once
using the _ON method, and once using the GPIO. Additionally the _ON
method is waiting for 20ms after reset while the OS driver uses a 50ms
delay. The Raydium TS datasheet specifies 20ms for FW ready time, so the
OS driver is adding additional padding.
The reference design has a 32ms rise time on the reset line. So without
this patch, the OS tries to reset the TS using the _ON method and it
waits for 20ms. This is not enough time for the reset line to reach
high, let alone account for the FW ready time. The OS driver then tries
to reset the device by toggling the GPIO. It waits 50ms which is still
2ms less than required.
This CL removes the GPIO from being exported in the _CRS so the OS
driver won't try and reset the device. It also increases the reset delay
by 32ms to account for the rise time.
This isn't a complete fix. I think that the slow rise time is causing
some kind of metastability in the TS reset hardware. Using a script to
bind and unbind the TS driver, the TS device becomes unresponsive after
~200 iterations. The only way to reset the device is to power cycle.
The TS power is also not currently controlled by the power resource.
This means that we have no guarantee over when the reset line is
toggled. This will lead to issues while spending and resuming.
BUG=b:160854397
TEST=Boot trembyle and make sure TS works. Suspend/Resume trembyle 300+
times.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I23131be5d7109eed660a8bd6e2c156c015aa3c4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Earlier versions of Dalboz did not correctly handle HS400. One fix was
to add stitching vias, but these boards did not have them. b/156539551
Another possible fix is to add tuning parameters including drive
strength, but that is still a WIP. b/158959725
This should correct OS load failures in the meantime by running the bus
slower.
BUG=b:158845662
TEST=build, flash, boot sku 0x5a80000c to OS
BRANCH=None
Signed-off-by: Eric Peers <epeers@google.com>
Change-Id: Ia3e7a641bde04c5a7be29bf91c38dd8c110ed17a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43572
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the dirinboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161579679
BRANCH=master
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_DIRINBOZ
Change-Id: I33c03080ffbe0bca61acf4144417b9f5fff6389f
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reset the Touchscreen (TS) and disable the stop GPIO (report switch) at
the same time. Add a delay of 100 ms after disabling the stop GPIO. This
will ensure the required delay is inserted for both reset and stop
disable GPIOs simultaneously.
BUG=b:152936541
TEST=Build and boot the waddledoo mainboard. Ensure that the SiS
Touchscreen is functional.
Change-Id: Icbfb5e07a28ab72b1ff696ad1183a6c2173dcaac
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
H9HCNNNBKMMLXR-NEE
K4U6E3S4AA-MGCR
BUG=None
TEST=Build the drawcia board.
Change-Id: Id05c0b2a87b64bfedc761949cbc8ad6cf7dd73a5
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change does the following:
a. USI_REPORT_EN is no longer set to high in coreboot. Instead
GPIO_144 is exposed as stop_gpio in ACPI to allow OS to control this
pad as required.
b. Appropriate delays are added for power-down sequencing:
- Delay after REPORT_EN is disabled - 1ms
- Delay after RESET is asserted - 1ms
BUG=b:159501288
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: If4d12fa0d4f4e5123d8fdccdabda996dcafa4523
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPIO_91 is added to ACPI using the device tree entry for codec. So,
this change drops the TODO from GPIO table.
Change-Id: I9c2e91465ab554126531f8512028360ae5fb316d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43699
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change configures all missing pads in ramstage for dalboz
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Ia30da908d3827177a7b3594ffba38bff81018ab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change configures all missing pads in ramstage for trembyle
reference. This ensures that the state of all pads is set correctly
for the payload/OS. Also, all the pads for the platform are configured
in baseboard gpio table in ramstage to ensure that variants can
override any pads if required.
BUG=b:154351731
Change-Id: Idd827b6a4f995546493596f22249f8699bdf526b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops PULL_UP configured on pads in early_gpio table since
these pads have external pulls.
BUG=b:154351731
Change-Id: Id270e7b4f83dfa942655f513776a3b1c15c9678d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change fixes the definition of `GPIO_INT_ENABLE_STATUS_DELIVERY`
to use `GPIO_INT_ENABLE_DELIVERY` instead of
`GPIO_INT_ENABLE_STATUS_DELIVERY`.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I64d912200779875cf121cec4476fd39de74c0223
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most of the DXIO descriptors are used to configure PCIe engines and
lanes, but on Picasso system some of the DXIO lanes can also be
configured as SATA or XGBE ports.
Change-Id: I28da1b21cf0de1813d87a6873b8d4ef3c1e0e9dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43675
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The lane numbers in the PCIe/DXIO descriptor are the logical and not the
physical ones, so add logical to the corresponding field names of the
fsp_pcie_descriptor struct.
Change-Id: I7037fed225119218e87593932815aff815e83ff8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update .vbt file to support two DP outputs.
Change-Id: Ifd4163aafe4ef3070d04a72a4699303af72c5102
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This adds ACPI code for System76 EC and converts system76/lemp9
to use EC_SYSTEM76_EC.
Tested on system76/lemp9.
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Change-Id: I1f693268d94b693b6764e4a3baf4c3180689f3be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Michael Niewöhner
Add function to send POST start command to BMC. This function is
used in romstage and the POST end command will be sent in u-root.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 Jul 15 16:36:11 bmc-oob. user.info fby3-v2020.23.1:
ipmid: POST Start Event for Payload#2
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: Ide0e2a52876db555ed8b5e919215e85731fd80ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Create SMBIOS type 9 by getting PCIe config from BMC.
TEST=Check SMBIOS type 9 is created correctly on different SKUs
Change-Id: Ifd2031b91c960ff2add8807247271eb7c38a0bf2
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SystemMemoryMapHob is necessary for SMBIOS type 17 among other things.
It is a fairly large structure, so the pointer to the data instead of
the structure itself, is included in the HOB. Use pointer to
SystemMemoryMapHob structure to interpret SystemMemoryHob HOB body.
Adjust the structure definition to match with CPX-SP ww28 release.
Display more fields to ensure the structure definition is correct.
TEST=Boot DeltaLake server, and check field values of SystemMemoryMapHob
to make sure they are correct:
0x7590a090, 0x00000020 bytes: HOB_TYPE_GUID_EXTENSION
f8870015-6994-4b98-95a2bd56da91c07f: FSP_SYSTEM_MEMORYMAP_HOB_GUID
================== MEMORY MAP HOB DATA ==================
hob: 0x777f7000, structure size: 0x6c88
lowMemBase: 0x0, lowMemSize: 0x20, highMemBase: 0x40, highMemSize: 0x5d0
memSize: 0x600, memFreq: 0xb76
NumChPerMC: 3
SystemMemoryMapElement Entries: 2, entry size: 16
memory_map 0 BaseAddress: 0x0, ElementSize: 0x20, Type: 0x1
memory_map 1 BaseAddress: 0x40, ElementSize: 0x5d0, Type: 0x1
BiosFisVersion: 0x0
MmiohBase: 0x80000
0x777f7000: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................
...
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I271bcbd6030276b8fcd99d5b4f2c93f034dd9b52
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43336
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the SkipCpuReplacementCheck config for jasperlake rvp
to avoid the forced MRC training with the soldered down SOC.
BUG=b:160201335
BRANCH=None
TEST=Build and verify on jasperlake rvp with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530
Change-Id: I40fb9a25170e8db3c63a71428ba459160a918961
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43146
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch enables the CSE Lite SKU for the dedede baseboard.
BUG=b:160201335
TEST=Build and boot waddledoo with CSE Lite SKU.
Cq-Depend: chrome-internal:3142530
Change-Id: I24d7d715d55524807af0127aa4a346a008164b8c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patches enables the SkipCpuReplacementCheck config for
the dedede baseboard to avoid the forced MRC training for all
its variants with the soldered down SOC.
BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddledoo.
Cq-Depend: chrome-internal:3142530
Change-Id: I611e66f74a3b9b090ab5e0d836231643d3f919dc
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Add SkipCpuReplacementCheck config to control the FSPM UPD used
for skipping the CPU replacementment check to avoid the forced
MRC training for the platforms with soldered down SOC.
BUG=b:160201335
TEST=Build and verify CSE Lite SKU on Waddleddo.
Cq-Depend: chrome-internal:3142530
Change-Id: I63fcdab3686322406cf7c24fc26cbb535cc58c8d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Other Intel southbridges use this name for the HD audio codec.
Change-Id: Ic96797e6c2028f082130211bb5f4270391f866c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Other Intel southbridges use this name for the HD audio codec.
Change-Id: I50dbf0a079944b7fa6cfd6622c0626bc9139af85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is impossible for `find_resource` to return NULL, it dies instead.
Change-Id: If8e26f768383e741100e3690322db3dabeec1922
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
A recent Coverity scan found an issue with the way the
EC_HOST_EVENT_MASK macro was being used. It was being passed values
between 0 and 63, but since it is doing basically (1ULL << (value - 1)),
this caused a shift of -1 when `i` is 0 and also doesn't reach the 63rd
bit of the mask. This is fixed by incrementing the start and end
conditions of the loop by 1, so the event mask ranges from bits 0 to 63,
instead of -1 to 62.
Found-by: Coverity CID 1430218
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6a7cfa64545f3d313de24407f0a91b48368f2a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43460
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on jasperlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If95e46124660b4ed457434f727c9f9f7b02b0327
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43539
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on cannonlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change PCH power policy. Set default of
POWER_STATE_DEFAULT_ON_AFTER_FAILURE to n in order to change power
state to S5 when power is reapplied after power failure.
TEST=Base on CB:42289, CB:43338 and build for Deltalake.
The following Kconfig options must be selected:
select SOC_INTEL_COMMON_BLOCK_PMC
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select CPU_INTEL_COMMON_SMM
Boot the system and check the last bit of GEN_PMCON_B is set to 1
through ITP with command: pch.pm_dump
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I4d4f14bdfc18740976171fd5d369b2d79a916dc4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42976
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Read VPD variable 'fsp_log_level' to decide FSP log level.
2. Define the default values when the VPD variables cannot be found,
put all the values to vpd.h for better documentation and maintenance.
Tested=On OCP DeltaLake, the fsp_log_level can be changed from the VPD variable.
Change-Id: I44cd59ed0c942c31aaf95ed0c8ac78eb7d661123
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The three mainboards using this southbridge are desktop boards, which
are not dockable. The Dell Precision M6400 laptop is dockable, but even
though it has an Eaglelake MCH, it uses an i82801ix southbridge instead.
So, one could still port that laptop to coreboot after this change! :P
Also, drop the now-unnecessary `chip` and `dev` variables.
Change-Id: Ic9ab497c91d66032929190cde22d59a208887f50
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The three mainboards using this southbridge do not define it. Note that
the default value of zero might be wrong, so add a FIXME comment.
Change-Id: Id16bb12a4628daf311bddf7e4701fc480d6b18e5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42656
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There are more Jacuzzi followers coming and we want to have a simplified
way of adding new boards. Now, detachable and tablets should select
BOARD_GOOGLE_KUKUI_COMMON and clamshells should select
BOARD_GOOGLE_JACUZZI_COMMON.
BUG=None
TEST=make menuconfig; make -j # for kukui, krane, jacuzzi, juniper
BRANCH=kukui
Change-Id: Ifc1eb6a3792f46c5db6b5346902f1114955b28ae
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Create the madoo variant of the waddledoo reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:161191394
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_MADOO
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I6d3f611606f86036d67be9c8b0fda833ab61ecc1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change drops the pulls configured on override GPIOs as they
already have external pull-ups. Also, pads which are unused are
configured as PAD_NC.
BUG=b:154351731
Change-Id: I8da5d51af25bbe2694c21ecb0868c9cc387243cb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace it with t430s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.
This makes diff between boards smaller.
Change-Id: I633702d363134654e71e35404237d75b499f089a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Replace it with t420s/gma-mainboard.ads which is licensed under more
flexible terms (GPL-2.0-only vs. GPL-2.0-or-later). Apart from licensing
terms these files are identical.
This makes diff between boards smaller.
Change-Id: I5393a603b5a4cd353149c1fa9e3e29020946b962
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Jenkins does not build `config.stm` because the file name lacks the
mainboard name. So, the code was not being build-tested, and it does not
build because several files lacked the definition for `bool`.
Add the missing #include directives. Renaming the config file so that
Jenkins build-tests it is done in a follow-up.
Change-Id: Idf012b7ace0648027ef6e901d821ca6682cee198
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43622
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This ID is reported by newer mfg date SOCs. Needed for newer GBYT4 boards.
Change-Id: I6af746d66a15f67553de1dc1c925e5cb0b181898
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge)
- RAM: native raminit tested (4G+4G, 8G+8G)
- USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4)
- LAN: tested in Linux
- SATA: all 4 ports work, tested in SeaBIOS and Linux
- iGPU: I can't test it as I only have a Xeon for this socket
- PEG: tested with an nVidia GT210, initialized by SeaBIOS
- PS2 keyboard and mouse combo port: no devices to test with
- Front panel header: tested, works
- Audio: tested, works
- Diagnostic LEDs: TBD
Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While it looks different, the early SMBus code for this southbridge is
still the same. In addition, this code was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.
Change-Id: I95ae4db399ce5592cefca82fa75f349220023b8c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42006
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.
Since this southbridge is used with two different northbridges, we need
to update both of them. Plus, x4x raminit no longer needs to know which
southbridge it is paired with, since both i82801gx and i82801jx use the
common early SMBus code, so we drop some preprocessor around includes.
Change-Id: Ic60a3f89bda6000fbe646461f05240c1b09db6e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42005
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The early SMBus code for this southbridge checked if the PCI device ID
is valid. However, we can't easily do that in common code, and we should
not attempt to do so either: if a SMBus device behaves differently, then
it should not be using the common code anyway.
Change-Id: I5c21e091e437d23a173ddcf35d4f1efada6194cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42004
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The early SMBus code for this chipset was not checking the vendor ID
before. It is assumed that adding this check does not pose a problem.
Change-Id: I0c36c8cd8aca8db860b1edafd29d4f2dbaa2c822
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42003
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looks like no one uses early SMBus for now, but that may change someday.
Change-Id: I42971662a279860a8c2e058fcb194fe5eba7c740
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42001
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
