* Configure and enable MMU.
* Cover the whole I/O space.
* A minimum of 512KB TTB space is required.
* Use secure mem attribute as firmware is running in ARM TZ region.
Tested on Cavium SoC.
Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
This adds Cavium CN81xx SoC and SFF EVB files.
Code is based off of Cavium's Octeon-TX SDK:
https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK
BDK coreboot differences:
bootblock:
- Get rid of BDK header
- Add Kconfig for link address
- Move CAR setup code into assembly
- Move unaligned memory access enable into assembly
- Implement custom bootblock entry function
- Add CLIB and CSIB blobs
romstage:
- Use minimal DRAM init only
devicetree:
- Convert FTD to static C file containing key value pairs
Tested on CN81xx:
- Boots to payload
- Tested with GNU/Linux 4.16.3
- All hardware is usable (after applying additional commits)
Implemented in future commits:
- Vboot integration
- MMU suuport
- L2 Cache handling
- ATF from external repo
- Devicetree patching
- Extended DRAM testing
- UART init
Not working:
- Booting a payload
- Booting upstream ATF
TODO:
- Configuration straps
Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688
Signed-off-by: David Hendricks <dhendricks@fb.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/23037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Config ISH in SOC side by checking if ISH device is turned on.
"IshEnable" is not needed anymore since ISH device on/off will tell
if ISH should be enabled or not. "IshEnable" will be removed from chip.h
in separate CL.
Atlas board specific ISH setting is needed, which is committed in
separate CL.
BUG=b:79244403
BRANCH=none
TEST=Verified on Atlas board with ISH rework. ISH log showed on console.
Change-Id: I3fc8648b3e6551497617ef1ebd2889245cdd31c3
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://review.coreboot.org/26485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
* Add SSDT generator to add dynamic ACPI code.
* Implement GBDC and SBDC for thinkpad_acpi kernel module.
Required for BDC power control from userspace.
Tested on Lenovo T430:
The bluetooth module is detected and can be powercycled using network manager.
Change-Id: Ida825196650966194a883945896a038b0790fe45
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These two files were added before I was able to get the updated linter
committed. Updated/Add the headers so the stable header lint check
can be updated.
Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GCC pre-defined some macros for detecting ISA extensions.
We should use these macros to detect ISA features.
Change-Id: I5782cdd1bf64b0161c58d789f46389dccfe44475
Signed-off-by: XiangWang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/27300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Move the APCI HKEY device to a new file and include it.
The follow-up commits will extend it and this way it remains readable.
Change-Id: Ie59b59e5a4148807125c71a362161026f685a97e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/22463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is
defined as IRQF_TRIGGER_LOW, so do not invert it twice.
BRANCH=poppy
BUG=b:78613978
TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not
increment wildly.
Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/27221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It can not emit byte data without BytePrefix.
design to:
Or (Local5, GPIO_PIN_OUT, Local5)
error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means
nothing in AML spec.
so it will include next emitted string in Or:
Or (Local5, Local5, \_SB.GPW2)
fix:
Store (0x40, Local0)
Or (Local5, Local0, Local5)
BUG=b:110962003
BRANCH=master
TEST=emerge-grunt coreboot
extract SSDT then check ACPI syntax is correct
Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Clean up leftovers of old SPD generation and utilize
common procedure to produce SPD binary.
Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27301
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Since none of the boards using chromeec select DRIVERS_PS2_KEYBOARD
now, there is no need to call pc_keyboard_init anymore. This change
gets rid of the call and adds an error message in case any mainboard
using chromeec tries to select this config.
BUG=b:110024487
Change-Id: Ia0b56abe0a5990e527277eaf3397e00dccda3e50
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the
keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until now, chromeec was doing keyboard initialization for the boards
that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not
leave the keyboard controller in a default reset state. This could
result in payloads or OS failing to probe the controller as there
could be stale data buffered in the controller during the handoff.
Since the boards using chromeec already perform keyboard
initialization in payload, there is no need to initialize the keyboard
in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD
selection from all google mainboards using chromeec.
BUG=b:110024487
TEST=Keyboard works fine after booting to OS even if user hits keys
during BIOS to OS handoff.
Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27291
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Useful for debugging or for cases where we need to enter SMM.
Probably should be moved to commonlib or libpayload.
Change-Id: I7a9cc626dae9a7751034615ef409eebc6035f5c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
To uniform the naming of the 'Dual Graphics' mode amongst the ThinkPads that
support it, the T400 CMOS value needs a change. This was the outcome of a
discussion on another patch: https://review.coreboot.org/#/c/coreboot/+/23040/
This might cause breakage for automated NVRAM configuration scripts, and
manuals. I only found one manual using the previous 'Switchable' option:
https://libreboot.org/docs/install/r400_external.html#a-note-about-gpus
Change-Id: I2e4d8bafbae5de97c78dab118f75fdefff1d7c37
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/27158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to
function correctly.
BUG=b:110817463
TEST=ran firmware_CorruptFwSigB on grunt
Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.
BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.
Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the mainboards using Chrome EC set SCI mask for power
button. Thus, the EC will never generate SCI for power button
events. This change removes the Notify call for power button as part
of clean up for getting rid of the power button device in coreboot.
BUG=b:110913245
Change-Id: I86c72fd82f1a0e6d5693ebbcd58e2aea808f8817
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Using common mtcmos code to power on audio and display modules in SOC.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui. Passes the status check at the end of
mtcmos_power_on()
Change-Id: I41f16ba36432a8bbc47793cec2979753c9f84b43
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move mtcmos code which can be reused into a common directory under
soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: I92b138890424b4f4a68cdb00bf2326eef9cd87b7
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27029
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor mtcmos code which will be reused among similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Ibfd0a90f6eba3ed2e74a3fd54279c7645aa41774
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Old return value was not used, and function body
has die() in case of errors in allocation.
Change-Id: I89b0e9c927d395ac6d27201e0b3a8658e9585187
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When AllocationMethod == ByHost, buffer has to be
provided by caller.
Improve code symmetry, the named parameter is now
always pointer to the struct.
Change-Id: I2085f7d5d63ef96f4bd9d5194af099634c402820
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Enable Image Processing Unit and CIO2 device that constitute IPU3.
BUG=None
TEST=Build and boot up into Nocturne platform and check with lspci.
Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/27124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sensors and CSI2 receiver configuration for Nocturne platform.
IMX355 module has VCM, NVM and is on the second port of receiver.
IMX319 module has NVM and is on the first port of receiver.
Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com>
Signed-off-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-on: https://review.coreboot.org/26283
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
change sd_mmc_go_idle to be accessible from other files
so that we have an api to send CMD0 and reset the card.
BUG=b:78106689
TEST=Boot to OS
Change-Id: I064a9bded347be5d500047df92d1c448c3392016
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/25066
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These bits start the acquisition process. They should only be set by the
driver.
BUG=b:74363445
TEST=compile
Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/27265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to sona thermal table, PL2 need to check cpu id.
And then set PL2 value.
BUG=b:110867809
TEST=The thermal team verify OK
Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
An ACPI RMRR table is requried for IOMMU to work properly with an
iGPU (without using passthrough mode), so create one along with the
DRHD DMAR table if the iGPU is present and enabled.
Test: build/boot google/chell and purism/librem13v2 with kernel
parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated
graphics functional without corruption.
Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Add DMAR RMRR table entry and helper functions, using the existing
DRHD functions as a model. As the DRHD device scope (DS) functions
aren't DRHD-specific, genericize them to be used with RMRR tables as
well. Correct DRHD bar size to match table entry in creator function,
as noted in comments from patchset below.
Adapted from/supersedes https://review.coreboot.org/25445
Change-Id: I912b1d7244ca4dd911bb6629533d453b1b4a06be
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27269
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It used the sandybridge systemagent binary and mentioned that in the
help text which is simply wrong and won't work.
This copies the nb/intel/haswell/Kconfig to not include an mrc.bin by
default.
Change-Id: I2e151a66abc6dab710abdbb92c0c28884d88912e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both southbridges need to be done at once since this southbridge code
is used for different northbridges, which fails to compile when done
separately.
This needs an acpi_name functions in the northbridge code to be
defined.
TESTED on Intel DG43GT: show correct PIRQ ACPI entries in
/sys/firmware/acpi/tables/SSDT.
Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
For this to work the northbridge and lpc bridge device need acpi_name
functions.
TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in
/sys/firmware/acpi/tables/SSDT
Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22980
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit changes the uid and desc fields for the sx9310 entries
in the devicetree to be unique, and correctly identify the position
of the respective sensors.
Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
The stoneyridge bootblock no longer makes AGESA calls. Remove the
support files from the bootblock build.
TEST=boot Grunt
Change-Id: I14d2336d5fb766a1acf5e812337ae0ab3ca4a6c1
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove residual code that allowed successful building of the heapmanager
code. Now that stoneyridge no longer makes AGESA calls in bootblock, it
is safe to elimate the workaround.
BUG=b:74518368
TEST=boot Grunt
Change-Id: Ie169a691a177bcd8283c31c8188ce28bcbce82af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This enables the user to set the completion timeout value in PCI
Express Device Control 2 register via devicetree.cb.
Based on corebootBDE-270-iou-complto.patch in Arista EOS 4.20 release.
Change-Id: If0527899bc2047d0e57c11f7801768d07f9a5179
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/26225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
mca_configure needs to be called for each core before
booting to OS, else OS would keep dumping MCEs
Change-Id: I95ca46fda7be65d74714bdb344e339922cbb6305
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/26392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
add an unused param so that mca_configure can be called
by mp_run_on_all_cpus to run it on all cores.
Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/26391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Will be used on Cavium SoC to delete devicetree entries that aren't
available with the board/configuration.
Change-Id: I7c58a2411206bca62d0e96fa627530e937383ac9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
If CPU 0's stack grows to large, it will overflow into CPU 1's stack.
If CPU 0 is handling the interrupt then CPU 1 should be in an idle loop.
When the stack overflow occurs it will override the return pointer for
CPU 1, so when CPU 0 unlocks the SMI lock, CPU 1 will attempt to return
to a random address.
This method is not foolproof. If code allocates some stack variables
that overlap with the canary, and if the variables are never set, then
the canary will not be overwritten, but it will have been skipped. We
could mitigate this by adding a larger canary value if we wanted.
I chose to use the stack bottom pointer value as the canary value
because:
* It will change per CPU stack.
* Doesn't require hard coding a value that must be shared between the
.S and .c.
* Passing the expected canary value as a parameter felt like overkill.
We can explore adding other methods of signaling that a stack overflow
had occurred in a follow up. I limited die() to debug only because
otherwise it would be very hard to track down.
TEST=built on grunt with a small and large stack size. Then verified
that one causes a stack overflow and the other does not.
Stack overflow message:
canary 0x0 != 0xcdeafc00
SMM Handler caused a stack overflow
Change-Id: I0184de7e3bfb84e0f74e1fa6a307633541f55612
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27229
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The stub flash driver is a temporary hack that planned to adapt eMMC to
SPI flash. Remove the hack since SPI flash is what we really expect.
BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui
Change-Id: If29869461fc8c2efe26bb8c901737ee85935d27f
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
We would use GPP_B20 instead of board id to determine nautilus SKU.
BUG=b:80052672
BRANCH=poppy
TEST=Verified the new coreboot could determine SKU correctly
Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27220
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix a linking problem with VBOOT and USE_OPTION_TABLE enabled.
Make use of cbfs_locate_file_in_region() and always search the
cmos_layout.bin in the 'COREBOOT' region.
With this change applied there's no need to include the vboot_locator
in SMM any more, we can't break NVRAM with different CMOS layouts,
and we keep VBOOT and non VBOOT behaviour the same.
Only include cmos_layout.bin and cmos.default in RO region.
Add notes explaining the decisions.
Tested on Intel Sandybridge, builds and boots with vboot enabled.
Change-Id: I10ae94d7936581bbb5ea49384122062bd4934ea5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change a86d1b8 (soc/intel/common: Add SMM common code for Intel
Platforms) moved APL to use common SMM code. However, smi.c and smm.h
files under soc/intel/apollolake/ were not removed. This change
removes the dead files since they are not used anymore.
BUG=b:110836465
Change-Id: I1ff213372521fd47e2335de6a4b438d16c74ecd3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure
that we do not end up in a recursive SMI handler loop as mentioned in
change 74145f7 (intel/common/pmc: Disable all GPEs during
pmc_init). Thus, this call was added at the end of
pmc_fill_power_state as we want to ensure that all the GPE registers
are backed up before being cleared for identifying the wake source in
ramstage.
This resulted in a side-effect on APL where pmc_fixup_power_state was
called much later in the boot process. Even though we have got rid of
pmc_fixup_power_state, this change moves the call to
pmc_disable_all_gpe to happen just before enabling SMIs. This helps to
keep the disabling of GPEs logically before the enabling of SMIs and
any clean ups that happen in pmc or soc-specific code should not
affect the state of GPEs.
BUG=b:110836465
TEST=Verified that wake sources are correctly identified on KBL and
APL. Also, no SMI handler issues observed when resuming.
Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.
BUG=b:110836465
Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On APL, call to pmc_fixup_power_state was added because GPE0_EN
registers did not have the right bits set on resume from S3 -- this
was a result of GPE_CFG registers getting reset to their default state
on resume. GPE_CFG registers are programmed as part of pmc_gpe_init
which was previously done only in ramstage.
However, with change a673d1c (soc/intel/apollolake: Initialize GPEs in
bootblock), call to pmc_gpe_init was added to bootblock which means
that GPE_CFG registers will have the right state by the time control
reaches romstage where pmc_fill_power_state is called. Thus, call to
pmc_fixup_power_state is totally redundant and in fact leads to
side-effects because of the call to pmc_disable_all_gpe at the end of
pmc_fill_power_state.
BUG=b:110836465
TEST=Verified on yorp that wake source is correctly identified on
resume from S3.
Change-Id: Ia63ddbe381ce8a59736c231d745fd71d008d5d92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
%edx gets clobbered before the c handler is invoked. This is just a
cleanup cl to make the next cl look clean.
BUG=b:80539294
TEST=verified SMI still works on grunt.
Change-Id: I21bf41ed4fdeaaa8737c883f202a39cb57c2b517
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27228
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When generating a backtrace we need an indicator when we have hit the
beginning of the stack. The i386 ABI states that %ebp points to the next
stack frame. NULL can be used to indicate the end of the stack.
We could add a NULL return pointer at %ebp+4, but I decided to omit it
since a NULL stack pointer can be used as an indicator that there is no
return pointer.
BUG=b:80539294
TEST=built and tested on grunt
Change-Id: I8a48114d31a5c716335d264fa4fe4da41dc5bf11
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27226
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the cognitive overhead of referencing locals via esp since
it changes with every push.
BUG=b:80539294
TEST=built and booted on grunt.
Change-Id: Ib7eb98ce3483d4fc803696c1b2496d8384317536
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This makes it easier to spot unused RAM.
BUG=b:80539294
TEST=built and tested on grunt. Verified unused memory was set to 0xcdcdcdcd
Change-Id: I335eaf642bd8526f31819eaac95ce80c2df3c300
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Type of vbt_len should be size_t, change to fix compiler error
Change-Id: I22798fa0edb98fcb9acc1b2dd52f34a61bc511e9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
An unidentified combination of speculative reads and branch
predictions inside WRPROT-cacheable memory can cause invalidation of
cachelines and loss of stack on models based on NetBurst
microarchitecture.
Therefore disable WRPROT region entirely for all family F models.
As an extreme example, just changing the location of a constant string
passed to printk() has been witnessed to make a the boot fail early on
in romstage.
Change-Id: I1df84ad55e2d8d6d4e8dca10125131b5f525f0d7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For cases with POSTCAR_STAGE=y this reference pulled
in the implementation of run_ramstage() which we would
not call.
Using _program results with the same region being marked
as WRPROT-cacheble.
Change-Id: Ie1eaf6f5bb8baa13e946112c4fc3d854dbf750a3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Keith Hui <buurin@gmail.com>
Don't consume CBMEM for stage cache when we would
never use it.
Change-Id: I606e0457ff3085822554c4041fc56f0d28cc9c2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disabling the MMU with proper cache behavior is a bit tricky on ARM64:
you can flush the cache first and then disable the MMU (like we have
been doing), but then you run the risk of having new cache lines
allocated in the tiny window between the two, which may or may not
become a problem when those get flushed at a later point (on some
platforms certain memory regions "go away" at certain points in a way
that makes the CPU very unhappy if it ever issues a write cycle to
them again afterwards).
The obvious alternative is to first disable the MMU and then flush the
cache, ensuring that every memory access after the flush already has the
non-cacheable attribute. But we can't just flip the order around in the
C code that we have because then those accesses in the tiny window
in-between will go straight to memory, so loads may yield the wrong
result or stores may get overwritten again by the later cache flush.
In the end, this all shouldn't really be a problem because we can do
both operations purely from registers without doing any explicit memory
accesses in-between. We just have to reimplement the function in
assembly to make sure the compiler doesn't insert any stack accesses at
the wrong points.
Change-Id: Ic552960c91400dadae6f130b2521a696eeb4c0b1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some arm64 files that were imported from other projects use the
__ASSEMBLY__ macro to test whether a header is included from a C or an
assembly file. This patch switches them to the coreboot standard
__ASSEMBLER__, which has the advantage of being a GCC builtin so that
the including file doesn't have to supply it explicitly.
Change-Id: I1023f72dd13857b14ce060388e97c658e748928f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This file has been dead since commit 7dcf9d51 (arm64: tegra132:
tegra210: Remove old arm64/stage_entry.S), I just forgot to remove it.
Change-Id: I0dd6666371036ecd42c1b256dbbe22a01ae959b8
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/27236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
TPM config items added upstream before ready
SPI/TPM is not functional on Cheza yet
Change-Id: I302e00014dc31279fe2574765763ecdbf326b449
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/27213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Limit is the maximum number of bits to be tested, however it's being checked
against the number of bytes of uint32_t. when it should be number of bits.
Create a macro to provide the number of bits, and use it instead of sizeof.
BUG=b:75996437
TEST=Add debug messages to see code passing beyond the check, build and
boot grunt, check that it passed the limit check, remove debug code.
Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Adds Open Cellular rotundu mainboard supports.
Working:
- 2x Ethernet support
- MSATA support
- CPU init
- Memory init
- USB support
- EMMC but disabled
Not working:
- TPM support
Create directory structure and Kconfig files for OpenCellular
Rotundu and copy sources from intel/minnowmax.
Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4
Signed-off-by: Hong Gan <hgan@fb.com>
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/22894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This adds another camelbackmountain_fsp derivative, along with a .fmd
file for the board. For now it's been tested to build and boot.
Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/25884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Now that sconfig is able to support variant-specific override trees,
this change updates octopus boards to use this feature. Following
devices are moved from baseboard devicetree to variant specific
devicetree:
1. Touchscreen
2. Trackpad
3. Digitizer
4. Audio codec
BUG=b:80081934
TEST=Verified that the right devices show up in static.c for each
variant.
Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27219
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new config option OVERRIDE_DEVICETREE that allows
variants to provide an override devicetree file to override the
registers and/or add new devices on top of the ones provided by
baseboard devicetree using CONFIG_DEVICETREE.
BUG=b:80081934
Change-Id: Ica046b7e0d70d0f1e8d94da714d1e62032277916
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V
leakage. To fix this problem, add GPP_C3 into config for Pantheon
Synaptics touchscreen.
BUG=b:78436458
BRANCH=None
TEST=Let DUT in S0ix mode and check GPP_C3 is normal.
Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af
Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27177
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Recent patches in coreboot have fixed the freeze issues related to the
use of me_cleaner on Nehalem.
However, at least on the Lenovo X201, with me_cleaner some PCIe devices
(like the SATA and USB controllers) disappear. In particular, setting
the AltMeDisable bit ("-S" or "-s" flag) makes them disappear
completely, while unsetting it makes them disappear only during cold
boots.
This kind of behaviour was already observed by Youness Alaoui on the
Purism Librem laptops ([1]), and it seems related to some required
board-specific PCIe configuration in the ME's MFS partition.
For this reason, on the Lenovo X201, "-w EFFS" has been added to the
me_cleaner arguments, which whitelists the MFS-equivalent partition for
ME generation 2. This fixes all the issues, and the PCIe devices work as
expected.
[1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/
Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/27178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
During Speaker playback, quad Channel I/V feedback data is
captured from SSP0 Rx. Out of these 4-channels, Stereo V-Sense data
needs to be given as echo ref stream.
So, adding stereo capture config to max98373_capture_formats.
BUG=b:110074225
TEST='Audio playback and Capture Stereo echo ref data'
Change-Id: I6fe619ece94d5011caffe37ef10b48f956938db9
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27182
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
i2c/alps driver implementation is an exact copy of the i2c/hid driver
with only the addition of ALPS0001_HID. This can be supported by the
i2c/hid driver using the hid field in devicetree which is what glkrvp
mainboard does. So, this change removes the i2c/alps driver which is
anyways unused.
Change-Id: I60761c384f3d800532b2b346272da7be28b77acd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change fixes the issue reported by Coverity CID 1393576 to ensure
that config is checked for NULL before it is actually used.
Change-Id: I5f0cd2bf2437fc640f4cf8d8203a971daf1f8d17
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Enrico Granata <egranata@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested with GRUB 2.02 as a payload, booting Arch Linux as
well as Debian. This code is based on the output of autoport
as well as other mainboards supported in coreboot already.
Working:
- Serial port I/O
- S3 suspend/resume. Untested with SeaBIOS since it failed
to resume on a similar board. It is likely to be due to
low memory corruption, but I have not worked on it.
- USB ports and headers
- USB3 ports attached to the ASM1042 controller. SeaBIOS can
boot from them, and it is likely GRUB can detect devices on
those ports as well. The chip has a small SPI flash nearby,
which seems to hold an Option ROM.
- Gigabit Ethernet
- Integrated graphics (libgfxinit)
- VGA BIOS for integrated graphics init
- PCIe x16 graphics
- PCIe x1
- SATA controller
- Hardware Monitor
- Fan Control (fancontrol on linux works well)
- Native raminit
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware.
- NVRAM settings. Only debug_level has been tested.
Untested:
- DVI port. It can detect a "fake" display, that is, an
EEPROM connected to the DVI port. Thus, gma-mainboard.ads
has been setup accordingly.
- PS/2 port.
- Audio: Only rear output (green) has been tested.
- EHCI debug.
- Parallel port header.
- Non-Linux OSes
- ACPI thermal zone and fan control (probably not working)
Not working:
- Booting from devices attached to the ASM1061 controller.
Devices on ports work fine once Linux has loaded.
- Any SATA devices with Tianocore (payload issue)
Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/26419
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Regarding "Intel 945G/945GZ/945GC/945P/945PL Express Chipset Family",
Document Number: 307502-005, page 91, if Channel B is empty,
all of the C1DRBs are programmed with the same value as C0DRB3.
Mobile 945 express chipset datasheet doesn't mention this specific case.
Change-Id: Ic26103aac7f920e5696b445e125d33405df4f43b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27204
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This configures a GPIO pin for enabling/disabling bluetooth on the
next version of the atlas board. The default is for bluetooth to be
enabled at this point.
BUG=b:110614620,b:110613353
BRANCH=none
TEST=none
Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27185
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures serial debug is not enabled by default on Cannonlake
platform.
Change-Id: Id925c8c73971a027e45ea3c61e878f134bc9feff
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and
select it for bip and fleex only.
Functional change in this CL is that EC SW sync will be enabled for
phaser.
BUG=b:110523400
Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Bootblock has grown beyond 32K, grow to 40K
Change-Id: Iedc52151e223ebf4ff5b35a419b5378a6f1c661b
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/26760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Commit 77034fa [intel/common: compress VBT] compressed vbt.bin in
CBFS, but only changed the loader in soc/intel/common, forgetting
the separate one used by FSP 1.1.
As the soc/intel/common loader has now been rolled into the one in
drivers/intel/gma, replace the VBT loader used by FSP 1.1 with the GMA one.
Also, remove 2 now-unused header files.
Test: build/boot google/chell, observe display initialized prior
to OS load, no FSP warning in cbmem console due to invalid VBT signature.
Change-Id: Iba882ee4d9e83dcd88bdf7dd2f5591f66005a3fe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds a new driver for the SX9310 proximity detector device.
The purpose of this is to enable the device's calibration information
to be stored in firmware, and then transferred over to the kernel
via ACPI.
This device has more than 10 individual configuration parameters,
so they would not fit in the generic driver's properties table.
Change-Id: Id8c434eec9fe2da731e142442503a12e88db2236
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/27173
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Alternative buffer communication support for PTT is no longer
needed for CNL onwards and coreboot does not need to reserve additional
4KiB memory for PTT support.
Change-Id: I11993cef77fd5e879eedabc1ed344f91f8257c90
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/27176
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use SPI_BASE_ADDRESS instead of PRERAM_SPI_BASE_ADDRESS like
big core in order make common code implementation straightforward.
Change-Id: Ibcb013fc95de29234253e89c9ca100cc468d44f6
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/27097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No Change in BUILD_TIMELESS.
Change-Id: I634526269d45ebdc6c31cdc28d9ec846b397211d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
In the end it does not look like RCBA register offsets are fully
compatible over southbridges.
This reverts commit d2d2aef6a3.
Is squashed with revert of "sb/intel/common: Fix conflicting OIC
register definition" 8aaa00401b.
Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.
BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.
Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Is unused in the tree.
Change-Id: I8a5308b6c7773d791d47832e620558394f1d727e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22132
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models
already. Enabling this option ensures that the NVIDIA GPU is powered.
More PCI devices can be observed when activating this setting. It was verified
on a W520, also by loading a VGA option ROM and achieving a working Dual
Graphics system.
The CMOS default has been kept to 'Integrated Only', as the usage of Dual
Graphics requires an option ROM and drains the battery more quickly.
Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f
Signed-off-by: Nico Rikken <nico@nicorikken.eu>
Reviewed-on: https://review.coreboot.org/26114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When played Left Only Audio and Right Only Audio, we observed that Audio
got swapped. Left Data played on Right Speaker and Viceversa.
This patch fixes the above issue.
BUG=b:73635449
TEST=Play Left only & Right only Audio and cross check Audio.
Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/27167
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for SKL and KBL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I1343f343bfac9b787f13c15b812c0a201dcccb38
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The entire StdHeader field is really supposed to
be forked from a template for each entry into the
AGESA API. Current code assumes only Callout would
be relevant, which is not quite the case.
Change-Id: I0cc66d01d62fa8dc6bb7c9f9fab6fa4753827554
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Set register speed_shift_enable=0 in devicetree to disable
p-states in coreboot as a temporary workaround for an SoC hang.
BUG=b:79666828
BRANCH=none
TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage",
flash spi image onto nocturne, boot to kernel and verify device
stays alive and responsive for several minutes without locking up.
Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
DRAM_DMA section is used for the special SPI NOR controller on legacy
SOC. Remove it since no driver need it currently and we don't have the
special SPI NOR controller on mt8183.
BUG=b:80501386
BRANCH=none
TEST=Boots fine on Kukui
Change-Id: I6ba0757adbf4f1f8d2688e5ab1a36007e4e0d0fd
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Using common watchdog timer (WDT) code for reset. Set up watchdog timer
in mtk_wdt_init() to get reset status and disable auto-reboot. Link
common do_hard_reset() to support hard reset.
BUG=b:80501386
BRANCH=none
TEST=both mtk_wdt_init() and do_hard_reset() work on Kukui.
Change-Id: I4be3a133dbb8a64604133cefb0c5f02d01afd0d4
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27026
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move watchdog timer (WDT) code which can be reused into a common
directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: Icbeb04f775c3c0fdc18dd198df8591f5c4b6ddce
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27025
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor watchdog timer (WDT) code which will be reused among similar
SOCs.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Elm
Change-Id: I745c2f204924d9eee1941c0f3e9b6ba45cfb1958
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/27024
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is a temporary hack to test camera presence before we have full
camera support implemented. Basically, we can now probe the camera
over i2c to verify that it's connected and the camera LED turns on.
BUG=b:80106316
BRANCH=none
TEST=camera LED comes on and camera can be probed over i2c.
Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27128
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We plan to use i2c-hid compatible trackpads on atlas, so this switches
the trackpad config to i2c-hid.
BUG=b:80662079
BRANCH=none
TEST=used trackpad to verify motion tracking
Change-Id: I2702e61a6aa96250c0c09ea4bd15d0c671eedadc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/27126
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change defines SAR sensor device into devicetree.cb.
Since only LTE sku has SAR sensor, we will use GPP_B20 as a device_present_gpio.
BUG=None
BRANCH=poppy
TEST=Verified SAR sensor device is loaded by driver in Chrome OS
Change-Id: Ib4969e4b82d18b1b1a599de8226c2d7d4bda7915
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27149
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nautilus 2nd SKU has a leakage voltage at GPP_D0 in S5 state. We need to set this to LOW when entering S5 for clear the leakage.
BUG=None
BRANCH=poppy
TEST=Verified the leakage is gone after update coreboot
Change-Id: I054e707b2bc2e63d6f99cd2fd8a57be20615f111
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For supporting new SKU, we need to override GPIO table and device configuration.
The board ID of 2nd SKU of nautilus is started from 9, so we would determine SKU with it.
BUG=b:80052672
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: I7242f23f47010664cc29ea86a126e63c9dd62ccd
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27147
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a file for uncore ASL code that is common among
Broadwell-DE mainboards but is currently copy + pasted in each of
their dsdt.asl files.
This is only for clean-up purposes. It is unclear if the code itself is
really necessary, but until we can do further investigation and testing
it will be left in.
Change-Id: I188e5e46dfa7c2ed3991fb97f2c1b5e062e2212d
Signed-off-by: David Hendricks <dhendricks@fb.com>
Reviewed-on: https://review.coreboot.org/27155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Collected timestamps indicate LZMA decompression of ramstage
is 4x slower when ROM is marked WP-cacheable, in contrast to
having ROM as US. A simple copy WP->WB with uncompressed
ramstage also appeared to be twice as slow as UC->WB copy.
It should be noted that if POSTCAR_STAGE was removed from build,
un-lzma takes 130 seconds instead of 45 milliseconds.
Change-Id: I2cf995395ef2d303ad0bc044dbfa160990a705d0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This change fixes the following issues with EC_IN_RW signal:
1. EC_IN_RW is an input signal to the SoC. Configure it accordingly in
GPIO table for baseboard and bip.
2. GPIO_EC_IN_RW is passed in coreboot tables so that payload can
re-sample the GPIO at runtime.
BUG=b:110084012
TEST=Verified that EC_IN_RW signal is read correctly in depthcharge.
Change-Id: I1c5f5b4b914ced98e89a571dc398df5ba1fe8460
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Add support for parsing and booting FIT payloads.
* Build fit loader code from depthcharge.
* Fix coding style.
* Add Kconfig option to add compiletime support for FIT.
* Add support for initrd.
* Add default compat strings
* Apply optional devicetree fixups using dt_apply_fixups
Starting at this point the CBFS payload/ can be either SELF or FIT.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.16.3.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.15.0.
Tested on Cavium SoC: Parses and loads a Linux kernel 4.1.52.
Change-Id: I0f27b92a5e074966f893399eb401eb97d784850d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Import from https://chromium.googlesource.com/chromiumos/platform/depthcharge
Coding style and coreboot integration will be done in a separate commit.
Change-Id: Iee56db328d7eeffb0eaf829841243b0b9195c199
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set the payload argument in selfload, as other (non self) payloads, are
going to set a different argument.
Change-Id: I994f604fc4501e0e3b00165819f796b1b8275d8c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25861
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to schematic, we need to correct USB OC pin configuration.
- OC0 for Type-C Port 1
- OC1 for Type-C Port 0
- OC2 for Type-A Port
- OC3 to NC
BUG=NONE
BRANCH=poppy
TEST=emerge-nautilus coreboot
Change-Id: Ic71baef646926cc6aadcc5dda7cb14f00e8d3687
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/27099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This creates a fleex variant for octopus. Nothing is set in the variant
files here; everything is picked up from baseboard.
BUG=b:110085182
TEST=None
Change-Id: Ia8b8bb757f67bea997b7f43489c38cac62f7682d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/27105
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This moves CAR stack under variable MTRRs and removes
old CAR code that used complex fixed MTRRs and placed
stack in low memory.
Change-Id: I75ec842ae3b6771cc3f7ff652adbe386c03b9a5f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/26586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These CAR init files are no longer used.
The _ht variant will be used as basis for P3 CAR
using with variable MTRRs so we only move file.
Change-Id: Iace8762c11e2f282df1850f7be170c841d4881f4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/27084
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DEVEN defines are wrong, but weren't used at all.
Fix them as they are needed by the hybrid_graphics_driver and
use the defines instead of magic values.
Tested on Lenovo T410: The IGD turns on with the correct value.
Change-Id: Idf9fc0115de5c72f7d5d88cbb09ae1d2fee0afd0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/27104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The dram controller cannot fully initialize the dram on warm
reset (receive enable calibration consistently fails) therefore
requiring cached timings.
This option is mostly useful when rebooting after having flashed a new
rom which overwrites the mrc cache region.
Change-Id: I405c0eca076fe081641ede9a670f734c98cbf8fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/27100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
All Grunt variants should identify as grunt in SMBIOS so that
they're recognized correctly as a unibuild Grunt variant.
BUG=b:110244268
TEST=Careena identifies as grunt
Change-Id: Iaf254149fbec9551d9220018d6d6a0a1be741538
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/27117
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pin does not have a native function for eSPI. Nonetheless if we use
eSPI, it should be configured as a GPIO and kept unconnected to allow
S0ix entry.
Also removed initialization of LPC pins in mainboard code as they are
already initialized in chipset code. The settings fpr LPC pins in
chipset code were updated to those that were previously in mainboard
code and have been validated on LPC flavor of Geminilake RVP.
BUG=b:79251613
BRANCH=none
TEST=From kernel prompt in bip, type powerd_dbus_suspend.
Check on EC console that SOC enters S0ix.
Change-Id: Ie0c1013fee638a3b7a91469736efc0c25a1597fa
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23742
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support booting a GNU/Linux payload on non x86, the FIT format
should be used, as it is the defacto standard on ARM.
Due to greater complexity of FIT it is not converted to simple ELF format.
Add support for autodecting FIT payloads and add them as new CBFS_TYPE 'fit'.
The payload is included as is, with no special header.
The code can determine the type at runtime using the CBFS_TYPE field.
Support for parsing FIT payloads in coreboot is added in a follow on
commit.
Compression of FIT payloads is not supported, as the FIT sections might be
compressed itself.
Starting at this point a CBFS payload/ can be either of type FIT or SELF.
Tested on Cavium SoC.
Change-Id: Ic5fc30cd5419eb76c4eb50cca3449caea60270de
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Update dptf.asl and TCC parameters from tuning of the thermal team.
BUG=b:72974136
TEST=Match the result from DPTF UI
Change-Id: Ic0ffc169ad3939cacb46824ed23999c61a23d2c4
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/27086
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable keyboard backlight by Careena SKUID
Set to 10% as the same as google/snappy project
BUG=b:110065836
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I7d302c4f50528b0e6b7ef4d990f342a69cff34f5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Libgfxinit provides a better alternative to the native C init. While
libgfxinit mandates an ada compiler, we want to encourage use of it
since it is in much better shape and is actually maintained.
This way libgfxinit also gets build-tested by Jenkins.
Change-Id: I4843f52307b87cff6fa6f4d0c74b87428fefa8ac
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
TESTED Intel DG41WV with VGA, Intel DG43GT with VGA and HDMI1 and
HDMI2.
Change-Id: I774b79cc0ef9dc72ccf48901ab94376b27ed9c7a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some things were coding errors, other things need to be fsb specific.
Most things here don't seem to matter all that much but better to get
it right.
Change-Id: I1afa637a16a083c3a945ba3e2a71292b005736fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It looks like this hardware has a bug where the display controller
does not work properly when dram is clocked 533MHz and the channels
are configured in non-stacked mode.
The workaround is to select stacked mode in this configuration.
Change-Id: I6f37ce15a4e98a4cdbd6d893f22846a65c8be021
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There seems to be a hardware bug where the combination of non-stacked
channel settings, both channels populated and 533MHz dram speed cause
the display to be unusable.
The code to actually select stacked mode based on hardware
configuration will be add in a followup patch.
This patch does the following:
* Add option to the sysinfo struct for stacked mode
* Fix programming channel 1 DRB which needs special care for the last
populated rank in stacked mode
TESTED on Intel dg41wv (with stacked mode hardcoded and dram at 533MHz)
Change-Id: I95965bfea129b37f64163159fefa1c8f16331b62
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
GSMI Set Event Log is taking more than 1K in stack. This causes the
stack to overflow into the adjacent stack. This has the side effect of
causing any CPU waiting for the SMI handler to complete to crash when
the lock is unlocked because the return pointer has been smashed.
BUG=b:80539294
TEST=built on grunt and tested by running `halt` from the OS.
Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27033
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Stoneyridge is running into a stack overflow in the SMM handler.
BUG=b:80539294
TEST=built on grunt
Change-Id: I94e385497bd93c3638c69fb08d9b843c3bbb55ce
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27034
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_E2 will be used as a BT reset line, so configure GPP_E2 as an
output and initialize it high (high = out of reset).
BUG=b:80089559
BRANCH=none
TEST=none
Change-Id: If45ef3a592c389a0b80298c59eea849d07d9671e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27023
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FCAM_PWR_EN signal is changing to connect to GPP_B4 instead of
GPP_D8 as it needs a 3.3v gpio to provide enough power to also
directly power the camera LED.
BUG=b:79667559,b:78122599
BRANCH=none
TEST=none
Change-Id: Ie875ced45dfa2aa7069851004edde8f77329df34
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/27022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
C1E is disabled by the kernel driver intel_idle at boot. This does not
address the S3 resume case, so we lose state and C1E is enabled after S3
resume.
Disable C1E for GLK as it is for APL. This gives a coherent state before
and after S3 resume.
TEST='iotools rdmsr cpu 0x1fc'. Returns the same value after boot and S3
resume with bit [1] set to zero (0x20005d).
Change-Id: I437cbaca75c539c2bc5cd801ab8df907e7447d10
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27019
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit. Define POWER_CTL_C1E_MASK to be used subsequently.
Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method to retrieve a node's phandle.
Useful for board specific devicetree manipulations.
Change-Id: I966151ad7e82fc678ab4f56cf9b5868ef39398e0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.
Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.
Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.
TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368
Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement an optional callout for AgesaHeapRebase which allows AGESA
to override any internal hardcoded heap addresses.
Designate a region in CAR that may be used for pre-mem heap and return
that address before DRAM is configured. After DRAM is up, the address
in cbmem is returned.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ieda202a6064302b21707bd7ddfabc132cd85ed45
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Implement a new AGESA callout that may be used to find the correct
temporary location in DRAM to store heap data.
Near the end of AmdInitPost, AGESA migrates its heap from a CAR-based
location to a temporary region. Once cbmem has been established, the
heap will be relocated again in AmdInitEnv from the temp location to
the final one.
This patch does not materially affect the behavior of AGESA's heap
management. It only puts coreboot in control of the location. Future
work may refactor the copying.
TEST=Boot grunt with patchstack and experimental blob
BUG=b:74518368
Change-Id: Ibc5cc988e3e80d78f50cf0195e952b657141e570
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new callout definition for AgesaGetTempHeapBase and displace
AgesaHeapRebase (which was merged too soon) in the ordering. Also
add its structure.
AGESA will be modified to ask coreboot for the location for temporary
storage of heap data at the end of InitPost. The old methodology is
to use 0xb0000 but the change will allow coreboot to determine the
location.
BUG=b:74518368
Change-Id: I0bc894d7842cf4b3eb728a90704277b17f4bf7be
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26145
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After removing most geode_lx boards, some mainboard
directories are left empty. This patch cleans them up.
Change-Id: I2e99eba3d49dec90ceb2ce0c7f61612a9840ce59
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/27092
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The -S flag of me_cleaner, in addition to the standard code removal,
sets the the AltMeDisable bit (ME 6.x-10.x) or the HAP bit (ME 11.x),
which asks Intel ME to stop the execution after the hardware
initialization.
This should bring some advantages:
* The state of Intel ME can be easily obtained by reading the Current
Operation Mode register to trigger specific adjustments in the
raminit (as already done in bd82x6x)
* Intel ME falls into a more defined state, instead of being in a
generic "Image Failure"
* Hopefully, less code is run by Intel ME, as the execution should
stop before even trying to load additional modules
Tested on:
* Nehalem, Sandy Bridge and Ivy Bridge (Nicola Corna)
* Broadwell, Skylake and Kabylake (Youness Alaoui)
If needed, the -S flag can be removed or integrated with other
board-specific options by overriding CONFIG_ME_CLEANER_ARGS.
Change-Id: I2c12d09124dcc39924d1dc4eaf53a2dc1f69a2ac
Signed-off-by: Nicola Corna <nicola@corna.info>
Reviewed-on: https://review.coreboot.org/25508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
This adds stoneyridge specific versions.
BUG=b:79546790
TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS,
activate ACPI debug, activate S3 stress test. Interrupt stress test, do a
"cat /var/log/messages" saving the serial output. Examine the serial
output, see added debug code showing action taken. Confirm action by
reading proper register. Debug code removed.
Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Shuffle words and drop the _DATA_FILE suffix.
Change-Id: I0b0d50ea729e5580c0bc7b43f250ff387ce59cfc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is Garrett's patch with a bit of cleanup.
BUG=b:65442212
TEST=Was able to boot, suspend and resume on grunt.
Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change checks to ensure that config is not NULL before it is
accessed for the first time.
Reported by: Coverity CID #1393312
Change-Id: Ic248c79783da9c2bfdf3b7f737e5963feff7558c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Fix regression (supposedly) after commit:
23d62dd lib/bootmem: Add more bootmem tags
Without RELOCATABLE_RAMSTAGE, payload is allowed to overwrite
memory regions of the running ramstage. This case is handled
gracefully via a bounce-buffer implementation in arch/x86/boot.c.
Change-Id: I1c9bbdb963a7210d0817a7a990a70a1e4fc03624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: I08644892d34925574f791b000b0035d5afad7022
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26722
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most things still need to be filled in, but this will allow us to build
boards which use this SOC.
BUG=b:80501386
BRANCH=none
TEST=timer and uart work fine
Change-Id: Ie81fa56ffce85188e1f9e979f9b0e64b764c2627
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26659
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As a result of commit:
[711fb81] soc/intel/skylake: Swap PCI devfn resides in same PCI device
fizz's chip_info for the LAN driver is being overwritten/nulled, as the
LAN device is on function 2 (PCIe port 3), but the driver info was set
for the post-swapped PCIe port (1).
Move the driver chip_info to function 2/port 3, so that it follows the
PCI device function when swapped after FSP-s, and is correctly passed
to the LAN driver.
Test: boot google/fizz (teemo variant), check cbmem console and
verify ethernet MAC address and LED config correctly set.
Change-Id: I08810c0c89d99af5799f42c7c4e51814f09aafec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Why would that be a user visible option? Drop the prompt and the
`default n` and select it automatically when needed. I hope I
caught all its users.
TEST=Confirmed that systems with ELOG_GSMI or DEBUG_SMI compile
and link.
Change-Id: I44aeec530cc333f4ed4c8cfe67c7b5c9d8fb0049
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Clean it up and add all flash chip drivers to postcar stage thereby.
There seem to be SPI controllers that don't need the individual
flash chip drivers. For those postcar support was added in b6b1b23
(console/flashconsole: Enable support for postcar). However for
SPI controllers that need the individual drivers (i.e. those with
CONFIG_SPI_FLASH_INCLUDE_ALL_DRIVERS=y), linking of the postcar
stage was broken.
For all other stages, the set of compilation units stays the same.
Change-Id: Ib8bdb824bfcf2d31ac696e39f797c4355b765756
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26871
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Let the linker take care of it.
Change-Id: I67d2636ceb042f833c1b44888b98135d728940e0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This code is no longer needed. Removing Kahlee options allows some
Kconfig options to be optimized.
BUG=b:77693343
TEST=Build Grunt, verify that nothing's changed.
Change-Id: I4eeeee7f35381bba8760c8a530251c475d0ee29b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The initial subsystem ID had a device ID but not a vendor ID.
This change adds the Google vendor ID to the subsystem ID.
Change-Id: I14897da115fd6f2ddd492b6c565bd23227197232
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/26987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Making exceptions for some payload to be loaded near
and under 1 MiB boundary sounds like a legacy 16-bit
x86 BIOS thing we generally do not want under lib/.
Change-Id: I8e8336a03d6f06d8f022c880a8334fe19a777f0a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add tablet motion control config to nami devices.
BUG=None
BRANCH=None
TEST=run evtest
make sure tablet switch value is 1 in tablet mode and 0
when not in tablet mode
Change-Id: Ie1480934dc003d9b467883e001ed89f9a3694d10
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26970
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Use pci_devfn_t or pnp_devfn_t instead of device_t in romstage.
Change-Id: Ie0ae3972eacc97ae154dad4fafd171aa1f38683a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26984
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I07e00afbbd2c19cf3ea6e08f228eb39e45f1ad0c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use of device_t has been abandoned in ramstage.
Change-Id: I064ff5e76dd95c1770cd24139195b2a5fff2d382
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch sets the ACPI FADT flag ACPI_FADT_LOW_POWER_S0
if S0ix is enabled for the platform.
BUG=b:79559085
TEST= Boot to OS and check the ACPI_FADT_LOW_PWR_IDLE_S0
flag is set in FACP table - FADT.Flags[21] bit.
Change-Id: I0b8a86118232a66e7466d5b8116eff6087b51210
Signed-off-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/26940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Careena uses a different keyboard backlight method, so let the EC
handle the different SKUs and backlight methods.
BUG=b:80106042
TEST=None
Change-Id: I47f7a9ac13538f0216fbb0f64fdd22f66097820c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Until these need to be separated out, use a common file for mainboard
and romstage to make upkeep easier.
BUG=b:80106042
TEST=Build Grunt and Careena
Change-Id: I65188bee1958d442bfe64637c3b93dc05583a686
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This fixes the following failure on certain google/peppy configs:
build/postcar/lib/reset.o: In function `__hard_reset':
/home/pgeorgi/coreboot/src/lib/reset.c:24: undefined reference to `do_hard_reset'
Change-Id: I448a8702a30108f1fc82179a766cbdd209336df7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/26986
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Looking at the 100MHz signal, we were violating the timing requirements.
66MHz still isn't great, but it's a good tradeoff between improving
the signal and losing boot speed time.
This slows down the boot time by about 20mS.
BUG=b:109583457
TEST=Boot grunt, look at signal on scope
Change-Id: I7ce70c992822dd17c5877226e74c1890660768c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Configuring EC_PCH_WAKE_L as an SCI enabled GPIO allows the EC to wake
the AP from S3 on keyboard presses.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) press a key on the internal keyboard
=> system resumes from S3
Change-Id: I30f72460fd588706f91f4fc3ea4ff007c96e9ebe
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26931
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change b41ae2 (mb/google/octopus: Enable wake-over-wifi for octopus
variants) changed the GPE mappings to accomodate for WiFi wake
pin. However, this resulted in TPM interrupt pin being removed from
the GPIO to GPE mapping. Since we do not support true interrupts in
coreboot, GPE_STS registers are used to identify if an interrupt has
triggered. Change in GPE mapping resulted in this information to be
lost when talking to TPM thus resulting in "Timeout wait for tpm
irq".
This change fixes the above issue by assigning GPIO block for TPM
interrupt back to DW1 and moving GPIO block for wake-over-wifi pin to
DW3. DW3 was mapped to NW_31_0 which only has debug header pins and
CNVI pins (none of them are used for reading GPE_STS or as wake
sources).
BUG=b:109824918
TEST=Verified that there are no "Timeout wait for tpm irq" messages
when talking to TPM.
Change-Id: I30768177a838a684948f7485d760c8b83c3190f7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TPM over SPI/I2C config selection got changed in
https://review.coreboot.org/c/coreboot/+/24903 so this CL is fixing the
same.
BUG=None
BRANCH=None
TEST=Build for Soraka & make sure that TPM is probed over I2C interface
rather than SPI.
Change-Id: I077e4dc03520e26eb9f6404a7eb1edd99925de77
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26890
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since there are two cameras on Nami and only one camera on Sona.
We need to disable rear camera/DMIC on all Sona sku.
BUG=b:109710674
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Sona
Change-Id: Id84ee22c9ffc15db78be3bbad148af5cd7dc866e
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since there are two cameras on Nami and only one camera on Pantheon.
We need to disable rear camera/DMIC on all Pantheon sku.
BUG=b:109720689
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Pantheon
Change-Id: Ibe48a945dc57f2c05344479253040ad1945d92fd
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As we suppress output now before console_init() is done, the log level
read at start of ramstage is always -1.
Change-Id: Ia078d647c47aaa41ca9f2df9cf8506148ef86538
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/26832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch moves uart, timer and cbmem code which can be reused into a
common directory under soc/mediatek.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I5210149b324947ee90f1a481b42f0e2e1f7cfc25
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This patch refactor cbmem and timer code which will be reused among
similar SOCs.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: I397ebdc0c97c7616bd547022d2ce2a8f08f3c232
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26881
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch fix whitespace and formating issues:
1. Using two spaces between code and single line comment.
2. No space after asterisk.
3. Fix checkpatch error.
4. Remove spaces after cast operators.
BUG=b:80501386
BRANCH=none
TEST=the refactored code works fine on the new platform (with the rest
of the patches applied) and Elm platform
Change-Id: Ib36c99b141c94220776fab606eb36af8f64f65bb
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/26880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
TSEG can be used as a stage cache and SMM can be relocated here.
Change-Id: Ifa3acce57f0c13eee326b7c203a43453c74c3161
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25593
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TSEG can be used as a stage cache and SMM can be relocated here.
Tested on Intel D945GCLF, still boots.
Change-Id: I0da5a00c98c4c4fb309b2691dc1d4645eb35b4fd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25592
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a common function to decode the TSEG size from the ESMRAM
register. This will come in handy when SMM in TSEG is implemented.
This function is used both in romstage and in ramstage.
Change-Id: I4e163598752fb6cd036aec229fce439ebad74def
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23448
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For enable_resource & set_resource, use default DEVICE_NOOP so that they
are not reported as missing during enumeration.
BUG=None
BRANCH=None
TEST= Build & boot soraka.
Change-Id: I0fcfb8df39c6313c8a5bab5b780a8ffa7531d210
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/26869
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update GPIOs in baseboard to match latest schematics:
1. Get rid of STEST GPIOs(GPIO_{62,84-89})
2. Get rid of SD_CD_ODL(GPIO_134)
3. Get rid of KB control GPIOs(GPIO_{144-146})
4. Configure GPIOs for pen eject (GPIO_{144,145}). Additionally, fix the
configuration for other pen GPIOs.
BUG=b:109764138
Change-Id: I8e40dd90b2784596f055538e57ea67482c4c517a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26874
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds a INTEL_GMA_VBT_HAVE_DATA_FILE Kconfig option for the path
to point to the mainboard dir and to select
INTEL_GMA_ADD_VBT_DATA_FILE by default.
Change-Id: I730cb0737945631e2d5379a9e26b8c039ec6dc49
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With RELOCATABLE_RAMSTAGE, variables RAMBASE and RAMTOP
have no meaning any more.
Change-Id: I711fe98a399177c2d3cb2a9dcdefba61031fb76d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Chip sections must be covered by a PCI device.
Fixes chip_ops not being executed and TPM shows up in OS.
Change-Id: Id0ecd2f2f3e303f2228743369a8025b327bee61d
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/26750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When the normal termination is None, the standby termination is
none also as per Doc# 572688. So when termination is only needed in
standby, use the IOSSTATE setting that drives low/high via the
Tx mode instead.
Also disabled Speaker in Standby state to save power.
BUG=b:79874891, b:79982669
BRANCH=None
TEST=Compiled and flashed image on Bip. Checked that suspend_resume cycles
pass. Checked that bluetooth is functional on resume. On Yorp, checked
that speaker is functional after a suspend/resume cycle.
Change-Id: I6a3852548f944176a80feb32e9885b03b8af25db
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/26762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Issue observed on the board is: too many jack interrupts.
cat /proc/interrupts | grep da7219
58: 84292 15709 0 0 IO-APIC 58-fasteoi da7219-aad
Updated pad configuration for Jack IRQ pin to fix the issue.
BUG=b:109655907
TEST=Jack insertion & removal detection is working.
Change-Id: I41ef9d40325677b01ca94ec3215e7feded76dcc3
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/26851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
During measurement of signals during Elan touchscreen power on, saw
that the enable_gpio delay was not sufficient as there is a +1.5 ms
delay during power on. Adding more delay to take this into account.
BUG=b:78311818
BRANCH=None
TEST=probe power on signals to ensure meet timing requirements
Change-Id: Id661a202188a97aef97514ebecd0be6fc022d21e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Power off does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/power off.
BUG=b:78311818
BRANCH=None
TEST=Run "poweroff" command from AP console with SMI_DEBUG enabled
Make sure delays are consistent with spec
Change-Id: Ifeea545fe268be249793b3e508c51f5e4c1a3460
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/26724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove the last bits of building romstage with romcc.
Change-Id: I70bb1ed23a5aeb87bf7641e0b0bd604a4e622e61
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26807
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch creates a glue layer between SOC and common block IPs in terms
of PCH. All common IP blocks now can be selected based on
SOC_INTEL_COMMON_PCH_BASE config option.
BUG=none
BRANCH=b:78109109
TEST=Build and boot Cannonlake RVP and EVE.
Change-Id: I4e1f009489f2d8338ae94b78d7e9eb3f88a85d99
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).
All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.
A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.
BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option
Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change enables wake-over-wifi functionality for all octopus
variants by making the following changeS:
1. Configure GPIO_119 as SCI active-low
2. Update GPE0_DW1 to include the group that GPIO_119 falls under
3. Add wake property to wifi device
BUG=b:77224247
TEST=Verified that wake-over-wifi works on yorp.
Change-Id: Ibae199c43e4d96da4c2f68f71a849c2f23d3e7b9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Bit 63 is part of GPIO_GPE_NW group 1 and group 2 starts from bit
64. This change corrects macro name to GPIO_GPE_NW_95_64 to reflect
this.
BUG=b:77224247
Change-Id: Ib94617ad102eea5084281f0dda3475e33d3a7833
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/26852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since Vayne added one more skuid 3A67, we need to disable rear
camera/DMIC for vayne skuid 3A67.
BUG=b:75073617
BRANCH=master
TEST=Verify if only front camera/DMIC shown on Vayne
Change-Id: I9131b4c41bf189829be4e7e6bfaf4a96765cfa15
Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/26855
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for APL and GLK.
Change-Id: I9253af6f28bf694782c117296766fd8564dc2b14
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization for CNL.
Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.
Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init
Default coreboot does MP initialization.
Change-Id: I8de24e662963f4600209ad1b110dc950ecfb3a27
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GCC 7.1 found an int-in-bool-context in northbridgeinit.c. The logical
`&&` in `if (shadowByte && (1 << bit))` should be changed to bitwise
`&`.
Also fix off-by-one error with the bitmasks.
Change-Id: I7d7720121d4730254542372282f5561739e7214b
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20808
Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is active work to convert remaining two boards,
PC Engines alix1c and alix2d, to EARLY_CBMEM_INIT.
Change-Id: I87e3963af7ef719e9fa2a8b0df34a896265905f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Prepare a common cache as ram for CPU's featuring a Non eviction mode
MSR.
Change-Id: I7fa3853498856050855b3b97546f4d31f66d12f7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26789
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This changes the following:
- compute amount variable MTRR's during runtime
- Wait for all CPU's to be in Wait for SIPI state after sending init
INIT IPI to all AP's
- compute the PHYSMASK high during runtime and preload it to the
MTRR_PHYS_MASK msr's
Change-Id: I8d8672f8b577c2e7cef6e80978c4464a771f430c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Split of the model_6ex cache as ram to support POSTCAR_STAGE, which is
also needed for future C_ENVIRONMENT_BOOTBLOCK.
When using POSTCAR_STAGE the p4-netburst/exit_car.S is using since it
is identical.
Change-Id: Ibe9f065fdf1d702b73333ea7bb32daca15ba1293
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/26783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
After FSP-S, a device on PCI function n will be function swapped
to function 0 if there is no device presnet on function 0.
It needs some modification for DT and causes mismatches between
software configuration and hardware schematic. This patch is
from d779605, which swaps the devfn of the first enabled device
in DT and function 0 resides in a PCI device.
BUG=b:80105785
BRANCH=None
TEST=Make sure the device is still enabled after coalescence with
device on bus 0 and w/o device on bus 0. Test with suspend
and resume and ensure it's consistent.
Change-Id: Ibbc5d6e979977011f5904c8bd4b2f1be16bd23dc
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/26479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested on Lenovo T430:
The TPM is advertised through ACPI tables and the version can be
read using tpm_version, tcsd and tpm_tis.
Change-Id: I0b0c39e7aa1be4a479325d4b5eff5892a7e2f69f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/26780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This allows to lock down spi among other things
Mostly copied from bd82x6x.
Tested on Intel DG41WV with the MRC_CACHE driver write protecting the
mrc_cache region.
Change-Id: If9c3a6118f4586d51c093edec896c347ba904b8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Based on Nicola Corna's work.
This allows for CONFIG_CONSOLE_SPI_FLASH to be used, which writes the
console output to the SPI flash.
TESTED to still work in ramstage on x220 (correctly writes MRC CACHE),
the option CONFIG_CONSOLE_SPI_FLASH compiles for targets using the
common Intel SPI code (untested though).
Change-Id: I4671653c0b07ab5c4bf91128f18f142ce4f893cf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/25414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Id41279a1cdc7c68d3dcc44e238863f2f4a452499
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ia36b4ef7d66c50a044bc51f452ac8b7c7ff14323
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: I6db25850d46ea3a940ea2a6f263303d4b5304cb3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26539
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ifadb894f98ce60cf0778de7fbcec67d125e48fd6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Ibf21100eb2232932ea52740bd5250319d3c9adfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: Idf47ea3b29c3fab7256d7a6722c7978594001d8d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Patrick Rudolph