Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during
verstage. The interrupt is left in APIC mode as the GPE is
still latched when the GPIO is pulled low.
BUG=chrome-os-partner:53336
Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Support reading the ACPI GPE status (on x86) to determine when
the cr50 is ready to return response data or is done processing
written data. If the interrupt is not defined by Kconfig then
it will continue to use the safe delay.
This was tested with reef hardware and a modified cr50 image
that generates interrupts at the intended points.
BUG=chrome-os-partner:53336
Change-Id: I9f78f520fd089cb4471d8826a8cfecff67398bf8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Implement the generic acpi_get_gpe() function to read and clear
the GPE status for a specific GPE.
Tested by watching GPE status in a loop while generating interrupts
manually from the EC console.
BUG=chrome-os-partner:53336
Change-Id: Id885e98d48c2133a868da19eca3360e2dfb82e84
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Initialize the GPEs from mainboard config in bootblock, so they
can be used in verstage to query latched interrupt status.
I still left it called in ramstage just to be sure that the
configuration was not overwritten in FSP stages.
Tested by reading and reporting GPE status in a loop in verstage
and manually triggering an interrupt on EC console.
BUG=chrome-os-partner:53336
Change-Id: I1af3e9ac1e5c59b9ebb5c6dd1599309c1f036581
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Add a function that can be implemented by the SOC to read
and clear the status of a single GPE. This can be used
during firmware to poll for interrupt status.
BUG=chrome-os-partner:53336
Change-Id: I536c2176320fefa4c186dabcdddb55880c47fbad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Unify the function names to be consistent throughout the driver
and improve the handling while waiting for data available and
data expected flags from the TPM.
BUG=chrome-os-partner:53336
Change-Id: I7e3912fb8d8c6ad17d1af2d2a7189bf7c0c52c8e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Clean up the mask and timeout handling in the locality functions
that were copied from the original driver.
BUG=chrome-os-partner:53336
Change-Id: Ifa1445224b475aec38c2ac56e15cb7ba7fcd21ea
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Rename the low-level functions from iic_tpm_read/write to
cr50_i2c_read/write to better match the driver name, and pass in the
tpm_chip structure to the low-level read/write functions as it will
be needed in future changes.
BUG=chrome-os-partner:53336
Change-Id: Ib4a68ce1b3a83ea7c4bcefb9c6f002f6dd4aac1f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Use two different timeouts in the driver. The 2ms timeout is needed
to be safe for cr50 to cover the extended timeout that is seen with
some commands. The other at 2 seconds which is a TPM spec timeout.
BUG=chrome-os-partner:53336
Change-Id: I77fdd7ea646b8b2fef449f07e3a08bcce174fe8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reduce the static buffer size from the generic default 1260
down to 64 to match the max FIFO size for the cr50 hardware
and reduce the footprint of the driver.
BUG=chrome-os-partner:53336
Change-Id: Ia88facca607f3fd5072d0d986323fde075f15855
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Originally I thought it would be cleaner to keep this code in one
place, but as things continue to diverge it ends up being easier
to split this into its own driver. This way the different drivers
in coreboot, depthcharge, and the kernel, can all be standalone
and if one is changed it is easier to modify the others.
This change splits out the cr50 driver and brings along the basic
elements from the existing driver with no real change in
functionality. The following commits will modify the code to make
it consistent so it can all be shared with depthcharge and the
linux kernel drivers.
BUG=chrome-os-partner:53336
Change-Id: Ia9a65e72519b95f5739e3b7a16b9c2431d64ebe2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Move the common enums and variables to tpm.h so it can be
used by multiple drivers.
BUG=chrome-os-partner:53336
Change-Id: I0febe98620d0ddd4ec6b46cd3073e48c12926266
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
This patch sets some magic number in magic undocumented registers that
are rumored to make USB 2.0 signal integrity better on Kevin. I don't
see any difference (unfortunately it doesn't solve the problems with
long cables on my board), but I guess it doesn't hurt either way.
BRANCH=None
BUG=chrome-os-partner:56108,chrome-os-partner:54788
TEST=Booted Kevin with USB connected through Servo. Seems to have
roughly the same failure rate as before.
Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84
Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/370900
Original-Reviewed-by: Guenter Roeck <groeck@chromium.org>
Original-Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-on: https://review.coreboot.org/16265
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add FSP 2.0 support in ramstage.
Populate required Fsp Silicon Init params and configure mainboard
specific GPIOs.
Define function fsp_soc_get_igd_bar needed by fsp2.0 driver for
pre OS screens.
Change-Id: Ib38ca7547b5d5ec2b268698b8886d5caa28d6497
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16592
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Remove fsp1.1 driver code that adds vbt.bin & use soc/intel/common
instead to add vbt.bin in cbfs.
Also, VBT blob is added to CBFS as RAW type hence when walking the
CBFS to find vbt.bin, search with type as RAW.
Change-Id: I08f2556a34f83a0ea2b67b003e51dcace994361b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16610
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This implements PRW method for WLAN and configures PCIe wake pin to
generate SCI.
BUG=chrome-os-partner:56483
TEST=Suspend the system into S3 or S0ix. System should resume through wake
event from wifi.
Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16611
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.
Change-Id: I08677976792682cc744ec509dd183eadf5e570a5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16551
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This implements "Keep VESA framebuffer" behavior on VGA output of gm45.
This patch reuses Linux code to compute vga divisors.
Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16338
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The intel x4x and gm45 have very similar integrated graphic devices.
Currently the x4x native graphic init enables VGA, while gm45 can output
on LVDS.
This patch reuses the x4x graphic initialisation code
to enable output on VGA in gm45 in a way that the behavior is similar to vbios:
If no VGA display is connected the internal LVDS screen is used.
If an external screen is detected on the VGA port it will be used instead.
Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Implement postcar stage cbmem console support. The postcar stage
is more like ramstage in that RAM is already up. Therefore, in
order to make the cbmem console reinit flow work one needs the cbmem
init hook infrastructure in place and the cbmem recovery called.
This call is added to x86/postcar.c to achieve that. Additionally,
one needs to provide postcar stage cbmem init hook callbacks for
the cbmem console library to use. A few other places need to
become postcar stage aware so that the code paths are taken.
Lastly, since postcar is backed by ram indicate that to the
cbmem backing store.
BUG=chrome-os-partner:57513
Change-Id: I51db65d8502c456b08f291fd1b59f6ea72059dfd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16619
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The console_init(), MTRR printing, and loading ramstage
logic was previously all in assembly. Move that logic
into C code so that future features can more easily be
added into the postcar boot flow.
BUG=chrome-os-partner:57513
Change-Id: I332140f569caf0803570fd635d894295de8c0018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16618
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The declarations for console_init() were unconditionally
exposed even though there is a Kconfig option. Correct this
by honoring the CONFIG_POSTCAR_CONSOLE condition.
BUG=chrome-os-partner:57513
Change-Id: Id45ae3d7c05a9f4ebcf85c446fc68a709513bb0f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16617
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When the boot media is memory mapped mark it as cacheable
after romstage. Otherwise the boot media is uncacheable and
all loads from it take longer. Loading FSP-S alone in ramstage
went down to 17.5ms from 54ms.
BUG=chrome-os-partner:56656
Change-Id: I6703334ba8fe98aca26ba1c995d6d3abb0ddef33
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16613
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add a stripped-down version of libgnat. This is somehow comparable to
libgcc but for Ada programs. It's licensed under GPLv3 but with the
runtime library exception. So it's totally fine to link it with our
GPLv2 code and keep it under GPLv2.
Change-Id: Ie6522abf093f0a516b9ae18ddc69131bd721dc0c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/11836
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com>
There are certain board-specific options for reef variants. The
big one is the DPTF settings. Rearrange the ASL files such
that dsdt.asl is the main landing area. The ACPI options for
Chrome EC are contained in the variant/ec.h header so the
actual code #includes can just reside in dstd.asl. Since most
of the mainboard specific peripherals are auto generated by
the acpigen from devicetree there's no real separate need
for mainboard.asl. The one thing not addressed in this CL
is the notion of a variant having the Chrome EC or not (along
with lid, etc). Future indirection can be provided when needed
to address that requirement.
BUG=chrome-os-partner:56677
Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16604
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Currently we are setting the gpio_tier1_sci in smihandler before
going to S3. But this won't work for S0iX as it happens from Linux
kernel and SMI handler is not involved in that flow. We need to
set this bit i.e. bit 15 in ACPI gpe0a register at 0x430h. The Linux
kernel before going to sleep checks what values are passed through
ASL as wake events (through _PRW), keeps those enabled only and
clears other bits in gpe0 enable registers. So we need to inform
the kernel to keep gpio_tier_sci also set as these are needed for
any wake event. This patch adds ASL code for sleep button device with
HID id PNP0C0E. We are adding _PRW method for sleep button device
with this patch.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: Ie8517cad9cd37c25788c22250894d4f9db344ff9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16564
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The h8s needs around 3s to respond to ps2 commands
Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/16505
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
In commit 4f2754c
'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode'
the default operation mode of SERIRQ was changed from continuous to quiet.
Set the mode to continuous for this mainboard to keep the behavior unchanged.
Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
- Update lines to make them shorter than 80 chaacters
- Update using #defines from acpi_ivrs.h
Change-Id: I1bf6cdac00e28f5b0969fd8f98e37c66f8e43110
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16568
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
I put in the decimal values for these instead of the hex values.
Instead of running them through a BCD converter, update them to use
the hex values.
Change-Id: I3fa46f055c3db113758f445f947446dd5834c126
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16567
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Functionally, this should be roughly the same. The only real difference
should be removing the 4 bytes of padding from the end of the 4 byte
entries. The spec mentions a boundary for the 4 byte entries (which we
are ignoring), but doesn't mention a boundary for the 8 byte entries,
and I can't think of any other reason that the padding might be needed.
- Wrap long lines.
- Combine if statements to clean up indentation.
- Use #defines from acpi_ivrs.h to make commands easier to understand.
- Remove padding from 4 byte entries that made them 8 bytes in length.
- Set the pointer p at init, and clear the value at p if the device
we're looking at is enabled instead of setting p in every if statement.
- Look at the command type to update current and length.
- Treat malloc & free as if they were typical instead of coreboot
specific versions. Check to make sure the malloc worked and only
free on the last loop instead of every time.
Change-Id: I79dd5f9e930fad22a09d1af78f33c1d9a88b3bfe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16532
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16566
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
move lb_framebuffer function in soc/intel/apollolake
to driver/intel/fsp20 so that fsp 2.0 bases soc's can
use common lb_framebuffer function.
Change-Id: If11bc7faa378a39cf7d4487f9095465a4df84853
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16549
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Populate SoC related Memory initialization params.
Post memory init, set DISB, setup stack and MTRRs using the postcar
funtions provided in postcar_loader.c.
TEST=Build and boot kunimitsu, dram initialization done.
ramstage is loaded.
Change-Id: I8d943e29b6e118986189166d92c7891ab6642193
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16315
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
If FSP_M_XIP is selected, then relocate FSP-M binary
while adding it in CBFS so that it can be executed in place.
Change-Id: I2579e8a9be06cfe8cc162337fb1064d15842229f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16563
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The TPM driver was largely ignoring the meaning of the command
ready bit in the status register, instead just arbitrarily
sending it at the end of every receive transaction.
Instead of doing this have the command ready bit be set at the
start of a transaction, and only clear it at the end of a
transaction if it is still set, in case of failure.
Also the cr50 function to wait for status and burst count was
not waiting the full 2s that the existing driver does so that
value is increased. Also, during the probe routine a delay is
inserted after each status register read to ensure the TPM has
time to actually start up.
Change-Id: I1c66ea9849e6be537c7be06d57258f27c563c1c2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16591
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
It is very useful to have the ability to see I2C transactions
performed by the host firmware. This patch adds a simple
Kconfig option that will enable debug output.
Change-Id: I55f1ff273290e2f4fbfaea56091b2df3fc49fe61
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16590
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change modifies the lpss_i2c driver to behave more like
the Linux kernel driver. In particular the controller is only
enabled when processing a transaction, and is disabled after.
This means that errors in one transaction will not affect later
transactions.
Also when disabling the controller the code is supposed to wait
on the enable bit in the "enable status" register and not in
the enable control register. In order to get access to this
register the reg map was expanded to include all registers.
This was tested with the cr50 TPM driver to ensure that if a
transaction does fail that it can be successfully retried instead
of the bus being unusable.
Change-Id: I43a546d54996ba0f08550a801927b8f7a6690cda
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16589
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configure PERST_0 and assign the pin in devicetree.
BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.
Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Due to an incorrect value set for the power limit PL1, the
system is not able to leverage full TDP capacity. FSP code
sets the PL1 value as 6W in RAPL MMIO register based on
fused soc tdp value. This RAPL MMIO register is a physically
separate instance from RAPL MSR register. This patch sets
PL1 value to 15W in RAPL MMIO register.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package power
with heavy workload.
Change-Id: Ib344247cd8d98ccce7c403e778cd87c13f168ce0
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16595
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This configures PERST_0 in devicetree. For boards without
PERST_0, the pin should be disabled. For boards with PERST_0
the correct GPIO needs to be assigned.
BUG=chrome-os-partner:55877
Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16603
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This implements GNVS variable to store the address of PERST_0,
_ON/_OFF methods to power gate PCIe during S0ix entry, and
PERST_0 assertion/de-assertion methods.
BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.
Change-Id: I9f63ca0b8a6565b6d21deaa6d3dfa34678714c19
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16351
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The code was not previously initializing the GNVS structure
to all 0's in the ACPI write tables path. Fix this and also
rearrange the ordering of updating the fields to only handle
the chip_info specific bits till last such that most of the
structure is filled in prior to bailing out in the case of a
bad devicetree.
Change-Id: I7bdb305c6b87dac96af35b0c3b7524a17ce53962
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16597
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add MKBP as a SCI event: the EC is then able to send events coming from
the sensors.
BUG=b:27849483
TEST=With EC configure to send MKBP events, check sensor information are
retrieved by the kernel.
Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://review.coreboot.org/16594
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
cpu/amd/family_10h-family_15h.
Change-Id: Ia1b155eeb7b67d94cf7aaa7789843a3e4ed3497a
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16436
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/lenovo/t60.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16405
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/agesa/hudson.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I39cd2afe5e2b6ee3963fd3e949eab1db9e986d71
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16401
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/nehalem.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16406
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/ibexpeak.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Ic569aada9301b37e73196872584e191d553acd86
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16408
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82801gx.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Ia257318a7068b54739f319bfbba35f2a07826940
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16370
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82801ix.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Ibf20e6c08994b09d2a2e68a1a1d38a7a477493aa
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16403
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/gm45.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/via/vt8237r.
Change-Id: I9c1211e698ef35f56dd71c2c021dea680091c1ee
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16489
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/sis/sis966.
Change-Id: I9e731fedc6f21eaa2685f794ea2172eb4800628b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/nvidia/mcp55.
Change-Id: I98ac468940eaf6c456fa95540ec3e718edfe26a7
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16487
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/nvidia/ck801.
Change-Id: I43d4d2175f0b6b9e7e2e6fe665ba3d99d792427c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/sb800.
Change-Id: I488cde4504128331106f50b34869905e30f5ab83
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16480
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/sb700.
Change-Id: I44b0be2070719066dd18bbf2882c417caef5d8b2
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16479
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/sb600.
Change-Id: I0227cc0c611324f513f8170c9d8819a88af39b39
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16478
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/rs780.
Change-Id: Ia9929baeec7423e9e2f06324038ddfbec006beb7
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16477
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/rs690.
Change-Id: Ief43393f62312bfe82e960faf56b1e2ec048f4ff
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16476
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/pi/hudson.
Change-Id: I8b22a8d9f0e90afaf0f218c5c0924a78883b7498
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16475
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/cimx.
Change-Id: Ibe2766b956b0ca02be63621aee9a230b16d9923b
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16474
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/amd/amd8111.
Change-Id: I76cdc32171b7ce819b53c534b3a5e57e9dd5f3dd
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16473
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdht.
Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16468
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdk8.
Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16467
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdfam10.
Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16466
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/bcom/winnetp680.
Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16465
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/gigabyte/*.
Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
mainboard/asus/*.
Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16438
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This driver is only a prototype driver, real driver
will be integrated at a later time.
Testing: booted successfully.
Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16554
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This driver uses BootROM callback to read and write
to the nvm using I2C.
Testing: booted successfully.
Change-Id: I8639af3e004f6631d7e596507c106159835f979f
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
APMU is the AP power management unit.
It is a separate processor that handles enabling
individual power rails.
This driver handles sending and receiving commands
from/to APMU.
Testing: booted successfully.
Change-Id: I5ae07849f8432bece8a0ae9066a3f786e6e8d2fe
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15518
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Load_validate: it loads and validates images from
flash using hash values stored in the BDB.
Testing: booted successfully.
Change-Id: I0b00e8c60ed76622d03cb232d5c4273b4077aae7
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/16148
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Most things still need to be filled in, but this will allow
us to build boards which use this SOC.
Nvidia Tegra210 SOC and Rochchip Rk3399 SOC has been used
as templates to create this directory.
Change-Id: I8cc3e99df915bb289a2f3539db103cd6be90a0b2
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15506
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The serial IRQ (SERIRQ) used by the LPC interface can operate either in
continuous or in quiet mode. Add a Kconfig switch to select the desired
mode. This switch can now be used on mainboard level to enable the
needed mode per mainboard.
Change-Id: Ibe246b88164a622f9c71ebe7bab752a083a49a62
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16575
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Since this mainboard provides 4 COM ports on LPC, enable decoding of
the corresponding addresses using the generic LPC decode registers.
Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16535
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This creates a config for the Lenovo T60 sound card based
on values taken from vendor bios
(in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16).
The sound card configuration on the vendor bios is the same
as the one on the Lenovo x60.
It improves the default behavior of the sound card:
- internal microphone is chosen by default
- when jack is inserted it is chosen instead of internal speaker
Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This change adds armv7-r support for all stages.
armv7-r is an ARM processor based on the Cortex-R series.
Currently, there is support for armv7-a and armv7-m and
armv7-a files has been modfied to accommodate armv7-r by
adding ENV_ARMV7_A, ENV_ARMV7_R and ENV_ARMV7_M constants
to src/include/rules.h.
armv7-r exceptions support will added in a later time.
Change-Id: If94415d07fd6bd96c43d087374f609a2211f1885
Signed-off-by: Hakim Giydan <hgiydan@marvell.com>
Reviewed-on: https://review.coreboot.org/15335
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add header files as is from FSP build output.
Move the FSP header files to new location as in apollolake.
Update all the FSP structure references now that they are
typedef'd.
Change-Id: I148bff04c064cf853eccaaaf7a465d0079c46b07
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16517
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
'bool' type is reported undefined due to missing stdint.h inclusion,
Fix it by including the same.
Change-Id: Ib09c121471bd8c490442330a478145a7d1d8855f
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16538
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the current implementation of postcar_frame_add_mtrr,
if provided size is bigger than the base address alignment,
the alignment is considered as size and covered by the MTRRs
ignoring the specified size.
In this case the callee has to make sure that the provided
size should be smaller or equal to the base address alignment
boundary.
To simplify this, utilize additonal MTRRs to cover the entire
size specified. We reuse the code from cpu/x86/mtrr/mtrr.c.
Change-Id: Ie2e88b596f43692169c7d4440b18498a72fcba11
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16509
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Move the funtion to find most significant bit set(fms)
and function to find least significant bit set(fls) to a common
place. And remove the duplicates.
Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
postcar_loader.c has a useful library of funtions for
setting up stack and MTRRs. Make it available in romstage
irrespective of CONFIG_POSTCAR_STAGE for use in stack setup
after Dram init.
The final step of moving the used and max MTRRs on to stack
is moved to a new function, that can be used outside of
postcar phase.
Change-Id: I322b12577d74268d03fe42a9744648763693cddd
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Removes PCIe blocker for S0ix.
2. Set the correct PCIe root port for wifi/bt on EVT.
3. Turn off CLKREQs of unused PCIe root ports to power gate the IP.
Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091
Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/16557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The serial IRQ configuration register is only 8 bit wide so switch the
PCI access from 16 bits to 8 bits.
Change-Id: Ia9fbc02251e00b31440bf103e2afc2ff285b7f2e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16534
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82801dx.
Change-Id: Ic08a23f672f8b5e40b837d49a9475d52c728a306
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82801ax.
Change-Id: I46f0cc92e1034f045988b42df7246f5d0c8d24fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i82371eb.
Change-Id: Ie15a656c817a2ffe0f44ee3a89659d138a1bf212
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16483
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/i3100.
Change-Id: Ic9616d5135cfb7206e086e51aaf82eb66540c4bb
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16482
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/fsp_rangeley.
Change-Id: I6665f85c74eb3e37d78f6eecbec977dc21a5ad12
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16481
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/x4x.
Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/i5000.
Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/e7505.
Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16469
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Although the goal was to hide the ME device by disabling
the PCI bridge, the original comment that this bridge was ME related
was a mistake, this bridge is for PEG not for ME.
We still need this PCI bridge "on" to enable pci express graphics
add-on cards.
Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16496
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Replace the use of the old device_t definition inside
northbridge/intel/fsp_rangeley.
Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16470
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.
Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME. Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.
Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Move the current devicetree.cb to be under variants/baseboard.
New variants can provide their own devicetree as needed.
BUG=chrome-os-partner:56677
Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16510
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The early TPM probe was done directly in tis.c ignoring the lower
layer that provides appropriate access to the chip. Move this into
a tpm_vendor_probe() function so it can use iic_tpm_read() with all
of the built-in delays and semantics instead of calling i2c_readb()
directly from the wrong layer.
This fixes early init failures that were seen with the cr50 i2c tpm
on the reef mainboard.
Change-Id: I9bb3b820d10f6e2ea24c57b90cf0edc813cdc7e0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable the hexdump function in verstage as it can be useful there for
debugging I2C and TPM transactions.
Change-Id: If9dc4bcc30964e18ff5d8a98559f6306c0adec6f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16528
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For an unknown reason the printed address in the SPI debug messages is
modified before it is printed by subtracting the constant 0xf020 from
the passed in address.
What I suppose this debug code should do is to print the used register
address within the SPI controller while any parts of this address that
belongs to the SPI base address should be omitted. To fix that remove
the subtraction of 0xf020 and adjust the address mask to 0x3ff so that
only the offset to the registers inside the SPI controller will be
visible in the debug messages.
In addition switch to uint8_t and friends over u8 to sync up with used
types in this file.
Change-Id: I93ba7119873115c7abc80a214cc30363a6930b3b
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16500
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Hardcoding the microcode filenames into the makefiles is great when
the microcode is in the blobs directory. When the microcode isn't
posted to the blobs directory, we need some method of supplying the
microcode binary into the build. This can of course be done manually
after the build has completed, as can be done with everything that
we're including in the ROM image. Instead of making life hard for
everyone though, let's just add a way to specify where the microcode
rom comes from.
BUG=chrome-os-partner:53013
Change-Id: I7c5127234809e8515906efa56c04af6005eecf0b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/16386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Defining this OpRegion for SMBus controller prevents linux kernel
driver i2c-i801 from registering SMBus under sysfs, with following
error in dmesg:
ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI)
Solution taken from intel/bd82x6x. Worth noting we do not
define ENABLE_SMBUS_METHODS anywhere currently.
Removed remaining reference to HSTS from GETAC P470.
Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16266
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Similarly to 2b2f465fcb
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.
Tested on d945gclf
Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16319
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The script checkpatch.pl complains about these files. Fix
the warnings.
Change-Id: I4271cc35bb101447a316a75273cf8a6e95ed62d5
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/16011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
DIV_ROUND_CLOSEST and DIV_ROUND_UP are useful macros for other
architectures. This patch moves them from soc/nvidia/tegra/types.h
to commonlib/include/commonlib/helpers.h .
Change-Id: I54521d9b197934cef8e352f9a5c4823015d85f01
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16415
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is necessary for PCI express graphics card add-ons,
otherwise the pci allocator cannot fit the mmio for the
add on card into the space it has available and the OS
turns off the card. Old value was 1GiB.
Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No more hang on DMI init when wait for DMI is re-enabled.
Previously the virtual channel arbitration table was not being
set up in the south/north bridges causing invalid DMI state.
This has been tested on GA-G41M-ES2L with patches following.
An NVIDIA GT218 card was detected by the OS and displayed using
the nouveau driver with no blobs.
Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16491
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The field that was previously named 'efr' is actually the iommu feature
info field. The efr field is a 64-bit field that is only present in
type 11h or type 40h headers that follows the iommu feature info field.
Change-Id: I62c158a258d43bf1912fedd63cc31b80321a27c6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16508
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The revision field was correct, but the comment was wrong. The revision
1 means that the IVRS table only uses fixed length device entries.
Update the field to use the IVRS revision #define.
Change-Id: I4c030b31e3e3f0a402dac36ab69f43d99e131c22
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
According to "G45: Volume 3: Display Register
Intel ® 965G Express Chipset Family and Intel ®
G35 Express Chipset Graphics Controller" some registries
are set incorrectly in gm45/gma.c.
Some values are changed after comparing them with the values
the i915 linux kernel (3.13 was used) module sets while modesetting.
The values were obtained using 'intel_reg' from intel-gpu-tools,
during a normal boot and with 'nomodeset' as a kernel argument.
Some registers that don't exist on gm45 are set in gma.c, which is
probably the result of copying code from a more recent intel
northbridge.
The result is that that gm45 laptops with wxga displays still work as
before. gm45 laptops with wxga+ or higher resolution now just work,
where previously a black screen was shown.
TEST: build with native graphic init and flash on a gm45 target, like
lenovo x200.
Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16217
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove an unusued function declaration that caused problems while
compiling the target.
Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16435
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
If the TPM completely fails to respond then the vendor structure may not
have assigned handlers yet, so catch that case and return error so the
boot can continue to recovery mode instead of asserting over and over.
Change-Id: If3a11567df89bc73b4d4878bf89d877974044f34
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16416
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable the I2C based TPM on the reef board at
bus 2 and address 0x50.
This makes vboot functional without needing MOCK_TPM and
results in the following in the SSDT:
Device (TPMI)
{
Name (_HID, "GOOG0005") // _HID: Hardware ID
Name (_UID, Zero) // _UID: Unique ID
Name (_DDN, "I2C TPM") // _DDN: DOS Device Name
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings
{
I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80,
AddressingMode7Bit, "\\_SB.PCI0.I2C2",
0x00, ResourceConsumer)
Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive)
{
0x00000039
}
})
}
Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16398
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add code to generate an ACPI descriptor for an I2C TPM based
on the device as described in devicetree.cb.
This currently requires the devicetree to provide the HID,
since we don't currently talk to the TPM in ramstage and I
didn't want to add yet another init path for it here.
This was tested on a reef board to ensure that the device
is described properly in the SSDT.
Change-Id: I43d7f6192f48e99a4074baa4e52f0a9ee554a250
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16397
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for the cr50 TPM used in apollolake chromebooks.
This requires custom handling due to chip limitations, which
may be revisited but are needed to get things working today.
- timeouts need to be longer
- must use the older style write+wait+read read protocol
- all 4 bytes of status register must be read at once
- same limitation applies when reading burst count from status reg
- burst count max is 63 bytes, and burst count behaves
slightly differently than other I2C TPMs
- TPM expects the host to drain the full burst count (63 bytes)
from the FIFO on a read
Luckily the existing driver provides most abstraction needed to
make this work seamlessly. To maximize code re-use the support
for cr50 is added directly instead of as a separate driver and the
style is kept similar to the rest of the driver code.
This was tested with the cr50 TPM on a reef board with vboot
use of TPM for secdata storage and factory initialization.
Change-Id: I9b0bc282e41e779da8bf9184be0a11649735a101
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16396
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Allow the sleep durations used by the driver to be set by the
specific chip so they can be tuned appropriately.
Since we need to read the chip id to know the values use very
conservative defaults for the first command and then set it
to the current values by default.
Change-Id: Ic64159328b18a1471eb06fa8b52b589eec1e1ca2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16395
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use CAR accessors where needed for accessing static data.
In some cases this required some minor restructuring to pass
in a variable instead of use a global one.
For the tpm_vendor_init the structure no longer has useful
defaults, which nobody was depending on anyway. This now
requires the caller to provide a non-zero address.
Tested by enabling I2C TPM on reef and compiling successfully.
Change-Id: I8e02fbcebf5fe10c4122632eda1c48b247478289
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fix a few more instances of global variable usage in the tlcl
and marshaling code for tpm2.
For the tlcl case this buffer doesn't need to be static as it
isn't used after this function exits.
Change-Id: Ia739c81d79c6cee9046ae96061045fe4f7fb7c23
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16393
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Place config DEVICETREE after the sourced mainboard Kconfig. This
gives the mainboard the opportunity to set a unique default value.
Change-Id: Id877e1e8f555334a99b6c0ee1782d06a4a2b7a04
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16493
Tested-by: build bot (Jenkins)
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the config switch CONFIG_DEBUG_SPI_FLASH on compiler level rather
then on preprocessor level to ensure that the code is compiled even if
the switch is not selected. In addition the following two changes are
introduced:
1. Prepend the debug messages with 'SPI:' to make the output more
meaningful.
2. Change the address mask from 0xffff to 0x3ff and remove the subtraction
of the constant value 0xf020 in order to print only the register
offset within the SPI controller and avoid the visibility of any
fragments from SPI base address.
3. Switch to uint8_t and friends instead of u8 to sync up with other
code in the same file.
Change-Id: Iaf46f29a775039007a402fe862839df06a4cbfaa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16499
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The pull up for CLKRUN is required to resolve keyboard slowness
and malfunctioning observed on some reef systems. The CLKRUN
signal was probed and found to be floating when the pull up
was not enabled. Also Added pull ups for the LPC Multiplexed
command, address and data lines LAD0:3 because the LPC
Interface specification requires them.
BUG=chrome-os-partner:55586
BRANCH=none
TEST=When a key is pressed, the character is immediately visible
on the screen. Also the interrupt count for i8042 increments
immediately in /proc/interrupts.
Change-Id: I16df1a0301a3994c926a609f61291761219f9e01
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/16426
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
The last vestige of the proto boards is the memory sku id
gpios. The internal pullups are still required because there's
only pulldown stuffing options available on the reef boards.
BUG=chrome-os-partner:56791
Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16432
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move the current NHLT configuration implementation to the baseboard
area such that other variants can leverage it or provide their
own configuration.
BUG=chrome-os-partner:56677
Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16431
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Move the current memory configuration implementation to the baseboard
area such that other variants can leverage it. The swizzle config
is exported as a global to allow duplicate swizzles to use the same
structure while still allowing different memory SKUs.
BUG=chrome-os-partner:56677
Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16430
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add support for Chrome OS gpio ACPI table information by
providing weak implementation from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16422
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Since multiple boards will be living within one directory move all
the macros for defining anyting related to GPIOs to the gpio.h
header file. That way, when other boards land they can override
or use them as is.
BUG=chrome-os-partner:56677
Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16421
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
There's no common EC header file in the code base, and I didn't
want to use a header file for single declaration. Therefore,
just move the declaration to each file that uses that symbol.
BUG=chrome-os-partner:56677
Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16420
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Provide APIs for the board_id() and gpio table functionality.
Default and weak implementations are provided from the baseboard.
BUG=chrome-os-partner:56677
Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16419
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Commit e96543e1 (vendorcode/intel: Add UDK 2015 Bindings)
had an extra underscore at the end of one of the make lines that
we missed in the review. Remove it.
Fixes this build warning:
.../Makefile.inc:34: Extraneous text after `ifeq' directive
Change-Id: I0bc76d827207b4f641ac5ff08f540a114347533b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16411
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
A recently announced Turbot system populates two Ethernet
controllers. Enable the remaining disabled PCIe port.
Also add a clarifying comment regarding the port associated
with Function 0. Coreboot must not be allowed to disable the
function which breaks PCI compatibility.
Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MinnowBoard Turbot systems have a GPIO-controlled LED that is
generally used to indicate the CPU is running. Commit 2ae9cce8
changed the parameter for GPIO_NC, exposing an issue with the
assumed behavior of the signal. Use a pull-down to turn on the
LED.
Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16428
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/i945.
The patch has been tested both with the arch/io.h definition of
device_t enabled and disabled in order to ensure compatibility
while the transaction takes place.
Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16371
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the argument to #ifdef from __PRE_RAM__ to __SIMPLE_DEVICE__
in order to account for the coreboot stages that do not define device_t
and are not __PRE_RAM__ (i.e. smm) device_t
Change-Id: Ic6e9b504803622b60b5217c9432ce57caefc5065
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16369
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
northbridge/intel/sandybridge.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16409
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Avoid the inclusion of a function declaration if the argument type
device_t is not defined.
This was not a problem until now because the
old declaration of device_t and the new one overlapped.
Change-Id: I05a6ef1bf65bf47f3c6933073ae2d26992348813
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16404
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
southbridge/intel/bd82x6x.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I7166bfab7904f80b745855d3bbcfb910cbc89f56
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16407
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
To further the ability of multiple variant boards to share code
provide a place to land the split up changes. This patch provides
the tooling using a new Kconfig value, VARIANT_DIR, as well as
the Make plumbing. The directory layout with a single variant,
reef (which is also the baseboard), looks like this:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/reef - code
variants/reef/include/variant - headers
New boards would then add themselves under their board name
within the 'variants' directory.
No split has been done with providing different logic yet.
This is purely a organizational change.
BUG=chrome-os-partner:56677
Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16418
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Instead of completely duplicating the a reference board's directory
when doing a variant or follower device start providing a means to
share code within a single directory. This change just starts the
process from the Kconfig side, but subsequent patches will follow
which disentangles the board specific pieces from and common
logic.
BUG=chrome-os-partner:56677
Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16417
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The superio.asl wasn't being included within the right scope.
Fix that as well as clean up the per-mainboard header includes
to be in one place.
BUG=chrome-os-partner:56677
Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16413
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Some of the macros in gpio.h are no longer used because
devicetree.cb is being used to autogeneric the ACPI AML.
Therefore remove the unused macros.
BUG=chrome-os-partner:56677
Change-Id: I433a929229a0318f6c1df652655d046a5152cc63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16412
Tested-by: build bot (Jenkins)
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit 93ef3ff makes the following only print the part number when
the ROM is built. In Makefile.inc, $(MAINBOARDDIR) is the variable
that has the quotes stripped off from $(CONFIG_MAINBOARD_DIR), so
use it instead of $(MAINBOARD_DIR).
build_complete:: coreboot
printf "\nBuilt %s (%s)\n" $(MAINBOARD_DIR) \
$(CONFIG_MAINBOARD_PART_NUMBER)
Change-Id: I729a583182937db7a926eb75aa28dfb53360046c
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/16410
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Increase the default timeout in the LPSS I2C driver to 4ms
from 2ms. During testing with some slower devices I found
that the existing timeout could be too short leading to
transaction failures.
Change-Id: Ied86c7a0aa26d55b31f447c5938803c194d0045e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/16392
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
FSP header files should be located in vendorcode, not soc directory.
This patch includes changes any references to the old location to
the new location.
Change-Id: I44270392617418ec1b9dec15ee187863f2503341
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
UEFI 2.6 spec casts the return of FFS_FILE2_SIZE to a UINT32
which cannot be read using read_le32(&returnval). Add in a
cast in order to safeguard for any non x86 architecture that may
use this relocate. The proper change will be to get the UEFI
header files changed to not cast this return value.
Change-Id: Ie1b50d99576ac42a0413204bbd599bab9f01828e
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16309
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
mainboard/lenovo/x60.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16372
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Uses gpio.h instead of default_southbridge_gpio_setup to configure
southbridge GPIO's. This is more consistent with how GPIO's are
configured on newer targets.
Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16379
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All but ga-g41m-es2l/cmos.default had multiple final newlines.
ga-g41m-es2l/cmos.default had no final newline.
Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16361
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Antonello Dettori <dev@dettori.io>
Instead of using a mix of _N and _NORTH, _NW and _NORTHWEST for GPIO
community names, follow one single convention. This allows for re-using
macros easily.
Change-Id: Icd9cf9ef70d03576d864688cf5d6946124c259c3
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16353
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Many changes make proto boards very hard to work with since
proto boards were using A stepping processors. Everyone has
moved on. Therefore, drop non-proto support.
BUG=chrome-os-partner:56791
Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16377
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
A pen interface was added. Prepare for possibly testing it by
plumbing in the gpio configuration. It's very possible these
changes need to be tweaked, but no driver code has been seen
yet nor a datasheet detailing how some of these signals actually
function.
BUG=chrome-os-partner:56739
Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16376
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The formerly name FP_INT_L net is actually active high and is push-pull.
Therefore adjust for the new net name, FP_INT, and polarity. The
pulldowns are there because the device is on another board that isn't
always available.
BUG=chrome-os-partner:56740
Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16375
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The recent changes to this file from commit 6e5421d2
(sb/amd/sb700: Add option to increase SPI speed to 33MHz)
were accidentally removed in a code cleanup patch:
commit ba28e8d7 (src/southbridge: Code formating).
Change-Id: I6cf3e8f29d5c0384d35637f35e051be40318d20f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16384
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins)
Before, we calculate the pwm duties for cpu cores and centerlogic by
hand, adding pwm_regulator.c to handle this. The default pwm design
min/max voltage may be different between revs.
With the pwm regulator, this patch changes the little cpu frequency from
600M to 1512M, and raises CPU voltage to 1.2V correspondingly.
This also means we decide to drop the ES1 because it may fail to
bootup with 1.5G ~ 1.2v.
BRANCH=none
BUG=chrome-os-partner:54376,chrome-os-partner:54862
TEST=Bootup on kevin board
Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9
Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b
Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com>
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/364410
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16368
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add Initial pieces of code to support fsp2.0 in skylake keeping
the fsp1.1 flow intact.
The soc/romstage.h and soc/ramstage.h have a reference to
fsp driver includes, so split these header files for
each version of FSP driver.
Add the below files,
car_stage.S:
Add romstage entry point (car_stage_entry).
This calls into romstage_fsp20.c and aslo handles
the car teardown.
romstage_fsp20.c:
Call fsp_memory_init() and also has the callback
for filling memory init parameters.
Also add monotonic_timer.c to verstage.
With this patchset and relevant change in kunimitsu mainboard,
we are able to boot to romstage.
TEST= Build and Boot Kunimitsu with PLATFORM_USES_FSP1_1
Build and Boot Kunimitsu to romstage with PLATFORM_USES_FSP2_0
Change-Id: I4309c8d4369c84d2bd1b13e8ab7bfeaaec645520
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16267
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c
The intel documentation on i945, "Mobile Intel® 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.
The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.
What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.
TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version
Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage.c is more board related than soc specific, like
setting the pwm regulators, so moving it to mainboard/gru.
BRANCH=none
BUG=chrome-os-partner:54819
TEST=Bootup on kevin board
Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474
Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/375398
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16367
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Disable ps8640 mipi mcs function to avoid recognizing the normal mipi dsi
signal as msc cmd.
BUG=chrome-os-partner:56346
BRANCH=none
TEST=build pass elm and show ui
Change-Id: I91c690fb1ff3bd9b5c1f227205829c914347cd30
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4fd441b46300fea9f238b27c9c1cda4e9e53c80d
Original-Change-Id: I85b9f1e6677e4bf8ab1e30c2e69445079fff2d18
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/373219
Original-Commit-Ready: Daniel Kurtz <djkurtz@chromium.org>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/16365
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add delay before and in polling ps8640 ready to reduce the frequency
of polling.
BUG=chrome-os-partner:54897
BRANCH=none
TEST=build pass elm and show ui
Change-Id: I43c833af910490e53496a343330a6a6af35623a9
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: bc8c3d6f7cf0b2da693a465cf3845e8bbc53825a
Original-Change-Id: I5c725eed8110ff9f545c1142ca28bcff336b6860
Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/371718
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: jitao shi <jitao.shi@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/16364
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide GBB's hardware ID (used on Chrome OS devices) because it will be
dropped from depthcharge.
BRANCH=none
BUG=none
TEST=none
Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00
Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/372579
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Certain LPDDR4 models have some HW issues that can be worked around
by turning off Periodic Retraining feature in the memory controller.
Add option to disable PR per SKU.
BUG=chrome-os-partner:55466
TEST=run RMT test, pass
Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Update FSP Header files to provide UPD for periodic training
disable. This is for the SIC 1.1.3/150_11 FSP release.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=built coreboot image with new headers for reef
Change-Id: I2ba11aa3d2d664c1d34e39c4c8144fb1c4f2149a
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/16352
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
If ramstage caching outside CBMEM is enabled
i.e CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM, then a
helper function to determine the caching region in SMM
should be implemented. Add the same to FSP2.0 driver.
FSP1.1 driver had the same implementation hence copied stage_cache.c.
The SoC code should implement the smm_subregion to provide
the base and size of the caching region within SMM. The fsp/memmap.h
provides the prototype and we will reuse the same from FPS 1.1.
Change-Id: I4412a710391dc0cee044b96403c50260c3534e6f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16312
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Currently boards based on fsp_broadwell_de fail to compile if the config
switch CONFIG_DEBUG_SPI_FLASH is selected. The error is caused by the
usage of const for the address pointer in the functions writeb_, writew_
and writel_. The reason why it stayed hidden for so long is the fact that
the switch is used with the preprocessor and nobody really selects it
until there is a bug one want to find in this area.
This patch fixes the parameter type definition which solves the error.
In addition the config switch is not used on preprocessor level anymore
but instead on compiler level. This ensures that at least the code
syntax is checked on build time even if the config option is not
selected. Also prefix the messages with "SPI:" to make them more
meaningful in a full log.
Change-Id: I3514b0d4c08bf5a4740f2632641e09af1b3aaf3a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16347
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This corrects indentation for sdram configs in nyan_blaze.
Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: https://review.coreboot.org/16342
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The reef board needs at least ~28ms for its S0 rails to discharge
when S3 is entered. Because of the granularity in the chipset the
effective SLP_S3_L assertion width is 50ms.
BUG=chrome-os-partner:56581
Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16327
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In order to provide time for the S0 rails to discharge one needs
to be able to set the SLP_S3_L assertion width. The hardware default
is 60 microcseconds which is not slow enough on most boards. Therefore
provide a devicetree option for the mainboard to set accordingly
for its needs. An unset value in devicetree results in a conservative
2 second SLP_S3_L duration.
BUG=chrome-os-partner:56581
Change-Id: I6c6df2f7a181746708ab7897249ae82109c55f50
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16326
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Add new option to set up Cache-As-RAM by using CQOS, Cache Quality of
Service. CQOS allows setting ways of cache in no-fill mode, while keeping
other ways in regular evicting mode. This effectively allows using CAR
and cache simultaneously.
BUG=chrome-os-partner:51959
TEST=switch from NEM to CQOS and back, boot
Change-Id: Ic7f9899918f94a5788b02a4fbd2f5d5ba9aaf91d
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since whole L2 (1MiB) is not used, it is possible to shrink CAR size
to 768 KiB. Since 768 KiB is not power of two, 2 MTRRs are used to
set it up. This is a part of CQOS enabling.
BUG=chrome-os-partner:51959
Change-Id: I56326a1790df202a0e428e092dd90286c58763c5
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/15453
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we now have so much more room for activities in our romstage SRAM
section, we can easily fit the LZMA decompressor to enable ramstage
compression. Also shuffle around memlayout sections a little more to
make use of unused space, and balance out leftover memory so that all
sections that might need future expansion have a reasonable amount.
Change-Id: I47f2d03e520fc3103ef04257b4ba7e93874b8956
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16334
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch changes Gru SDRAM parameters from structures that just get
compiled into the romstage to individual CBFS files. This allows us to
only load the parameter set we need for the board we're booting from
flash, which reduces our boot time and the SRAM memory footprint
required to hold the romstage.
TEST=Booted Kevin.
Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16274
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The current CBMEM code contains an optimization that maintains the
structure with information about the CBMEM backing store in a global
variable, so that we don't have to recover it from cbmem_top() again
every single time we access CBMEM. However, due to the problems with
using globals in x86 romstage, this optimization has only been enabled
in ramstage.
However, all non-x86 platforms are SRAM-based (at least for now) and
can use globals perfectly fine in earlier stages. Therefore, this patch
extends the optimization on those platforms to all stages. This also
allows us to remove the requirement that cbmem_top() needs to return
NULL before its backing store has been initialized from those boards,
since the CBMEM code can now keep track of whether it has been
initialized by itself.
Change-Id: Ia6c1db00ae01dee485d5e96e4315cb399dc63696
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16273
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds functionality to compile a C data structure into a raw
binary file, add it to CBFS and allow coreboot to load it at runtime.
This is useful in all cases where we need to be able to have several
larger data sets available in an image, but will only require a small
subset of them at boot (a classic example would be DRAM parameters) or
only require it in certain boot modes. This allows us to load less data
from flash and increase boot speed compared to solutions that compile
all data sets into a stage.
Each structure has to be defined in a separate .c file which contains no
functions and only a single global variable. The data type must be
serialization safe (composed of only fixed-width types, paying attention
to padding). It must be added to CBFS in a Makefile with the 'struct'
file processor.
Change-Id: Iab65c0b6ebea235089f741eaa8098743e54d6ccc
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16272
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds support for the CBFS attributes that were already
introduced in cbfstool and libpayload. I'm only copy&pasting the header
definitions needed for this once more. Really, we should be unifying the
definitions (and possibly part of the code) from cbfstool with
commonlib, but apparently that hadn't been done when this feature was
introduced and I don't really have time to do it cleanly now.
Also add a function to extract info from the compression attribute,
which can then be used to run cbfs_load_and_decompress() on the file.
Change-Id: I7b6463597757122cfe84f006c946a1658bb3acc6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16271
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This enables the C4 low power state on the lenovo x200 and t400.
It's inspired by the thread on the mailinglist:
"[coreboot] Lenovo X200 running Coreboot drains 3-4W more power
than with Vendor BIOS".
What this does, is to enable a C3 state using MWAIT(C3) request
and set the southbridge config c4onc3_enable to automatically
upgrade C3 to the lower power C4 state.
The latency (0x37) is the same value used by the vendor bios.
With C4 enabled the idle power consumption is about ~2-3W lower.
TEST= build and install on target. Use powertop top to measure power
usage. To manually disable c-state to compare them,
do (tested on linux 4.4):
echo 1 > /sys/devices/system/cpu/cpu*/cpuidle/stateX/disable
Change-Id: I1a1663a7662ebc7157a965667680688ad6a33545
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/15251
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some SB700-based systems and ROMs support high speed (33MHz) SPI
access instead of the power-on default 16.5MHz. Add an option
to enable high speed SPI access in the bootblock, and set the
default value to Disabled. This greatly decreases boot time on
SB700-based systems, especiall when a large payload is in use.
On a KGPE-D16 with a Petitboot (Linux + initramfs) payload, the
command prompt was accessible within 20 seconds of power on, which
incidentally is faster than the proprietary BIOS on the same machine
could even reach the GRUB bootloader.
Change-Id: Iadbd9bb611754262ef75a5e5a6ee4390a46e45cf
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Test: Booted KGPE-D16 with Linux payload
Reviewed-on: https://review.coreboot.org/16306
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add in the base for ELOG for APL. Some PM events still need to be
added but the basic events are logged here. This enables the
basic functionality of ELOG for Apollolake.
BUG=chrome-os-partner:55473
BRANCH=none
TEST=Verified image boots on Amenia
Change-Id: I8682293e5a55b3efb5fdd9f1be1f3e4bf8d0757c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/15937
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Call power management utility function clear_wake_sts
from southbridge_smi_sleep before going to sleep.
This is needed to clear the wake status bits in ACPI
registers GPE0.
BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
powerd_dbus_suspend command issued from built-in
keyboard.
Change-Id: I204a59f8a19137d6a192ea2d89939eefcd5d41ce
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16299
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds a power management utility function to
clear wake status bits in ACPI GPE0 registers. We need
to call this function before going to sleep from
common smi handler function.
BUG=chrome-os-partner:55583
BRANCH=None
TEST=Verified that system goes to sleep on lidclose and
powerd_dbus_suspend command issued from built-in
keyboard.
Change-Id: Icd095d377c82f2e154f2e2db773f737aa49cda64
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16298
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On x86 platforms, google_chromeec_early_init() is used to put the EC
into RO mode when there's a recovery request. This is to avoid training
memory multiple times when the recovery request is through an EC host
event while the EC is running RW code. Under that condition the EC will
be reset (along with the rest of the system) when the kernel verification
happens. This leads to an execessively long recovery path because of the
double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the
bootblock size on the skylake boards. Additionally, this provides the
the correct logic for all future boards since it's not tied to FSP
nor the mainboard itself. Lastly, this double memory training protection
works only for platforms which verify starting from bootblock. The
platforms which don't start verifying until after romstage need to
have their own calls (such as haswell and baytrail).
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16318
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
When UART_DEBUG is enabled bootblock size grows more than the current
32K. Bump this up to 48K.
Change-Id: I580137dfdc9b4ad226c866f2b23b159bd820c62c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16317
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The chromium tree is currently using a different config for
Chrome OS than what is being built in coreboot.org. Align those
settings to reflect how skylake Chrome OS boards are actually
shipped to provide proper parity between coreboot.org and chromium.
Change-Id: I7ab9c1dfa8c6be03ac2125fb06cb7022f3befa97
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16313
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The SPI drivers for the various chipsets are not consistent in
their handling of when they are accessible. Coupled with the
unknown ordering of boot_device_init() being called this can
lead to unexpected behavior (probing failures or hangs). Instead
move the act of initializing the SPI flash boot device to when
the various infrastructure requires its usage when it calls
boot_device_rw(). Those platforms utilizing the RW boot device
would need to ensure their SPI drivers are functional and
ready when the call happens.
This further removes any other systems failing to boot as
reported in https://ticket.coreboot.org/issues/67.
BUG=chrome-os-partner:56151
Change-Id: Ib3bddf5e26bf5322f3dd20345eeef6bee40f0f66
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16300
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Implement PS0 and PS3 methods to support eMMC power gate
in S0ix suspend and resume.
BUG=chrome-os-partner:53876
TEST=Suspend and Resume using 'echo freeze > /sys/power/state'.
System should resume from S0ix.
Change-Id: Ia974e9ed67ee520d16f6d6a60294bc62a120fd76
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16233
Tested-by: build bot (Jenkins)
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The return value check was incorect and checking for failure
in the success path. Fix the return value check so that it
actually checks for success.
BUG=chrome-os-partner:56151
Change-Id: Ie7960b89a916dec261015c97c3e0552be56b5b5d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16303
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
vboot_named_region_device_rw() is supposed to provide a writable
region_device. However, it was calling fmap_locate_area_as_rdev()
which only provides a read-only one. Fix this.
BUG=chrome-os-partner:56151
Change-Id: I6279fde32132b1b6138292c3ef771c59709e00c6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16302
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Normally machine-mode code operates completely within physical address
space. When emulating less privileged memory accesses (e.g. when the
hardware doesn't support unaligned read/write), it is useful to access
memory through the MMU (and with virtual addresses); this patch
implements this functionality using the MPRV bit.
Change-Id: Ic3b3301f348769faf3ee3ef2a78935dfbcbd15fd
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16260
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Not all SBI calls are implemented, but it's enough to see a couple dozen
lines of Linux boot output.
It should also be noted that the SBI is still in flux:
https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM
Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16119
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The timestamp code asserts that the _timestamp region (allocated in
memlayout for pre-RAM stages) is large enough for the assumptions it
makes. This is good, except that we often initialize timestamps
extremely early in the bootblock, even before console output. Debugging
a BUG() that hits before console_init() is no fun.
This patch adds a link-time assertion for the size of the _timestamp
region in memlayout to prevent people from accidentally running into
this issue.
Change-Id: Ibe4301fb89c47fde28e883fd11647d6b62a66fb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16270
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
A new Kconfig option, DEBUG_PRINT_PAGE_TABLES, is added to control this
behaviour. It is currently only available on RISC-V, but other
architectures can use it, too, should the need arise.
Change-Id: I52a863d8bc814ab3ed3a1f141d0a77edc6e4044d
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16015
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add cmos.default file in order to ease future testing and debugging of
cmos related code.
Change-Id: I7c6a0aa4e38bb08a520e4838fa216c81b50f2917
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16247
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Update the config variable that gets set to use DMIC 2 channel blob for
intel/apollolake platforms. This flag is set in mainboard.
Change-Id: Ic6deb9f08d345cc45351d61a7597bc7075ee20f9
Signed-off-by: Saurabh Satija <saurabh.satija@intel.com>
Reviewed-on: https://review.coreboot.org/16251
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It's necessary to call spi_init() prior to calling spi_flash_probe()
such that the SPI drivers can do any work required prior to performing
SPI transactions. It could be argued that the drivers should handle
such situations, however the SPI API implementations seem to assume the
callers ensured spi_init() was called before any SPI transactions.
This fixes systems that failed to boot introduced by [1]. Issue tracked
in https://ticket.coreboot.org/issues/67.
[1] I2aa75f88409309e3f9b9bd79b52d27c0061139c8
https://review.coreboot.org/16200
BUG=chrome-os-partner:56151
Change-Id: I2d8d5ac685833521f1efe212b07a4b61ba0d9bc3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16297
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The ASUS KGPE-D16 accepts an optional Infineon LPC TPM module.
Expose the TPM LPC device to the host operating system.
Change-Id: If500e9162bf1e233ccaa35db79452daa59a34f2f
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/16269
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.
BUG=chrome-os-partner:56395
Change-Id: I3addc1ea065346fbc5dbec9d1ad49bbd0ae05696
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16259
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Before reading the data provided by EC to the host, ensure that data
ready flag is set. Otherwise, it could result in reading stale/incorrect
data from the data buffer.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is read correctly by host on reef.
Change-Id: I88e345d64256af8325b3dbf670467d09f09420f0
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16258
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Calling halt in poweroff when in SMM prevents SLP_SMI to be triggered
preventing the system from entering sleep state. Fix this by calling
halt only if ENV_SMM is not true.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified lidclose behavior on reef.
Change-Id: If116c8f4e867543abdc2ff235457c167b5073767
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16257
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
sts_index is calculated incorrectly because of wrong use of
parenthesis. This lead to wrong bit being checked for EC_SMI_GPI on reef
and lidclose event was missed.
BUG=chrome-os-partner:56395
BRANCH=None
TEST=Verified that lidclose event is seen and handled by SMM in
coreboot on reef.
Change-Id: I56be4aaf30e2d6712fc597b941206ca59ffaa915
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16256
Tested-by: build bot (Jenkins)
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add support for SMBIOS memory HOB save.
Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB.
BUG=chrome-os-partner:55505
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: I53b4a578f31c93b8921dea373842b8d998127508
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16249
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Read FSP produced memory HOB and use it to populate DIMM info.
DIMM 'part_num' info is stored statically based on memory/SKU id.
BUG=chrome-os-partner:55505
TEST='dmidecode -t 17' and 'mosys -k memory spd print all'
Change-Id: Ifcbb3329fd4414bba90eb584e065b1cb7f120e73
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/16246
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There's no need to be SPI specific w.r.t. how the flash is
connected. Therefore, use the RW boot device to write the
contents of VBNV. The erasable check was dropped because that
information isn't available. All regions should be aligned
accordingly on the platform for the underlying hardware
implementation. And once the VBNV region fills the erase
will fail.
BUG=chrome-os-partner:56151
Change-Id: I07fdc8613e0b3884e132a2f158ffeabeaa6da6ce
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16206
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Explicitly provide a RW view of an vboot FMAP region. This is
required for platforms which have separate implementations of
a RO boot device and a RW boot device.
BUG=chrome-os-partner:56151
Change-Id: If8bf2e1c7ca9bff536fc5c578fe0cf92ccbd2ebc
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16205
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Explicitly provide a RW view of an FMAP region. This is required
for platforms which have separate implementations of a RO boot
device and a RW boot device.
BUG=chrome-os-partner:56151
Change-Id: Ibafa3dc534f53a3d90487f3190c0f8a2e82858c2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16203
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.
BUG=chrome-os-partner:56151
Change-Id: Ifd51a80fd008c336233d6e460c354190fcc0ef22
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16202
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
If the boot device is SPI flash use the common one in the
early stages. While tweaking the config don't auto select
SPI_FLASH as that is handled automatically by the rest of the
build system.
BUG=chrome-os-partner:56151
Change-Id: If5e3d06008d5529dd6d7c05d374a81ba172d58fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16201
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
On many x86 platforms the boot device is SPI which is memory
mapped. However, in order to write to the boot device one needs
to use the SPI api. Therefore, provide a common implementation
of boot_device_rw() which has no mmap() functionality. It only
reads, writes, and erases. This will be used in the existing
infrastructure but in a SPI agnostic way.
Two options are added:
1. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP
2. BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY
The former is auto-selected when COMMON_CBFS_SPI_WRAPPER is not
selected. The latter can be used to include the implementation
in the early stages such as bootblock, verstage, and romstage.
BUG=chrome-os-partner:56151
Change-Id: I2aa75f88409309e3f9b9bd79b52d27c0061139c8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16200
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
It shouldn't matter if COMMON_CBFS_SPI_WRAPPER is selected to
include the SPI flash support in all stages. Therefore, include
the SPI flash support files in all the stages. While there include
the same set of files for all stages. They were out of sync for
some reason.
BUG=chrome-os-partner:56151
Change-Id: I933335104203315cbbcf965185a7c176974e6356
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16198
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The spi_flash_probe() routine was setting a global varible
unconditonally regardless if the probe was for the boot device
or even if the boot devcie was flash. Moreover, there's no need
to report the SPI information if the boot device isn't even SPI.
Lastly, it's possible that the boot device is a SPI flash, but
the platform may never probe (selecting SPI_FLASH) for the
actual device connected. In that situation don't fill anything
in as no correct information is known.
BUG=chrome-os-partner:56151
Change-Id: Ib0eba601df4d77bede313c358c92b0536355bbd0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16197
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
This aligns the code in qemu-riscv with the code in spike-riscv.
The previous code gives an error in the updated toolchain as the
send_ipi CSR is no longer valid.
This gave the build error:
src/mainboard/emulation/qemu-riscv/qemu_util.c:64:
Error: Instruction csrw requires absolute expression
Change-Id: Iac0f66e8e9935f45c8094d5e16bedb7ac5225424
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/16244
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable. Additionally,
include the SPI support code as well as its dependencies in
all the stages.
BUG=chrome-os-partner:56151
Change-Id: I0192ab59f3555deaf6a6878cc31c059c5c2b7d3f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16196
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Using malloc() in SPI code is unnecessary as there's only
one SPI device that the SoC support code handles: boot
device. Therefore, use CAR to for the storage to work around
the current limiations of the SPI API which expects one to
return pointers to objects that are writable.
BUG=chrome-os-partner:56151
Change-Id: If4f5484e27d68b2dd1b17a281cf0b760086850a7
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16195
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide the RW boot device operations for the common cbfs
SPI wrapper. The RW region_device is the same as the read-only
one. As noted in the boot_device_rw() introduction patch the
mmap() support should not be used in conjuction with writing
as that results in incoherent operations. That's fine as the
current mmap() support is only used in the cbfs layer which
does not support writing, i.e. no cbfs regions would be
written to with any previous or outstanding mmap() calls.
BUG=chrome-os-partner:56151
Change-Id: I7cc7309a68ad23b30208ac961b1999a79626b307
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16199
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The current boot device usage assumes read-only semantics to
the boot device. Any time someone wants to write to the
boot device a device-specific API is invoked such as SPI flash.
Instead, provide a mechanism to retrieve an object that can
be used to perform writes to the boot device. On systems where
the implementations are symmetric these devices can be treated
one-in-the-same. However, for x86 systems with memory mapped SPI
the read-only boot device provides different operations.
BUG=chrome-os-partner:55932
Change-Id: I0af324824f9e1a8e897c2453c36e865b59c4e004
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16194
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Indicate to the build system that a platform provides support
for a writable boot device. The following will provide the
necessary support:
COMMON_CBFS_SPI_WRAPPER users
soc/intel/apollolake
soc/intel/baytrail
soc/intel/braswell
soc/intel/broadwell
soc/intel/skylake
The SPI_FLASH option is auto-selected if the platform provides
write supoprt for the boot device and SPI flash is the boot
device.
Other platforms may provide similar support, but they do that
in a device specific manner such as selecting SPI_FLASH
explicitly. This provides clearance against build failures
where chipsets don't provide SPI API implementations even
though the platform may use a SPI flash to boot.
BUG=chrome-os-partner:56151
Change-Id: If78160f231c8312a313f9b9753607d044345d274
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16211
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The common boot device spi implementation is very much
specific to SPI flash. As such it should be moved into
that subdirectory. It's still a high-level option but
it correctly depends on BOOT_DEVICE_SPI_FLASH. Additionally
that allows the auto-selection of SPI_FLASH by a platform
selecting COMMON_CBFS_SPI_WRAPPER which allows for culling
of SPI_FLASH selections everywhere.
BUG=chrome-os-partner:56151
Change-Id: Ia2ccfdc9e1a4348cd91b381f9712d8853b7d2a79
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16212
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.
BUG=chrome-os-partner:56151
Change-Id: I06f138078c47a1e4b4b3edbdbf662f171e11c9d4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16228
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
In SMM, gpio configuration could be done to avoid leakage. ITSS
configuration is not required when entering sleep. Thus, bail out early
from itss configuration if in SMM.
BUG=chrome-os-partner:56281
Change-Id: I4d8be0513aa202f001f980bb91986b50b8ed2a5b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16242
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Replace a token that is not used anymore.
Change-Id: I36fffd1b713ae46be972803279fc993254bb5806
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16240
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Omar Pakker
Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Update eMMC DLL setting for amenia board, after that system can
boot up with eMMC successfully.
BUG=chrome-os-partner:51844
TEST=Boot up with eMMC
Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/16237
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
DCACHE_RAM_SIZE_TOTAL is set to 0x40000 and is being used to
set up CAR. Whereas DCACHE_RAM_SIZE which is set to 0x10000
is used to calculate the _car_region_end in car.ld. If the FSP CAR
requirement is greater than or even close to DCACHE_RAM_SIZE then,
the CAR region for FSP will be determined to be below the overall
CAR region boundary i.e, out of CAR memory range.
This is working with FSP 1.1 because we provide the FspCarSize
and FspCarBase explicitly in a UPD. Hence, FSP is still able to
use the upper region of CAR memory for its purpose.
However, it will be a problem in case of FSP2.0 where FSP usable CAR
is calculated using _car_region_end.
So, Remove the the use of DCACHE_RAM_SIZE_TOTAL and set
DCACHE_RAM_SIZE to correct value i.e, 0x40000(256KB)
Change-Id: Ie2cb8bb0705a37edb3414850d7659f8a3dd6958b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16236
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
There is a lot of code that is being referred to in bootblock but
resides under skylake/romstage folder. Hence move this code
into skylake/bootblock, and update the relevant header files
and Makefiles.
TEST=Build and Boot kunimitsu.
Change-Id: If94e16fe54ccb7ced9c6b480a661609bdd2dfa41
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/16225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Prepare Skylake for FSP2.0 support.
We do not use FSP-T in FSP2.0 driver, hence guard the
FspTempRamInit call under a switch.
In addition to the current early PCH configuration
program few more register, so all in all we do the following,
* Program and enable ACPI Base.
* Program and enable PWRM Base.
* Program TCO Base.
* Program Interrupt configuration registers.
* Program LPC IO decode range.
* Program SMBUS Base address and enable it.
* Enable upper 128 bytes of CMOS.
And split the above programming into into smaller functions.
Also, as part of bootblock_pch_early_init we enable decoding
for HPET range. This is needed for FspMemoryInit to store and
retrieve a global data pointer.
And also move P2SB related definitions to a new header file.
TEST=Build and boot Kunimitsu
Change-Id: Ia201e03b745836ebb43b8d7cfc77550105c71d16
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/16113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Almost all boards and chipsets within the codebase assume or
use SPI flash as the boot device. Therefore, provide an option
for the boards/chipsets which don't currently support SPI flash
as the boot device. The default is to assume SPI flash is the
boot device unless otherwise instructed. This falls in line
with the current assumptions, but it also allows one to
differentiate a platform desiring SPI flash support while it not
being the actual boot device.
One thing to note is that while google/daisy does boot with SPI
flash part no SPI API interfaces were ever implemented. Therefore,
mark that board as not having a SPI boot device.
BUG=chrome-os-partner:56151
Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16191
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
pmc_gpe_route_to_gpio returns -1 on error. However, the value was being
stored in unsigned int and compared against -1. Fix this by using local
variable ret.
Change-Id: I5ec824949d4ee0fbdbb2ffdc9fc9d4762455b27b
Reported-by: Coverity ID 1357443, 1357442, 1357441
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16218
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We're changing the PWM regulator bounds on Kevin from rev6 onwards, so
we'll need to use different duty cycle values for them. We really want a
proper PWM regulator driver that can calculate these values
automatically from voltages, but until we have that this patch just
hardcodes the new numbers in.
(Yes, this is a patch for the mainboard/google/gru board family that only
touches a file from the rockchip/rk3399 SoC. That too is something
that'll be fixed up in a later CL.)
BRANCH=None
BUG=chrome-os-partner:54888
TEST=Booted Kevin rev4 (for whatever that's worth...).
Change-Id: Ibb6ab5c6517d83ffb5e32cb17d0de33e8ec10293
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 4cb2a939295e2b6443c5dbd3374982224322304b
Original-Change-Id: I8757cc54f2478d20bb948a1a0a7398b0404a7b1f
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/368410
Original-Commit-Ready: Dan Shi <dshi@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/16235
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Program MCHBAR, DMIBAR, EPBAR, EDRAMBAR and GDXCBAR.
Also program the PAM registers. The system agent was being
programmed in romstage during pre-console initialization, after
moving to C_ENVIRONMENT bootblock this was missing, restoring
the same.
TEST=Build and Boot Kunimitsu
Change-Id: Iaf310cfb83e58eb8d5affb481dfc343f5d45961b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16224
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector
code) the reboot counter stored in `reboot_bits` isn't reset on a reboot
with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR
enabled, later stages (e.g. payload, OS) have to clear the counter too,
when they want to switch to normal boot. So change the bits to (h)ex
instead of (r)eserved.
To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also
remove all occurences of the obsolete `last_boot` bit that have sneaked
in again since 24391321 (mainboard: Remove last_boot NVRAM option).
Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/16157
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS.
Change the code guard for do_printk_va_list() accordingly, since it's
used by vboot (not Chrome OS) code.
Change-Id: I44e868d2fd8e1368eeda2f10a35d0a2bd7259759
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16230
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CONFIG_VBOOT was recently moved to be independent from CONFIG_CHROMEOS.
However, the latter still has some 'select' clauses to ensure that
required TPM libraries are built. The TPM is an essential part of vboot,
and without these libraries the vboot code cannot compile... therefore,
they should be moved under CONFIG_VBOOT.
Change-Id: I0145558e5127c65c6a82d62f25b5a39e24cb8726
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16229
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk
for emmc")
Enabling this clock in coreboot is no longer needed as it's handled
in the kernel driver now.
BUG=chrome-os-partner:52873
TEST=boot from usb/sdcard and check there is /dev/mmcblk0
BRANCH=none
Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0
Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13
Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/367421
Original-Commit-Ready: Brian Norris <briannorris@chromium.org>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/16152
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This is a temporary work-around since the current threshold of 70 on
TSR2 results in thermal trip and shutdown while the kernel is
booting. Changing this threshold to 100 allows kernel to boot up to
userspace. Following values were read:
$ cat /sys/class/thermal/thermal_zone4/temp
81800
$ cat /sys/class/thermal/thermal_zone4/type
TSR2
BUG=chrome-os-partner:56155
BRANCH=None
TEST=Boots to OS.
Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16156
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This reverts commit a83bbf5854.
This was submitted out of order.
Change-Id: Ic5a28faf94c1f1901a72e46343722eb4224c5086
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16226
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of assuming all region_devices have an mmap() and munmap()
implementation fail those calls when one isn't provided.
BUG=chrome-os-partner:56151
Change-Id: I9b03e084aa604d52d6b5bab47c0bf99d9fbcd422
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16190
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The SPI host controller for the SPI boot device doesn't allow
normal probing because it uses the hardware sequencer all
the time. Therefore, it's pointless to include unnecessary
SPI flash drivers.
BUG=chrome-os-partner:56151
Change-Id: Ifcc6492b4bccf7d01b121d908976c9087d12deb0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16189
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
The SPI host controller for the SPI boot device doesn't allow
normal probing because it uses the hardware sequencer all
the time. Therefore, it's pointless to include unnecessary
SPI flash drivers.
BUG=chrome-os-partner:56151
Change-Id: I04551fdb0b207c7ec2f1f171cff62ed7334a5ad5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16188
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
All flash drivers are automatically included in the build unless
COMMON_CBFS_SPI_WRAPPER was selected. However, there are cases
where these drivers are unnecessary such as certain intel platforms
where spi controller uses hardware sequencing without any ability
to manually probe the device. Therefore, provide an option that the
SoC can set the default value for. The COMMON_CBFS_SPI_WRAPPER
option is still honored by not including all drivers when that
is selected.
BUG=chrome-os-partner:56151
Change-Id: Ie9aa447da450f7c8717545f05cff800139a9e2dd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16187
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This option is no longer used in the code base. Remove it.
BUG=chrome-os-partner:56151
Change-Id: Ia73cce7546c9839518c9e931b03c50856abc2018
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16186
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make the indication of the boot device being memory mapped
separate from SPI. However, retain the same defaults that
previously existed.
BUG=chrome-os-partner:56151
Change-Id: Ibdd7c8754f9bf560a878136b1f55238e2c2549d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16193
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the
code. Remove its usage.
BUG=chrome-os-partner:56151
Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16185
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Having an assignment in assert does not make sense. This seems like it
was intended to check if chip is always same as segments->chip.
Change-Id: I297d9e76a0404a1f510d43f8b9c39e96b557689f
Reported-by: Coverity ID 1357439
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/16219
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Provide more informative messages when CONFIG_ELOG_DEBUG is enabled
as well as more informative error messages in the case of
elog_scan_flash() failing. In the sync path the in-memory buffer is
dumped in before the contents are read back from the non-volatile
backing store and dumped again if the subsequent parsing fails.
BUG=chrome-os-partner:55932
Change-Id: I716adfb246ef6fbefc0de89cd94b3c1310468896
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
