All supported x86 chips select HAVE_CF9_RESET, and also use 0xcf9 as
reset register in FADT. How unsurprising. We might as well use that
information to automatically fill in the FADT accordingly. So, do it.
To avoid having x86-specific code under arch-agnostic `acpi/`, create a
new optional `arch_fill_fadt` function, and override it for x86 systems.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ib436b04aafd66c3ddfa205b870c1e95afb3e846d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
They are ignored if the ACPI_FADT_WBINVD flag is set, which is required
on current ACPI versions and only maintained for ACPI 1.0 compatibility.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Ief1219542ba71d18153b64180e0ff60bd1e7687b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Looks like some preparation is needed before reset. However, Picasso
also needs some special handling and still selects this option without
selecting HAVE_CF9_RESET_PREPARE. So, just add HAVE_CF9_RESET for now.
Change-Id: I0c6da9a43a28dbee916fd6bda9ae380ebd619edf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43388
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead, just flip the desired bits using bitwise operations. As this is
initially zero, the resulting value is the same. This allows flags to be
set from anywhere regardless of execution order.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Icfd580a20524936cd0adac574331b09fb2aea925
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43387
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Both `acpi_fill_fadt` and `soc_fill_fadt` set many FADT fields. Since
the latter runs later, the values programmed in it overwrite any other
values. Drop unused assignments and consolidate everything in a single
function. Use `acpi_fill_fadt` as it is mandatory (no weak definition).
Change-Id: Ia8248f20dae2b93426f309605bb2076592b08df4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43386
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to Intel Order Number 290562 (PIIX4 datasheet), 0xcf9 is the
reset register, and setting bits 1 and 2 will result in a hard reset.
Change-Id: Id5ada6a10b2269d51908c6a5fd7745ef6c33a29a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to Intel Document 290744 (ICH4 datasheet), 0xcf9 is the reset
register, and setting bits 1 and 2 will result in a hard reset.
Change-Id: Id1a532857d9643d222d61c3902faadd471ae2a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The PM2_CNT register block is not present on this southbridge, as per
Intel Document 290744 (ICH4 datasheet). Also, the ACPI specification,
version 6.3, section 4.8.1.3 (PM2 Control Register), says:
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Also delete a comment about `pm2_cnt_len`, which said that the right
value differs from zero. Looks like that comment was wrong instead.
Change-Id: Icbb32f5db7b368c764b3477c40f8ae9c788df5ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43383
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PM2_CNT register block is not present on this southbridge, according
to comments on the code. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Change-Id: Ib3ff0fd9e0725f61c38e60ba56b95e6e77b0b1ed
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43382
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PM2_CNT register block is no longer needed, as explained in some
comments. While they may have been copy-pasted around a lot, they are at
least true for Hudson, and it makes sense to assume that they are true
for newer chipsets as well. As per the ACPI specification, version 6.3,
section 4.8.1.3 (PM2 Control Register):
This register block is optional, if not supported its block pointer and
length contain a value of zero.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything to indicate PM2_CNT is not supported. So, drop unneeded values.
Change-Id: Iabc7985c84aabe40ad98fdc9fc6ccbbab0a516c1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43381
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has PM1b_EVT nor PM1b_CNT event
register blocks. According to the ACPI specification, version 6.3,
sections 4.8.1.1 and 4.8.1.2 (PM1 Event/Control Registers):
If the PM1b_EVT_BLK is not supported, its pointer contains a value of
zero in the FADT.
If the PM1b_CNT_BLK is not supported, its pointer contains a value of
zero in the FADT.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with PM1b for now. So, drop unneeded writes to PM1b fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iff788b2ff17ba190a8dd9b0b540f1ef059a1a0ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43380
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
None of the currently-supported chips has a GPE1 block. The ACPI spec,
version 6.3, section 4.8.1.6 (General-Purpose Event Registers) says:
If a generic register block is not supported then its respective
block pointer and block length values in the FADT table contain zeros.
Since the FADT struct defaults to zero in coreboot, we don't need to do
anything with GPE1 for now. So, drop the unneeded writes to GPE1 fields.
Tested on Asus P8Z77-V LX2 with Linux 5.7.6 and Windows 10 at the end of
the patch train, both operating systems are able to boot successfully.
Change-Id: Iefc4bbc6e16fac12e0a9324d5a50b20aad59a6cd
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43379
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2.
BRANCH=none
BUG=b:150515720
TEST=build and check the USB3 gen2 register on DUT is correct.
Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Add configs for USB 3.1 Gen2 EV settings so that people can set the
EV settings per board in device tree.
BUG=b:150515720
BRANCH=none
TEST=build coreboot and fsp with enabled fw_debug.
Flashed to puff and checked the log.
All usb configs were set correctly.
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: Id4860665619095139c329565d433d9eb495cac02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39448
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that libgfxinit has been fixed, trying to enable the Analog port no
longer hangs the system, nor fills the monitor with unreadable garbage.
Tested with linear framebuffer, displays correctly on a 1920x1080 VGA
monitor. Scaling also works when a smaller HDMI monitor is connected as
well. Legacy VGA text mode is also functional on either monitor, too.
Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update FSP headers for Tiger Lake platform generated based FSP
version 3274.
Compared to the current version 3197, v3274 adds most of the legacy UPDs
in both FSPM and FSPS.
BUG=b:159151231
BRANCH=none
TEST=build and boot volteer proto2
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Id3f957aa9d9ad9710a3c930717c22f485699315e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43473
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If CONSOLE_SERIAL is not set, do not reconfigure the UART LDN.
Otherwise, SerialICE stops working when the UART LDN is disabled.
Change-Id: Ie3113e6b7b830dfdddc4d7709f00719f29e094bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
GTSH was 2 instead of 20 (so it's 2 degrees K hysteresis), and TSRD was
accidentally defined to take 0 arguments, instead of 1.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I14d28bacf44ac65043060b8579b3fbcec758c56c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43532
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The DPTF._OSC method incorrectly assumed that all available UUIDs would
be present in the IDSP package, but this is not always the case. Instead
of matching an incoming UUID against an index into IDSP, search the IDSP
package for the matching UUID.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I718b6abe09152647b14f7c1405b2d0d20035726b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Since there is now a mechanism to generate DPTF ACPI tables and methods
at runtime, dedede should switch to using that instead of raw ASL files.
This patch converts the existing .asl files into devicetree entries.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The previous DPTF patch train missed the proper scope operator around
all of the TSR options. Without this, the optional GTSH and/or _STR
Methods end up in the wrong scope.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I9298c442c047c5f7f606574d900057a7c004b47f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43458
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In the initial DPTF refactor, the scope of the TCPU device was
incorrectly set as \_SB, instead of \_SB.PCI0. However, because of the
way that the acpi_inject_dsdt() callback currently works (it injects
contents before the dsdt.aml file), the Scope where the TCPU
device lives (\_SB.PCI0) doesn't exist yet. Therefore, to avoid playing
games with *when* things are defined in the DSDT, switch to defining all
of the DPTF devices in the SSDT.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia4922b4dc6544d79d44d39e6ad18c6ab9fee0fd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43529
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While the DPTF refactor was in progress, TSR3 was added to volteer's
dptf.asl file, and I forgot to update the devicetree with TSR3 as well.
Also missed a swap in the passive policies of TSR0 and TSR1. This patch
fixes those.
BUG=b:149722146
TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Vilboz requires a different HID than rest of the zork variants. Hence,
this change sets the HID to AMDI1015 for I2S machine device in vilboz
overridetree.cb.
BUG=b:157708581
Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2S machine device has its own driver now. So, this change drops the
support for adding I2S machine device ACPI node from ACP driver.
BUG=b:157708581
Change-Id: I9069d92ae991e05fddcc7d45a2fd21e98c3b0de8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change switches zork devices to use the newly added
i2s_machine_dev driver in devicetree rather than passing
dmic_select_gpio in SoC config.
BUG=b:157708581
Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a new driver for AMD I2S machine device. Currently,
this device is added as part of `acp_fill_ssdt()` in Picasso, but with
addition of this driver, this device can be added just like any other
device in the devicetree.
BUG=b:157708581
Change-Id: I49d1a867d7941397acca1054632b6ad855a021de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change increases the maximum length of device path string to 40
characters to accommodate growing hierarchy of devices.
TEST=Ensured that "\_SB.PCI0.LPCB.EC0.CREC.TUN0.RT58" is correctly
added to SSDT.
Change-Id: Id2ef71a32b26e366b56c652942a247de4889544a
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This board uses the in-PCH GbE controller, and its IFD has a GbE region.
Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a macro `PAD_NC` for configuring no-connect pads. This
configures the pad as input with pull-down.
Change-Id: I47c41c88ccfebe2c5dd9a24f85a120af9c8f56b5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change drops mainboard.asl from zork because none of the objects
defined in it are used.
Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops mainboard.asl from zork because none of the objects
defined in it are used.
BUG=b:153879530
Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops _INI and OSFL methods under \_SB since they are not doing
anything useful. _INI only calls OSFL and OSFL initializes OSVR if not
already initialized and returns OSVR value. However, OSVR is not used
anywhere and hence both these functions can be dropped.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4f3e1c93a855006cc115087fded20bfb76c1133e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43515
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Global variable `PMOD` that stores the interrupt mode used by OS is
required by all mainboards. This change moves the variable definition to
globalnvs.asl under picasso.
Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC
until _PIC() method is called by OS. Thus, this change also updates the
default value of PMOD as 0 i.e. PIC mode.
BUG=b:153879530
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I731c03d965882281a7a23f55894451210ba72274
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_9 is associated with gevent 22. Correct all the misconfigurations
and use macros for clarity as to what bit offset is being used instead
of open coding things.
BUG=b:161205804
Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change uses read-modify-write to update ACP_I2S_PIN_CONFIG instead of
a write operation since the other bits in the register are reserved.
Change-Id: Ic64e1907858ec293c5f759e627d19c00d748a30e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43503
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support for configuring ACP_PME_EN and ACP_I2S_WAKE_EN
using the mainboard setting for `acp_pme_enable` and `acp_i2s_wake_enable`
in the devicetree. This is required to get I2S_Wake event on headset jack
plug/unplug when using CODEC_GPI pad.
BUG=b:146317284,b:161328042
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Change-Id: I522d7497940f499fbc3181d866f2b44e979bba7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/1969104
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43495
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 56da63c3dc removed overriding that
field in the FADT.
Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Dali supports two SATA ports, but no PCIe alternate function on those
pins.
Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The DXIO descriptors use the logical and not the physical lane numbers,
which are different.
Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently, the code and data in psp_verstage is ~59K. Adding the code
to save vbnv to the SPI rom increases that to 66K.
Getting rid of VERSTAGE_SIZE allows verstage to grow as it needs to.
BUG=b:161366241
TEST=Build & Boot Morphius with VBOOT_VBNV_CMOS_BACKUP_TO_FLASH enabled
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic6853b70073f9e781fc10402a2a47c9c8e0d49d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43486
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
mainboard_romstage_entry_s3() was dropped from zork (CB:43476). This
function call in picasso does not do anything and hence is being dropped.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I10e15422d7eef5af9c19737c32e433718b6479d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43477
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe
GPIOs can be configured early on in bootblock rather than waiting until
romstage. This change moves the call to variant_pcie_gpio_configure() to
happen in bootblock and drops romstage.c file.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in
romstage. This change moves the configuration of PCIe related GPIOs to
variant_pcie_gpio_configure() to keep all the configuration for WiFi and
non-WiFi PCIe pads in one place. It also drops the function
variant_romstage_gpio_table() as it is unused.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the power and reset GPIO configuration for non-PCIe devices is
dropped from romstage GPIO table, the tables for pre-v3 and v3 version of
schematics are exactly same. So, this change drops the duplicate table and
also removes the check for v3 schematics when configuring the pads in
romstage.
BUG=b:154351731
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change keeps pen power enabled in sleep state to allow it to
charge in S3.
BUG=b:155422911
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I6190496653878327f34a01f6a743db474d32e929
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit a5ca4a0c75.
Reason for revert: Breaks coreboot tree because of non existent kconfig symbol
Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Currently the common soc code automatically selects
POWER_STATE_DEFAULT_ON_AFTER_FAILURE which making other mainboard
options unselectable.
However, there're some cases that power state should change to different
states after reapplying power.
Make POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y but do not select it
in soc code so that we can disable it and select other options in the
mainboard code.
Tested on OCP Delta Lake.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: Ifa853d81ee9477d2440ceaa67b2bd6b863ee52c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Implement sending POST start/end command to BMC.
TEST=Read POST command log in OpenBMC,
if command received successfully, message may show as below,
root@bmc-oob:~# cat /var/log/messages |grep -i "POST"
2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST Start Event for Payload#1
2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2:
ipmid: POST End Event for Payload#1
root@bmc-oob:~#
Signed-off-by: TimChu <Tim.Chu@quantatw.com>
Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed
are expected.
Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1
Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
This pin has been removed from recent revisions (or at least moved to a
pin that's not controlled like a normal GPIO). It has also never been
used on older ones (I think?). The same GPIO is now used as a SKU ID
pin, so make sure we're not incorrectly configuring it as an output
(although sku_id() overrides that later anyway, but it's still
incorrect).
BUG=b:160754995
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This information is redundant since it's already specified in
baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb
domain 0 is still required because sconfig uses it as an identity anchor
to match devicetree and overridetree.
BUG=b:157580724
TEST=Boot zork, usb functional
Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the AP actually needs to write to the TPM, then it is important and
the TPM should commit those changes to NVMEM immediately in case there
is an unexpected power loss (e.g. from a USB-C port partner reset upon
cold reboot request).
BRANCH=none
BUG=b:160913048
TEST=Verify that puff will no longer reboot loop when coreboot writes a
new Hmir (Hash mirror) in the TPM
Change-Id: I9597a55891d11bdf040d70f38b4c5a59c7888b8a
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SataPortsEnableDitoConfig Enable DEVSLP Idle Timeout settings DmVal and
DitoVal. SataPortsDmVal and SataPortsDitoVal helps to determine when to
enter Device Sleep. Device Sleep enables the host bus adapter (HBA) to
assert the DEVSLP signal as soon as there are no commands outstanding
to the device and the port specific Device Sleep idle timer has expired.
Device Sleep Idle Timeout values (PxDEVSLP.DITO and PxDEVSLP.DM) are
port specific timeout values used by the HBA for determining when to
assert the DEVSLP signal. They provides a mechanism for the HBA to apply
a programmable amount of hysteresis so as to prevent the HBA from
asserting the DEVSLP signal too quickly which may result in undesirable
latencies. This patch is created based on Intel Tiger Lake Processor
PCH Datasheet with Document number:575857 and Chapter number:12.
* PxDEVSLP.DM -> SataPortsDmVal: Enable SATA Port DmVal DITO multiplier.
Default is 15.
* PxDEVSLP.DITO -> SataPortsDitoVal: Enable SATA Port DmVal DEVSLP Idle Timeout
(DITO), Default is 625ms.
BUG=b:151163106
BRANCH=None
TEST=Build and boot volteer and TGL RVP.
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Change-Id: I6a824524738a9e0609f54bea9d892b4a42a1d3db
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42214
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
0xc50, 0xc52, 0xc6f don't exist on Picasso. The PCI config space
registers define SATA and OHCI which are at the wrong bus locations.
I just remove the whole section since it's not used. We never access the
PCIe Error region, or the PM2 region either.
BUG=b:153001807, b:154756391
TEST=Build Trembyle
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98aee09770f1df9f553c94580c1ee00c06a9cec1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no reason to create a named variable. We can just return the
package.
BUG=b:153001807, b:154756391
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This PCI ID is required in order for JSL devices to perform SSDT
generation for DPTF.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I42209d15bc4f1654814465ce1412576f7349dddc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43421
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The ACPI specification, version 2.0 says:
_BFS is an optional control method.
So, remove them. They have been copy-pasted around quite a bit, and do
not do anything useful. Plus, it's deprecated in later ACPI versions.
Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turning the DXIO and DDI descriptor fields in the FSP_S_CONFIG struct
into arrays allows to properly iterate over the fields.
BUG=b:158695393
TEST=Mandolin still boots.
Change-Id: I85debe4d52399e933768b89b665ff10c9f7779f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43434
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Forgetting to add the #pragma pack() at the end of the header file can
lead to hard to debug breakage, so get rid of the #pragma pack usage and
add a __packed to the structs that need to be packed which has less
possibly unwanted side effects.
Since commit d44221f9c8 coreboot always
includes commonlib/compiler.h which provides __packed.
TEST=Timeless build results in identical binary.
Change-Id: Icc53168f4fbc3a63a859f686b18e7023d225f8d2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drop it before it grows moss.
Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Morphius cannot support 100Mhz fast SPI causing it to not boot.
Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe.
BUG=b:161233767
TEST=Boot morphius
Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I2fd2ec5a3029dc1bd1fa65dc3d1af5505f1f1dad
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Intel southbridges do this. Also make `acpi_sci_irq` non-static as it is
needed outside acpi.c with this change.
Change-Id: I702988493e3b29d807a75c70485baaa2ff6d1aa2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Add USB ports, USB user-facing camera and USB bluetooth to devicetree.
USB ports 4 and 5 are duplicated for picasso and dali.
BUG=b:158096224
TEST=Boot Trembyle and Dalboz, Dump acpi tables
Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split zork baseboard devicetree between dalboz and trembyle.
The devicetree is simply duplicated, no other changes in this commit.
BUG=b:158096224
TEST=Build coreboot for zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Screen flickered on VT2 on some devices after idle a period of time.
Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking
issue disappeared, and didn't affect acoustic noise much.
Because CB:38212 (commit eae254e) caused this issue.
BUG=b:160754994
TEST=build dratini, observe that screen flick issue disapppered
Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SaGv needs to be enabled for only QS. On ES2, we are seeing system
instability.
BUG=b:159198381
TEST=Tested for boot. Power and performance tests were run with
volteer2 with qs setup. System showed stability.
Tested for boot stability on on delbin.
Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Configure volteer2 and delbin, the two variants currently using
preQS or QS silicon, to use CSE Lite.
BUG=b:158140797
TEST=cd to volteer's asset_generation folder, execute
"./gen_all_variant_images.sh" and verify that all variant
images are produced.
Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Extract DRAM info from AMD_FSP_DMI_HOB and store it as mem_info in
cbmem with id CBMEM_ID_MEMINFO. Subsquently extract mem_info objects
from cbmem to build SMBIOS type 17 tables.
BUG=b:148277751,b:160947978
TEST=dmidecode -t 17
BRANCH=none
Change-Id: Iacedbb017d19516674070f89ba0aa217f55383e3
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi
power enable") added helper functions for determining if a board uses
v3 schematics. However, it introduced a regression by adding a wrong
check for variant_uses_v3_schematics() in variant_audio_update(). This
change fixes the check to ensure that dmic_gpio is updated when
variant is not using v3 schematics.
BUG=b:161141258,b:161128964
TEST=Verified on trembyle that trackpad works again (it was broken
because of the regression).
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the woomax variant of the zork reference board by copying
the template(coreboot-zork/util/mainboard/google/trembyle)
files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.1).
BUG=b:158343602
BRANCH=None
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2.
“1-2-2" means command, address and data are transmitted
through 1 wire, 2 wire and 2 wire, respectively.
BUG=b:160603142
TEST=Boot on trembyle, verify register settings.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As with other macros, convert PAD_CFG0_ROUTE_* to PAD_IRQ_ROUTE() to
make the code in gpio_defs.h cleaner.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: Iadc9c4b3c96ae04c56d060cb060737a8eba7f165
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41034
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_RX_POL_* macros to PAD_RX_POL() to make the code
cleaner and reduce the length of the macro.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 on T10-TNI carrierboard
does not change.
Change-Id: I09a048fd38ccb994f53c8829c549bc2b368fa546
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41033
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts PAD_CFG0_TRIG_ * macros to PAD_TRIG() to make the code cleaner
and reduce the length of the macro, which is often used.
Tested with BUILD_TIMELESS=1, Kontron COMe-mAL10 & T10-TNI carrierboard
does not change.
Change-Id: I9e1b4118fd6c6f0d58ee38a743aa8c27535f0dd9
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41032
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds SMI handler for SCI, S3/S5 wake up and LID closed
events on tglrvp platform.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change allows EC to change state of host-controlled USB MUX.
TEST=Built image and booted to kernel.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia7c331157b1b4039e42c373f5b130a66f7594458
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42955
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set default of PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE to n as this breaks
booting Windows with a PCIE NVIDIA.
Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Current the common soc code automatically selects PCIEXP_CLK_PM and
PCIEXP_L1_SUB_STATE which breaks booting Windows with a PCIE NVIDIA
graphics card attached on mainboards that do not have a CLKREQ# signal.
This is commonly used on server and workstations boards where the
additional power savings of L1 substate are not required.
Make the PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE default y but do not
select it anymore by the soc code, thus we can disable it in the
mainboard code.
Tested on CFL with Windows 10.
Change-Id: I025e13d6d8183256647e4c034e31bafa235f7eb7
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41696
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For variants with slightly different GPIO configuration, add support to
pass an override GPIO configuration table.
BUG=None
TEST=Build and boot the waddledee mainboard.
Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Delta Lake uses GPIO pin GPP_B20 for POST complete event,
BIOS needs to pull this pin low for BIC (Bridge IC) to start
reading sensors.
Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm
the pin is low.
Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Share "EC in RW" GPIO with depthcharge. Also we define the CONFIGS
needed CHROME, CHROME_EC and use the chrome lid and recovery.
BUG=None
BRANCH=None
TEST=Build and boot TGL RVP. Check recovery works with
crossystem recovery_request.
Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Platform HOBs (in particular IIO_UDS and MemoryMap HOBs) are of HOB type
HOB_TYPE_GUID_EXTENSION, therefore they do not have resource structure.
Remove the erroneous code related to resource structure.
Remove unnecessary function prototypes from header files, and define them
as static in hob_display.c.
Since we have the HOB pointer, there is not need to search HOB by GUID.
Remove unnecessary calling of fsp_find_extension_hob_by_guid().
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Change-Id: Ib99bce39e6eb2aeb95242dfba36774653bbe91fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43335
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Provide the data structures for parsing SPD information
supplied by FSP.
BUG=b:160947978
Change-Id: If847646625448547599018a823712d5c14e4bd76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43350
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not.
With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and
would be set to enabled if both places cannot find it.
Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable
and verified the results are expected.
Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: insomniac <insomniac@slackware.it>
CPX-SP FSP ww28 release adds UPDs to allow enablement of VT-d and VMX.
Also update IIO UDS HOB definition file accordingly.
Intel CPX-SP FSP has been using FSPM_CONFIG intead of FSP_M_CONFIG.
Other Intel FSPs have been using FSP_M_CONFIG. The feedback from Intel
is that they will converge to use FSPM_CONFIG over time. So both will
co-exist for some time. Today coreboot common code expects FSP_M_CONFIG.
Accomodate this situation in FspmUpd.h.
The CPX-SP soc code is updated accordingly.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: If6d0a041eaad9eb2f811e74d219fff1cc38e95a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43315
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
On ChromeOS systems with a serial-enabled BIOS and vboot writing a new
firmware image to the Chrome EC, it was possible for the TCO watchdog
timer to trip 2 times before tco_configure() was called in romstage.
This caused an extra reboot of the system (at a rather inopportune time)
and because the EC didn't perform a full reset, the system boots into
recovery mode.
This patch moves the call to tco_configure() for Tiger Lake from
romstage to bootblock, in order to make sure the TCO watchdog timer is
halted before vboot_sync_ec() runs in romstage. It should be harmless to
configure the TCO device earlier in the boot flow.
BUG=b:160272400
TEST=boot Volteer (to a non-recovery kernel!) with a freshly imaged EC
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Iefdc2c861ab8b5fde7f736c04149be7de7b3ae0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43313
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IRQ 10 and IRQ 11 are valid for all southbridges using this code, as per
their respective datasheets. So, add them for the sake of completeness.
Change-Id: Ib4504861ed316a95b9735e0ed79f108f18071b3b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43158
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ida12426c51313a7642b5c363e58a79d77b1b096b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I65fedfa7e8b2fbb72b3109a8790445e38909976a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I8280d29b9a7bc835c2cb7e3e3dfca70768672a5f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Enable CpuReplacementCheck for TGLRVP with a CPU socket.
Test=build and verified with tglrvp
Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
This adds Type-C Intel Input Output Manager(IOM) device with HID
INTC1072. It provides MMIO range from 0xfbc10000 with size 0x1600.
Intel Input Output Manager(IOM) kernel driver reads relevant
information such as Type-C port status (whether a device is connected
to a Type-C port or not) and the activity type on the Type-C ports
(such as USB, Display Port, Thunderbolt) using this memory resource.
BUG=b:156016218
TEST=Able to detect USB, TBT and USB4 on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ic733e831643bda6e052edf797ba0e6206eb4ddd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41762
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This adds Type-C IO Manageability engine base address and size.
Tigerlake EDS(#575681) section 3.4.3 describes host bridge
REGBAR(MCHBAR) + 7110h for IOM REGBAR with size 1600h. IOM has a
port ID 0xc1. MCHBAR is programmed with 0xfedc0000. IOM REGBAR is
determined from mmio (MCHBAR + 0x7110), which has value 0xfb000000.
IOM has base address 0xfbc10000 from IOM REGBAR + (0xc1 << 16).
BUG=🅱️156016218
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I70d88ba318087f7acacd1ee84609c9db5b65f907
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41759
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add new IGD device ID for new Tigerlake SKU support.
BUG=b:160394260
Branch=None
TEST=build, boot and check IGD device is reported.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I1903d513b61655d0e939f80b0fd0108091fdd7e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43163
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
We only want to return an ACPI name for a USB port if the controller
physically has the port. This has the desired side effect of making the
usb_acpi driver skip generating an ACPI node for a device which has
no port. This prevents writing an invalid SSDT table which the OS then
complains about.
BUG=b:154756391, b:158096224
TEST=Boot picasso trembyle and verify HS05, HS06 and SS05 are no longer
generated. Also checked the logs and saw the devices being ignored.
\_SB.PCI0.LPCB.EC0.CREC.TUN0: Cros EC I2C Tunnel at GENERIC: 0.0
\_SB.PCI0.LPCB.EC0.CREC.MSTH: Cros EC I2C Tunnel at GENERIC: 1.0
\_SB.PCI0.LPCB.EC0.CREC.ECA0: Cros EC audio codec at GENERIC: 0.0
\_SB.PCI0.PBRA.XHC0.RHUB.HS01: Left Type-C Port at USB2 port 0
\_SB.PCI0.PBRA.XHC0.RHUB.HS02: Left Type-A Port at USB2 port 1
\_SB.PCI0.PBRA.XHC0.RHUB.HS03: Right Type-A Port at USB2 port 2
\_SB.PCI0.PBRA.XHC0.RHUB.HS04: Right Type-C Port at USB2 port 3
xhci_acpi_name: USB2 port 4 does not exist on xHC PCI: 03:00.3
xhci_acpi_name: USB2 port 5 does not exist on xHC PCI: 03:00.3
\_SB.PCI0.PBRA.XHC0.RHUB.SS01: Left Type-C Port at USB3 port 0
\_SB.PCI0.PBRA.XHC0.RHUB.SS02: Left Type-A Port at USB3 port 1
\_SB.PCI0.PBRA.XHC0.RHUB.SS03: Right Type-A Port at USB3 port 2
\_SB.PCI0.PBRA.XHC0.RHUB.SS04: Right Type-C Port at USB3 port 3
xhci_acpi_name: USB3 port 4 does not exist on xHC PCI: 03:00.3
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia645380bea74f39fd94e2f9cbca3fcd4d18a878e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is some boilerplate required to iterate over the USB supported
protocol structs. Encapsulate all the in a method to make the callers
simpler.
BUG=b:154756391
TEST=Built test trembyle.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I401f10d242638b0000ba697573856d765333dca0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43352
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no generic way to tell whether a mainboard has an EC or not.
Making Kconfig symbols for these options seems overkill, too. So, just
put them on the devicetree. Also, drop unnecessary assignments when the
board's current value is zero, as the struct defaults to zero already.
Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC
to enable it as well. No one can ever forget to set this option anymore!
Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
And use it instead of directly writing to the MRC struct.
Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Check the PCH's LPC device ID to know the system type instead of relying
on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe.
Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Current code only cares whether the PCH is LP or not. However, MRC wants
to differentiate between desktop and non-LP mobile platforms as well. As
the PCH is soldered onto the mainboard, add a facility to retrieve which
platform coreboot is running on by checking the PCH's LPC device ID. The
only user of the `pch_silicon_type` function is the `pch_is_lp` function
so replace the former with the new `get_pch_platform_type` function. The
function needs to be defined in both romstage and ramstage where PCI ops
have different signatures, hence the two copies.
Change-Id: Ib6276e0069eaa069a365faf6ae02dd934307d36c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43123
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This Kconfig symbol allows doubling the memory's refresh rate, assuming
that the MRC actually cares about it. It is disabled by default except
on the mainboards which explicitly enabled this setting in `pei_data`.
Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Several of these includes are no longer necessary. Get rid of them.
Since "raminit.h" already includes "pei_data.h", we can omit including
the latter for brevity's sake.
Change-Id: Ia7e9dadf87114ca9ea4761b89909ea035cdfc38a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43121
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All mainboards have a non-zero SPD address to implemented DIMM slots.
Knowing this, it is possible to compute the MRC slot population masks
automatically instead of hardcoding the values on each mainboard.
Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These settings are the same on all boards. Since the other boards
currently overwrite the struct contents, it doesn't make a difference.
To ease review, the same settings will be dropped from other boards in
separate commits, one board at a time.
Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
This is what sandybridge does, and if done properly allows factoring out
common settings. Said refactoring will be handled in subsequent commits.
Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide,
so do not use 32-bit operations to program them.
Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so
using 32-bit operations on them is correct.
Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
It only contains a pointer to another struct. Flatten it.
Change-Id: Iab427592c332646e032a768719fc380c5794086b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of using function pointers, we can use weak functions. So, drop
the pointer from `romstage_params`, leaving `pei_data` as the only
remaining member. This will be cleaned up in a follow-up commit.
Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The current value of 0x1000 would overlap the first PCI bridge IO
window. As we commonly reserve IO range 0x0 .. 0x1000 for LPC and
integrated device use, change SMBUS_IO_BASE to 0x400. This is the
prevalent value among Intel southbridges, too.
Change-Id: I5c299f001f9012d6766b155a2f5def5cff6e88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43023
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to use ugly preprocessor here when regular C conditional
statements will work just fine.
Change-Id: I5abd445a335b43fb95e4df087d44e82c3f44349b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
We only need ACPI for the PS/2 devices. Plus, the NCT6776 ACPI code
makes Windows BSOD with STOP 0xA5 (ACPI_BIOS_ERROR), which is bad.
Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42430
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function is called at the end of `romstage_common`. Only one board
makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call
it after `romstage_common` has done nearly everything.
Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Code has evolved such that there seems to be little
use for global definition of cbmem_top_chipset().
Even for AMD we had three different implementations.
Change-Id: I44805aa49eab526b940e57bd51cd1d9ae0377b4b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43326
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of duplicated "if" statement in imdr_create_empty().
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: I80c074d09f222086092478f8fd3ac665235ebb31
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I5e33526a02872c14e9fa37a485d2f93dea8b088f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I4d0e678a8725c1fdf9263b9fae4e4fb6bb5ab4de
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43268
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icb98f3535f6c5f51081fc82262f6413f4b1a5733
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43261
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I2a244436adb8f41e4246aad7e3bfaf0986f2d832
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43260
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I14c575ac20cd94af1cfbb1204e2923149ef2920d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43259
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I2a97954a36e5af37dc3c379c39afa24030daceea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This provides the functionality to provide the GPE to the pci_xhci
driver.
BUG=b:154756391, b:160651028
TEST=Dump ACPI tables and verify GPE is set. Also dump SMI regs and
verify GPE is set. Resume using a USB keyboard.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ice7203831a1f65ed32f3a6392fe02c4b17d42617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is now a generic xhci driver we can use to generate the xHCI ACPI
nodes.
BUG=b:154756391
TEST=Boot trembyle and look at ACPI table
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3e9973dd416ccd51971f4d9410bed991eb7c3c41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41901
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can use xhci_for_each_ext_cap to inspect the xHC so we generate the
correct number of device nodes.
Scope (\_SB.PCI0.PBRA)
{
Device (XHC1)
{
Name (_ADR, 0x0000000000000004) // _ADR: Address
Method (_STA, 0, NotSerialized) // _STA: Status
{
Return (0x0F)
}
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x1F,
0x03
})
Device (RHUB)
{
Name (_ADR, Zero) // _ADR: Address
Device (HS01)
{
Name (_ADR, 0x01) // _ADR: Address
}
Device (HS02)
{
Name (_ADR, 0x02) // _ADR: Address
}
Device (SS01)
{
Name (_ADR, 0x03) // _ADR: Address
}
}
Name (_S0W, Zero) // _S0W: S0 Device Wake State
Name (_S3W, 0x04) // _S3W: S3 Device Wake State
Name (_S4W, 0x04) // _S4W: S4 Device Wake State
}
}
BUG=b:154756391
TEST=Boot trembyle and look at ACPI table. See all xHCI nodes.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44ebaef342e45923bc181ceebef882358d33f0d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI names can only be 4 characters long. Define a constant that defines
the size of the name + the NUL terminator.
BUG=b:154756391
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iad230c029f324005620ddad66c433ada26be78cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:160711124
TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage"
and verify that the build does not fail.
Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Data fabric devices are PCI devices which support PCI configuration
space but do not require any MMIO/IO resources. This change adds a PCI
driver for the data fabric devices which only provides device
operations for adding node to SSDT and returning the ACPI name for the
device.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I3da9287db5febf1a1d7eb1dfbed9f1348f80a588
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds a driver pcie_gpp.c which provides device_operations
for external and internal PCIe GPP bridges. These device operations
include standard PCI bridge operations as well as operations for
generating ACPI node for the device and returning appropriate ACPI
name for it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I9f8809c2735bdc09435deda91a570c89e71e8062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It's useful to see the stack when an exception happens so you can see
the variables on the stack, and also manually recreate the back trace.
If you need to recreate the back trace, you will need to add
-fno-omit-frame-pointer to the CFLAGS.
BUG=b:159081993
TEST=Caused an exception and saw the stack dumped. Then I manually
recreated the back trace.
0xcc6fff6c: 0xcc6ce02e <- 0xcc6ce02e is in dev_initialize
0xcc6fff68: 0xcc6fff88 <-- frame 1
0xcc6fff64: 0x00000005
0xcc6fff60: 0x000000dc
0xcc6fff5c: 0x00000000
0xcc6fff58: 0x00000200
0xcc6fff54: 0x00000000
0xcc6fff50: 0x00000400
0xcc6fff4c: 0xcc6d72d4 <- 0xcc6d72d4 is in setup_default_ebdad
0xcc6fff48: 0xcc6fff68 <-ebp
0xcc6fff44: 0x00000005
0xcc6fff40: 0xcc6f571c <-esp
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3822ea7aa23202ecc98612850402eeb4b1f7b5ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Zork devices shut down the i2c controllers in S3 to save power. On
resume, they need to be enabled in verstage before being accessed or
the system hangs.
BUG=b:160834101
TEST=Resume works with psp_verstage.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43334
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When entering S3, zork shuts down the i2c controllers to save power.
On resume, we need to re-enable i2c before accessing them, so we need
to map the AOAC registers in verstage.
BUG=b:160834101
TEST=psp_verstage works after resume.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia8aa4923898a50f2202b6ca8434cee61a5918e91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43333
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I3fc616eeb975aae7a5937f8b555ae554010d8dd3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icc3f9a4f71001547ef3d1efe6fc7551b5c690f92
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I18ddd8a4821d83c038f0a1d17f50247271566e42
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ic09b0ee6437766a3ddf126217540f25854a2a562
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43234
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9cc4fe7c643458c9d2fa124539a0fd21013ef451
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Sort them by stage execution order, then alphabetically. Place more
complex rules at the end.
Tested with BUILD_TIMELESS=1, Roda RK9 remains identical.
Change-Id: Ieadda7c264e0288a212b73febbe9f73351cc4de4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42649
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sort them by stage execution order, then alphabetically. Place more
complex rules at the end.
Tested with BUILD_TIMELESS=1, Intel DG43GT remains identical.
Change-Id: I1b36d6c0b2e615938272d65456cf10be54f66c38
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42648
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the diffstat between the two boards.
Change-Id: I6754d22139be52c66a9dda5d8e71f1092ecf0697
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43272
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I9311dd07b8259384badec65da649fa0cf2da1e01
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43267
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Nothing selects this driver. Drop it before it grows moss.
Change-Id: I7f06ea45f90d502053c52ea0b7cd7aa6d52295c0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43266
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Idc600d7a1ce1e47ea4c361caf2b32f1faa56e0f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43265
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I41a4f73df7fdd372ec7a80a41c8216c502054c39
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43262
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I9ceb37186e3622f2eac37393fa7ac5ced8efadf3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43258
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I27e4d66a1c8e2ed0eb5152f6bd56cc3fec2dea8e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michael Niewöhner
Nothing is selecting this driver. Drop it before it grows moss.
Change-Id: I9e2ba205154a9b37455c522721f5eb2ef9d76b40
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Iebd9080cd0e859dce5e6c5398429c38d1aa075dc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Iff5007256fedebd98082a575773d7de181b321ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I216f8459afc69ced98ea1859ee6b1f8e4d43bc4a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I379166c330d91c41846ba6562207fe5ad660040d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icb59d04c2a8f6ec3b0d1b8b74336c003f521acfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I8836bf05dc84a25640dc63b41e1232d8fb1f50a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I8781912fe87ee568b7ea6003414c75f255c8cd07
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I54f3fe0d3b0c988ab6f9065bea81a385507e9747
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I3f9b31a2bfb85ceb9ff833c076e062291c944923
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I88cb6116c112b76336846d01e31f2cd40d6ca4cb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I0fbdf8d7a3d89fefcd321dc3ba4ddd82c309e667
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I51a2b71abc7762b550f69f2980dd34f0e4947ab5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43219
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Id3f9dd264e82f93a438422e388d70e3f88ae0df9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I16fe12368ce7ffe2fd4d2a5580dd92c19a695848
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I76bf20bb2ec1cdd7ffee4430c80609978afaa1a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
The expected lane numbers in the fsp_pcie_descriptor struct are the
logical and not the physical ones.
Change-Id: I14166bbd397a9e5f5c5370717e039b9e71cbdb07
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43311
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMM_LOCK bit isn't in SMM_MASK_MSR, but in HWCR_MSR, so move it
there. The soc/amd/* code itself uses the bit definition when accessing
HWCR_MSR, so SMM_LOCK was just below the wrong MSR definition.
Also remove SMM_LOCK from comment about masking bits in SMM_MASK_MSR,
since that bit isn't in that MSR.
TEST=Checked the code and the corresponding BKDG/PPR.
Change-Id: I2df446f5a9e11e1e7c8d10256f3c2803b18f9088
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43309
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I23f9aa969febe58dd3842e6a7cc75a6777b90b17
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43255
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I4f06e5e8a0d25308ba56d09a3d8b71f04dbd27b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Julius Werner <jwerner@chromium.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ia314148abc900685d85aede3add480614fa8e99c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Michael Niewöhner
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ie01d65f80caf32a8318d5109ad48321661c5a87b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43213
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Ifda2bbd87cd8ef5ec8e449d2c4d303be37b4d7c7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43212
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I4772680875b20308e57da073bbcdc4597aeed893
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43215
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43216
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43218
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This code is not even being build-tested. Drop it before it grows moss.
Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43217
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The kernel requires the display oprom is loaded and ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:160560510
TEST=Boot Trembyle in developer mode and normal mode
Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Information taken from the boardviews. We are not configuring any GPIO
in bootblock, but we may want to do so in the future.
Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old values were completely out of whack. Use the same settings as
vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites
configured settings, so drop it from Kconfig to prevent conflicts.
Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This simplifies things and makes type checking possible.
Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
It is no longer used anywhere. Drop it before it rots.
Change-Id: I4bc3d5bd898058e575144a3c6c3fccb78dcff2e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Instead of passing around a pointer to an array, just write the relevant
registers directly. Note that intel/baskingridge used spaces to indent
line continuations and had to be replaced with tabs to quell Jenkins.
Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The common fast SPI driver has a function to set up the SPI OPCODE menu.
Use this function here instead of coding it again as it results in the
very same register values being written.
TEST=Compare register values in both cases and make sure they match.
Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43166
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: <uwe.poeche@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between Bay Trail and Braswell.
The resulting binary changes, but it shouldn't matter.
Change-Id: Ic930ab7eee265e86a7cc1095021e3744885f2c25
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This can result in accesses outside array bounds. Copy what Braswell
does, which is slightly safer.
Change-Id: If3d6f4e1f8921f0be7f4e5e438b7e73c46b8ef95
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: Idfdb1e6ec9bd0c1a11ef36ce0434ed5e12895187
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Tested with BUILD_TIMELESS=1, Google Ninja remains identical.
Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
This reduces the differences between Bay Trail and Braswell.
Change-Id: I60e4db72eed17cdeebd30b010f351e1ffc4187e3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
The PCI COMMAND register is 16 bits wide, so do not use 32-bit ops.
Change-Id: I1baba632bda4a50d5279ca3659047d1dd1e8da34
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Remove I2C4 since it is a slave device used for USB-C mux control
and should not be included with the other master devices.
BUG=b:160624619 b:160292546
TEST=EC can communicate with AP mux I2C4 slave
Change-Id: Idaad618e90d6264d881dc66628cf581a856c231d
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43263
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If CONFIG_CMOS_POST is enabled, psp_verstage breaks because the
spinlock code is missing. Add dummy spinlock code as the spinlocks
aren't needed in the PSP.
TEST=Build with CONFIG_CMOS_POST enabled.
BUG=None
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Iea6f31e500e1b26f0b974c6eaa486209b9c81459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43310
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops the selection of VARIANT_SUPPORTS_PRE_V3_SCHEMATICS
for Vilboz since it did not have any build with pre-v3 schematics.
Change-Id: I3919ad43e1dae95a4fa71073e83865e92f30dfec
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43225
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds following two helper functions:
1. variant_uses_v3_schematics() - Check whether the variant is using
v3 version of schematics.
2. variant_has_active_low_wifi_power() - Check whether the variant is
using active low power enable for WiFi.
In addition to this, Kconfig options are reorganized to add two new
configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and
VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper
functions to return `true` early without checking for board version.
Eventually, when a variant decides to drop support for pre-v3
schematics, it can be dropped from selecting
VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant
decides to drop support for active high power enable for WiFi, it can
be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH.
Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change moves the configuration of GPIO_137 to happen in ramstage
since there is nothing in coreboot that requires the state of write
protect GPIO for zork.
Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change removes "write protect" entry from the list of GPIOs
shared with depthcharge as done for other Chrome OS boards in CB:39318.
Change-Id: Ibd39e8d6835e465b2ab5eebcc245e45db5d84deb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43222
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This results in a wake from S5 as well. Since the PS/2 keyboard now
works, this behavior is annoying and, therefore, undesired.
Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42431
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the CPU fan tach signal to reach the Super I/O.
Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Otherwise, there are complaints about it from the allocator.
Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings
under the correct PnP device. Confirmed findings against boardviews.
Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No wonder why the PS/2 keyboard was being detected as a mouse!
Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42398
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only one generic decode range is needed for the HWM.
Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42131
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Perform the same operations as the RCBA reg script did, but directly
writing the corresponding registers. Some of these operations could be
simplified, but it is not done on this commit to ease verification.
Change-Id: I4c3177ab14ca9bfa2e8d11c27fb249850183eee5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Comments stating that this was mainboard-specific were very wrong.
Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Why use a Rube Goldberg machine to write and then read one register?
Change-Id: I282c12f162b5ae69c40729903c09ae81a14c9761
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Other platforms do this as well. It will ease refactoring on follow-ups.
Change-Id: I643982a58c6f5370c78acef93740f27df001a06d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
The "normalized" boot mode is only used in a single place, so there's no
need to use a variable. Also, reword the associated comment, which seems
to be unnecessarily vague: the hardcoded assumptions are inside the MRC.
Change-Id: I260d10f231f5de765d2675416d7047717d391d8f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
There's no need to repeat the same values over four variants.
Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Files are identical for all southbridges, except bd82x6x. We will take
care of that in subsequent commits.
Change-Id: I38e5d440e188d26f8997bc22a956187b728487ca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43157
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files are identical between all three southbridges, and differ for PCH.
Change-Id: Ic6a926af675bda3db3a5795df9e8f490caf3ebf4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43156
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reduces the differences between ACPI for these three southbridges.
Change-Id: If49bad776ebc98cab439f8ea6942471520c476a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43155
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It does nothing special, so why have it in the first place?
Change-Id: I27aff0ed67e9c69ab78050d35b49f6e26924d31a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43174
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was silently commenting out the line after it.
Change-Id: I2714090b8f99193ace420ad02e2d42b324349c9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Remove some unneeded newlines, add some commas for consistency and
relocate comments to match the code.
Tested with BUILD_TIMELESS=1, Foxconn D41S does not change.
Change-Id: I0ac18a692bf613c75083c4aa1860e0a9f07e68d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use C-style comments, drop unneeded newlines, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Getac P470 remains identical.
Change-Id: I37fffb60944c35dfb5e0491bb023babfcf2c6a73
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43177
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use C-style comments, drop an unneeded newline, add missing commas for
consistency and relocate a comment to match the code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I3f91d1b57eb5530c8adcf5f682e73747435f0d47
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43172
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
