Currently the throttle event handler method THRM is defined as an
extern on the intel bd82x6x and lynxpoint chipsets, then defined
again in the platform with thermal event handling. In newer versions
of IASL, this generates an error, as the method is defined in two
places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
This also requires moving the thermal handler, which now includes
the define to before the gnvs asl file.
TEST=Build before and after, make sure correct code is included.
Change-Id: I7af4a346496c1352ec20bda8acb338b5d277d99b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26123
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As far as I can see this Kconfig option was used wrong ever since it
was added. According to the commit message of 107f72e (Re-declare
CACHE_ROM_SIZE as aligned ROM_SIZE for MTRR), it was only necessary
to prevent overlapping with CAR.
Let's handle the potential overlap in C macros instead and get rid
of that option. Currently, it was only used by most FSP1.0 boards,
and only because the `fsp1_0/Kconfig` set it to CBFS_SIZE (WTF?).
Change-Id: I4d0096f14a9d343c2e646e48175fe2127198a822
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix lint error due to non-ASCII characters
BUG=none
BRANCH=none
TEST=check if no error in checkpatch.pl script.
Change-Id: Iec7682e460c8e0d467a70349a23390554cc1de92
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26562
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board was used a test target for the x4x DDR3 raminit patches and
has an easy to access DIP8 socket.
What is tested and works:
* S3 resume
* PEG, PCI, USB, SATA
* Sound
* Ethernet
* Native graphic init (textmode and linear fb) on the VGA output
* Passing memtest86+ with 2 2Rx8 4G dimms
* PS2 Keyboard
* Flashing coreboot internally from vendor BIOS.
What does not work:
* Running dram at 533 MHz (limited at 400MHz currently)
Tested with two 4G dual rank DDR3 dimm, booted SeaBIOS and Linux
4.10.
Change-Id: If01bf658e52d273c3c203d362f21c3cb9c623f40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20003
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GeminiLake platform is fan-less design. We do not need these DPTF_CPU_ACTIVE_ACx
defines. Removing these for GeminiLake RVP board as these are not being used.
Change-Id: I810809bf58198a028e6cfcdbd68887f5f154a0ad
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/26469
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I791a69aeca9b44daabc9a3e5fb9ac92e6b22f3e5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
In order to use the shared code in intelblock, this patch renames the
denverton specific implementation to not use the same names (for files
and types).
- rename pad_config to remove conflict with soc/.../intelblocks/gpio.h
- rename gpio.c, soc/gpio.h to not conflict with intelblock
Note: There is no functional change in this patch.
Change-Id: Id3f4e2dc0a118e8c864a96a435fa22e32bbe684f
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24926
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: Ie2c466a280d18979d5f9ca182793ed43431d2010
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This change also makes sure that the sum the uma regions (TSEG, GSM,
GSM) is 4MiB aligned. This is needed to avoid cbmem_top floating between
2 usable ram region, since cbmem_top is aligned 4MiB down to easy MTRR
setup for ramstage. At least tianocore requires this and fails to boot
without it.
Better MTRR are achieved by making the memory 'hole' till 4GiB exactly
2Gib.
This code mimics how it is done in nb/intel/gm45 and achieves similar
results.
TSEG is enabled and set to 8M since this makes it easier to reuse the
common smm setup / parallel mp code and makes it possible to cache the
ramstage in there like how it's done on newer targets.
TESTED on Intel DG43GT.
Change-Id: I1b5ea04d9b7d5494a30aa7156d8c17170e77b8ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For cannonlake_rvp, want to support two sound configurations based on
relevant daughter board connected (either of these configurations:
SND_MAX98373_NHLT and SND_MAX98357_DA7219_NHLT).
By default SSDT included all codec entries.
This patch corrects and includes relevant codec entries in SSDT
BUG=None
BRANCH=master
TEST=Verify 'emerge-cnlrvp coreboot' compiles successfully.
Change-Id: I4f9487f3a81ef2d24315f75ec1d34bfab8560224
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-on: https://review.coreboot.org/24918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the common xDCI function to check if the controller is allowed
in the current mode before enabling it. Otherwise, disable the
PCI device if it has been enabled in devicetree.
To make the SOC behavior consistent the XdciEnable config option
is removed in favor of direct control by devicetree.cb and the
mainboards that had defined it were adjusted accordingly.
This was tested on an Eve board with xDCI enabled in devicetree.cb
to ensure the xDCI device is enabled in developer mode and disabled
in normal mode.
Change-Id: Ic3c84beac87452f17490de32082030880834501d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/25365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables ThunderPeak WiFi card on M.2.
TEST=Verify wlan card shows up in lspci
Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/24931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets the PNP config value to PNP_PERF_POWER.
The config values for soc can be found in chip.h
TEST = Built and booted glkrvp, verified warm and cold
reboot and suspend resume.
Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/25309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the config for setting SPD DIMM size to 512 bytes
for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory
SPD data for channel0 and channel1. Set the UserBd UPD to
BOARD_TYPE_DESKTOP for kblrvp8.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I985968d331991884050c3920ec9798cd4cb371c7
Reviewed-on: https://review.coreboot.org/25194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ#
from mainboards instead of defining a separate property for each root
port. This allows us to use memcpy to copy the entire array into FSP
params as well as new properties for PCIe root ports can be added as
arrays in future CLs.
BUG=b:74633273
BRANCH=reef,coral
Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Many generations of Intel hardware have identical code concerning the
RCBA.
Change-Id: I33ec6801b115c0d64de1d2a0dc5d439186f3580a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Read cse file was not getting cached and taking about 500ms on every boot.
Change-Id: I8c92eefc64fe146c628d9c104d7dfb016204004c
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This format (one hex digit, followed by 'b', followed by binary digits)
is arguably useful, but also confusing. Use the more common format
instead.
Change-Id: Ide7b0a999483a2dd863a70f8aa42cd0865e2babf
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23715
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for KBL RVP8 board
* Add KBL RVP8 support in Konfig.
* Add KBL RVP8 config option in make menuconfig.
* Add descriptor and ME binary paths for RVP8 in Kconfig.
* Add RVP8 board name Kconfig.name.
* Add devicetree.cb for RVP8 in the variants path.
* Add gpio.h for RVP8 in variants/include/variant path.
TEST= Build and boot RVP8.
Change-Id: I6ba177c223f6aa3285c0fe5eba0cd55b2a50c4ed
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/23383
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface.
BRANCH=none
BUG=none
TEST=Verify masks with ec hostevent command on S0, S3, S5 and S0ix. Also
check that lidclose/lidopen command from EC console wakes system up from
S3 or S0ix.
Change-Id: I60343aaa9e0ddfd38d42b6d0aa2820e2fd880fb7
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/23453
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now SOC code can select the require UDK support package for any
platform going forward with FSP2.0 model.
Change-Id: Ie6d1b9133892c59210a659ef0ad4b59ebf9f1e45
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/23426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add config option SOC_ESPI in glkrvp Kconfig. This is to disable LPC
and enable eSPI instead.
TEST=Boot to OS
Change-Id: I3116b656d41d1d7719c254888d1e3640628a97ca
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Audio DMIC_DATA needs to be ON in S0ix to support Wake on Voice.
By doing this, SoC can see the DMIC DATA and use for WoV processing.
Thus configuring GPIO_173 as IGNORE IOSSTATE.
TEST=put DUT in S0ix, verify DUT wakes up
Change-Id: I8bf403564e927deb8fed7f415e334bb230107cb0
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/23246
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i82810
Mainboards:
src/mainboard/asus/mew-am
src/mainboard/asus/mew-vm
src/mainboard/ecs/p6iwp-fe
src/mainboard/hp/e_vectra_p2706t
src/mainboard/intel/d810e2cb
src/mainboard/mitac/6513wu
src/mainboard/msi/ms6178
src/mainboard/nec/powermate2000
Change-Id: Ib273316c59f499e6cd3a0e4c4dc4c2cce94ff291
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/23300
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The PNOT method never notifies the CPU to update it's _CST methods due
to reliance on inexisting variable (PDCx).
Add a method in the speedstep ssdt generator to notify all available
CPU nodes and hook this up in this file.
The cpu.asl file is moved to cpu/intel/speedstep/acpi since it now
relies on code generated in the speedstep ssdt generator. CPUs not
using the speedstep code never included this PNOT method so this is
a logical place for this code to be.
Change-Id: Ie2ba5e07b401d6f7c80c31f2bfcd9ef3ac0c1ad1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23144
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Things cleaned up in this patch:
* Add macros for the GENx_DEC registers;
* replace many magic numbers by macros;
* remove many writes to DxxIP since they were 'setting' reset default
values;
* fix some comments about decode ranges.
Change-Id: I9d6a0ff3d391947f611a2f3c65684f4ee57bc263
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch adds the EC_GOOGLE_CHROMEEC_SWITCHES option so that we
use the common switch.c file
Change-Id: I93a2ba63015db17989c89ce1b5897de6a93e201f
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/23131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds recovery cache.
TEST:glkrvp boots with this change and also FAFT test
firmware_CorruptRecoveryCache passes.
Change-Id: I9b32628d814693fb0591fc3750348d48cf9e26f1
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/23067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of duplicating code in each mainboard that supports HDA use
the common driver and provide the HDA verb table.
This was compile tested for both variants with "abuild -t intel/kblrvp"
Change-Id: Ie3bab7aabcfa040935062b7764853df8fb19b04d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested on Linux 4.13.14:
SuperIO resources show up as reserved in /proc/ioports and friends.
Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Especially on ICH7 failing to do so results in i2c block read being
unusable. On ICH10 this problem doesn't manifest itself that much.
This moves disabling the watchdog reboot to the northbridge code like
i945 (even though it technically is southbridge stuff).
TESTED on Intel DG41WV: hacking on raminit is much nicer since no
need to do a hard power down for +4s are needed to clear the timeouts.
Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/22997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In commit 7a95204 (intel/dcp847ske: Add Intel NUC DCP847SKE)
the default_irq_route.asl file was removed, but this mainboard
was missed. Follow suit with the original intent of the commit
and fix the build breakage.
Change-Id: I909dad7cfc0fab37e29187b2358f7f056216a403
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22975
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
https://ark.intel.com/products/71620/Intel-NUC-Board-DCP847SKE
Created using autoport and manual edits.
mainboard_fill_pei_data copied and adjusted from samsung/lumpy.
Tested:
- RAM slots with 2x4GB Kingston KVR1333D3S9/4G (DDR3-1333 1.5V).
- RAM slots with 2x4GB Kingston KVR16LS11/4G (DDR3L-1600 1.35V).
- SeaBIOS stable payload.
- Linux 4.13.14 payload.
- Booting into Linux 4.13.14 with Debian/unstable installed on the
internal mSATA slot.
- Non-native raminit (works).
- Native raminit
- KVR1333D3S9 doesn't work.
- KVR16LS11 only works at 1.5V.
- Native VGA init, HDMI port detection with libgfxinit.
- Basic ACPI functions (power button event; power-off; reboot).
- Suspend to RAM and resume works.
- PCIe WLAN in half-minicard slot.
- USB device in half-minicard slot.
- PCIe device in full-minicard slot.
- mSATA device in full-minicard slot.
- Fan spins up/down in response to CPU load.
Known issues:
- Native raminit fails timC calibration with the RAM I have.
- Technical Product Specification mentions overcurrent protection
for back panel and front panel USB connectors, but I haven't
been able to trigger it with either native fw or coreboot
(tried up to 2.5A load).
Untested:
- USB debug port.
Change-Id: I6e210310f55c051eaf61e0698fed855eda5d7d90
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/22683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.
BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka
Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch configures the EC_SCI_GPI when ESPI is enabled.Also adds
mainboard espi handler function.
TEST= Boot to OS and SMI/SCI is working when ESPI is enabled/disabled.
Change-Id: I2b3845d54ad7c1f14edc86f71b3f968424711999
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SATA was enabled only for internal testing. Since we do not use
SATA on chrome platforms, it can be disabled.
Change-Id: I907b440562b39e6d97f604e7e63b6b99e487aaa8
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/22875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add initial files to support the Saddle Brook board. This board uses the
Skylake FSP 1.1 image and does not build without the FspUpdVpd.h file.
Most of the code has been taken carried over from kunimitsu with changes
done for Saddle Brook.
Saddle Brook is a reference board for Skylake SOC and has DDR4.
TEST=Build with uefi payload and boot to Linux 4.9 on CRB successfully.
Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e
Signed-off-by: Anuj Mittal <anujx.mittal@intel.com>
Signed-off-by: Teo Boon Tiong <boon.tiong.teo@intel.com>
Reviewed-on: https://review.coreboot.org/21436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add proper variants gpio.h in dsdt.asl where the GPE_EC_WAKE and
EC_SCI_GPI is defined.
Change-Id: Ideb6dd4d0ac496a81721cd883865218cb19583d9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On GLK EC does not support temperature reads and does not control
the fans anymore, OS is responsible fan control through EC.
This hack enables running of the fan for boards without External EC.
Change-Id: I361e53d4fd53678f3abb8fe9862071aec6e149a7
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-on: https://review.coreboot.org/22235
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This patch does not put CLKRUN in IOSTANDBY.
Change-Id: I7fedd729d3bb66c2b52a63166e461f8760457721
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Audio DMIC_CLK needs to be ON in S0ix to support Wake on Voice.
So, configuring GPIO_171 to be as IGNORE IOSSTATE, so that
clock is ON in S0ix state.
BUG=None
TEST=put DUT in S0ix, verified DMIC_CLK
in scope when wov capture path is ON
Change-Id: I147cf3c12acb11429c6cb234e8c511f57886b6b4
Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/22675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.
Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These typos were found through manual review and grep.
Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since we move from cannonlake U DDR 4 platform to cannonlake U LPDDR4
platform, it is also critical to revisit the GPIO settings as they are
different. Remove unused GPIO setting for old platform, and clean up the
native function definition. PAD_CFG_NF can only select NF1,NF2 ..., set
to GPIO mode is illegal.
TEST=Boot up in chromeos successfully.
Change-Id: I0022b791bd8459ea2afdcd0241b603ce81408785
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
SCI trigger logic had to be inverted.
This patch enables the system to wake up from S3 when lid is opened
when the system is in suspend state.We are trying to match what a
external EC card running ChromeEC FW is sending on the signal.
TEST = Verified that system wakes up from S3 on toggling lid switch
back to open state.
Change-Id: Ib42a38088ee028eddc6769921b0552c569da25a9
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/22117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maximilian Schander <coreboot@mimoja.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Leaving the wifi related gpios unmodified for now
due to FSP problem. If H0-H3 is configured as native mode
and GPIORXDIS, GPIOTXDIS bits in DW0 are cleared, it causes
FSP to assert when wifi module is attached. coreboot gpio
macros clears these 2 bits because they are suppose to be
"don't care" in native mode.
TEST=Boot to OS and verify wifi
Change-Id: Ica5e1c43802d04a9471cdfa0087e86f669122fff
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22094
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change the board name from cannonlake U DDR4 to U LPDDR4 to match
actual platform.
TEST=NONE
Change-Id: Id350e3cbc299d49431197ef5f914ea9a7310a0a5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Include common platform.asl to have generic indication of power
transition state of system.
TEST=Enter and resume from S3, check the post code had been changed to
0096 and 0097.
Change-Id: Ic38ac6d7e60441caeba5c088c9dbe4d901355782
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22111
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Replace the support for Cannonlake U DDR4 board to Cannonlake U LPDDR4
platform.
TEST=Able to boot up on CNL U LPDDR RVP.
Change-Id: I2a3dd39875705dcb93a60ceba7c143e3e5328148
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Turn on PCIe express port 9 of PCIe controller 3,
to enable NVMe SSD via M.2 socket 3 on RVP board.
TEST=Boot to OS using Intel NVMe SSD Pro 6
Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/21908
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
It makes no sense for Das U-Boot which uses the same setting.
Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Reviewed-on: https://review.coreboot.org/21611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
There's an occasional issue on machines which use CMOS for their
vbnv storage. The machine that just powers up from complete G3
would have had their RTC rail not held up. The contents of vbnv
in CMOS could pass the crc8 though the values could be bad. In
order to fix this introduce two functions:
1. vbnv_init_cmos()
2. vbnv_cmos_failed()
At the start of vboot the CMOS is queried for failure. If there
is a failure indicated then the vbnv data is restored from flash
backup or reset to known values when there is no flash backup.
BUG=b:63054105
Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add EC entries into chromeos.fmd file.
BRANCH=None
BUG=None
TEST=Flash image and confirm system can get out of reset successfully.
System will not be able to reach reset vector if flash map described in
coreboot does not match intel flash map generated from fit.
Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/21526
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This board uses the reset defaults for DxxIP and DxxIR.
The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family"
mistakenly says in the D31IP register that all function have INTB as
default. This is however not true as documented in the reset default
value.
This fixes the DSDT such that the SMBus device gets a route for the
INT C interrupt it uses.
Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21442
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TESTED: NGI works on VGA with adapter on DVI-I port
Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This makes the VGA output on the DVI-I connector usable.
This reuses vendor settings.
Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/21440
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This reverts commit 6c0f3c7ee1.
Reason for revert:
Broke master builds, this was submitted out-of-order, some
of the dependencies have not passed review with +2 yet.
Change-Id: Ib7bcb1b98623d16e074caeca839a936d71ded709
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
The Harcuvar CRB is a reference platform of Intel Atom C3000 SoC
("Denverton" and "Denverton-NS") for the communications segment/market.
The MohonPeak coreboot was used as the starting template with
additions/modifications from other Intel Apollo Lake/Skylake coreboot.
Tested with TianoCore payload (UDK2015) and Poky (Yocto
Project Reference Distro) 2.0 with kernel 4.1.8 booted from
SATA drive and external USB pendrive.
Change-Id: I088833e36e2d22d1fe1610b8dca1454092da511a
Signed-off-by: Mariusz Szafranski <mariuszx.szafranski@intel.com>
Reviewed-on: https://review.coreboot.org/20862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
working gbe in this configuration though)
* USB.
What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)
Not tested:
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configuring the clockgen like vendor bios fixes the issue where the
display wobbles from left to right on the analog VGA output.
Note: This seems to be common issue/requirement on Intel devices from
that generation (also happens on dg43gt).
TESTED on Intel D510MO.
Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC1 and PMIC2,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable Azalia controller, HD Audio DSP and select
the HDAudio IoBuffer Ownership for rvp3.
Check if device is enabled in HDA codec init function
to avoid failure when Azalia controller is disabled in
the devicetree.cb.
BUG=None
TEST=Build for kblrvp3, Make sure booting is fine irrespective of HDA
enable/disable.
Change-Id: I87212fe16ecc6053d6d00372904a5fd5d6f6b209
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For an unknown reason, the I2C ACPI devices were placed
under \SB intead of \SB.PCI0, as with all other non-Atom
based Intel platforms. While Linux is tolerant of this,
Windows is not. Correct by moving I2C ACPI devices where
they belong.
Also, adjust I2C devices at board level for intel/strago
and google/cyan as to not break compilation.
Change-Id: Iaf8211bd86d6261ee8c4d9c4262338f7fe19ef43
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The new config choice is called RUN_FSP_GOP. Some things had to happen
on the road:
* Drop confusing config GOP_SUPPORT,
* Add HAVE_FSP_GOP to chipsets that support it,
* Make running the GOP an option for FSP2.0 by returning 0
in random VBT getters.
Change-Id: I92f88424004a4c0abf1f39cc02e2a146bddbcedf
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/19815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Changes the offsets of some options so that options that span multiple
bytes are byte aligned.
To make the cmos.layout file more consistent some things where moved
around in the cmos.layout of thinkpads X200 and T400.
Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18321
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The separate directory was the old way of handling variant boards.
Update bakersport_fsp to the new method. All of the other pieces
were already moved into bayleybay_fsp.
Change-Id: I5712c1b399570bd7ab7fc9e42af25fbf15a0ba78
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove MONOTONIC_TIMER_MSR selection from mainboard
Konfigs, as it only does a reduntant selection of
HAVE_MONOTONIC_TIMER config, already selected under
skylake soc Kconfig.
Change-Id: Ib3177ceb9e8b6c16ce0e437a4a02b94f215af58f
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/20002
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
This board is almost identical to D510MO, the only differences are
some differences in populated connections, CPU with less L2 cache and
a 10/100 Realtek NIC.
The vendor uses the very same binary for both D510M0 and D410PT.
Change-Id: I220515365b69e785ef249c4e3a9af5f7fddf02f9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Instead of assuming the mapping of dimm number to SPD SMBus address,
allow the mainboard to provide its own mapping. That way, global
resources of empty SPD contents aren't wasted in order to address
a dimm on a mainboard that doesn't meet the current assumption.
Change-Id: Id0e79231dc2303373badaae003038a1ac06a5635
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/19915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Since the conversion of this board to soc/broadwell in 0aa06cbf18
(wtm2: Convert to use soc/intel/broadwell), the NGI for this board
is not hooked up anywhere. Also, the code doesn't compile anymore.
Change-Id: I6387203349b78c8e95333eaf44b345aa30eac7c5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/19801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Move drivers/storage into commonlib/storage to enable access by
libpayload and indirectly by payloads.
* Remove SD/MMC specific include files from include/device
* Remove files from drivers/storage
* Add SD/MMC specific include files to commonlib/include
* Add files to commonlib/storage
* Fix header file references
* Add subdir entry in commonlib/Makefile.inc to build the SD/MMC driver
* Add Kconfig source for commonlib/storage
* Rename *DEVICE* to *COMMONLIB*
* Rename *DRIVERS_STORAGE* to *COMMONLIB_STORAGE*
TEST=Build and run on Galileo Gen2
Change-Id: I4339e4378491db9a0da1f2dc34e1906a5ba31ad6
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Configure the SD controller to handle the SD card slot.
* Galileo supports a removable SD card slot.
* Set SD card initialization frequency to 100 MHz.
* Set default removable delays.
* Build SD/MMC components by default
TEST=Build and run on Galileo Gen2
Change-Id: Iaf4faa40fe01eca98abffa2681f61fd8e059f0c4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/19212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable audio:
* Add verb table for ALC286 & ALC298
* Enable virtual channel 1 for DmiVc1 & HdaVc1.
TEST= Build for kblrvp3 as well as kblrvp7. Boot to OS & verified
working of audio on both the boards.
Change-Id: Id27e3cf585b93ed4131d7bf3d3b53d3f5404b18e
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/18875
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Replace ram_check with quick_ram_check, because ram_check is slow and
is destructive for dram content.
Change-Id: I5fb1bfe711549aabb6e597bda22848988a7e9cbe
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19416
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For raminit to succeed on a hot reset the following things are
prevented from running:
* Clearing self refresh
* Setting memory frequency
* programming sdram dll timings
* programming rcomp
TESTED on Intel d510mo.
Change-Id: I8f7e5c2958df29a96cdf856ade2f4f33707ad362
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19337
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There is no need to override CBFS_SIZE since there is no additional
firmware needed on the flash.
Also due to it having a description CBFS_SIZE was displayed twice in
menuconfig, which is fixed by this.
Change-Id: I1a8e2e458ac4d420f3fd4628c2805b6d4e2ee529
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19331
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
TPM ACPI entries are automatically generated, and the old static
TPM ASL file is obsolete. Remove the reference to this obsolete
static and empty ASL file.
Delete src/drivers/pc80/tpm/acpi/tpm.asl.
Change-Id: I6163e6d59c53117ecbbbb0a6838101abb468de36
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19291
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently when enabling Deep S3 or Deep S5 it unconditionally gets enabled
in both DC and AC states. However since using Deep S3 disables some
expected features like wake-on-USB it is not always desired to enable the
same state in both modes.
To address this split the setting and add a separate config for Deep Sx in
AC and DC states.
All motherboards that set this config were updated, but there is no actual
change in behavior in this commit.
BUG=b:36723679
BRANCH=none
TEST=This commit has no runtime visible changes, I verified on Eve that the
Deep SX config registers are unchanged, and it compiles for all affected boards.
Change-Id: I590f145847785b5a7687f235304e988888fcea8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/19239
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch cleans up the code by:
o adding necessary default definitions to Kconfig
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
devicetree.cb and minnow3.fmd carried over a lot of code from google/reef
which is not correct for Minnow3 hardware. Minnow3 is not intended to
boot Chrome OS and does not need Chrome related flash regions. The
erroneous code is removed.
These changes are the same as those done for leafhill in commit:
6a48923 mainboard/intel/leafhill: Clean up
This was tested by building with the new configuration and
booting to UEFI Payload
Change-Id: I620dcbcd622f9326917c74b2a38984d9e49cff2b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18963
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This fixes the following issues, with no functional changes:
ERROR:POINTER_LOCATION: "foo * bar" should be "foo *bar"
ERROR:SPACING: space required after that ',' (ctx:VxV)
WARNING:LONG_LINE_COMMENT: line over 80 characters
WARNING:SPACE_BEFORE_TAB: please, no space before tabs
ERROR:FUNCTION_WITHOUT_ARGS: Bad function definition
ERROR:SPACING: space prohibited before that close parenthesis ')'
WARNING:RETURN_VOID: void function return statements are not generally
useful
2 unfixed issues:
ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in
parentheses
Verified that the binary was the same before and after the changes.
Change-Id: Ie9afb50e268f4140872e39fe8bede231a43d5cc6
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/19078
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
All boards select INTEL_EDID, move it to nb folder.
Change-Id: I35f075a87f2d841856b208f9440cf41af6a3c8e6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19086
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch attempts to finish the separation between CONFIG_VBOOT and
CONFIG_CHROMEOS by moving the remaining options and code (including
image generation code for things like FWID and GBB flags, which are
intrinsic to vboot itself) from src/vendorcode/google/chromeos to
src/vboot. Also taking this opportunity to namespace all VBOOT Kconfig
options, and clean up menuconfig visibility for them (i.e. some options
were visible even though they were tied to the hardware while others
were invisible even though it might make sense to change them).
CQ-DEPEND=CL:459088
Change-Id: I3e2e31150ebf5a96b6fe507ebeb53a41ecf88122
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18984
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The virtualized developer switch was invented five years ago and has
been used on every vboot system ever since. We shouldn't need to specify
it again and again for every new board. This patch flips the Kconfig
logic around and replaces CONFIG_VIRTUAL_DEV_SWITCH with
CONFIG_PHYSICAL_DEV_SWITCH, so that only a few ancient boards need to
set it and it fits better with CONFIG_PHYSICAL_REC_SWITCH. (Also set the
latter for Lumpy which seems to have been omitted incorrectly, and hide
it from menuconfig since it's a hardware parameter that shouldn't be
configurable.)
Since almost all our developer switches are virtual, it doesn't make
sense for every board to pass a non-existent or non-functional developer
mode switch in the coreboot tables, so let's get rid of that. It's also
dangerously confusing for many boards to define a get_developer_mode()
function that reads an actual pin (often from a debug header) which will
not be honored by coreboot because CONFIG_PHYSICAL_DEV_SWITCH isn't set.
Therefore, this patch removes all those non-functional instances of that
function. In the future, either the board has a physical dev switch and
must define it, or it doesn't and must not.
In a similar sense (and since I'm touching so many board configs
anyway), it's annoying that we have to keep selecting EC_SOFTWARE_SYNC.
Instead, it should just be assumed by default whenever a Chrome EC is
present in the system. This way, it can also still be overridden by
menuconfig.
CQ-DEPEND=CL:459701
Change-Id: If9cbaa7df530580a97f00ef238e3d9a8a86a4a7f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18980
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
VBOOT_DYNAMIC_WORK_BUFFER and VBOOT_STARTS_IN_ROMSTAGE are equivalent in
practice. We can't have a dynamic work buffer unless we start in/after
romstage, and there'd be no reason to go with a static buffer if we do.
Let's get rid of one extra option and merge the two.
Change-Id: I3f953c8d2a8dcb3f65b07f548184d6dd0eb688fe
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18979
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of defining a separate LID device for mainboards using
chromeec, define EC_ENABLE_LID_SWITCH for these boards.
Change-Id: Iac58847c2055fa27c19d02b2dbda6813d6dec3ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18964
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently, it’s impossible for the user to select `NO_POST`, for boards
selecting `CONSOLE_POST` in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS) selects CONSOLE_POST which has unmet
direct dependencies (VENDOR_SIEMENS && BOARD_SIEMENS_MC_BDX1 || !NO_POST)
```
This is currently done for Intel Camelback Mountain and Siemens MC-BDX1.
Selecting the option `CONSOLE_POST` in board specific configuration is
not a good idea, as this should be user configurable over Kconfig, and
also the tree-wide defaults should be the same for these options.
Kconfig is different, as commit 97535558f1 (mainboard/{google,intel}:
Change config option selection) only touch the Intel board.
Change-Id: I91c1e0cb92ed218b6bbc7c33759b91f748cf6f51
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18878
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently, it’s impossible for the user to select `NO_POST`, for boards
selecting it in their config.
```
warning: (BOARD_SPECIFIC_OPTIONS && BOARD_SPECIFIC_OPTIONS &&
BOARD_SPECIFIC_OPTIONS) selects POST_IO which has unmet direct
dependencies (VENDOR_ASUS && (BOARD_ASUS_F2A85_M ||
BOARD_ASUS_F2A85_M_PRO || BOARD_ASUS_F2A85_M_LE) && (BOARD_ASUS_F2A85_M
|| BOARD_ASUS_F2A85_M_PRO) || VENDOR_MSI && BOARD_MSI_MS7721 ||
PC80_SYSTEM && !NO_POST)
```
This is currently done for Intel Mohon Peak, and its descendants.
Selecting the option `POST_IO` in board specific configuration is not a
good idea, as this should be user configurable over Kconfig, and also
the tree-wide defaults should be the same for these options.
Change-Id: Ia4ab0d942b7d66f18466a770ef739109ab0db629
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18877
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
commands:
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I02eb0ef647cd34c13a5fe8be0bdbe1bb38524d0c
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18821
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the move to FSP 2.0 the number of VR types supported was
reduced to 4, and the VR_RING type is no longer present.
This means all existing boards using FSP 2.0 are incorrectly
passing VR configuration into FSP as the values corresponding to
"GT Sliced" and "GT Unsliced" have changed.
Fix this by updating the skylake SOC VR handling to account for
changes in the FSP configuration and no longer provide VR_RING
type when using FSP 2.0.
BUG=b:36228330
BRANCH=none
TEST=manual: build and boot on Eve
Change-Id: I59eea9fba006a4c235d7b42d07fdc6e4f44f7351
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/18818
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Add the necessary files and changes to support vboot.
TEST=Build and run on Galileo Gen2 with a SparkFun CryptoShield
1. Obtain and install a SparkFun CryptoShield.
https://www.sparkfun.com/products/13183
2. Edit src/mainboard/intel/galileo/Kconfig to select
VBOOT_WITH_CRYPTO_SHIELD
3. Use make menuconfig to update the config values and select a
payload that will fit. I used SeaBIOS which does not boot.
4. Build coreboot
5. Use the command file below to generate the signed coreboot image.
6. Flash build/coreboot.rom onto the Galileo board
7. The test is successful if verstage detects that it needs recovery
after Phase 1. This is expected because the image does not contain
the GBB section.
8. Flash build/coreboot.signed.bin onto the Galileo board
9. The test is successful if verstage reaches Phase 4 and selects SLOT
A to load the rest of the files.
#!/bin/sh
#
# The necessary tools were built and installed using the following
commands:
#
# pushd 3rdparty/vboot
# make
# sudo make install
# popd
#
# The keys were made using the following command
#
# 3rdparty/vboot/scripts/keygeneration/create_new_keys.sh \
# --4k --4k-root --output $PWD/keys
#
#
# Create the GBB area blob
#
gbb_utility -c 0x100,0x1000,0x7ce80,0x1000 gbb.blob
#
# Add the empty GBB to the coreboot.rom image
#
dd conv=fdatasync ibs=4096 obs=4096 count=1553 \
if=build/coreboot.rom of=build/coreboot.signed.rom
dd conv=fdatasync obs=4096 obs=4096 seek=1553 if=gbb.blob \
of=build/coreboot.signed.rom
dd conv=fdatasync ibs=4096 obs=4096 skip=1680 seek=1680 \
count=368 if=build/coreboot.rom of=build/coreboot.signed.rom
#
# Add the keys and HWID to the GBB
#
gbb_utility \
--set --hwid='Galileo' \
-r $PWD/keys/recovery_key.vbpubk \
-k $PWD/keys/root_key.vbpubk \
build/coreboot.signed.rom
#
# Sign the firmware with the keys
#
3rdparty/vboot/scripts/image_signing/sign_firmware.sh \
build/coreboot.signed.rom \
$PWD/keys \
build/coreboot.signed.rom
Change-Id: I96170412e7bbc2b9c747ff5e2c845f29220353ed
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18041
Tested-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the error detected by checkpatch and update the copyright date.
TEST=Build and run on Galileo Gen2
Change-Id: Idc55169913e7b7b0aca684c26f6ed3b349fc6c09
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch tries to clean the code by:
o removing duplication of LPC GPIO pads
o removing incorrect definitions from devicetree
o removing irrelevant entries from FMD file
Also adds vital defaults in Kconfig so it is possible to build an image.
Change-Id: Id9913f3b053189166392271152ce5300d82a7de8
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/18479
Tested-by: build bot (Jenkins)
minnow3 doesn't build right now due to API divergence on master branch.
Follow up with recent changes.
Change-Id: Iee84750292f22aa040127bcbfe523a0b9eaa8176
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18476
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Set the proper memory configuration for the MinnowBoard 3. The current
values are copied from intel/leafhill. Set the proper values for
MinnowBoard 3.
Change-Id: Ie37842f5ce2cabaa892f42ee945c91fe3ace527a
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18374
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit adds the initial scaffolding for the MinnowBoard 3
with Apollo Lake silicon.
This mainboard is based on Intel's Leafhill CRB with Apollo Lake
silicon. In a first step, it concerns only a copy of intel/leafhill
directory with name changes. Special adaptations for MinnowBoard 3
mainboard will follow in separate commits.
Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18298
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is done to avoid any conflicts with same IRQ enums defined by other
drivers.
BUG=None
BRANCH=None
TEST=Compiles successfully
Change-Id: I539831d853286ca45f6c36c3812a6fa9602df24c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18444
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Wacom I2C driver does the same thing as I2C HID driver, other than
defining macros for Wacom HID. Instead of maintaining two separate
drivers providing the same functionality, update all wacom devices to
use generic I2C HID driver.
BUG=None
BRANCH=None
TEST=Verified that ACPI nodes for wacom devices are unchanged.
Change-Id: Ibb3226d1f3934f5c3c5d98b939756775d11b792c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18401
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Linux kernel expects that power management with ACPI should always be
handled using PowerResource. However, some kernel drivers (e.g. ELAN
touchscreen) check to see if reset gpio is passed in by the BIOS to
decide whether the device loses power in suspend. Thus, until the kernel
has a better way for drivers to query if device lost power in suspend,
we need to allow passing in of GPIOs via _CRS as well as exporting
PowerResource to control power to the device.
Update mainboards to export reset GPIO as well as PowerResource for
ELAN touchscreen device.
BUG=chrome-os-partner:62311,chrome-os-partner:60194
BRANCH=reef
TEST=Verified that touchscreen works on power-on as well as after
suspend-resume.
Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18238
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit makes the initial changes to support the Intel Leaf Hill
CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set.
The google/reef directory is used as a template, and the same IFWI
stitching process as reef is used to generate a bootable image.
Apollo Lake silicon requires a boot media region called IFWI which includes
assets such as CSE firmware, PMC microcode, CPU microcode, and boot
firmware.
Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18039
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit adds the initial scaffolding for the Intel Leafhill CRB
with Apollo Lake silicon.
The google/reef directory is used as a template. This commit only
makes the minimum changes to Kconfig and Kconfig.name needed for
the build bot to not have issues.
Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b
Signed-off-by: Brenton Dong <brenton.m.dong@intel.com>
Reviewed-on: https://review.coreboot.org/18038
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Found-by: Coverity Scan #1291162
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18092
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some part of preram cbmem console output is truncated.
Increase preram cbmem console size to 0xd00 to avoid the same.
Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
These headers & comments indicating a lack of functionality don't help
anything. We discourage copyrights and licenses on empty files, so
just clear these.
Change-Id: Id2ab060a2726cac6ab047d49a6e6b153f52ffe6d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17657
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add support for Kaby Lake RVP7 board
* Add RVP7 board support in Kconfig
* Override default descriptor and ME binary paths in Kconfig
since those binaries will differ for RVP3 and RVP7
* Add RVP7 board name in board_info.txt and Kconfig.name
* Add devicetree.cb for RVP7 in the variants path
* Add gpio.h for RVP7 in variants/include/variant path
* Made board specific code for retrieving spd, i.e., in RVP7
there is non-soldered DIMMs, so SPD is read through smbus,
unlike RVP3 where memory DIMMs are soldered down with board.
Hence for RVP3, the spd binaries will be fixed and can be
kept as binary file in cbfs.
BUG=none
BRANCH=none
TEST=Built and boot Kaby Lake RVP7
Change-Id: I6f3d17d857bad1b5cf39f0bc900c760fee72da48
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17637
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the ACPI header there's an OEM revision field that was previously
just being implicitly set to 0. Allow for a board to provide a
non-zero value for this field.
Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17650
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support of Variant board model for existing intel/kblrvp,
since there might be more RVP board supports under
intel/kblrvp. Existing is for KBL RVP3 board.
BUG=none
BRANCH=none
TEST=Built and boot Kaby Lake RVP3
Change-Id: I041a07a273dbb77e422d48591f06b5f1011cd9f7
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17630
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Use common lib spd_bin to get spd.
Change-Id: If94413fc36a98f7694f560955bbb80abefe32166
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17435
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With commit 2c3054c1(soc/intel/skylake: Add USB Port Over
Current (OC) Pin programming) USB OC pin programming is already
initiated from devicetree.cb, hence remove it from ramstage.c.
BUG=none
BRANCH=none
TEST=Built and booted KBLRVP from USB device
Change-Id: Icb47533aa57f208d5a52560db924169b908c7a88
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/17635
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With this the system falls back to sane default
settings when nvram is invalid.
Change-Id: Ie13fd01c4f8403cbedbd7497ad9012c30f494a69
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17042
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.
Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.
Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When MRC cache is available, first read only the SPD unique
identifier bytes required to detect possible DIMM replacement.
As this is 11 vs 256 bytes with slow SMBus operations, we save
about 70ms for every installed DIMM on normal boot path.
In the DIMM replacement case this adds some 10ms per installed DIMM
as some SPD gets read twice, but we are on slow RAM training boot path
anyways.
Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Instead of defining the same functions for reading/clearing boot-mode
switches from EC in every mainboard, add a common infrastructure to
enable common functions for handling boot-mode switches if
GOOGLE_CHROMEEC is being used.
Only boards that were not moved to this new infrastructure are those
that do not use GOOGLE_CHROMEEC or which rely on some mainboard specific
mechanism for reading boot-mode switches.
BUG=None
BRANCH=None
TEST=abuild compiles all boards successfully with and without ChromeOS
option.
Change-Id: I267aadea9e616464563df04b51a668b877f0d578
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17449
Tested-by: build bot (Jenkins)
Reviewed-by: Julius Werner <jwerner@chromium.org>
In preparation of merging the lpss i2c config structures on
apollolake and skylake move the i2c voltage variable to its
own field. It makes refactoring things easier, and then there's
no reason for a separate SoC specific i2c config structure.
BUG=chrome-os-partner:58889
Change-Id: Ibcc3cba9bac3b5779351b673bc0cc7671d127f24
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17347
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Program I/O expander connected on I2C bus 4
Change-Id: I1a431f50e7b06446399a7d7cb9490615818147e7
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17338
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Configure overcurrent pins for various usb ports.
Configure CdClock to 3.
Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17251
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
After tuning the temperature values for optimal performance,
this patch updates few DPTF settings for Kunimitsu board.
BUG=None
BRANCH=None
TEST=Built and booted on Kunimitsu boards. Verified these
updated DPTF settings with different workloads.
Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/350223
Reviewed-on: https://review.coreboot.org/17069
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Update gpio.h to set proper pad config for Kaby Lake RVP3.
2. Set spd index to zero.
3. Remove nhlt specific init.
Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch updates the _ART table with other external sensor
TSR0 for Fan speed control on Skylake-U based Kunimitsu and
Lars boards.
Also, updates the temperature values in DPTF policy for
better performance.
BUG=chrome-os-partner:51025
BRANCH=firmware-glados-7820.B
TEST=Built and booted on kunimitsu and lars EVT boards.
Verified this updated _ART table on these boards with
different workloads.
Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/332349
Reviewed-on: https://review.coreboot.org/17066
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the FADT from the individual mainboards and select and
use COMMON_FADT in the SOC instead. Set the ACPI revision to 5.
Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17138
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for Kaby Lake RVP3.
Use kunimitsu at commit 028200f as base.
Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel
LPDDR3 DIMM.
* Update board name to kblrvp
* Remove fsp 1.1 specific code( As Kabylake uses fsp2.0)
* Remove board id function.
* Remove unused spd & add rvp3 spd file.
This is an initial commit does not have full support to boot.
Will add more CLs to boot Chrome OS with depthcharge.
Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17032
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of hard-coding the polarity of the GPIO to active high/low,
accept it as a parameter in devicetree. This polarity can then be used
while calling into acpi_dp_add_gpio to determine the active low status
correctly.
BUG=chrome-os-partner:55988
BRANCH=None
TEST=Verified that correct polarity is set for reset-gpio on reef.
Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/16877
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Add PCI device id to native graphic init and add the Native graphic init
option in Kconfig.
Change-Id: I136122daef70547830bcc87f568406be7162461f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Switch from FSP 1.1 to FSP 2.0 as the default build.
BRANCH=none
BUG=None
TEST=Build and run on Galileo Gen2
Change-Id: Icbb3a36cdde68baf4d68fbfc371f8847c56e1162
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16810
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add Kconfig values to select the FSP setup:
* FSP version: 1.1 or 2.0
* Implementation: Subroutine or SEC/PEI core based
* Build type: DEBUG or RELEASE
* Enable all debugging for FSP
* Remove USE_FSP1_1 and USE_FSP2_0
Look for include files in vendorcode/intel/fsp/fsp???/quark
BRANCH=none
BUG=None
TEST=Build FSP 1.1 (subroutine) and run on Galileo Gen2
Change-Id: I3a6cb571021611820263a8cbfe83e69278f50a21
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a header file to provide common declarations that the
mainboards can use regarding EC init.
BUG=chrome-os-partner:56677
Change-Id: Iaa0b37eff4de644e969a18364713b90b7f27fa1c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16734
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins)
The mainboard is not being worked on anymore, not available outside of
Intel and thus has litle practical use. Remove mainboard code completely.
Change-Id: Ic2c7ea3810ee70afc01a42786f8ccba9313134e4
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16725
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In spd_util.c function mainboard_get_spd_data(), spd_file can
either be NULL or will point to the first byte of the SPD data,
and should not be dereferenced.
Change-Id: I08677976792682cc744ec509dd183eadf5e570a5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16612
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In commit 4f2754c
'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode'
the default operation mode of SERIRQ was changed from continuous to quiet.
Set the mode to continuous for this mainboard to keep the behavior unchanged.
Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/16576
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch removes setting of gpio_tier1_sci_en from mainboard
smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl
now.
BUG=chrome-os-partner:56483
TEST=System resumes from S3 on lidopen, powerbutton and USB wake.
Also from S0iX system is resuming for WIFI wake.
Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/16565
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Configure PERST_0 and assign the pin in devicetree.
BUG=chrome-os-partner:55877
TEST=Suspend and resume using 'echo freeze > /sys/power/state'.
System should resume with PCIE and wifi functional.
Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/16350
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch sets tuned RAPL power limit PL1 value to
12W in acpi/dptf.asl for RAPL MSR register. With PL1
as 12W for WebGL and stream case, we measured SoC power
reaching upto 6W. Above 12W PL1 value, we observed that
Soc power going above 6W. With PL1 as 12W, system is
able to leverage full TDP capacity.
BUG=chrome-os-partner:56524
TEST=Built, booted on reef and verifed the package
power with heavy workload.
Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/16596
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Similarly to 2b2f465fcb
"mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA"
SATA must function in "plain" mode because it does not work in
"combined" mode.
Tested on d945gclf
Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16319
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
A recently announced Turbot system populates two Ethernet
controllers. Enable the remaining disabled PCIe port.
Also add a clarifying comment regarding the port associated
with Function 0. Coreboot must not be allowed to disable the
function which breaks PCI compatibility.
Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16429
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MinnowBoard Turbot systems have a GPIO-controlled LED that is
generally used to indicate the CPU is running. Commit 2ae9cce8
changed the parameter for GPIO_NC, exposing an issue with the
assumed behavior of the signal. Use a pull-down to turn on the
LED.
Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/16428
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The following patch is based off of the UEFI 2.6 patch. The FSP header files
are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated
since the other headers expect it to be in the root of an includable directory.
Any struct defines were removed since they are defined in the headers and no
longer need to be explicity declared as struct with the UEFI 2.6 includes.
BUG=chrome-os-partner:54100
BRANCH=none
TEST=confirmed coreboot builds successfully
Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>#
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/16308
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On i945 the vram size is the default 8mb. It is also possible
to set it 1mb or 0mb hardcoding the GGC register in early_init.c
The intel documentation on i945, "Mobile Intel® 945 Express Chipset
Family datasheet june 2008" only documents those three options.
They are set using 3 bits. The documententation also makes mention
of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it.
The other non documented (straight forward) bit combinations allow
to change the VRAM size to those other states.
What this patch does is:
- add those undocumented registers with their respective vram size to
the i945 NB code;
- make this a cmos option on targets that have this northbridge.
TEST: build, flash to target, set cmos as desired and boot linux.
On Debian it can be found using "dmesg | grep stolen".
NOTE: dmesg message about reserved vram are quite different depending
on linux version
Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/14819
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide GBB's hardware ID (used on Chrome OS devices) because it will be
dropped from depthcharge.
BRANCH=none
BUG=none
TEST=none
Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00
Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/372579
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16363
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
On x86 platforms, google_chromeec_early_init() is used to put the EC
into RO mode when there's a recovery request. This is to avoid training
memory multiple times when the recovery request is through an EC host
event while the EC is running RW code. Under that condition the EC will
be reset (along with the rest of the system) when the kernel verification
happens. This leads to an execessively long recovery path because of the
double reboot performing full memory training each time.
By putting this logic into the verstage program this reduces the
bootblock size on the skylake boards. Additionally, this provides the
the correct logic for all future boards since it's not tied to FSP
nor the mainboard itself. Lastly, this double memory training protection
works only for platforms which verify starting from bootblock. The
platforms which don't start verifying until after romstage need to
have their own calls (such as haswell and baytrail).
Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16318
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Provide a default value of 0 in drivers/spi as there weren't
default values aside from specific mainboards and arch/x86.
Remove any default 0 values while noting to keep the option's
default to 0.
BUG=chrome-os-partner:56151
Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/16192
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Update eMMC DLL setting for amenia board, after that system can
boot up with eMMC successfully.
BUG=chrome-os-partner:51844
TEST=Boot up with eMMC
Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/16237
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
