disable_all_smi_status() was not clearing SMI_EVENT_STATUS. This caused
us to complain in the eventlog (ELOG_SLEEP_PENDING_GPE0_WAKE) and then
wake early from sleep when waiting for a cr50 reset to turn on a cr50
update.
BUG=b:121203745
TEST=Careena remains in S5 until cr50 reset after cr50 update, and
ELOG_SLEEP_PENDING_GPE0_WAKE is no longer seen in eventlog.
Change-Id: I2eec014109249d5c3574c4dbdec5569e2a0bfc8e
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is needed so the next patch can set up GPIOs before
AGESA runs.
BUG=b:120436919
TEST=Verified romstage mainboard code runs before AGESA
Change-Id: I76c035e166cd64382b52dff5ae00a6f115cbac9b
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30038
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD traditionally claims the resource at I/O port 61 for the onboard
PC-AT speaker. In later designs, the speaker may be omitted in favor
of routing the SPKR signal to the codec.
Some systems implement neither, and for those it is not correct to
identify the resource as a speaker. Modify the EISAID reported to
the OS depending on the system design. The default is that port 61
is reported as reserved. In order to report a speaker, add #define
in mainboard//dsdt.asl.
TEST=check /proc/ioports and iasl -d for both ways using a Grunt
BUG=b:117818432
Change-Id: I33aafb187f9fea7b38aae43c399292c7521fcfc4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30037
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
When building grunt with flags set to detect variables that get a value but
then are unused, there are 5 instances that causes error (unused variable).
In most cases it's enough to simply remove the variable. Other instances,
is better to simply use the variables (one instance it's a return value, on
the other instance using the variables makes code more readable).
BUG=b:120260448
TEST=Build and boot grunt.
Change-Id: I0d00fb6a42db20afb34c76b9445a741a57096ead
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29985
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replace IO access to ACPI registers with the new MMIO access functions.
BUG=b:118049037
TEST=Build and boot grunt. Test ACPI related functionality.
Change-Id: I7544169bb21982fcf7b1c07ab7c19c6f5e65ad56
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
ACPI registers can be accessed through IO or through MMIO. However, the
offset relationship is not one to one. Therefore, definitions with the
correct offset for MMIO access are needed.
BUG=b:118049037
TEST=Use Chrome OS IOTOOLS io_readxx and mem_readxx to find the correct
relationship between ACPI IO and ACPI MMIO.
Change-Id: Id20754c0fc0af35bc9eb1a4b40c62fbf9ed6304d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that the relationship between IO access and MMIO access has been
established, create read/write functions to access ACPI standard registers
through MMIO.
BUG=b:118049037
TEST=Build grunt
Change-Id: I32c26f342885c0d99b082be98730edcf16ab5dfc
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Makes vboot measured boot mode available for all boards.
* Increase Tegra210 and Rockchip3228 SRAM for
romstage/verstage.
* Add missing files for Intel apollolake and
AMD stoneyridge as TPM driver target.
Change-Id: I35a85b8f137f28cd9960f2c5ce95f8fa31185b82
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/29840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some "magic" numbers became public available registers/bits after the code
was originally written. Find all magic numbers, and if available in a public
BKDG than replace them with literals.
BUG=b:117648026
TEST=Build and boot grunt.
Change-Id: I96ac59fd92c4a5e27c3836f77bf6633e9b0c4990
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/29198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
There are several files under soc/amd that use units defined by file
porting.h. These units use upper case, and are not recognized by checkpatch,
thus causing problems when defining a pointer (request to use space before
and after the star symbol). These are the definitions from porting.h showing
the units that this patch will change and their coreboot definitions (not all
are actually used):
typedef uintptr_t UINTN;
typedef int64_t INT64;
typedef uint64_t UINT64;
typedef int32_t INT32;
typedef uint32_t UINT32;
typedef int16_t INT16;
typedef uint16_t UINT16;
typedef int8_t INT8;
typedef uint8_t UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
typedef unsigned char BOOLEAN;
typedef void VOID;
BUG=b:118775313
TEST=Build and boot grunt.
Change-Id: Ic1bd64d6224a030a65d23decabf0e602cee02871
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
1. Add two parameters for panel initialization timing.
> lvds_poseq_varybl_to_blon
> lvds_poseq_blon_to_varybl
2. The BL_PWM is controlled by APU_EDP_BKLTEN_L/APU_DP_VARY_BL/
EDP_BKLTEN_L, so move APU_EDP_BKLTEN_L to early init stage,
and be enabled depends on SKU, thus we can control the delay
time by config APU_DP_VARY_BL.
BUG=b:118011567
TEST=emerge-grunt coreboot.
Change-Id: Ib20c48813b208d697b950b2f02a70a690e483fdb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There some files that do have at least 1 line over the 80 characters limit.
Find and fix them.
BUG=b:117950052
TEST=Build grunt.
Change-Id: I1083a7559919e05a3e3a2dac99f571c161bb4c27
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Pointer math with void pointers is illegal in many compilers, though it
works with GCC because it assumes size of void to be 1. Change the pointers
or add parenthesis to force a proper order that will not cause compile
errors if compiled with a different compiler, and more importantly, don't
have unsuspected side effects.
BUG=b:118484178
TEST=Build and boot grunt.
Change-Id: Ibfeb83893f09cb897d459856aff2a4ab2a74e6e5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
In commit 41baf0c3ff (soc/amd/stoneyridge: Remove dev_find_slot where
possible), the register being read was changed accidentally from
HT_DEV (Device 18h, Func 0) to NB_DEV (Device 18h, Func 5)
This doesn't return the correct value, and causes Grunt to reboot.
BUG=b:118721473
TEST=Boot grunt
Change-Id: I7b73358a074dd27639aafead7c8b39f0fad5685f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The function domain_read_resources() didn't have any code to actually
reserve any resources - it was just creating an empty resource entry.
I looked at fixing it to actually reserve the space, but the values in
the registers at the point when this runs aren't the final values that
we want to reserve anyway, they're temp values with a range much larger
than we want to reserve.
I next looked at moving the amd_initcpuio() function earlier so that we
could get the correct values for the registers, but even that doesn't
give us what we really want.
Ultimately removing this whole function seems to be the right thing.
BUG=None
TEST=Verify that the only resource that changes is the empty resource:
PCI: 00:18.0 resource base 0 size 0 align 0 gran 0 limit 0 flags 1 index 1080
Change-Id: I83bd3ea8db141416632c12fc883386070363f2f1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Instead of forcing the IOMMU to be enabled, change it to only be enabled
if the device is enabled in devicetree.
BUG=b:118612241
TEST=Verify that IOMMU is disabled.
Change-Id: I6cfd6c81f47de23c54a49ec7cf87b219215ced5e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29343
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
The procedure dev_find_slot has 3 main uses. To find configuration
(devicetree), to verify if a particular device is enabled at build \
time, and to get the address for PCI access while in bootblock/romstage.
The third use can be hidden by using macros defined in pci_devs.h,
making it very clear what PCI device is being accessed. replace the
temporary pointers to device used with PCI access with SOC_XXX_DEV where
XXX is the device being accessed, and remove the setting of the temporary
pointers.
BUG=b:117917136
TEST=Build grunt.
Change-Id: Ic38ea04bfcc1ccaa12937b19e9442a26d869ef11
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
File ramtop.c has one instance of if()/else where the if tests for top mem
in lower 4GiB, and returns just before the "else" statement. These "else"
statements are not needed.
BUG=b:117648025
TEST=Build and boot grunt.
Change-Id: Iba16a416e78dae75a95a11d38179161c5a11b2ad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29247
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The file smbus.asl has 0 bytes (no content). Now that it's no longer included,
remove it.
BUG=b:117814641
TEST=Build grunt and gardenia.
Change-Id: I66389c721e272053d86357f71a6d1242ca767edd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add an `amdblocks` internal API and rename
soft_reset() => warm_reset()
hard_reset() => cold_reset()
as these terms are commonly used in the surrounding code.
On Stoney Ridge, make board_reset() call cold_reset() to keep
current behaviour of common code calling hard_reset(). But add
a TODO if this is intended.
Note: Stoney Ridge is using CF9 for the actual reset but the
configuration for a cold reset doesn't use the usual full reset
bit but some other mechanism.
Change-Id: Id33eda676d79529db759b85fa8e28386846e6fa4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Register 0x40 of miscellaneous MMIO is double defined, with different names,
which makes it confusing. Eliminate MISC_MISC_CLK_CNTL_1, and move its only
bit definition to MISC_CLK_CNTL1 (which is correctly placed among MMIO
registers.
BUG=b:117818431
TEST=Build grunt.
Change-Id: I5ca5045498b8a81943282e0d6ecfbaecbd600d19
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SPI100_SPEED_CONFIG is double defined. Bits and shift definitions on the
first definition are unused. Remove first definition and its associated
bits and shifts.
BUG=b:117818430
TEST=Build grunt.
Change-Id: I8175b9a2f379b47475a71f93096f682bc56d051c
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
WIDEIO_RANGE_ERROR and TOTAL_WIDEIO_PORTS are defined twice. Remove the
definitions within MMIO definitions, as wideio is not related to MMIO.
BUG=b:117814228
TEST=Build grunt.
Change-Id: I370a5b387b908fe7a840eb7579d45c1a6a9ca615
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The definition DEV_D18F4 is only used once, in file tsc_freq.c, and is
the same as SOC_PM_DEV. Remove the definition, and replace its use in
tsc_freq.c with SOC_PM_DEV.
BUG=b:117754424
TEST=Build and boot grunt.
Change-Id: I9eeeaa084e5b16280713b8b833b4faa78d277586
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29166
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
GPIO control a mux base addresses are defined within MMIO definitions
and again bellow as GPIO specific base addresses. Eliminate those outside
MMIO bases. Rename them to something indicating that they are both MMIO
and related to GPIO.
BUG=b:117754420
TEST=Build grunt.
Change-Id: I53f7cf17d6267e6f8daa650b5f864bab688dc3f0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29156
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no indication that they are accessed through D0F0. Add a D0F0 header
and move IOAPIC definitions under it. The registers defined to be accessed
through index/data pair should be indented relative to the index/data pair
definition.
BUG=b:117754786
TEST=Build grunt.
Change-Id: If4fb6514bb13f1c944d0e1756d8d9de1f08c99f3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29155
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In function smm_setup_structures(), the function name is used in a print
string. Use __func__ instead.
BUG=b:117642170
TEST=Build grunt.
Change-Id: Icac5ea997289ef75fb246a09715cbca4442a57f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29154
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Comparison should place the constant on the right side. Southbridge.c has 6
instances where the opposite happens. Reverse the order of six comparisons
to eliminate checkpatch warnings:
WARNING: Comparisons should place the constant on the right side of the test
BUG=b:117656929
TEST=Build grunt.
Change-Id: I94f17b81f845fa94599f93c0be1144ffcb8e4165
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29153
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
File smbus_spd.c has 2 instances of if()/else where the if tests for an
error condition and returns just before the "else" statement. These "else"
statements are not needed.
BUG=b:117648025
TEST=Build and boot grunt.
Change-Id: Ie8298773ae455dbb1125420ec65df24f3c65eb44
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29152
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make #define definitions for PMxEF and replace the hardcoded values.
Note that this doesn't change the current functionality of the source.
The existing code has been propogated from the sb//hudson port, which
seems to attempt to enable 100% of all OHCI and EHCI controllers that
may be present in the system.
Change-Id: I6018b0062730de19e3283a010144dfedc2b11423
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29075
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove nonpreset controllers from the PCI device identifier function
(ignoring any CONFIG_USBDEBUG_HCD_INDEX). The extra devices appear
to be holdovers from the original sb/hudson source.
TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and
verify proper BDF is returned in romstage and ramstage.
Change-Id: I2e819d5e998922ad427c4a094c29a590f249a0d3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Delete an unmatched opening parenthesis in the definition for the EHCI
hub config register definition. This wasn't causing a problem unless
EHCI debug was enabled.
TEST=Jam Makefile.inc to unconditionally build enable_usbdebug.c and
verify successful build
Change-Id: I5f461d1573e416b5a8ee24329142e3c46b6a05e3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29073
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The AMD implementation of this register is only 16 bits. Change the
source accordingly.
TEST=Suspend/Resume a Grunt several times
Change-Id: Ib900468cc1c790fa7d57bb6faa91aee012173f7a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29016
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Shorten the names in the MISC CGPLL_CONFIG, and make the formatting match
the surrounding source.
Change-Id: I71cf1ff6bd4bca7a25484b4da9388c17cfecc043
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Make the field names of the MISCx00 GPPClkCntrl more manageable by
shortening their names. Make the definitions look more like the
rest of the header file.
Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Group definitions so they're near others of the same type, e.g. PCI,
AcpiMmio, etc.
Change-Id: Ia6ef21431db0e758eba0ea043b54c036ec6235fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29013
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Match the rest of the soc/stoneyridge source.
Change-Id: I4531e6dad0362be73499647d9fc93c168b6f163e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Delete artifacts remaining from the original "hudson" and "yangtze"
controller hub designs.
Husdon devices had a configurable AcpiMmio base address, and a selection
for I/O vs. MMIO decode. Modern products are fixed at 0xfed80000 in MMIO.
Remove the flash control register definitions for the old generations.
The manual reset register appears to not function as hudson.
PMIO_DEBUG is named differently now, and not used, so remove its
definition too.
Change-Id: I6484bb2ca80b65318565dfee1a3368b121aea9de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
STAPM devicetree registers do not indicate the unit, which causes confusion.
More importantly, the time was assumed to be in seconds when it's actually
milliseconds. This caused early STAPM configurations to fail.
BUG=b:117590953
TEST=Build grunt
Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD's SOC do not wait for I2C transactions to complete before executing
a reset. Because of this, it's possible for the reset to happen in the
middle of a transaction, resulting on a slave hang. There are 2 possible
solutions:
If the slave has a reset pin connected to a GPIO pin, it can be used to
reset the slave, else the only solution is to bang SCL 9 times. Create
code that makes it easy to implement SCL bang, using a devicetree
register to define which I2C SCL lines needs to be reset.
BUG=b:114479395
TEST=Build and boot grunt. Look at transactions on a scope.
Change-Id: I7f74b7e45c509044825355874753969f074e2382
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28574
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the step of setting the SATA controller to S0 as the system is
entering S3. This had been duplicated from AMD's FchCarrizo.asl file,
but upon closer inspection, the conditions for this step to run cannot
be met. This does not affect Grunt's behavior, as the SATA controller
is disabled.
TEST=Suspend and resume Grunt
BUG=b:77602074
Change-Id: Ib269a5363d03c7048abd0c8a9a28df92a773790c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Use BIOS_DEBUG consistently to log PM1 and PMxC0 status registers
on boot. print_num_status_bits() was already using BIOS_DEBUG.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: If7da8c7c86e90a661338903ad05cc41e11f507d2
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28885
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the function vboot_platform_prepare_reboot() which is normally
a weak function.
The SlpTyp field of the PM1 register is not reset to its default value
when the APU restarts. This change prevents a failing condition if
vboot decides to reset the system instead of allowing an S3 resume to
continue.
TEST=Resume Grunt when vboot attempts a reset, verify a fresh boot instead
BUG=b:117089826
Change-Id: I6e0e3e541bad89ca5b23d6ddb6e5c0df7f762f10
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28877
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the IOMMU in AGESA and copy the AGESA generated IVRS ACPI table.
BUG=b:116196614
TEST=Check dmesg for AMD-Vi messages.
Change-Id: I688d867c7bd4949a57b27c1b6a793c6a6e4a717a
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/28753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Add methods, and call them, for transitioning EHCI and xHCI to D0 or
D3cold. Add device objects necessary for waking the system via USB.
In order for USB to wake the system, it must be in the D3cold state.
Then on resume, its firmware must be reloaded.
This code relies heavily on AMD's FchCarrizo.asl (delivered in NDA PI
package), and has been modified to fit the coreboot ASL names. In
addition, AMD's methodology is to generate a SW SMI for saving/restoring
certain settings. This has been ported into U3D0 and U3D3, as the
necessary registers are now publicly documented.
BUG=b:77602074
Change-Id: I83d0dce13411601691318cc67c99adf291ccf3bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28772
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a method to assist with setting the PwrGood Control register, which
will be useful for various devices.
BUG=b:77602074
Change-Id: Ief602c4bc42d27b3e236d24db815b990f3a2419c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add methods that can be used for preparing all controller hub devices
for sleep, and that will turn the devices back on.
BUG=b:77602074
Change-Id: I4b0c48e96aff23b4c31c9e89582b9fa80dba7bda
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28770
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Duplicate ASL from AMD's FchCarrizo.asl (available in NDA PI package)
that can put AOAC devices into D0 or D3cold. The argument numbers
coincide with the AOAC register offsets for the various devices.
SATA, USB, and SD require additional device configuration. Add a
placeholder and mark as todo.
BUG=b:77602074
Change-Id: I32426f744a5ebbad9e8d3f2f37c4d214ad6dd3d4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28769
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Define various AMD_SB_ACPI_MMIO_ADDR registers at 0xfed80000. Define
various PCI config space registers. These are duplicated from AMD's
FchCarrizo.asl file.
BUG=b:77602074
Change-Id: Ie7447fef682424b05fa912b60c7b80112c6202de
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28768
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Indicate the devices that are enabled. This is somewhat rudimentary, but
could be improved in a later patch (e.g. get settings from devicetree).
Calculate values that may be used for reinitializing the xHCI firmware.
Add the EHCI BAR's current base address to gnvs.
BUG=b:77602074
Change-Id: I8af69c030eb2353ad75beeb2bfd3bef24abff04c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28767
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A later patch will rely on two USB settings from the BIOS. Add these
to the global_gnvs_t structure.
The first is a data that will be used to locate the xHCI firmware for
reloading after a resume. Although the existing calculations will be
somewhat simple, keeping this on the coreboot side will help in the
event multiple FWs are eventually in the build.
The second item is a usable EHCI base address that may be programmed
during S3 suspend and resume. At the time the PTS and WAK code runs,
the BAR will be clear.
BUG=b:77602074
Change-Id: I32205ac8a6908cca4a38dd68a7c7b591e76c06bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
A later patch will leverage AMD's ASL support for handling AOAC
devices. This will gather coreboot's device enables from a bitwise field,
where each bit corresponds to the register offset used to control
each devices.
Create an identical structure, and add it to the nvs ASL and global_nvs_t
structure.
BUG=b:77602074
Change-Id: I40f0161cc0bbc574ad703e34278372f2504de100
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The globalnvs.asl file had become mixed with tabs and spaces to align
columns. Use all tabs to align the comments.
BUG=b:BUG=b:77602074
Change-Id: Ife4cf86372a8e24e78b38cca0254dd9fa00dd6b0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Martin Roth <martinroth@google.com>
As per internal discussion, there's no "ChromiumOS Authors" that's
meaningful outside the Chromium OS project, so change everything to the
contemporary "Google LLC."
While at it, also ensure consistency in the LLC variants (exactly one
trailing period).
"Google Inc" does not need to be touched, so leave them alone.
Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/28756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
STAPM programming was created inside function OemCustomizeInitEarly().
It should be SOC specific, and called by agesawrapper just before the
call to OemCustomizeInitEarly().
BUG=b:116196626
TEST=build and boot grunt
Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28705
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When preparing transition of AGESA calls to romstage, I placed a comment
indicating the place to move a particular call. Now that the AGESA call
has been moved to romstage, the comment became obsolete.
BUG=b:116095766
TEST=none.
Change-Id: I2811657385ab088747e32d4c66b99fdd01e7315e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
According to AMD, there exists an undocumented MSR which must be
written with the PSP's base address. Read the value from the PSP's
config space and sync each core's copy of the MSR to match.
BUG=b:76167350
TEST=boot Grunt and verify "rdrand: disabled" goes away from dmesg
Change-Id: I30027d3b0a6fbd540375e96001beb9c25bf3a678
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28608
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Default STAPM percentage causes a lot of thermal throttling on grunt.
AMD experimented with 80%, it works for grunt. This is initial code to
provide easy change path for other grunt based platforms.
BUG=b:111608748
TEST=build and boot grunt.
Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Instead of gpio_num, gpio_address should be used as the address in
write32. This lets us also get rid of a few casts.
Commit c9ed3ee8d8 ("soc/amd/stoneyridge: Fix gpio_set function") fixed
one instance of this bug, but it was more widespread.
TEST=None
Change-Id: I0cf87aac2f1b87b6eac2b506515e48fe908c1f2b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a duplicate ACPI_BERT symbol with a 'y' default setting and additional
help text.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I817111cbd3e81b93d8b02d0654ba68c8678b1bbe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Expand the BERT reserved region size setting to account for the
possibility of no TSEG configuration. This change is only for
completeness, as stoneyridge must always use TSEG.
Change-Id: I90753fa408cfac4de38aff08979c45349bb62a66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add a Boot Error Record Table to the ACPI information. Avoid a driver
error message by skipping the table altogether when no errors are found,
or support isn't built in.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I6fe38eefacaad0bc73d0cb4ae44a339a45857128
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28478
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to build a Boot Error Record Table region based on
settings found in the MCA registers.
Two entries are reported for each error due to the nature of the ACPI
driver. The first is a Generic Processor Error, which the OS recognizes
and parses. Generic errors cannot convey much error description or
processor context. Therefore an IA32/X64 Processor Error is also added,
which allows reporting the values found in the MCA MSR registers.
Follow-on work could decode the MC errors more precisely, and better
completing the Generic Error and the Check structure. The current
level of support is sufficient to identify a (i.e., human readable)
problem in dmesg, and provides adequate context information for
analysis.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I4d4ce29ddefa22aa29e6d3184f1adeaea1d5f837
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28477
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Convert the Machine Check reporting to use a newly defined structure.
This will facilitate later patches that will pass pointers to the MSR
values.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0a98aecc83a0fa1c5ca7926849a89145a595d9ff
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28476
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the process of interrogating the Machine Check registers into
its own file. This rearranges source code in preparation of supporting
a Boot Error Record Table, which stoneyridge will use to report latent
MC errors to the OS.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: Ia3275e9135dc96ba4a717c9371f38843fa1e3e64
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Carve out memory to be reported to the OS as reserved. This makes
room for a region usable for Boot Error Record Table information.
The BERT region reserved size is larger than likely requried, however
the SMM region's base must be on a boundary matching the granularity
of its size.
BUG=b:65446699
TEST=inspect BERT region, and dmesg, on full patch stack. Use test
data plus a failing Grunt system.
Change-Id: I0958f6b6bab3fe9dae36c83e1fd9ae6ed0290a18
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/28474
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Remove unused acpi_get_chromeos_acpi_info (see CB:28190)
- Make function naming in gnvs.h consistent (start with "chromeos_")
BUG=b:112288216
TEST=compile and run on eve
Change-Id: I5b0066bc311b0ea995fa30bca1cd9235dc9b7d1b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Function pci_ehci_dbg_set_port() used NDA register DEBUGPORT_MISC_CONTROL,
which was deprecated in favor of a public PCI register (though only the
bits to enable debug port became public) 0x90. Therefore code needs to be
updated.
BUG=b:69231009
TEST=Build and boot grunt.
Change-Id: Ibb25992729d984b8570712f91a03a7cd1e9b8643
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28344
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.
Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
There's a small window of opportunity when CPU is already in SMM but has
not yet entered S3 for a wake event to happen, which would cause a failed
S3 entry. Check for pending events at the very last moment possible, and
if there are pending wake events report them.
BUG=b:111100312
TEST=build and boot grunt.
Change-Id: I9472fdf481897fcf9f4c669f6b1514ef479fce7a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can derive chromeos_acpi's location from that of
ACPI GNVS, remove chromeos_acpi entry from cbtable and
instead use acpi_gnvs + GVNS_CHROMEOS_ACPI_OFFSET.
BUG=b:112288216
TEST=None
CQ-DEPEND=CL:1179725
Change-Id: I74d8a9965a0ed7874ff03884e7a921fd725eace9
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/28190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix the IASL build warnings:
Object is not referenced (Name [CDW2] is within a method [_OSC])
Object is not referenced (Name [CDW3] is within a method [_OSC])
Remove the not referenced objects. They are not needed.
BUG=b:112476331
TEST=IASL doesn't give the warning.
Change-Id: I5b38d4de3f9875c5b013a49eb5146bf5916b96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28121
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Print the PMxC0 S5/Reset status bits to the console.
TEST=Inspect console for Grunt
BUG=b:110788201
Change-Id: Ia905bb325a535fd4aa7082011cdfe92f08dff2cb
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://review.coreboot.org/28020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Remove VENDORCODE_FULL_SUPPORT from /soc/amd/stoneyridge/Kconfig and
from vendorcode/amd/pi/00670F00/Makefile.inc, thus completing the removal
of VENDORCODE_FULL_SUPPORT from coreboot.
BUG=b:112578491
TEST=none, VENDORCODE_FULL_SUPPORT already not used.
Change-Id: Idb5f6dc7add1617f7a97a97ae110901b2dec0996
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a method in bootblock that can be used for printing registers.
BUG=none
TEST=compiled grunt
Change-Id: I8dff30e589761fbad92cfc2709546dba169993d8
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/28059
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By setting this register in bootblock AmdInitEnv will no longer trigger
a reset in romstage. This fixes a few vboot test failures and also
speeds up boot time.
BUG=b:111610455
TEST=Built grunt and made sure bootblock only happens once on cold boot,
and S3 resume.
Change-Id: Ie19f7a14deaef45ac63156bec6946273c1b9447e
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a function to provide a rudimentary dump of the Machine Check
Architecture registers. These values survive a warm reset.
BUG=b:65445599
TEST=Verify on a Grunt having propensity for #MC errors
Change-Id: Ib6875cabe3041e65c811d8b2232f7ac6bedd1a02
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Extend the existing reset handling features in Stoney Ridge to plan for,
and recognize, warm resets. The ColdRstDet bit is always zero on a cold
reset, and is intended as a mechanism for the BIOS to determine the type
of a reset that occurred.
Set ColdRstDet=1 after all cores have been initialized, so that any
subsequent reset may be identified as warm/cold. A later patch will check
the value during mp_init.
Change-Id: I90255918de03018c9f090bff1e56a8bda5e7365e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use the value discovered in the MCG_CAP[Count] for the number of MCA
status registers to clear. The generations should have the following
number of banks:
* Family 10h: 6 banks
* Family 12h: 6
* Family 14h: 6
* Family 15h: 7
* Family 16h: 6
Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its
MC0_STATUS address.
Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In procedure generate_cpu_entries(), the code was copied from code that
could change variables "plen" and "pcontrol_blk" based on number of cores.
This is not the case with stoneyridge (2 cores only), and there's no need
to use the variables. Remove them and replace with fixed values.
BUG=b:112253891
TEST=Build and boot grunt.
Change-Id: I0258b19960b050e8da9d218ded3f1f3bfccad163
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27877
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD ALIB Function 1 accepts the AC/DC startup state. This
is reported to be required for AMD PSPP settings.
BUG=b:112020107
TEST= build test
Change-Id: Ibb6c872d84745217912956c15d6ca2e8ba387561
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27785
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that an updated bootloader with important fixes is available at coreboot
repository, all stoneyridge boards should use it. Move the selection of
SOC_AMD_PSP_SELECTABLE_SMU_FW from mb/google/kahlee to soc/amd/stoneyridge.
BUG=b:111428800
TEST=Build and boot grunt.
Change-Id: Idf8e348efbc85569aa1163125f412c5242c46eb4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27844
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
setup_spread_spectrum is called in early_init, meaning the console is
not initialized yet. So you won't see boot block booting twice.
BUG=b:111610455
TEST=booted grunt and verified that AmdInitReset does not reboot. I had
AGESA patched to skip the JTAG check.
Change-Id: Ia036ea513ac67d4b8bcf5a78029d969a4ae012a6
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Grunt boards don't use SATA, so it should be disabled to save power.
Check if SATA is enabled in devicetree, and enable/disable the device
based on that setting.
BUG=b:112139043
TEST=Buil and boot grunt, checked the absence of SATA PCI.
Change-Id: I4a3b5f65e612e8da5bedff0c557a0850f350dfa8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
2 bits of LPC host control were originally not public, and wrongly
identified as IMC related. Now that the bits are available in public BKDG,
fix the naming of the bits.
BUG=b:111912080
TEST=build and boot grunt.
Change-Id: I1921f46c6be54eda6329c98267cec27004caadd5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27744
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Per AMD, the Integrated Micro Controller is not a supported feature of
the Stoney Ridge APU. Systems are expected to implement an external EC
for desired features. Remove all stoney IMC files and functions from
src/soc/amd/stoneyridge.
There are 2 "IMC bits" left (and used) that are not truly IMC. New BKDG
describe these bits, so a new patch will be released later to fix the
names and comment.
BUG=b:111780177
TEST=Build grunt and gardenia
Change-Id: I6a24e4c3f03d04713a030b884c611d9c64c4cb3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27651
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The careena board needs different video settings to pass eye diagram test,
which does not affect negatively the grunt board. In preparation for new
VBIOS, create code that allows changing eDP training parameter.
BUG=b:111673328
TEST=Tested in child patch.
Change-Id: Ic0452618bfc5e05b9ef8280bb8ba398ec7b4ce95
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27625
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add internal graphics device 00.01.00 to the ACPI tables so that the
ACPI PCI option ROM save functions have a proper scope to save the
ROM to.
BUG=b:111697181
TEST=Check coreboot log doesn't have "PCI: 00:01.0: Missing ACPI scope"
and check _ROM method is added in the SSDT1.
Change-Id: I2c9ef8d9dff76805b1fcde2ccceef958a5b53b4f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Put the PCIe clock pins in power-saving mode for the WiFi module to save
power.
Note: This currently does not appear to have any effect on grunt.
BUG=b:110041917
BRANCH=none
TEST=boot without this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3ff
With this patch:
$ iotools mem_read32 0xfed80e00
0x0046f3f1
Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/27465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
GPIO functions are required by the Grunt SMI handler.
Change-Id: Id729139b02c10bdd922b3df298f8f9feb1aff745
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The gpio_set function was not writing the correct GPIO register
address.
Change-Id: Ib306773ac72505977b606836bbaf3e2067324894
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/27484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It can not emit byte data without BytePrefix.
design to:
Or (Local5, GPIO_PIN_OUT, Local5)
error due to GPIO_PIN_OUT is 0x40 but 0x40 encoding means
nothing in AML spec.
so it will include next emitted string in Or:
Or (Local5, Local5, \_SB.GPW2)
fix:
Store (0x40, Local0)
Or (Local5, Local0, Local5)
BUG=b:110962003
BRANCH=master
TEST=emerge-grunt coreboot
extract SSDT then check ACPI syntax is correct
Change-Id: I7a0704112b77105826de87b14a38ed2f665224d5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/27306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Legacy IO enables access to RTC IO 0x70-0x73. This is needed for CMOS to
function correctly.
BUG=b:110817463
TEST=ran firmware_CorruptFwSigB on grunt
Change-Id: I533226ba764f567e348577d7fcf6ebe43336609a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
If IO CF9 is not enabled, hard_reset() won't do anything in bootblock or
verstage.
BUG=b:110817463
TEST=built on grunt and made sure that hard_reset() reboots.
Change-Id: I5f091077a17db3dfe5b8e8367163312db6828360
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27267
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Limit is the maximum number of bits to be tested, however it's being checked
against the number of bytes of uint32_t. when it should be number of bits.
Create a macro to provide the number of bits, and use it instead of sizeof.
BUG=b:75996437
TEST=Add debug messages to see code passing beyond the check, build and
boot grunt, check that it passed the limit check, remove debug code.
Change-Id: Id1dfda26d789183b346b20c37fec923d996b80db
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27162
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to
save power. This requires use of an additional register (Misc control
register 2) and another bit in the existing 'protect' register. The naming
of bit 0 of that register is incorrect, based on the latest datasheet
(14 June 2018) so fix that too.
BUG=b:73726008
BRANCH=none
TEST=boot without this patch:
iotools mem_read32 0xfed80e00
0x0046ffff
With this patch:
$ iotools mem_read32 0xfed80e00
0x00463fff
Also see that the PCIe clock stops when eMMC is idle and can be started by
starting disk activity.
Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-on: https://review.coreboot.org/26515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
PM registers used for generating SWS values are being stored in a static
variable within southbridge.c. In order to have it available for any source
involved in building the platform, move the storage to cbmem, using id
CBMEM_ID_POWER_STATE. Also add a variable that informs from which state
the system is waking from, extracted from register ACPI_PM1_CNT_BLK. This
variable will later be useful in detecting failed S3 resume.
BUG=b:80119811
TEST=Add code to print SWS parameters and state it's waking from. Build
and boot grunt, suspend and resume, check output for valid values. Remove
the print code.
Change-Id: Ib27a743b7e7f8c94918caf7ba5efd473f4054986
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/27109
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GSMI Set Event Log is taking more than 1K in stack. This causes the
stack to overflow into the adjacent stack. This has the side effect of
causing any CPU waiting for the SMI handler to complete to crash when
the lock is unlocked because the return pointer has been smashed.
BUG=b:80539294
TEST=built on grunt and tested by running `halt` from the OS.
Change-Id: Ib170c7d03909ef3d20831726b285178a75007b06
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/27033
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With platforms moved to RELOCATABLE_RAMSTAGE, these
overrides no longer have a meaning.
Overrides existed because AGESA ramstage did not fit within
the default 1 MiB of RAMTOP - RAMBASE, when placed low.
Change-Id: I0185875dc550de74877c94f36128d5979e5553d6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26813
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the two ranges to be used for the new callouts, AgesaHeapRebase
and AgesaGetHeapBaseInDram.
TEST=Boot grunt w/experimental blob, try different addresses
BUG=b:74518368
Change-Id: Ic7716794dc7d75f849e6e062865d6efbeb4292df
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are some acpigen functionality that have not been implemented. They
are defined as week within acpigen.c, in order to not break the build.
This adds stoneyridge specific versions.
BUG=b:79546790
TEST=Build grunt with added debug code to gpio_lib.asl. Boot to OS,
activate ACPI debug, activate S3 stress test. Interrupt stress test, do a
"cat /var/log/messages" saving the serial output. Examine the serial
output, see added debug code showing action taken. Confirm action by
reading proper register. Debug code removed.
Change-Id: I9062d889f828a3175b89e6f4a3659ebbf90eac68
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
PM1 and GPE0 are being stored directly to NVS, when actually what should
be saved is the index of the bit responsible for waking. Fix the procedures
and add definitions to the actual IO addresses to be read when recording
status and enable registers.
BUG=b:75996437
TEST=Build and boot grunt. Once in OS, execute a sleep and a wake. See the
message indicating which indexes are being save in NVS for _SWS. Try sleep
stress test, verify that the index is different from that of power button.
Change-Id: I8bafc7bb7dd66e7f0eb8499e748535bbdcac5f53
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are some acpigen functionality that have not been implemented. In
order to implement them, ACPI GPIO functions to read and write to the
control MMIO of a particular pin is needed. So as a preliminary task to
implementing acpigen functions, create a library with functions to be
accessed by acpigen generated ACPI code.
BUG=b:79546790
TEST=Build grunt, more tests with commit 0f2acbd6b1.
Change-Id: I21c014b7f2698dd9193dae3113b18ee2a7303bcf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is Garrett's patch with a bit of cleanup.
BUG=b:65442212
TEST=Was able to boot, suspend and resume on grunt.
Change-Id: I55959b59a4e60b679d959ebd77de27e5d454f5f7
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/26478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
By default we use a 1:1 mapping between GEVENT bits and the corresponding
SCI_MAP entry. However, we still must program the SCI_MAP entries
with the GEVENT number.
BUG=b:109759838
TEST=(1) powerd_dbus_suspend
(2) move finger on touchpad for ~1 second
=> system resumes from S3
Change-Id: Ie7be45264f9bfec56efc47a03071fdb924d16b6a
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26930
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
No need to provide an option to try disable this.
Also remove explicit ´select RELOCATABLE_MODULES'
lines from platform Kconfigs.
Change-Id: I5fb169f90331ce37b4113378405323ec856d6fee
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/26815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add the ACPI devices defined in ASL to the soc_acpi_name() lookup
function.
BUG=b:80280671
TEST=Add ACPI method to specific GPP bridge. Boot and verify method
with ACPI dump.
Change-Id: I5117e0d39db831364173c9c61ccdab6e34f18c59
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/26698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds and updates headers in all of the soc files that
had missing or unrecognized headers. After this goes in, we can
turn on lint checking for headers in all soc directories.
Change-Id: I8b34dcd10c692f1048bd8d6c0fe3bfce13d54967
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/26569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The default interrupt control for GPIO pins within stoneyridge is for
edge triggered, high. However, sometimes these need to change, or maybe
the interrupt needs to be reported or delivered. This was the case of
platform grunt, where the interrupt related bits were being changed
afterwards. Ideally all the bits should be programmed through the same
procedure. Create several PAD_INT definitions (for general configuration,
for trigger configuration and for interrupt type configuration) and change
function sb_program_gpios() to accept the output from PAD_INT_XX and
program all the necessary bits while keeping compatibility with other
PAD_XX definitions.
BUG=b:72875858
TEST=Add code to report GPIO and interrupt configuration, build grunt and
record a baseline. Add new code, rebuild grunt and record a test output.
Compare baseline against test, there should be no change in GPIO or
interrupt programming.
Remove code that reports GPIO/interrupt configuration.
Change-Id: I3457543bdf64ec757fd82df53c83fdc1d03c1f22
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are already reporting the Wake source, but we must also report the
ACPI wake itself.
BUG=b:79865267
TEST=firmware_EventLog
Change-Id: Id26dff46379800a63ab9b77f135d23c6382f77e6
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/26522
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
_SWS is the recommended method of wake source retrieval. Now that PM1I and
GPEI are available at NVS, add the method _SWS to kahlee/grunt ACPI code.
BUG=b:76020953
TEST=Build grunt
Change-Id: I5930438af40e6f9177462582cafb65401d9c60f4
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
ACPI _SWS needs information on PM1 and ACPI events (though events can be
read directly). Unfortunately PM1 is cleared in normal path and in resume
path. Save PM1 and ACPI events in NVS to be accessed by ACPI _SWS.
BUG=b:75996437
TEST=Build and boot grunt recording serial. Run suspend stress test, after
3 resumes closed file and examined for the message indicating what was
being saved to NVS. Two different path, normal boot (first boot) and
resume path had different PM1.
Change-Id: If3b191854afb27779b47c3d8d9f5671a255f51b5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use of device_t has been abandoned in ramstage.
Change-Id: I84fbc90b2a81fe5476d659716f0d6e4f0d7e1de2
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/26458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add 64KB to the reserved memory used for stage_cache. This corrects
an error observed when using a debug build of the AGESA blob.
Messages on initial boot
AGESA: Saving stage to cache
Error: Can't add stage_cache 57a9e101 to imd
and during resume
AGESA: Loading stage from cache
Error: Can't find stage_cache 57a9e101 in imd
TEST=boot/suspend/resume Grunt with debug and release builds
BUG=b:79154155
Change-Id: I3f27059fcef37e335d0301142ba4dedb3809e369
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/26386
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds more parameters to bootblock_main_with_timestamp() to
give callers the opportunity to add additional timestamps that were
recorded in the platform-specific initialization phase.
Change-Id: Idf3a0fcf5aee88a33747afc69e055b95bd38750c
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/26339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for any
root hubs that may be present.
The AMD Stoney Ridge platform has separate controllers for USB 2.0
and USB 3.0. The USB 2.0 ports are connected through a hub to an
EHCI controller while the USB 3.0 ports are directly connected to
the xHCI controller.
This topology is described in ACPI and the port names are exposed
by the soc_acpi_name() function.
The USB controllers are configured to scan for static USB devices
in the devicetree and use the soc_acpi_name() function to identify
them.
Change-Id: I2bb677f84a49d2531929985dba319455b88e1686
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Vendor code is compiled as a library, thus the whole library is included
into the final image. However, not all procedures are required, they are
there because original AGESA code had them. We cannot remove them, in order
to facilitate porting of fixed AGESA code. Therefor add #if throughout the
code to allow the control if unneeded procedures will be build.
BUG=b:78610011
TEST=Build and boot grunt; build kahlee and gardenia.
Change-Id: I68f9e359b2331f715a3b85486c4181866985afdf
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/26135
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
oscout system clock is present in FCH misc device.
The kernel acpi misc driver will use the resource to
register oscout system clock.
BUG=b:74570989
TEST=Tested clock enable/disable in kernel driver
Change-Id: Ia90d3abab447fb5d27f454d9d6c33d0b5c3a0f16
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/25918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This bitmask sets the USB PORTSC.DR bit for each XHCI port.
This is mainboard specific, and only for non-removable
devices attached to the XHCI port.
BUG=b:72859972
TEST=Boot grunt
Change-Id: I0488b80da1fe4e57b06d3bc7a93ad9ebbfc97749
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/26015
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The sb_set_readspeed() was touching the wrong register and
the read speed settings are handled by sb_set_spi100(). Nothing
was using the function, so remove it.
Change-Id: I23b20cf559ee759ba94d49ff6810a9baa64e86fb
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25969
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Function gpio_output() is only setting the pin as an output, when in fact
it should also set the state (high/low) of the pin. Fix the procedure to
set the state of the pin.
BUG=b:78328773
TEST=None
Change-Id: I516192a0782a9bbb40124029f264a2711114c800
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25871
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When smi.h is included to southbridge.h (to use SCI/SMI definitions within
southbridge.h definitions), this causes a collision of the definition of NONE
(ioapic.h also has a NONE definition). As NONE is an enumeration of interrupt
types (SCI/SMI), add INTERRUPT_ at the start of each definition.
This is preparation to have GPIO table/code also declare/program SCI/SMI.
BUG=b:72875858
TEST=Build grunt.
Change-Id: I5c7b798f9f4d7c2a9f9c606c7ebffb7004a37b99
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25845
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that we have SPI flash writes working, we can support
VBOOT_VBNV_CMOS_BACKUP_TO_FLASH. This requires the mainboard to reserve
the area in FMAP.
BUG=b:77347873
TEST=Manually clear CMOS and check coreboot restores VBNV from flash.
Change-Id: I488dbfc4c200f5100374d47feb0a0522e6a60e88
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25842
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The argument order for smi_write32() is offset, value. Current code had
it backwards.
So, when disable_all_smi_status() was called by sb_slp_typ_handler(),
instead of clearing pending flag SlpTypeEvent65 (0x2) in SMIx88 SmiStatus2
by writing 0x00000002 to 0xfed80288, it would instead write
0x00000088 to 0xfed80202 - clearing the lower 2 bytes of SMIx04
Event_Enable, which disabled the lower 16 GPEs from waking the system from S3.
Thus, the EC events (Keyboard / lid switch) [GPE15] and touchpad [GPE7]
did not work as wake up sources.
BUG=b:78461678
TEST=powerd_dbus_suspend, tapping any key on keyboard wakes from S3.
Change-Id: Ie4fbe6db1bb73f603dcf409117fcce93479a1f46
Fixes:081851a9e4 ("amd/stoneyridge: Add SlpTyp SMI handler")
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
smi_sources is a file local array of constants.
Change-Id: I431f181449a591ccaf8395f01a84c8e006a29b52
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/25814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Additional LPC and SPI setup needed to move AGESA out of the bootblock.
Setup the prefetch, sio decode, and a bugfix for SPI.
BUG=b:70558952
TEST=Boots with AGESA moved out of bootblock.
Change-Id: I2c0d8632b25c036ff977c21477feb4778575189c
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/25755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Julius brought up confusion about the current spi api in [1]. In order
alleviate the confusion stemming from supporting x86 spi flash
controllers:
- Remove spi_xfer_two_vectors() which was fusing transactions to
accomodate the limitations of the spi controllers themselves.
- Add spi_flash_vector_helper() for the x86 spi flash controllers to
utilize in validating driver/controller current assumptions.
- Remove the xfer() callback in the x86 spi flash drivers which
will trigger an error as these controllers can't support the api.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-April/086561.html
Change-Id: Id88adc6ad5234c29a739d43521c5f344bb7d3217
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIO definition structure has evolved to a point where it's no longer
specific to stoneyridge, though probably still specific to AMD. Therefore,
rename the GPIO declaration structure removing stoneyridge from it.
BUG=b:72875858
TEST=Build kahlee, grunt, gardenia.
Change-Id: Ib034d3f7840c36ee8f5c5384241d7326d3fe5543
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25726
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the exception of code that deals directly or indirectly with AGESA,
all other code should be independent of vendor code reference. Therefore,
remove vendor code reference from any GPIO code.
BUG=b:77999987
TEST=Build and boot grunt.
Change-Id: I9ba78767a269ad6b9b06fa11993d8a12350e4bad
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25695
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits. Fix these definitions, including the header file where they are
defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Icb5334110248d7806421200a161fa3befefcea8a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25665
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest public BKDG (3.6) releases some previously undefined (reserved)
bits, also some bits were wrongly named (possibly copied from previous chip).
Fix these definitions, including the header file where they are defined.
BUG=b:77940747
TEST=Build and boot grunt.
Change-Id: Ie8d3fcccb8443c1a6db828bdc2624778bad6ba9f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
There wasn't previously a way for Stoney platforms to run mainboard
specific code in romstage. This adds an early call for configuration
and passes along whether the system is currently resuming from S3.
BUG=b:77921345
TEST=Build, verify that weak function implementation gets called.
Change-Id: Id94855e1084814ec37956e603cd093d70f01a559
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/25635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Relocate setting the temp range MTRR, for the SPI flash device, to
after completion of mp_init. The mp_init functionality mirrors the
BSP's exact MTRR settings into the AP cores. The ranges need to be
the correct calculated values and not some temporary setting.
This solves an MTRR sync issue on APUs with more than two cores,
i.e. more than a single compute-unit. MTRRs within a CU are shared
so the AP always stays in sync.
BUG=b:77457944
TEST=run on Kahlee
Change-Id: Idc4cccdf721e252bc87d6cba62a3406a9f19b940
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As part of moving AGESA calls from bootblock to romstage, create
infrastructure to pass a pointer to the AP cores, so they can jump directly
to romstage.
BUG=b:74236170
TEST=Build and boot grunt, actual test will be performed at a later patch.
Change-Id: If716d1c1970746f2ad90ef71ae9062c99f219897
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25526
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use standard coreboot function to set virtual wire mode on
the GNB IOAPIC.
BUG=b:74104946
TEST=Check GNB IOAPIC debug output on serial.
Change-Id: I4ff8698419890df1459b1107f0861cf8277a99b0
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/25541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Replace an absolute value with a #define value in bootblock. This is
in preparation for using an additional MTRR in a subsequent patch.
Change-Id: I006c7cfa0057b3ed4a21359fc8367caf6ec5baf3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
New macros were developed that replace previous way of defining GPIO, with
pin and intention very clear while keeping the table mostly identical to
previous method (there's no pull up or pull down when a GPIO is set as an
output). Change current gardenia table to use the new macros.
BUG=b:72875858
TEST=Build Gardenia.
Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
BUG=b:77345148
TEST=Pull power from grunt, verify CMOS power failure is detected.
Reboot and verify that CMOS power failure is not detected.
Change-Id: Idbf0254e197a6d282e618a98bced52ea5a44917f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25468
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print the wake status bits to the console. The format is kept similar
to Intel's to maintain compatilibity with inspection utilities. Add
relevant wake events from the register to the ELOG. Clear the register
before continuing.
TEST=Inspect console and ELOG for Grunt
BUG=b:75020968
Change-Id: Idc9d12326abb290e4f7a5c60677eb6e057d475b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/25300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The GPIO programming of configure_stoneyridge_UART() can be done by the early
GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart()
became redundant. Remove procedure configure_stoneyridge_uart().
BUG=b:74258015
TEST=Build and boot kahlee, observing serial output does not changes from
previous serial output.
Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25192
Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Call sb_spibase() early so that it will set up the SPI base address.
This is another step to moving AGESA calls out of the bootblock.
BUG=b:74427893
BRANCH=master
TEST=Build and boot Grunt.
Change-Id: I665d32f3acb0046eb6abbd363735561f0372f2a0
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
It was required for all cores use the same CAR teardown function
(exit_car.S and gcccar.inc). AGESA has already been modified to do the
AP to do the call out. Create assembly code to call chipset_teardown_car
and then enter an endless loop with halt instruction. Then create the
call out that will call this new assembly code.
BUG=b:70338633
AGESA COMMIT=3313d277
TEST=Created a debug version of AGESA that would print the returned
status of HALT_THIS_AP. Build code without the fix, see the return.
Build code with the fix, see that there's no return.
Change-Id: I05ee405812211d93dfdbdc5ee7d9978c2eb585e1
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/24999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Devices that need to have their AOAC register enabled do have a delay before
they become available. Currently each device has their own wait loop. Create
a procedure that initializes all AOAC devices in a table and wait for all
AOAC to become alive, then call this new procedure before the call to
initialize the UART. Then change all procedures that initialize some AOAC by
moving the devices to the table and removing AOAC initialization code.
BUG=b:74416098
TEST=Build and boot kahlee checking that UART is sending debug messages out.
Change-Id: I359791c2a332629aa991f2f17a67e94726a21eb5
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Call function sb_acpi_mmio_decode() from bootblock_fch_early_init().
This enables decoding of the FCH ACPI MMIO regions 0xfed80000 -
0xfed81fff. This is another step to moving AGESA out of the bootblock
for StoneyRidge
BUG=b:74586747
BRANCH=master
TEST=Build and boot on Grunt.
Change-Id: I8cf329e5cd2002b225742fefa5c1ddd2598de674
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25161
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for moving AGESA calls out of the bootblock:
* Add sb_tpm_decode to enable FCH decoding of TPM 1.2 regions and Legacy
TPM IO 0x7f-0x7e and 0xef-0xee
* Modify sb_tpm_decode_spi to additionally call sb_tpm_decode.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: I0e2399e113c765393209dd11fd835fc758cf3029
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
In preparation for moving AGESA calls out of bootblock:
Add function to enable the four stoneyridge I2C engines.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt (with other changes
to call code not committed at this time)
Change-Id: Icb55c49cf56c65a9c2e1838cff1ed5afc04e1826
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25026
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In preparation for moving AGESA calls out of bootblock:
* Add definitions for needed registers in southbridge.h
* Add function to enable AMD FCH ACPI MMIO regions 0xfed80000 to
0xfed81ffff. Will be called by a later commit.
BUG=b:65442212
BRANCH=master
TEST=abuild, build Gardenia, build boot Grunt (with other changes
to call code not committed at this time)
Change-Id: If26efa6c6f5b562ba898e7d9da4827833310dc26
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25025
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
File soc/amd/stoneyridge/sm.c has a CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
that's not used at all and has no control. It's also not used in the
build process. Remove the define from sm.c, create a true Kconfig
definition and use it to define if power should be restored after a power
failure/recovery.
BUG=b:72873003
TEST=Build kahlee. Use serial output to check what is being programmed
to RTC shadow. Build with and without selecting the Kconfig parameter.
Then remove serial output and leave the parameter unselected (always S5
at power recovery).
Change-Id: Iec82cb68cf1e2a820e610f12d8620488662232aa
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/25002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Limit dependency on vendorcode header files and use defines from
iomap.h and southbridge.h
* Factor out to functions, device power-on code for AMBA and UART.
BUG=b:69220826
BRANCH=master
TEST=abuild, build Gardenia, build and boot Grunt
Change-Id: Ibcf4d617e2a0a520a6d7e8d0d758d7a9705a84ea
Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/25010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The SMBus PCI device ID for Stoney wasn't updated when the code was
pulled over from hudson. This means that the IOAPIC wasn't being
initialized in coreboot.
BUG=b:74070580
TEST=Boot Grunt, see IOAPIC init messages in console.
Change-Id: Ida5d3f3592488694681300d79444c1e26fff6a1a
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/24930
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The printk() calls in sb_program_gpios() aren't necessary, and incur a
13 second delay if the function is called from
bootblock_mainboard_early_init(). This commit removes them so GPIOs can
be set up earlier.
TEST=call sb_program_gpios from bootblock_mainboard_early_init
BUG=b:73898539
Change-Id: I064291decf47d86132e36469e029b3262ec20172
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/24915
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The resource allocator was overly complicated due to porting
from a multi-node resource allocator. It had some assumptions
about the UMA memory and where it would be located. The
refactored allocations account for UMA being reserved above 4GiB.
TEST=Check CBMEM table has correct RAM regions.
Change-Id: I722ded9fb877ec756c3af11fcb5fea587ac0ba8e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit defines a set of macros for defining GPIO configuration that
are easier to read than the raw iomux function values used today.
TEST=None
BUG=b:72875858
Change-Id: Ie100c8494c565afa28fa44d78ff73155fc8c7ea8
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23828
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a function to configure interrupt settings for a GPIO. This does
not currently configure GEVENT signals.
The second function returns the GPIO interrupt status and clears the
flag if set.
BUG=b:72838769
BRANCH=none
TEST=Update and test interrupt settings for GPIO_9 on grunt
Change-Id: I1addd3abcb6a57d916b1c93480bacb0450abddf2
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Save the UMA values from AGESA to use in resource
allocation in ramstage.
Change-Id: I2a218160649d934f615b2637ff122c36b4ba617e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23817
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These typos were found through manual review and grep.
Change-Id: I6693a9e3b51256b91342881a7116587f68ee96e6
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This makes the flow for GPIO initialization more closely follow that
what is performed for other boards so that it's easier to read the flow
(and stops relying on BS_WRITE_TABLES).
BUG=b:72875858
TEST=Built and booted grunt, built gardenia.
Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23679
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the remaining model_15_init.c functionality to cpu.c, making it
similar to other soc implementations.
Change-Id: Ic8c62b09209fcdaa50ff8ffc7773ef155f979a1b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23724
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Add the X86_AMD_FIXED_MTRRS select back to Kconfig. This got lost
when stoneyridge was converted from a cpu/northbridge/southbridge
implementation to soc/.
Remove the setup from model_15_init.c because this is duplicated
functionality.
BUG=b:68019051
TEST=Boot Kahlee, check steps with HDT
Change-Id: Id5526dcff12555efccab811fa3442ba1bff051bb
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the correct conversion specifier `z` for `size_t` to fix the error
below.
```
error: format '%lx' expects argument of type 'long unsigned int', but \
argument 4 has type 'size_t {aka unsigned int}' [-Werror=format=]
```
Found-by: gcc (Debian 7.3.0-3) 7.3.0
Change-Id: I05d3b6c9eec0ebf77cdb9e9928037e837f87ea03
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/23770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
LAPIC setup is required to set virtualwire mode for legacy interrupts.
This was omitted when stoneyridge was changed to use the common mp_init.
BUG=b:72351388
TEST=Verify keyboard now works in SeaBIOS
Change-Id: I648d8b5b5a3744a5781446c7cb72934a071f9a72
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23718
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a function to allow an external region to be located in TSEG.
Select the option to use memory outside of cbmem. Increase the size
reserved in TSEG.
Change-Id: Ic1073af04475d862753136c9e14e2b2dde31fe66
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Provide a method for initializing i2c buses that are not marked as
early_init in the device tree. These i2c buses can be enabled in a
mainboard's ramstage, for example.
BUG=b:69407112
TEST=Boot depthcharge w/ CLI enabled on grunt.
devbeep
=> plays beep
BRANCH=None
Change-Id: I6e49b0de9116138ba102377d283e22d7b50d7dca
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A file that has several methods cannot be included inside a method. It has
to be included inside a scope, but not inside a method or it'll cause
problems (instability).
There is an ugly construction in method _INI. It's needed because if AmdImc
is not included then the call to ITZE would break the build.
BUG=b:62200858
TEST=Build kahlee.
Change-Id: If6c877df5a87df1b348de92868b91eed4a76de55
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Delay making TSEG valid until the end of POST. After the CPU setup,
there are times where coreboot needs to access the SMRAM from outside
of SMM. Also relocate locking of the SMM settings from the CPU init
to the end of POST (or just before resuming).
Change-Id: I70b7e33e7045d397e41f571caff6a2acbb64eaab
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The path for the GPIO devices needs to be '\_SB', not '\SB'. Fix
the path so that it references the system bus.
BUG=b:72121803
Change-Id: I7c6c38ecea0f8f95ff52b3390f92c5b7e79bcd6d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23501
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SPI controller on stoneyridge apparently has a large fifo
and an alternate method for programming the controller. The
fifo is directly accessible as well as the rx and tx pointer
in addition to the execute bit. Remove the unneeded #defines
and program the host controller with the above changes in mind.
In addition, add debug hooks to the driver so one can dump the
state of the controller when in operation.
The time it took to read 4KiB of flash in the elog driver went
from 20593 microseconds to 5693 microseconds on cdx03/kahlee.
BUG=b:65485690
Change-Id: Ie7ea9d18cef5511686700ad9b2b9fdfeb6d5685b
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23493
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The spi flash host controller has a dedicated register for the
opcode. Therefore, indicate to the spi subsystem that the opcode
size should not be taken into account when determining maximum
payload size in spi_crop_chunk(). This allows the full use of
the fifo when doing transfers.
BUG=b:65485690
Change-Id: Iab27a69ca72fd02bc443f0673983f3b22ffca0f5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23492
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
spi_crop_chunk() currently supports deducting the command length
when determining maximum payload size in a transaction. Add support
for deducting just the opcode part of the command by replacing
deduct_cmd_len field to generic flags field. The two enums supported
drive the logic within spi_crop_chunk():
SPI_CNTRLR_DEDUCT_CMD_LEN
SPI_CNTRLR_DEDUCT_OPCODE_LEN
All existing users of deduct_cmd_len were converted to using the
flags field.
BUG=b:65485690
Change-Id: I771fba684f0ed76ffdc8573aa10f775070edc691
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23491
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The scratch registers in northbridge used for storing the top of
cacheable memory are volatile. Use the BiosRam storage in the FCH
instead.
TEST=Suspend and resume Kahlee with complete S3 patch stack
BUG=b:69614064
Change-Id: Ieb3cfd173c70bf899a6391d62d1df87b38485f30
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the BiosRam read/write functions to use the fixed MMIO range at
0xfed80500. This is faster than two accesses per byte when using I/O
0xcd4/0xcd5.
Note that BiosRam may only be accessed byte-by-byte. It does not decode
normally.
Change-Id: I9d8baf2bd5d9d48a87bddfb6a0b86e292a8fdf7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23436
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The following two patches were independent, but they were
merged together. However, the first one changed the API
that the second was originally was written against. Fix build.
b94a2750 (i2c/designware: reduce API complication for bus config)
13101a7b (soc/amd/stoneyridge: Add I2C devicetree support)
BUG=b:72121803
Change-Id: I3678a8f414572dd2227c42ce5585daf6bc933df5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23445
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The TSC rate is empirically swinging during early boot. That
leaves timestamps and udelay()s to not be correct. To rectify this
stop using TSC for all of these time sources. Instead use the
performance TSC which is at a fixed 100MHz clock. That provides
stable time sources and legit timestamps.
BUG=b:72378235,b:72170796
Change-Id: Ia2693c415c557aac687bcb48ee69358ea1c53d67
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit adds device name to ACPI name bindings for various entries
in the devicetree.
BUG=b:72121803
Change-Id: I5564e4a7e56fdd1bc9f34497bdb78383093a2ba3
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
3rdparty/blobs was updated to move northbridge/amd/00670F00 contents into
soc/amd/stoneyridge. Now soc/amd/stoneyridge/Kconfig needs to be updated
to use VBIOS.bin new location.
BUG=b:70785272
TEST=Update 3rdparty/blobs master branch, try to build kahlee. It should
fail. Update soc/amd/stoneyridge/Kconfig, try to build kahlee again, it
should work (need to rebuild .config first).
CQ-DEPEND=CL:881709
Change-Id: I8cb9874eedc4a5d41d42b3f727c6d3cb9b920b5a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The CAR APIs already exist to deal with proper type useage.
Don't open code things that already exist.
BUG=b:65485690
Change-Id: I09593401513f6060a30cf5c02c94d14afbe8f4fd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
The TSC has been observed to be ticking at a non-constant rate
in early boot. The root cause is still not known, but this
misbehavior necessitates an alternative monotonic timer source.
Use the perf TSC which ticks at 100 MHz. This also means the
timestamp table is not accurate as well. Root cause of TSC rate
instability needs to be resolved in order to fix that.
BUG=b:72170796
Change-Id: Ie052169868a9d9f25f8cc0ce8dd8251b560e671f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23397
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add new function sb_program_gpio to be called after AGESA init_reset
and some point within ramstage. For AGESA init_reset, change
amd/stoneyridge/bootblock/bootblock.c function bootblock_soc_init
(add the function after the call to AGESA function).
BUG=b:64140392
TEST=Build kahlee, grunt, gardenia.
Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22987
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
CONFIG_STONEYRIDGE_SATA_MODE is compared against "magical numbers".
Because actual literals are in AGESA.h and adding agesa_headers.h to
southbridge.h causes compile errors, move comparison code from southbridge.h
to southbridge.c (where they are actually used). Replace these numbers
with actual literals.
BUG=b:71754828
TEST=Build kahlee.
Change-Id: I711473bf492d5ceca026ccd112c2c389a23bdbf9
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
At AGESA AmdInitReset, SATA enable and IDE enable (elements of
FCH_RESET_INTERFACE) are programmed twice (before calling AGESA
for AmdInitReset and from said AGESA function call out), using
different functions with different results. The first would result
in TRUE/FALSE, the second set would result in TRUE/TRUE. Use the
functions of the second set within the first set, and remove them
from the second set.
BUG=b:71754828
TEST=Build kahlle without the change, boot and record output. Rebuild
kahlee with the change, boot and record output. Compare both outputs,
the should be no change except in timing.
Change-Id: I326fcc8801542aa7feef286d02abdfe63354cdd0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove the BiosRam read and write functions that were brought over from
the hudson source. The functionality will be superseded later with new
general-purpose functions.
Change-Id: Ib80c66b838fdbdd388a392b4fedaac36bf0bbb0c
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22725
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The internal FCH contains 256 bytes of "BiosRam" that maintains its
state until RSMRST# is asserted or standby power is lost. Add functions
to support read and write operations.
Change-Id: I2ddf58a63e69b2775de9a8163534b13dad2ea2fe
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Relocate the acpi_get_sleep_type() function out of the southbridge
ramstage file. This will make it more convenient for using elsewhere.
Change-Id: Id7ba709bb867fb00ed6c7fa7526de087a3b9b3ca
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The ACPI unique identifier (_UID) should be unique.
This doesn't actually matter much for Linux, though, since the kernel
can handle it when the BIOS doesn't get this right.
See:
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=b4b6cae2f36d92b31788f10816709d5290a1119a
b4b6cae2f36d ACPI / platform: use ACPI device name instead of _HID._UID
Change-Id: I8b1b3143174584a93f3d45bf482b8922b3f0ec12
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
A side effect of using the common MTRR assignment code is the flash
device loses its WP setting and is no longer cacheable. After MTRR
setup, reenable the setting for the duration of POST.
TEST=Run on Kahlee and inspect MTRRs prior to AmdInitLate()
BUG=b:70536683
Change-Id: Ib4924e96e2876e1e92121bb52d1931ead723d730
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/23205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
The i2c_bus_address array doesn't need to be a global symbol.
Also, the array initializer had some weird indention and there
was an extra new line. For consistency the first entry is multiplied
by 0 so the formatting is similar.
BUG=b:69416132
Change-Id: I74f6dca3a22a245759536f792ce04ac61735b6d0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23170
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The build system for the SeaBIOS payload needs this when
DRIVERS_UART_8250MEM is set. Set it to the first uart controller,
which the coreboot code also seems to do.
Fixes: https://ticket.coreboot.org/issues/150
Change-Id: I962f750f89e0352082e0b7415ceaa9bd350fdf0b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stoneyridge related contents of 3rdparty/blobs/southbridge/amd/kern were
moved to 3rdparty/blobs/southbridge/amd/stoneyridge. Commit the new blob
to coreboot, and modify src/soc/amd/stoneyridge/Kconfig to use it.
BUG=b:69613465
TEST=Build and run kahlee.
Change-Id: I1784824dc7767c620e2fcbad7c6e5674934832ff
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Issue first reported at commit 1587dc8a2b, the call of functions
setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev()
to soc_init(). The function setup_uma_memory() no longer exists, its
functionality transfered to agesawrapper_amdinitpost.
Move setup_bsp_ramtop() as required.
BUG=b:62240756
TEST=Build and boot kahlee.
Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22948
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Stoneyridge has an RTC. Elog requires it for timestamps.
BUG=b:65485690
TEST=Build Kahlee with Elog. Check mosys eventlog list for
timestamps.
Change-Id: I4d820fbe11043e7e3153d67159f52274d5f14bae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22961
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A subsequent patch to the PSP library will rely on the device already
having its PCI command register set to allow memory decoding and
mastering enabled.
Program the command register ahead of loading the SMU FW1 blob in
bootblock. When the device has not been set up (e.g. when SMU FW
is not selectable), AGESA sets up the device. As a result, a
similar change is not required before sending the DRAM ready
command.
Change-Id: Id586106751286c4767b5c16ed7e1604523635492
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In function load_smu_fw1(), variable base receives one value and is
immediately overwritten. Remove the first line, as it's useless.
This fixes CID 1383612
BUG=b:70620140
TEST=Build kahlee and boot.
Change-Id: I1a1eae52722606a9e871e26faa7927e207102ae8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22873
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The AGESA wrapper should not use and CONFIG_STONEY* values, nor should
it make any assumptions about the capabilities of a particular device.
Move these into stoneyridge northbridge and southbridge files.
BUG=b:70670425
TEST=Build and run Kahlee
Change-Id: I706edbb6a048b64389ba3077d5df0fe6155070b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Solve issues related to agesawrapper_call.h that came up at review
75dd50e233 (review 19724). This includes a hard coded table size and
2 macros: AGESAWRAPPER_PRE_CONSOLE() and AGESAWRAPPER().
Remove AGESAWRAPPER_PRE_CONSOLE(), and replace AGESAWRAPPER() calls with
the actual content of the macro.
BUG=b:62240989
TEST=Build kahlee with no errors, boot recording serial output and compare
to serial output from a build without these changes.
Change-Id: Ic51917d3961a51d4e725ff45b04f45eefe149855
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22850
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove "\t" from name strings in soc/amd/stoneyridge/southbridge.c array
irq_association[], and change the print string in soc/amd/common/amd_pci_util.c
that use the names from "%s" to "%-20s". This sets a fixed field of 20
characters for the string name, allowing for variable length to the names
(up to 20 characters), thus saving memory space used by the strings.
BUG=b:70344551
TEST=Build and boot, record output of irq routing and verify alignment.
Change-Id: I92dfac9b64932fb0cd3359abd4d1aac651535f1a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Move AGESA related source files in soc/amd/common under block directory.
Folder soc/amd/common/block subfolders should mimic soc/intel/common/block
subfolders (one subfolder per subject).
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I497cdefe64e8dff00aaff7153c4ffa9c57c9acf8
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22792
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
- Change soc/amd/stoneyridge/Kconfig to set BOOT_DEVICE_SUPPORTS_WRITES
BUG=b:65485690
TEST=Build & boot kahlee.
Change-Id: I595a27ac27daa42c2499de1a343bc30be9a89fa6
Signed-off-by: John E. Kabat Jr <john.kabat@scarletltd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Due to review 20b8c821e4 being abandoned and review 376dc82dca being
merged, file amd_pci_int_types.h became orphaned (not included by any
file), while an array similar to intr_types[] (but that also includes
the associated register index) was created in southbridge.c replacing
the original array functionality.
Remove the header amd_pci_int_types.h from the repository.
BUG=b:70328428
TEST=Build kahlee with no errors.
Change-Id: I53a9d7ebb27edbc4e136c9b17f5c709930e35223
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We only need the apu firmware in the RO region when building
for ChromeOS. Adding it to the RW regions is a waste of space.
BUG=b:70027919
TEST=Build kahlee and use cbfstool to check for "apu/amdfw" sections.
Change-Id: Ieafe4a5ec4a5e3177e4e23fcf42afa2626a0b19f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the new wide IO functions from southbridge.c to simplify code in
functions set_child_resource and lpc_enable_childrens_resources.
BUG=b:64033893
TEST=Boot to OS, check serial output against previously recorded serial
output from an image without all 5 related changes.
Change-Id: I8533e8ff766df8a8261298559aace7666487826d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create new generic wide IO functions in southbridge.c. These new
functions must be usable by kahlee/ec.c and amd/stoneyridge/lpc.c.
BUG=b:64033893
TEST=Just build at this stage, full boot to OS and verify serial output
at related change 14fdd03a83. Some extra outputs for testing removed
when code was committed.
Change-Id: Icd0841a1959f3e109b3c35fa35bb4b3c44099dc3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Table intr_types[] is hard to maintain, and has unused spaces filled with
NULL. A new table format is needed that creates strong association between
the APIC register index and the associated IRQ name, is easy to maintain
and has no unused space (index) to indicate that a particular register is
unused while still indicating which registers are valid.
Also, the string that defines the name of associated IRQ should be declared
with "#define" in a header, but must be physically initiated in a source
file. The "#define" must make a strong association between the used register
index and the associated IRQ name. Example:
#define INDEX_0X16_NAME "PerMon\t"
BUG=b:69868534
TEST=Check serial output against BKDG for AMD Family 15h Models 70h-7Fh
Processors definitions for Pci_Intr_Index. Also, check for new output
format to confirm write_pci_int_table() is working as desired. There's
no test for write_pci_cfg_irqs, as it's not being used by kahlee.
Change-Id: I2dde4d016cc3228e50dcfadd2d3586a3609e608d
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add USB overcurrent support. Adds a weak call for mainboards
that don't suport USB OC.
BUG=b:69229635
Change-Id: Ie54c7a2baa78f21cf1cd30d5ed70c8c832cf3674
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
