The ASL 2.0 syntax for "!X" resolves to "LNot(X)" which will evaluate
the object as an integer and turn into a boolean. This may not do the
right thing if the object is actually a string and it can lead to
unexpected behavior.
Instead be specific about the object type and check for zero or an
empty string depending on what is being returned.
This fixes an issue where some VPD keys were causing the search to
stop and miss subsequent entries.
Change-Id: I1688842964f9c2f81ca31073da9c2d71a8c81767
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The definition of bootblock_systemagent_early_init was guarded by
!ENV_RAMSTAGE. But it's only called in the bootblock. So guard it
with ENV_BOOTBLOCK instead.
Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Should include vb2_sha.h header when SHA library functions or
constants are required. This replaces NEED_VB2_SHA_LIBRARY.
BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I9f32174dbf3de05fbe5279cb8017888757abf368
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583820
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Input: tell vb2api_fw_phase1 if display unconditionally available
Output: vb2api_fw_phase1 may request coreboot to initialize
display, if needed based on some internal request
Move setting the VBOOT_FLAG_DISPLAY_REQUESTED flag into
verstage_main.
BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I81c82c46303564b63b8a32e7f80beb9d891a4628
Cq-Depend: chromium:1564232
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The VbInitParams struct will be deprecated. Remove its
use in preparation.
Additionally, remove use of the flag
VB_INIT_OUT_ENABLE_USB_STORAGE, which is no longer used
downstream since vboot_reference CL:347257.
BUG=b:124141368, chromium:960226
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ibe02cb6ba639de0d7cbdf79fc4dbf49044c92278
Signed-off-by: Joel Kitching <kitching@google.com>
Cq-Depend: chromium:1583943
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32664
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.
BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add functions to read and write the region in the AcpiMmio block.
Convert gpio.c to use them instead of creating pointers.
Change-Id: I2a0f44b6ec7261648cf0357b44a6c18dd40d1504
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add 16 and 32-bit versions of read / write_misc functions. Find one
access of the MISC block still using read8() and write8(), and convert
it.
Change-Id: I296c521ea7f43210db406013bbe79362545ce6f3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add 8-bit functions to access the AOAC registers and use them in
southbridge.c. At this time, there is no reason to pursue WORD or
DWORD access and it's not known if those transaction sizes are
supported.
Change-Id: I3a8f493625f941fb855c0b8a0eff511a9a5ddfe8
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Convert smbus_read8() and smbus_write8() functions to use the same
arguments as the other AcpiMmio blocks, and add 16 and 32 bit versions.
Add matching functions for the ASF controller.
Change-Id: I3b0ecf21f20472245da98ab5e711a54e99dca93a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
In preparation to move code to a common directory, rearrange some of
the functions in sb_util.c. Add various comments. This change should
have no functional differences.
Change-Id: I1ad55a4a14a27e45459dcaf2fcc7449e29da6d4b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default
Also build test VBOOT on Lenovo T420.
Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.
Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Add function to wait for sense registers to become valid.
* Add function to retrieve Fn-Key state.
Tested on Lenovo T500:
* It takes about 700msec for the registers to become valid.
Tested on Lenovo T520:
* It takes less than 150msec for the registers to become valid.
Change-Id: Ie27e2881a256c4efb3def11f05070c446db6e5fc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29204
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Mark all known PCIe root ports as ExpressCard slot.
Tested on Lenovo T520.
Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Use the devicetree values for type 9 slots.
Tested on Lenovo T520.
Change-Id: I1961d8af2d21f755ff52ad58804ea9b31d2a5b9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32308
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Ignore NONE devices in dev_is_active_bridge that are commonly used to
indicate hotplug capable ports.
Tested on Lenovo T520:
The empty ExpressCard Slot is no longer marked as active bridge.
Change-Id: I23347270aaab17647023969091ce4bcdd41dd57a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add the new field 'smbios_slot_desc', which takes 2 to 4 arguments.
The field is valid for PCI devices and only compiled if SMBIOS table
generation is enabled.
smbios_slot_desc arguments:
1. slot type
2. slot lenth
3. slot designation (optional)
4. slot data width (optional)
Example:
device pci 1c.1 on
smbios_slot_desc "21" "3" "MINI-PCI-FULL" "8"
end # PCIe Port #2 Integrated Wireless LAN
Tested on Lenovo T520.
Change-Id: If95aae3c322d3da47637613b9a872ba1f7af9080
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
SMM final locks the SPI BAR, which causes flashconsole to hang.
Re-init it like SMM does with CONFIG_SPI_FLASH_SMM.
Change-Id: Ib802d7ee32f1fb0a68a84b0280480dcaefa9831f
Signed-off-by: Dan Elkouby <streetwalkermc@gmail.com>
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Checking the PrimaryDisplay parameter (added by patch with Change
Id Ie3f9362676105e41c69139a094dbb9e8b865689f) isn`t required. The
display connected to PEG works even if IGD is primary for output
image and at the same time this device is disabled
Tested on Asrock H110M-DVS with NVIDIA GTX 1060 GPU
Payload: tianocore edk2-stable201811-216-g51be9d0
Change-Id: I5615597881a151bb004676d914fbf40874ac1f68
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32615
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The DRAM base memory should be calculated even if IGD isn`t defined
in the board device tree
Tested on Asrock H110M-DVS
Change-Id: I3da51473e6c06da803bd969a4a6dff792c18f962
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
never consumed anywhere again. So just merge the used code into
`romstage.c` where it's effectively used.
Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.
Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
`chip.h` is usually used as devicetree interface.
Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: Ibc013ccea9f83ef29f22fe2da4c0d12096308636
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
These are part of a common concept and not SoC specific.
Change-Id: I9cb218d7825bd06a138f7f5d9e2b68e86077a3ec
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
It was only used locally.
Change-Id: Iaaad760e8ceca62655f5448c30846cf11959e8e1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The MacBook Air 4,2 uses eDP, according to the schematics.
Change-Id: Ifc98eab343fd89b8512e92e01fddf34ef8447d5f
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn off camera power when s0ix for power saving.
BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix
Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.
BUG=b:131876963
TEST=boot up and check SD card functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Remove use of deprecated GoogleBinaryBlockHeader struct, and
replace with vb2_gbb_header.
BUG=b:124141368, chromium:954774
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Iee3bd877cb1791a689efdeabda324f43f7d0c6f2
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The file is no longer used by any code. Remove it.
Change-Id: I73f06cac11201dc37218d352ab995cf4f012c36a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Part of this checks whether tolum_base and cbmem_top are the same - however,
cbmem_top hasn't been initialised at the point where this call occurs.
Change the ordering to fix that.
Signed-off-by: Matthew Garrett <mjg59@google.com>
Change-Id: Ib89e0513bdc35c3751a9d4c2a2789a2836046789
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reset GPI Interrupt status and enable registers from ramstage instead of
bootblock so that it applies to devices in field.
BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: Ib11b580ceb23bd1fe789f549b667a8ced2d859a1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A hook for romstage is already existing but not for ramstage.
It's very useful for debugging as it allows to run code
for testing purposes by the mainboard. Also, it allows to
run configuration code or configure FSP options, which
don't have a devicetree option.
Change-Id: I9edc543943c5cbc696fc6c615cb77ef68294c980
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Remove the bridge enable step of accessing D14F0x64. This method for
enabling the bridge appears to be last present in the SB700 device.
Beginning in the SB800 (and all FCH, SoC devices), the enable is in
PMxEC[0]. Since the bridge is enabled in bootblock to allow port 80h,
there is no need to maintain it in ramstage.
Correct the device used for misc. configuration of the LPC bridge.
The #defined value removed is 14.0 but the settings are in 14.3.
TEST=Boot Grunt, check console and dmesg for errors and warnings
BUG=b:131862871
Change-Id: I078be974dc3c78c94cb7c0832518f21bac029ff2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Relocate the function to the more appropriate file.
Change-Id: I92a3e8d0461ae228f6c01567db159e2458de5f6b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I can't claim that I really understand what this code does, but it looks
like there are platforms that use code from lib/spd_bin.c without
enabling CONFIG_GENERIC_SPD_BIN. Some functions in that file contain
references to CONFIG_DIMM_MAX, so that option probably shouldn't depend
on CONFIG_GENERIC_SPD_BIN.
Change-Id: I041c52b6bd255e9a9920e5a101165ba5fc5fa6f3
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32548
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the Librem 13v3 as a separate board; instead build a
single firmware image for the 13 v2/v3 boards.
Clean up Kconfig options:
- remove entries for 13v3 board
- fold entries into a single line where possible
- remove redundant MAINBOARD_VERSION option (will default to 1.0)
- remove unused microcode length/location (only needed for FSP CAR)
Test: build/boot Librem 13 v2/v3 boards with same image
Change-Id: Ic09b8ec5c576f4c4c48ef30ee3f60a4c2c286cd3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The {read,write}_index functions expect a 32 bit value, as
do the bitwise operations.
Found-by: Coverity Scan #1229584
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Idc2bc46c899d5a4e8b089644dca076a88d97dd7c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Make use of:
* southbridge/intel/common/rcba.h
* southbridge/intel/common/pmbase.c
* defines in pch.h
Get rid of dependency to DEFAULT_RCBA.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I879fce6a5bb80499e1986e618a1422a7aaa3a0c0
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32066
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Run CPU at the highest freqency (1989MHz) to speed up the boot time.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When we increase voltages, it takes 200us for voltages to stablize.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I5f32035693b6084dbe763411c612ae5d1f7c9e48
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.
BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest
and waking from s0ix confirm this works. The output of /proc/interrupts
confirms the correct interrupt is triggered.
Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Added macro named PAD_CFG_GPI_GPIO_DRIVER_SCI, for pads that need to be
configured as GPI, GPIO Driver mode, and SCI interrupt.
Also remove PAD_IRQ_CFG_DUAL_ROUTE macro (subsumed by
PAD_CFG_GPI_IRQ_WAKE).
BUG=none
BRANCH=none
TEST=Compiles
Change-Id: I0332c64e2fa62ce29c772444606adbfdf9c9afc4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32485
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change removes all the separate entrypoint dispatch
functions as they all share the same pattern.
Furthermore, none of the function definitions under vendorcode
binaryPI/AGESA.c file have proper declarations, the ones compiler
picks up from AGESA.h are for the internal implementations and
with sanely organized headerfiles would not be exposed outside
the build of AGESA at all.
Change-Id: I0b72badc007565740c93b58743cfd048e8b42775
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31485
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.
Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The entry for drivers/intel/fsp1_0/Kconfig was added under the
chipset menu before addtional FSP versions were added, and the
drivers/*/*/Kconfig entry added to support them. This results
in the fsp1_0 Kconfig items being duplicated in the Chipset and
Generic Drivers menus.
Remove the chipset entry since it's no longer needed.
Test: select FSP 1.0 mainboard (e.g. intel/minnowmax) in menuconfig,
observe FSP 1.0 Kconfig entries listed only under Generic Drivers menu.
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: If1e78fb9259b1a46d308db829881eb3b3d17cf40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32565
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.
BUG=N/A
TEST=Build Google Banon and Google Cyan
Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
DDR Training data
QCLib serial console output
DDR Information (base & size)
limits cfg data
TEST=build & run
Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
TEST=build & run
Change-Id: I222a56f1c9b74856a1e1ff8132bab5e041672c5d
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25207
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that support has been added for using the public FSP
repo for Braswell platform, clean up Kconfig options and
set sane defaults when using it.
The following changes have been made:
- add option to use the 3rdparty/fsp repo for Braswell platform
- reorder FSP 1.1 Kconfig entries for improved flow/readability
- set the default path for the FSP binary based on use of FSP
repo and platform
- set the CBFS location for the FSP binary based on platform
Change-Id: Ie2f732bf0ac4d4551908caa56360b8bb2869b4c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.
To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.
Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.
Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.
BUG=b:131144464
TEST=waveform test and hardware validation result pass.
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
BUG=b:122540489
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage
$cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat &
retrieve ssdt.dat from DUT &
$iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio"
under _DSD object
Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.
Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.
Includes Super speed mode support.
TEST=USB keypad and mass-storage device enumeration tested with this patch
Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: I38d086c379a3c2f54d1603a2fed5b33860f7f4d7
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Change-Id: Idebbbd89de05d949e6f953aa49d8662d64383d1a
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This implementation corrects the GPE DWx mapping for GPIO groups.
The assignments is done in GPIO MISCFG register for all GPIO communities.
And configures the which GPIO communities get register as Tier1.
Change-Id: I9c306d46e5194944def26c24cdb95f5ebada42b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch ports CB:32275 changes from CNL to ICL.
Ice Lake require that FSP-M component should be
XIP. This change selects FSP_M_XIP so that the right arguments are
passed into cbfstool when adding this component.
Change-Id: Icc5550f1f94957fa1b28c8bba6fc0efee98e233e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32507
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ports CB:31787 and CB:31908 changes from CNL to ICL.
This change moves soc_fill_power_state and soc_prev_sleep_state to
pmutil.c. It allows the functions to be used across romstage and smm.
Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
Change-Id: Ib7ab95b7bbcc97a076d27a11db2105f7b976b521
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32506
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ports CB:30718 and CB:31908 changes from CNL to ICL.
Add logging of chipset events on boot into the flash event log.
This was tested on a google/dragonegg board to ensure that events
like "System Reset" are added to the log as expected.
Also fix GEN_PMCON bit checks as below:
ICL PCH has PWR_FLR, SUS_PWR_FLR and HOST_RST_STS bits in GEN_PMCON_A
and so this change updates the check for these bits to use GEN_PMCON_A
instead of GEN_PMCON_B.
Change-Id: I25ec32e81f8801f8d5e69c6095ffed73d75dded6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
This patch ports CB:31902 changes from CNL to ICL.
The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.
Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit 351e3e5 ("src: Use include <console/console.h> when appropriate")
has broken the build here, see below, so we include console.h here again.
In file included from src/device/oprom/x86emu/x86emui.h:65,
from src/device/oprom/x86emu/debug.c:40:
src/device/oprom/x86emu/debug.c: In function 'x86emu_dump_regs':
src/device/oprom/x86emu/debug.h:46:22: error: implicit declaration of function 'printk'; did you mean 'printf'?
[-Werror=implicit-function-declaration]
#define printf(x...) printk(BIOS_DEBUG, x)
^~~~~~
src/device/oprom/x86emu/debug.c:366:5: note: in expansion of macro 'printf'
printf("\tAX=%04x ", M.x86.R_AX );
^~~~~~
Fixes: 351e3e5 ("src: Use include <console/console.h> when appropriate")
Change-Id: I75d0b7c08bfa6dcb07778bbb762223b62cfc3da7
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Chromebook doesn't require support wake on LAN in S5.
Disable it by default for power saving.
BUG=b:131571666
TEST= check LAN indicator is off under S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
a 1M CBFS size is inadequate when adding the FSP binary to
image due to default FSP location in CBFS, so bump to 2M
to ensure autobuilds succeed.
Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For GPIO pads that are configured as no-connect (PAD_NC), setting it
as GPI (with Rx enabled) leads to GPE0_STS being set
incorrectly. Though this is not an issue in practice (GPE0_EN is not
set, so no events triggered), it can confuse users when debugging GPE
related issues.
This change configures PAD_NC to have Rx disabled along with Tx to
ensure that it does not end up setting GPE0_STS bits for unwanted
GPIO pads.
P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that
configuration as is.
BUG=b:129235068
TEST=Verified that GPE0_STS bits are not set for pads that are marked
as PAD_NC.
Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Add more registers and make them optional, so they keep untouched/
their default if omitted.
Change-Id: I5d8008176d2972976b387c558658b8e70b50af8e
Signed-off-by: Max Blau <tripleshiftone@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Increase ramstage to 2M, required to actually embed the 7.2mb uImage
into the coreboot.rom, increase the postram cbfs cache in order for the
fit image to be loadable (without this increase the fit payload is found
but not loaded)
Change-Id: Iee0ed9f7958588ceda54bb32253c84cac68abea2
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The name OPROM is somewhat inaccurate, since other steps to bring
up display and graphics are needed depending on mainboard/SoC.
This patch cleans up OPROM code nomenclature, and works towards
the goal of deprecating vboot1:
* Rename CONFIG_VBOOT_OPROM_MATTERS to
CONFIG_VBOOT_MUST_REQUEST_DISPLAY and clarify Kconfig
description
* Remove function vboot_handoff_skip_display_init
* Remove use of the VbInit oflag VB_INIT_OUT_ENABLE_DISPLAY
* Add |flags| field to vboot_working_data struct
* Create VBOOT_FLAG_DISPLAY_REQUESTED and set in vboot_handoff
BUG=b:124141368, b:124192753, chromium:948529
TEST=make clean && make test-abuild
TEST=build and flash eve device; attempt loading dev/rec modes
BRANCH=none
Change-Id: Idf111a533c3953448b4b9084885a9a65a2432a8b
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT.
Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support
jack triggering on both edges.
BUG=b:130180492
TEST=build and boot on a CML EVT board.
Use evtest & verify headset jack detection functions as expected.
Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Suggested-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Trusted Firmware places some components in SRAM on RK3399 and therefore
restricts accesses to SRAM to the secure world. This makes the vboot
working data inaccessible to normal world payloads, so we need to
migrate it into CBMEM.
Change-Id: Ic7c95790f2f118ccbdd897550f13b5f987bdd831
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Implement mt_pll_raise_ca53_freq() in MT8183 to raise the CPU frequency.
Move the function declaration to common header.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: Ide8d767486d68177fa2bfbcc5b559879eca1bcda
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
With the default CPU voltage (0.8v), CPU frequency should be 1417Mhz at
most. We have to raise CPU frequency to 1989MHz after increasing CPU
voltage to 1.05v in romstage.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I4c3e0fa27ccda8e0efe422b6ab503a1efb1697e9
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
NEED_VB20_INTERNALS should always be specified when peeking
into vboot internal data structures.
BUG=b:124141368, chromium:956474
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: I5a47a28350fd5a68efeff0d06ca150c1ae145412
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Disable the GBB flag forcing manual recovery now that we can read
the manual recovery from H1.
Enable the GBB flag to skip EC software sync, since images built
from coreboot.org do not include the EC binaries by default.
Change-Id: I0e1d6304e3e29eda68c7b807cf0774275c37d710
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We do not want the RX signal to be floating on the board as that could
cause the ISH to remain in a higher power state (because there is logic
to keep the ISH in an higher power state when there is an active UART).
Add an internal 20K pull up on the RX line. In normal configuration this
will burn an additional 544uW.
BRANCH=R75
BUG=b:131241969
TEST=verify that ISH console still works with rework
Change-Id: Ifc9621bcafe4c86edfa9cd6d58b307254d3a81ca
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
If the Intel IGD device pci 02.0 is disabled or undefined in
the device tree, then internal graphics pre-allocated memory
and GFX-VT MMIO memory for virtualization won`t be allocated
in the SoC address space.
Thus, patch resolves the FSP-S hang problem on Skylake/ Kaby
Lake processors when the IGD device is disabled. This should
provide to run FSP 2.0-based coreboot on these CPUs families
without integrated graphics card.
The following boards were used for testing:
- Asrock H110M-DVS board (desktop i5-6600) & NVIDIA GTX 1060
as external GPU.
Virtualization and GFX 3D acceleration with nouveau driver
still works well (tested on VirtualBox 5.1.38 with Ubuntu
18.04.1 as guest and host OS)
- Intel KBL-R U RVP board (mobile i5-8350u) without GFX.
Payload: tianocore edk2-stable201811-216-g51be9d0.
Change-Id: Id7a0cba582d83e3fe7e8d20342ee219cdd369a53
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32467
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds the setting of psys_pmax to 136W. According to the
design, Rpsys is 11.8Kohm. Here is the equation to come out the
Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm / 2 = 1.2V
Hence, Psys_pmax is 136W.
BUG=b:124792558
BRANCH=None
TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.
BUG=b:130593883
BRANCH=octopus
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.
Change-Id: Ia3b9d3bf08472219348e20b53bae470c589039fb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support to reset the GPI Interrupt Status & Enable registers so that
the system does not experience any interrupt storm from a GPI when it
comes out of one of the sleep states.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up. Ensure that the system boots fine to ChromeOS.
Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.
Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The ACPI code of LPE device is included regardless of the
availability of the LPE controller.
Linux remains requesting the status of device LPEA even if
this device is disabled.
Include ACPI LPE controller code at Braswell mainboards with
LPE enabled.
BUG=N/A
TEST=Linux 4.17+ on Portwell PQ7-M107
Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The dqs_map array is used only for LPDDR3 and LPDDR4. It is not used for
DDR4, and so it can be removed from the baseboard memory initialization
code.
BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Change-Id: I07fac3097d68f37b4630d3f0010f987da2f03bd7
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
First configuration supported is 8 GB system memory:
4 x 2 GB (K4E6E304ED-EGCG).
BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Intel's DQ_DQS_RComp_Info_Utility generates data for 6 entries. MRC will
return errors if we don't have all 6 entries in the map.
BRANCH=none
BUG=b:131103736
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Change-Id: I20a768de0e4440d7dde7b717794c4e2d0c62819c
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Changes includes:
- enable TPM1 + add entry in devicetree
- configure LPC IO to make IPMI work + add entry in devicetree
- introduce DSDT and SMBIOS entries for IPMI to make it detectable
by ipmi_si driver
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Enable LTR for NVMe so it can use ASPM L1.2.
BUG=b:127593309
TEST=build and boot on sarien and check L1 substate with lspci
before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I9842beda6767f758556747f83cfcedbd00612698
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Remapping Hardware Status Affinity (RHSA) structure is applicable for
platforms supporting non-uniform memory. An ACPI Name-space Device
Declaration (ANDD) structure uniquely represents an ACPI name-space
enumerated device capable of issuing DMA requests in the platform.
Add RHSA and ANDD structures support for DMAR table generation.
BUG=b:130351429
TEST=Image built and booted to kernel
Change-Id: I042925a7c03831061870d9bca03f11bf25aeb3e7
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The IRQ tables don't support this path, so we shouldn't report presence
of the legacy PICs. As the _PIC method is optional and we ignore the
passed parameter anyway, drop it.
Change-Id: I51301a600e16f74fde00fdcb4595e1f47a52e207
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This patch revises the AC/DC loadline settings because some major
layout changes between proto and evt boards.
BUG=b:130740639
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS.
Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
The `printram` function only expands to a value only in debug builds.
This isn't done in default builds.
Change-Id: Ic88c4cc730ae2d0d0718c7f71260cd2b45a3ddcd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update submodule pointer to pull in newly-updated Braswell FSP.
Adjust FSP_FD_PATH for soc/cannonlake due to filename case change.
Change-Id: I02ee0d32fd4c04cd4971eff20fc5a7de3f9b07ec
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU
will get reset when coreboot enters bootblock.
BUG=b:130229952
BRANCH=none
TEST=Compiles (no Hatch device w/FP to test)
Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635f ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.
This patch has not been tested on hardware.
Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On EC end, we want to change this pin from push-pull to open-drain.
And since there is no external pull-up resistor on the board, we'll
have to configure this pin as internal-pull-up on AP end.
BUG=b:129306003
TEST=None
Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
FIT support takes more heap memory than most coreboot payloads.
Change-Id: Id17f25e94d97e937b0e9a9cee3dd1a8aef1d525d
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Not all Hatch variants utilize the SoC's native SD card support. Move
the support to board-specific variants instead of the base device tree.
BUG=none
BRANCH=none
TEST=compiles (no Hatch device to test with)
Change-Id: Iae24114aad2c4d042c25da6f8cb740ccc8960082
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32417
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to hatch(CB:32278), this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in
FSP.
This change also adds a device to kohaku override tree to ensure that
the settings in it take effect.
BUG=b:130310626
Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.
BUG=b:131144464
TEST=waveform test and hardware validation result pass.
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada. This is
needed so that platform properly boots after doing a Cr50 firmware
update when running on battery.
BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.
Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Modify the POWER_OFF_ON_CR50_UPDATE Kconfig option so that specific
mainboard implementations can disable the option.
BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.
Change-Id: I3beefaae21de61e53ae232dbdc8ea9dbb2c78cd5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.
BUG=b:129899315
TEST= Measure touchscreen power from Sarien during S0iX
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32330
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sarien will change Melfas from HID to I2C and change address from
0x10 to 0x34. So we don't need VPD to separate Elan and Melfas
anymore.
BUG=b:131194574
TEST=boot up and check no Melfas HID device exist
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32437
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We want to disable touch for non-touch sku. We can use
strap pin GPP_B4 to identify it is connected with touch
or not.
touch sku: GPP_B4 is low
non-touch sku: GPP_B4 is high
BUG=b:131132419
TEST=boot up and check no touch device exist
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If6681262c25e4b01e061a8520e38905d40345509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set CPU frequency from 1100MHz to 1989MHz to improve booting time.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: Id41c7ea8905c4db2537a5c32f96eb7c6b2c008ea
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32397
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The maximum CPU frequency is 1417MHz with current processor voltage
(0.8v). Set processor voltage to 1.05v for higher CPU frequency.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I24ecdac2c85d3f012d9235449c0d727d727dc185
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SSD reset pin had been added on DVT2, the power sequnence requires
toggle in boot stage.
BUG=b:130741066
TEST=Boot up with simulated DVT2 platform and confirm SSD can be
detected during warm reboot.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C params for I2C buses 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:131132499, b:128998988
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update SPI enable/disable and configure clock
API for supporting all the blsp and qup for qcs405.
Change-Id: I39622571cb671f62312283a010129ceecb654f61
Signed-off-by: Shefali Jain <shefjain@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fixes src/northbridge/intel/sandybridge/raminit_mrc.c:286:3: error:
implicit declaration of function 'enable_usb_bar'
Change-Id: I48bf59c56b518477a3fc0d75902fc58df6b7def7
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32400
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change-Id: Ic23eb57a4096d4301d7f9478d8e65aaeb233de7b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32399
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Change-Id: I7669b8dc07b1aa5f00e7d8d0b1305b3de6c5949c
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
When coreboot checks the TPM and key-ladder state it issues a reboot of
the Cr50 with a delay parameter. Older Cr50 code doesn't support the
delay parameter and reboots immediately, which prevented coreboot from
running the mainboard specific code needed for the AP to come back up.
This change calls mainboard_prepare_cr50_reset() prior to sending the
VENDOR_CC_IMMEDIATE_RESET command.
This change also fixes a false error message from the coreboot log that
indicated "Unexpected Cr50 TPM mode 3" when the Cr50 key ladder is
disabled.
BUG=b:130830178
BRANCH=none
TEST=build coreboot on sarien and grunt platforms.
TEST=Load Cr50 v3.15, run 'gsctool -a -m disable; reboot'. Verify
corebot send the
VENDOR_CC_IMMEDIATE_RESET command and that the AP boots normally.
Verify event log shows "cr50 Reset Required"
TEST=Force Cr50 automatic update. Verify event log shows "cr50 Update
Reset".
Change-Id: Ib05c9cfde8e87daffd4233114263de5b30822872
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Declare plaform level hook method before and after system sleep for
possible power management related usage.
BUG=N/A
TEST=pass with make what-jenkins-does
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie63711748b6dbb99d34910824f2059464543e162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without VBOOT_MEASURED_BOOT there is no need for these symbols.
Change-Id: I96391b7817c79f760713c67bc469164b5514879e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Commit 45d4b17 [nb/intel/sandybridge: Move southbridge code to bd82x6x]
moved early_pch_init() to the southbridge, but failed to include
early_pch.c for the non-native raminit case, which now fails to link.
As all boards default to native raminit, this was missed by the autobuilder.
Adjust early_pch.c to be compiled regardles of ram init type used
Test: build/boot google/stout with MRC ram init selected
Change-Id: I50db30fda9a1099fb434c04ea97bcc38f8455233
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
For full reset, use already defined full_reset() function.
Change-Id: Iec7dcf285f3cb1cdc8f48d348ff8496879625db5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Parameter passing is incorrect here, it should pass
complete StdHeader instead of attempting to fill
in HeapStatus that should be treated as a field private
to AGESA, based on where it is defined in the header
files.
Furthermore the while() loop did not evaluate the
return value. Feature can be brought back at a later
date after someone verifies it actually works correctly
across different stages.
Change-Id: Ib243b275f8700ecaeb330772c795d305c61899c5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31484
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each entrypoint to AGESA goes through the same sequence
and have same the function signature.
To avoid introducing bunch of preprocessor magic, rename
all the agesawrapper_amdXXX() functions that are actual
entrypoints to AGESA API, make them static, and provide
a single exposed entry function agesa_execute_state().
Change-Id: I96ae1874132da3843aa42c2f4e8a59ec771d3893
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31483
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.
BUG=b:129899315
TEST= Measure touchscreen power from Arcada during S0iX
Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add SMBIOS type 9 system slots into coreboot, the definiation is up to
date with SMBIOS spec 3.2
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ibcfa377c260083203c1daf5562e103001f76b257
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This change is mainly to control PlatformDebugConsent FSP UPD.
PlatformDebugConsent is enabled if SOC_INTEL_CANNONLAKE_DEBUG_CONSENT != 0.
PlatformDebugConsent in FspmUpd.h has the details.
BUG=b:130203864
TEST=boot ok and PlatformDebugConsent can be controlled by Kconfig
Change-Id: Ib845b5e42bc78fb352a0c97c6301f2aeca522f29
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32297
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Linux remains using SPI1 and PWM ASL even if these devices are disabled.
SPI1 and PWM are disabled by Intel FSP.
Remove ASL code.
BUG=N/A
TEST=Boot Ubuntu on Intel CherryHill CRB
Change-Id: Iec2ca7520081d00bf7a53d58ee054aa6f23e5606
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29417
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Serial bus revision [Byte 3] and serial bus specific revision [Byte 9]
are not the same.
Change-Id: I366f62e6aa0e9c0dfbc1ec17adeebc42a0e777eb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Include pch.h in the source files instead in sandybridge.h.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The pci_or_configx function makes the code shorter and more readable.
Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Droid/Blorb supports keyboard backlight feature, so enable the ASL code.
BUG=b:130330141
BRANCH=octopus
TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT.
Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When the components like LCM ID are not installed (i.e., NC), ADC will
return some value with much larger variation from standard value (out of
the tolerance we set). To support that, we should check tolerance only
on non-NC voltages.
Also improve the error messages so we can see the ADC raw values
instead of simple assertion error (which makes debugging more difficult
since we have to build another firmware image just to print the values).
BUG=None
TEST=Booted on Kukui and got correct SKU ID for NC LCMID.
BRANCH=None
Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, Arcada only supports D3hot during S0iX and there is leakage
power around 5~10mW depending on SSD vendors.
To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2
and two GPIOs are required to be configured.
GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to
control SSD reset.
BUG=b:130741066
TEST=Measure SSD power during S0iX from Arcada(DVT2)
Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sandy- and ivybridge use the same mrc.bin that has the heap in an
awkward location.
Change-Id: If985a48c6703c8a86d8051e67595cf0fd409d99a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Duncan Laurie