Make sure that the 48MHz clock output that is typically used as a clock
source for an I2S audio codec or a Super I/O chip.
TEST=On Guybrush before and after this patch the final state of
MISC_CLK_CNTL0 is 0x1006044, so BP_X48M0_OUTPUT_EN is set in both cases.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I38be344a95ccf166c344b2bddcb388fea437a4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56528
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds code to print the current SPI speeds for each of the 4
different speeds, Normal, Fast-read, Alt-mode, & TPM. It also displays
the SPI mode and whether or not SPI100 mode is enabled.
BUG=b:194919326
TEST: Display the speed, change speeds, show that new speeds are the
expected values.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I7825a9337474c147b803c85c9af7f9dc24670459
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Add the fch_spi_early_init call in fch_pre_init to perform early SPI
initialization which enables SPI ROM and setting the speed & read modes.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: Ibfbe6e16bd6b0dd46c13cecf2a35f0c0b4576b88
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56684
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get the settings for fast-read and mode from EFS, and reprogram those.
Program Normal reads, Alt-mode, and TPM speeds from Kconfig settings.
BUG=b:195943311
TEST=Boot and see that SPI was set to the correct speed & mode
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8a24f637b2a0061f60a8f736121d224d4c4ba69b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The common_i2c_save struct isn't specific to the I2C code and since it
contains the state of the GPIO control & status register and the state
of the GPIO MUX register, move it to include/amdblocks/gpio_banks.h and
rename it to soc_amd_gpio_register_save.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If7cd47e5a32427d856948e319de8dfad8c928e96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
No need to strip the quotes of the FSP-M file path in the size check and
it's always a good idea to not remove the quotes around file paths that
will get passed as parameters to shell programs so that spaces in the
path can't cause malfunction.
TEST=All cases still behave as expected for Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Nico Huber <nico.h@gmx.de>
Change-Id: Ieeea84b5861f9d15b2472208432169dc8e3f0049
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Power down the eMMC controller via the AOAC interface when it's not
enabled in the devicetree.
BUG=b:184978118
TEST=On guybrush the unused eMMC controller is disabled in AOAC after
applying this patch. Before this patch it was enabled.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I18f4626a29fdc422218777058341b0eae401bcd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
When CONFIG_FSP_M_FILE isn't defined, the parameter of the file-size
call evaluates to an empty string, so the file-size call will run
"cat | wc -c" which will cause make to get stuck in there. Also print a
message when no FSP-M file is specified that the resulting image won't
boot successfully.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b02774e2c79d12554fd076aa01bbe972176f372
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, The SPI speed/mode configuration is split between Kconfig
and devicetree. We'd like to have everything in one place. Since we
need the fast-read speed and the mode available in the Makefile to build
the AMD EFS table, we currently need it in Kconfig. Move all of the
settings to Kconfig and remove them from Devicetree in a later commit.
BUG=b:195943311
TEST=boot majolica & guybrush, verify spi settings
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I8f29e49e886bd99b39172905e21bfd392c6c10e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56884
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When modules are added to the FSP and they won't fit into the FSP binary
any more, the size can be increased in the FSP build. Especially in the
case of debug builds the increased size might not fit into the memory
region it gets decompressed into which starts at FSP_M_ADDR and has a
size of FSP_M_SIZE. SoCs can implement the soc_validate_fspm_header
function that ends up being called by the FSP driver in romstage to do
some additional checks on the FSP binary's header that includes the
version number and the image size. We can use the image size field to
check if it fits into the reserved region. Since the FSP-M memory region
is located after romstage loading it won't clobber the romstage code
where we do the check.
This runtime check is added in addition to the build-time check to also
cover the case when the FSP binaries in CBFS get replaced with ones that
don't fit into the reserved memory region after the coreboot build.
BUG=b:186149011
TEST=Mandolin still boots fine with the patch applied. When as a test
the FSP_M_SIZE Kconfig option in soc/amd/picasso is decreased to 0x10000
which is by far not enough for the decompressed FSP-M binary to fit into
it prints the newly added error message on the console and then stops.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b74a2d03993ba50b166eb6e87d4e57b93afc069
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57068
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP-M binary needs to fit into the memory region that starts at
FSP_M_ADDR and is FSP_M_SIZE bytes large, so error out during build time
if the uncompressed FSP-M file is larger than the size of the region it
will be copied into.
BUG=b:186149011
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Suggested-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ice4a59e5a723c3c0a40b1f3f3227aee6b9dcb39a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PSP_Verstage will take almost the entire time to run that
is allotted to S0i3 resume. Since coreboot isn't running,
the PSP needs to handle any security requirements. The long-
term plan is that the PSP won't even load psp_verstage on S0i3
resume, but when it is loaded, this makes sure we exit
immediately
BUG=b:177064859
TEST=Verify that PSP_verstage doesn't run on S0i3 resume
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ia7b2560ff3d7621922ec4bc0e8793961f5d7550f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56919
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are gremlins in the system. thread_coop_enable has an assert. This
is currently problematic for two reasons.
assert(current->can_yield <= 0);
When doing smm_do_relocate we are entering a deadlock. The root cause
hasn't been quite found yet, but it's related to co-op multi-threading.
For some reason the assert in thread_coop_enable is firing when
releasing the console_lock spin lock. I'm assuming cpu_info hasn't been
initialized yet. The assert tries to perform a printk, but since the
console_lock is still held we end up in a dead lock. This dead lock will
generally not happen after a warm reset. Again I'm assuming because the
cpu_info struct has some valid values at this point.
For now disable multi-tasking until we fix the cpu_info initialization.
BUG=b:194391185
TEST=Boot guybrush to OS
Co-developed-by: nikolai.vyssotski@amd.corp-partner.google.com
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia3143f538a31b5aaaea104aa1d8bcf44e6dcb528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57005
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use correct format for constraint list as expected by kernel driver.
With this change, kernel is able to correctly list dummy device in
constraint list.
BUG=b:194687976
TEST=Build and boot to OS in Guybrush.
Change-Id: I7af1941ffd21cd5864c7285f44cb2d063d2f225f
Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57012
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disabling the 4 DWORD bursts causes SPI DMA operations to stall, so
leave it enabled when SPI DMA is used.
BUG=b:194919326
TEST=Build and boot to OS in Guybrush.
Change-Id: I363acdcdb4178a10e4f7eb2bbcbd6d0ca7924f2d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Add a new Kconfig option to enable or disable the 4 DWORD burst support
of the SPI controller and use this setting to determine if the
corresponding feature bit in SPI100_HOST_PREF_CONFIG will be set or
cleared. Since fch_spi_disable_4dw_burst can now enable or disable the
feature, rename it to fch_spi_configure_4dw_burst. On Stoneyridge the
SPI_RD4DW_EN_HOST bit needs to be cleared (see the Rd4dw_en_host bit
definition in the SPIx2C SPI100 Host Prefetch Config register in the
public BKDG #55072 Rev 3.09), so add a SoC dependency to the Kconfig
option.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id754fa8d5f9554ed25cf9f3341bfdd1968693788
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Configure the IOMMU support upd if iommu is enabled.
BUG=b:194173037
Cq-Depend: chrome-internal:4027293,4027294
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I56b433cdc1ca5459c51b4b764e22292bd27b8892
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move IVRS acpi table generation code to common, so that it can be shared
by other programs.
BUG=b:190515051
TEST=Build picasso coreboot image. Compare IVRS tables before/after
change.
Change-Id: Icd5fec3a9d66e8301e267312020e726d9bc1aa70
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new IVRS kconfig option to control IVRS generation.
BUG=b:190515051
Change-Id: Iad0c6401dbccd2f3f75464a69e4c27f64d3507a5
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
A valid GEVENT number is never negative. The local variable in
set_single_gpio still needs to be a signed integer, since the return
value of get_gpio_gevent being -1 indicates that the GPIO can't generate
a GEVENT. The check for that makes the function return before calling
program_smi of program_sci, so the parameter of those functions can be
changed to unsigned.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6ce23ceed1585589932824b8cab2a138328672a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56705
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Each bit in the GPIO wake status index registers is set to 1 when at
least one of 4 corresponding GPIO pins has its wake status register set.
Added the comment since the gpio_base + i * 4 in the next line looked as
if it calculates some absolute register value which is not what the code
does or should be doing.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2fc8e9c5bd7c1b011f364b05d0cfdeb0df88ada6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56703
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the parameter the variable gets compared with is size_t type, use
size_t as type for that variable too.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If82a948bf71079d456616f4438f4b754e0d7262d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56702
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With the addition of the remote GPIO support, the GPIO number won't fit
into 8 bit any more, so use the gpio_t type instead which is an uint32_t
typedef.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3de93fd3a2f2af3c1e3b335fef84019c56482051
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56693
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The offsets of all GPIOs in the up to four regular banks are all
calculated relatively to ACPIMMIO_GPIO0_BANK, so we can just drop the
unused defines for ACPIMMIO_GPIO1_BANK and ACPIMMIO_GPIO2_BANK.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I832ffdca479c1f07219a23b4a7f9be69322dfe03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56675
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO bank 3 isn't used in coreboot, but the existence is documented in
both the Picasso PPR #55570 Rev 3.16 and Cezanne PPR #56569 Rev 3.01 and
for those two SoCs all 4 banks are covered by the corresponding
Memory32Fixed region in the DSDT.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id444a97a398d7e3abfd1f5c4a32e762ee6ff68f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56674
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The biosram accessor support in soc/amd/common/block/acpimmio/biosram.c
is only used on Stoneyridge and the old amd/southbridge code and not on
Picasso or Cezanne. It also only builds as a 32 bit binary and breaks
when trying to build as a 64 bit binary, since the size of an uintptr_t
is different on those two. There is no support for using the 32 bit
binaryPI with a 64 bit coreboot while there is code to use a 32 bit FSP
with 64 bit coreboot, so not building this for FSP-based SoC support
moves us one step closer to be able to build coreboot as 64 bit binary
for Picasso and Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d87ec2fa1b217eaf55d865e4390308812502e56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move the event logging helpers defined in acpi into a separate library.
This will allow logging power management and GPE events for both S3 and
Modern Standby. Introduce a single helper acpi_log_events function to
log both PM and GPE events.
BUG=None
TEST=Build and boot to OS in Guybrush.
Change-Id: I96df66edfc824eb3db108098a560d33d758f55ba
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
TEST=Checked on amd/mandolin with PCO APU and google/guybrush with CZN
APU that the McaXEnable bit is set in the CONFIG registers of all used
MCAX banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia4515ba529e758f910d1d135cdce819f83ea0b5c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It appears the pspp_policy enum is not the same as the FSP definition
currently being used. This means that the incorrect PSPP value setting
would get read by FSP. For Zork programs this meant we actually were
setting links as DXIO_PSPP_BALANCED instead of DXIO_PSPP_POWERSAVE.
This change adds DXIO_PSPP_DISABLED as the first enum value to properly
match the FSP definition and adjusts non AMD Customer Reference Boards
that reference the enum to still send the same value even though it has
now change definitions. If we actually want DXIO_PSPP_POWERSAVE for
those boards that can be adjusted in a future change.
BUG=b:193495634
TEST=Boot to OS with Majolica and Guybrush and run 10G iperf on wifi
with other server on local network.
Change-Id: I287b6d3168697793a2ae8d8e68b4ec824f2ca5ef
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Stoneyridge has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Picasso has an integrated FCH and no south bridge, so change the sb
prefix to fch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I82aed68104ea9570827646c818e100bd7e04d1af
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56526
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
sb_clk_output_48Mhz is only used in fch.c where it is also implemented,
so no need to have it visible outside of that compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2b0d10ff26bdf54ea791aa66bf400578466d54cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56525
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This enables the MCAX checking and BERT entry generation for Cezanne.
TEST=When printing all registers of all MCAX banks of core 0 on a
google/guybrush device, the registers have values that look correctly
and there is no general protection fault, so all MCAX MSRs that could be
accessed exist on Cezanne.
BUG=b:192997706
Change-Id: Ibe8047ce5bb5e7136a8786693bcced4d2225b1fd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56345
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RSA and SHA for cezanne since support has been added to the PSP.
Also picasso and cezanne have different enums definitions for
hash algorithm, so split that out into chipset.c.
BUG=b:187906425
TEST=boot guybrush, check cbmem -t and the logs
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I725b0cac801ac0429f362a83aa58a8b9de158550
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This allows keeping track of how long it takes to load the microcode.
BUG=b:179699789
TEST=Boot guybrush
112:started reading uCode 990,448 (10,615)
113:finished reading uCode 991,722 (1,274)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I86b67cf9d17786a380e90130a8fe424734e64657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If we don't escape the $ then the actual $(obj) path will be written
into the .config file. With this change `$(obj)` is written into the
.config file. The Makefile then does:
PSP_VERSTAGE_FILE=$(call strip_quotes,$(CONFIG_PSP_VERSTAGE_FILE))
Since this is a recursive assignment the $(obj) will be expanded at that
point.
This change makes it easier to compare full .config files.
BUG=none
TEST=Build ezkinil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic961df148d3f22585f3441d75c3f2454329c678a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This change allows preloading the payload.
BUG=b:179699789
TEST=Boot guybrush and see payload read/decompress drop by 20 ms. We
now spend 7ms decompression from RAM. By switching to LZ4 we drop that
to 500us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3ec78e628f24f2ba0c9fcf2a9e3bde64687eec44
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This CL adds a method that can start the processes of reading the APOB
from SPI. It does require more RAM in ramstage since we no longer mmap
the buffer in the happy path. This will allow us to reduce our
boot time by ~10ms. The SoC code will need to be updated to call
start_apob_cache_read at a point where it makes sense.
BUG=b:179699789
TEST=With this and the patches above I can see a 10 ms reduction in
boot time on guybrush.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I930d58b76eb4558bc4f48ed928c4d6538fefb1e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56232
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no telling when the next udelay will be, so explicitly call
`thread_yield()` after completing a transaction. This will allow any
pending transactions to immediately start.
BUG=b:179699789
TEST=Verify new transaction is enqueued right after another.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c1272bde46c3e0c15305b76c2ea7a6dde5ed0b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56321
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Once we enable COOP_MULTITASKING, we need to guarantee that we don't
have multiple threads trying to access the DMA hardware.
BUG=b:179699789
TEST=Boot guybrush with APOB patches.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ibb8e31c95d6722521425772f4210af45626c8e09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56231
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change will make it so the standard rdev readat call will use the
SPI DMA controller if the alignment is correct, and the transfer size is
larger than 64 bytes.
There is a magic bit that needs to be set for the SPI DMA controller to
function correctly. This is only available in RN/CZN+.
BUG=b:179699789
TEST=Boot guybrush to OS. This reduces loading verstage by 40ms,
verifying RW by 500us and loading romstage by 500 us.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be555956581fd82bbe1482d8afa8828c61aaa01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Also rename the existing PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU
definition to PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU_CEZANNE to clarify
that that is the one for Cezanne.
BUG=b:193888172
Change-Id: I1c5446c1517f2e0cd708d3275b08d2bce4be0ea8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56396
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Barcelo uses the same VBIOS image as Cezanne, but uses a different PCI
ID, so we need to implement map_oprom_vendev for the SoC.
BUG=b:193888172
Change-Id: I2eed43705f497245bd953659844b3fb461aa0b3b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56392
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also move the registers in the order they are in the hardware.
Change-Id: If018e746e58c14475caeda76feb8b5281d7732f1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56315
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only when ACPI_BERT is selected the BERT functionality needs to be
included in the build.
Change-Id: I8a21562f4535fb0ea3c53f2ea8df50f66cc6a64c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56314
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we don't need to skip the MCA check on cold boot on MCAX capable
systems, add a mca_skip_check implementation that always returns false.
Change-Id: Id8fc4b6f02b6c02b03172fe11f0451a9893e514d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This will allow moving mca_check_all_banks to mca_common.c.
Change-Id: I58e100c1447907bab984a2fdff6c6e0181910c23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This aligns the mca_check_all_banks implementation in the common mca.c
with the one in the common mcax.c file. Do the MCA bank count check
before the !is_warm_reset() check, so that a mismatch also gets printed
on the cold boot path.
Change-Id: Idbd3e9ce9c7483f84f87adab7adac47335cd59aa
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Since those functions are implemented and used only inside the common
MCA(X) code, there's no need to have them in the header file that gets
included in the SoC-specific code.
Change-Id: Ia84e149d67ac7d80de595379c73a6cf08730719d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
For Cezanne stubs are added for the functions that the SoC-specific code
needs to provide. Since the mca_is_valid_bank stub on Cezanne always
returns false, the checks get skipped for it at the moment. The actual
functionality will be added in a later patch.
Change-Id: Ic31e9b1ca7f8fac0721c95935c79150d7f774aa4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56290
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
To factor out the rest of the common MCAX code, mca_bank_name[] may only
be accessed by accessor functions, so implement this for the last place
that still accessed mca_bank_name[] directly.
Change-Id: Ic6548d3ceeb9c00ad344fc0bb3d97893e17a43a9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56294
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will allow factoring out and moving check_mca() to soc/amd/common.
Change-Id: I92c7657baef17c248a5aef1eda268e9647502837
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56280
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch changes the way how the not implemented MCA bank 3 gets
skipped. For the not implemented bank 3 the name gets set to NULL
resulting in mca_is_valid_bank returning false causing the bank to get
skipped. This is a preparation for commonizing the MCA(X) handing in the
soc/amd sub-tree.
Change-Id: I40d6a6752504d804c45b445fce7e763e80161211
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
In mca_check_all_banks only check valid MCA banks for errors. This
aligns the Picasso code a bit more with the Stoneyridge code base which
will be updated in a follow-up patch. This is a preparation for
commonizing the MCA(X) handing in the soc/amd sub-tree.
Change-Id: I0c7f3066afd220e6b8bf8308a321189d7a2679f6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56275
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The length of mca_bank_name should match the return value of
mca_get_bank_count which gets the number of MCA banks from an MSR.
TEST=No error message on serial console on amd/mandolin
Change-Id: Ibdad51a7ef27266e110dfbb43188361952618342
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56274
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also use array indices for the initialization.
TEST=Checked with the public Picasso PPR #55570-B1 Rev 3.16
Change-Id: I10a65210da73e64b67d613609fcc0f9a245a81fb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56273
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the AMD FCH architects, we should be using the default
value for the NO_HOG bit. This fixes a problem where the SPI DMA no
longer functions after the LPC init runs.
BUG=b:179699789, b:192373221
TEST=Boot guybrush and see SPI DMA working
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If015869657f36d3533f4ab9ebd1f54b0d4eb283a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There is no technical reason this needs to be done in romstage. Moving
it into ramstage allow us (in future CLs) to use threads to pre-load
the apob from SPI.
BUG=b:179699789
TEST=Boot and Ezkinil and Guybrush and verify APOB update still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I960437ff4400645de5a3e7447fcdbc52de85943e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The %p format specifier already prints out 0x, so remove the 0x from the
string. I also updated the other format specifiers to use the %# syntax
to print out the 0x.
BUG=b:179699789
TEST=see correct format.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5b00d2c06687e549f69486eb5e18f7bed560b2ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56225
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently the MCA support for Cezanne only clears the MCA status
registers. The MCA error handling and BERT table generation will be
added in subsequent patches.
Change-Id: Ib9b5174186c28c8c82f57ffd8936c8dad4e63c5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add this macro to be able to conveniently access the MC_CTL_MASK
register for each MCA bank. Also drop the unused definitions for
MC1_CTL_MASK and MC4_CTL_MASK.
Change-Id: I23ce1eac2ffce35a2b45387ee86aa77b52da5494
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This MSR isn't an architectural MSR, so it shouldn't be in the common
x86 MSR definition header file. From family 17h on this register has
moved to a different location.
Change-Id: Id11d942876da217034e6f912b1058f00bd15c22c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since we can use both the old MCA registers and the new MCAX registers
to access the MCA status registers, we can use the common
mca_clear_status function here.
Change-Id: I9ddcc119eca2659361b1496fd7ffe124fb323d26
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
When accessing the MCA MSRs, the MCA bank number gets multiplied by 4
and added to the IA32_MC0_* define to get the MSR number. Add a macro
that already does this calculation to avoid open coding this repeatedly.
Change-Id: I2de753b8c8ac8dcff5a94d5bba43aa13bbf94b99
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56243
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only the fields bank and sts from the mca_bank struct were used outside
a local scope, so remove the rest. Also rename the struct that now only
contains the bank number and the status MSR content to mca_bank_status.
Change-Id: I925347dff950ac2bd021635ca988c02fba48df7f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Those registers are architectural MSR and this also gets them in line
with IA32_MC0_CTL and IA32_MC0_STATUS. Also move them below the
definitions for IA32_MC0_STATUS, so that the numbers of the MSRs are
ascending.
Change-Id: Icef6526c896720248f5b648ddf1a271bdf46917c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56235
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since initial_lapicid() returns an unsigned int, change the type of the
local variables the return value gets assigned to to unsigned int as
well if applicable. Also change the printk format strings for printing
the variable's contents to %u where it was %d before.
Change-Id: I289015b81b2a9d915c4cab9b0544fc19b85df7a3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55063
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the common mca_get_bank_count function instead of open-coding the
functionality to get the MCA bank number. Also re-type the num_banks
variable from signed in to unsigned int, since the number of MCA bank is
always positive.
Change-Id: I126767cf9ad468cab6d6537dd73e9b2dc377b5c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change only enables the IOMMU device. We still require the IVRS
table to take advantage of the IOMMU. This will happen when the picasso
IVRS code is moved into common.
BUG=b:190515051
TEST=lspci shows IOMMU device
00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Device 1631
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5c7cae3d25af5a45d48658ffa948a2856adc4346
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Majolica UEFI ACPI tables have this listed as shared. It's already a
level interrupt, so no reason it shouldn't be shared.
This change makes it so Windows can correctly initialize the GPIO
controller.
BUG=b:186212501
TEST=Boot guybrush to windows and see GPIO controller functional. Also
boot guybrush to windows and verify GPIO controller still works.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I48c6d548a2a8d67599f25e37eeafc90764d9e2d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Allow hot plug devices to subscribe to IOMMU services. Currently the
IOMMU end range is limited to device B:0 D:1f F:6. This prevents the
devices on bus 1 and higher to subscribe to IOMMU services. As per AMD
IOMMU spec v3 section 5.2.2.1 all possible device IDs must be defined,
whether the device ID is actually populated or not. Device entries are
used to report ranges when hot-plug and SR-IOV devices are possible.
With this change the hot plug devices can now bind to IOMMU services
(as tested on kernel v5.4), and below errors are not seen in dmesg.
AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.3 domain=0x0000]
AMD-Vi: Event logged [IO_PAGE_FAULT device=05:00.0 domain=0x0000]
AMD-Vi: Event logged [IO_PAGE_FAULT device=04:00.4 domain=0x0000]
TEST= Verify dGPU can enumerate on hotplug. No IO page fault errors seen.
The hot plug devices can successfully bind to IOMMU services in
kernel.
Signed-off-by: Aamir Bohra <aamirbohra@gmail.com>
Change-Id: I256c0f8032662674a4d75746de49c250e341c579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55816
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: ritul guru <ritul.bits@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
TEST=Boot with CONSOLE_LOGLEVEL_3 and no longer see the message printed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0bdb92f547ceb8be624521211f4a3b94a91dae22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are currently reading the uCode for each CPU. This is unnecessary
since the uCode never changes.
BUG=b:177909625
TEST=Boot guybrush and see "microcode: being updated to patch id" for
each CPU. I no longer see CBFS access for each CPU. This drops device
initialization time by 32 ms.
Also boot Ezkinil and verify microcode was also updated.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I98b9d4ce8290a1f08063176809e903e671663208
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Start using the custom boot device.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4ae7272677f563e8827ba154fe5177c8c01155c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This is a copy of mmap_boot.c and mem_rdev_ro_ops. I split it up so it
was easier to review.
The next patches will add support for the SPI DMA controller. This will
provide a minor speed up vs using mmap reads. It will also provide the
facilities to perform asynchronous SPI loading.
BUG=b:179699789
TEST=Boot guybrush to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id26e2a69601d0f31e256d0010008904a447c8e21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55854
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Introduce the `ARCH_ALL_STAGES_X86` Kconfig symbol to automatically
select the per-stage arch options. Subsequent commits will leverage
this to allow choosing between 32-bit and 64-bit coreboot where all
stages are x86. AMD Picasso and AMD Cezanne are the only exceptions
to this rule: they disable `ARCH_ALL_STAGES_X86` and explicitly set
the per-stage arch options accordingly.
Change-Id: Ia2ddbae8c0dfb5301352d725032f6ebd370428c9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
To generalise the choice of 32-bit or 64-bit coreboot on x86 hardware,
have platforms select `ARCH_X86` directly instead of through per-stage
Kconfig options, effectively reversing the dependency order.
Change-Id: If15436817ba664398055e9efc6c7c656de3bf3e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With two versions of *speed_mhz_to_reported_mts() we need to call the
correct one based on the reported memory type.
BUG=b:184124605
TEST="dmidecode --type 17" in OS on Guybrush
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Change-Id: I92e834097546e3ef7130830444a80f818bdea3d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55852
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When initializing espi early, there may be mainboard requirements to
configure the bus properly. This allows the mainboard to do that.
BUG=192100564
TEST=Build along with next patch, eSPI works on guybrush
Change-Id: Icc02877a09b8f8ed20fd1b04f3cee0509f1a85c5
Signed-off-by: Martin Roth <martinroth@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In order to support Audio Co-processor (ACP) DMIC hardware runtime
detection on the platform, ACPI _WOV method is populated on the
concerned ACP device. This method returns the ACPI Integer value as 1
if ACP DMIC exists on the platform.
BUG=b:182960979
TEST=Build and boot to OS in guybrush. Ensure that the _WOV ACPI method
is populated under the scope of ACP device.
Scope (\_SB.PCI0.GP41.ACPD)
{
Method (_WOV, 0, NotSerialized)
{
Return (One)
}
}
Change-Id: Ide84f45f5ea2ae42d5efe71ac6d1595886157045
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55029
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If the NO_EARLY_BOOTBLOCK_POSTCODES config option is enabled, configure
eSPI as early as possible in the x86 boot sequence.
We found that there are situations that can cause the system to hang if
there are any port80h postcodes sent out before eSPI is initialized.
BUG=b:191370340
TEST=Build & Boot with and without NO_EARLY_BOOTBLOCK_POSTCODES enabled.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0badb1c529e96ee4f81134287db53ce32473de6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55732
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The original reason the BERT table was moved out of CBMEM was because
the OS was not able to access the region. This happened because the
CBMEM region was marked as type 16 in the e820 table. The OS isn't aware
of this type, so it prevents any drivers from accessing it. Depthcharge
now correctly labels the CBMEM region as reserved in the e820 table so
we can move the BERT table into CBMEM.
TEST=BERT ACPI table generation still works on AMD/Mandolin with SeaBIOS
as payload and BERT region inside CBMEM is inside a BIOS-e820 reserved
range. BERT generation also works on Zork with depthcharge.
Link: https://crrev.com/c/2939677
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie640e91c19ae5f9b275cc333284b4be34211fbf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Our existing native function gpio configuration macro (PAD_NF) only sets
the pull. For PCIe reset, we now need to be able to set it to its
native function (PCIE_RST_L), and drive it low, then high.
BUG=b:182805349
TEST=Configure GPIO, see correct behavior.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I636371517c99f94f76834abc4575795d51aa0368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55652
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pass the info if the non-graphics HD audio controller device is enabled
or disabled in the board's devicetree via a UPD to the FSP so that it
knows if it should enable or disable the corresponding device.
TEST=When adding "device ref hda on end" to the devicetree of
amd/majolica the non-graphics HD Audio controller shows up in lspci and
when that line isn't added the PCIe device doesn't show up.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9f5e164d308906bfc788e5c2674c13c7b2ebf471
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Currently the FSP only has one switch to disable both AHCI controllers.
If at least one of the two AHCI controller devices is enabled in the
board's devicetree, set the SATA enable UPD to 1 and otherwise set it to
0. Setting the UPD value to 0 when both AHCI controllers are disabled
saves around 60ms in boot time.
BUG=b:191385289
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I84e7c8bf2ab08c8254271ddfefd2e4e7d8c2e87b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55669
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Using existing defines instead of magic values improves readability of
the code. Also add comments to the MADT IRQ overrides to make it clearer
what those actually do.
TEST=Timeless build results in identical binary for amd/gardenia
(Stoneyridge), amd/mandolin (Picasso) and amd/majolica (Cezanne)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I224ffbe8eb65bcdd5fc70c0ff8b15d55b3f6be01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55613
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Factoring out those defines brings the Stoneyridge SoC code a bit more
in line with the Cezanne and Picasso SoC code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifba7f13cc926ac28376233aa0bf317164ca9bbd6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55588
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the default state of the MMIO UART devices in the chipset
devicetree is off, the mainboard devicetree entries that disable MMIO
UART devices are removed.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I913a587802020ce4e182b48632cdde1104c2a6e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55545
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating the APOB takes a considerable amount of time. I decided to be
granular and split out the operations so we know when we read vs read +
erase + write.
BUG=b:179092979
TEST=Boot guybrush and dump timestamps
3:after RAM initialization 3,025,425 (44)
920:starting APOB read 3,025,430 (5)
921:starting APOB erase 3,025,478 (48)
922:starting APOB write 3,027,727 (2,249)
923:finished APOB 3,210,965 (183,238)
4:end of romstage 3,210,971 (6)
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I08e371873112e38f623f452af0eb946f5471c399
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In acpi_soc_get_bert_region after the bert_errors_region call is was
checked if the region parameter is NULL after the call; since region is
a parameter of acpi_soc_get_bert_region, it's non-NULL. What we should
be checking here is if region points to a non-NULL pointer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Coverity (CID:1457506)
Change-Id: I0523504d65725ab2d2df4db28a5dedd90697b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Even though the code is currently commented out, replace the magic
numbers with the existing defines.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id0dbbadf71f2e5a4d23ee998e2aa0a8b67205845
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55534
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib9dfddb0d4f32a542fa652ff8c14e932c224f247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Factoring out those defines allows using them easily in the ACPI code
without having to use preprocessor macros.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I99cb03de8782a0eeeb505f567b982099b0e8a18d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55531
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Part of the soc/amd/stoneyridge code already uses the FCH_IOAPIC_ID and
GNB_IOAPIC_ID defines. Use those defines in the remaining location to
make sure that the IOAPIC IDs are always consistent between the hardware
register, the MADT and the IVRS ACPI tables.
TEST=Timeless build of amd/gardenia results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I410a6560de66889b153c8a66b8dc5474ac114ba7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Enable generation of DMI Type 17 data on Cezanne.
BUG=b:184124605
TEST="dmidecode --type 17" in OS on Majolica
Change-Id: Iaa89ee1ce6efa0280f17a443e07571a1190873a6
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52230
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Move dmi.c code to common/fsp to be shared among different SOCs.
BUG=b:184124605
Change-Id: I46071556bbbbf6435d9e3724bba19e102bd02535
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
if VBOOT_STARTS_BEFORE_BOOTBLOCK is set, call boot_with_psp_timestamp to
migrate PSP timestamps into x86 timestamp table.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I4d51802145263145d40908889de29147af54f50f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The warm reset bit in the NCP_ERR register doesn't behave as the PPR [1]
suggested; no matter if something was written to the register, the
NCP_WARM_BOOT bit never got set and the NCP_ERR register in I/O-space
always reads back as 0x7f.
[1] checked with PPR for AMD Family 19h Model 51h A1 (CZN) #56569 Rev
3.01
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I569372db9f36ec7bbc741f4d7312ade312daa70b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55101
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Linux, in order to set wake alarms >24 hours, the RTC Date Alarm
field must be set to a valid non-zero value. If not, there are two
consequences:
1. Alarms >24 hours don't work
2. The kernel will refuse to enter suspend because it can't resume as
expected to service the alarm.
Since the RTC Date Alarm and RTC AltCentury fields are supported on
Stoneyridge, set them.
This is a mirror of commit 041fcf5902
("soc/amd/picasso/acpi: Set missing RTC offsets") for picasso.
BUG=b:187516317
TEST=On a Chrome OS 'grunt' device, run
`time powerd_dbus_suspend --suspend_for_sec=172800`
and verify the system suspended and woke up after 48 hours
BRANCH=grunt
Signed-off-by: Anand K Mistry <amistry@google.com>
Change-Id: I10831b982662e680fa71aa81d02935e1b7e7a7a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Note that there are assumptions about LAPIC MMIO location
in both AMD and Intel sources in coreboot proper.
Change-Id: I2c668f5f9b93d170351c00d77d003c230900e0b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55194
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also adds BERT table gerenation support for Cezanne, but since the
functionality to populate the BERT memory region isn't implemented yet,
this won't result in a BERT table being generated on Cezanne, since
bert_generate_ssdt will always return false there.
TEST=BERT ACPI table generation still works on AMD/Mandolin
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I69b4a9a7432041e1f4902436fa4e6dee5332dbd2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55056
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Implement acpi_soc_get_bert_region so that the common ACPI code will
generate a BERT ACPI table that points to the BERT memory region instead
of generating the BERT table in the SoC=specific code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I86d4f5ef74d4d40cb93ac4a3feaf28b99022ebd5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since bert_errors_present() is only available when ACPI_BERT is selected
the ACPI table generation code needs to check that before calling the
function, so add bert_should_generate_acpi_table that returns false when
ACPI_BERT isn't selected or the return value of bert_errors_present()
when ACPI_BERT is selected.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia955f627c190ea38e05b5aaedc7cb2d030274e83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55024
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
EDK2 mandates HOB to be in increments of qword (8). This HOB has 13
elements which causes it be padded with 4 bytes of garbage. This
results in coreboot failing intermittently with invalid data. Add
"number of entries" field to specify the number of valid entries in
the table.
BUG=b:190153208
Cq-depend: chrome-internal:3889619
TEST=verify HOB is present and correct size (13) is reported
Change-Id: Iaafae304f04a5f26d75a41a6d6fcb4ee69954d20
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55237
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some of the I2C buses are required to operate at different voltage level
compared to other I2C buses eg. I2C bus to Google Security Chip (GSC)
should be at 1.8V level. By default, all the I2C buses are initialized
to operate at 3.3 V. Add support to configure I2C pad RX select through
devicetree and update the concerned devicetree.
BUG=b:188538373
TEST=Build and boot to OS in Guybrush. Ensure that the communication
with GSC is fine. Build Majolica mainboard.
Change-Id: I595a64736fdac0274abffb68c5e521302275b845
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The new cezanne PSP release added support for these svcs. So add those
functionality back to cezanne psp_verstage.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Id542f5ed0762f582ea966466d67ed938ecb9c1f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55137
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
GSC is connected with AP via i2c bus so we need to enable i2c in
psp_verstage.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I5f7b73be67a692ea7de31ae53bd111d0e4b6998c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55136
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since the MCA(X) registers have defined values on the cold boot path,
the is_warm_reset check can be dropped. Also the warm reset bit in the
NCP_ERR register doesn't behave as the PPR [1] suggested; no matter if
something was written to the register or the machine went through a warm
reset cycle, the NCP_WARM_BOOT bit never got set.
[1] checked with PPR for AMD Family 17h Models 11h,18h B1 (RV,PCO)
#55570 Rev 3.15
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I4e6df98ffd5d15ca204c9847a76c19c753726737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The chipset devicetree only has the essential PCIe devices enabled that
are needed for the SoC code to work. It also defines aliases for all
PCIe devices that can be used to reference the devices in the mainboard-
specific devicetrees and devicetree overrides. To make the change easier
to review that part will be done in a follow-up patch.
Despite missing in the PPR, device pci 18.7 exists on Picasso.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b7c3fd32579a23539594672593a243172c161c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The Guybrush platform needs to set up some GPIOs immediately before the
FSP-M runs. Add a platform specific call. This will be used in a
follow-on commit.
BUG=b:184796302, b:184598323
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I37d2625ff426347852e98a9a50f15368e0213449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54638
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PLTRST# is currently asserted and latched when eSPI_RST# gets asserted.
If eSPI_RST# isn't used on a platform or it doesn't properly assert
in all cases, then PLTRST# will never be asserted. This could result in
the AP and EC being out of sync.
BUG=b:188188172, b:188935533
TEST=Warm reset guybrush with partial #22 rework. Verify that peripheral
channel is correctly reset.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I20d12edf3efc6100096e24aa8d1aec76bbde264f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
On RW boot path psp_verstage call cbfs_map which calls chain of
_cbfs_alloc, cbfs_boot_lookup and cbfs_get_boot_device. Then
cbfs_get_boot_device initializes MCACHE which is used later.
However on RO boot path psp_verstage doesn't try to find anything in the
CBFS which results RO MCACHE not to be initialized. Add
cbfs_get_boot_device(true) to explicitly initialize MCACHE on recovery
boot.
BUG=b:177091575
BRANCH=none
TEST=build and boot jelboz
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I6c4b522fef5a4affd215faa122bdf6b53190cf3d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54711
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We were missing the stdint.h header, and the header was sorted
incorrectly in chip.h
BUG=non
TEST=build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I209d3c9c48e5b06b2a56759af51cf2858eb99f51
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Since the default for the corresponding UPD of the Picasso FSP is
DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE,
add a deviectree setting for each board that's using the Picasso SoC
code to not change the setting for the existing boards.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows boards to specify which PSPP policy (basically a dynamic
trade-off between power consumption and PCIe link speed) should be used
and also makes sure that the boards are using the expected PSPP policy
and not just the UPD default from the FSP binary that has already
changed once during the development.
BUG=b:188793754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1b6459b2984711e72b79f5d4d90e04cb4b78d512
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54930
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch also adds the additional 10 MCAX registers to the BERT MSR
error record.
BUG=b:186038401
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I31912d3b3e77e905f64b6143042f5e7f73db7407
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.
Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
ESPI_SLAVE_CHANNEL_READY is a read-only bit from the host perspective.
It is set when the eSPI peripheral has configured the channel.
We actually want to set the ESPI_SLAVE_CHANNEL_ENABLE flag. This never
caused an issue before because the peripheral channel is enabled by
default after PLTRST# is deasserted. This does fix the case where
periph_ch_en == 0. It now properly clears the enable flag.
BUG=b:188188172, b:188935533
TEST=Boot guybrush to OS, perform warm reset
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I24e0734d5652601ae9c967da528fec5e3f780991
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The ChromeEC might take longer than 1ms for the peripheral channel to be
enabled. The PLTRST# interrupt handler takes about ~539us.
This doesn't account for the time it takes for the interrupt handler
to be scheduled. Increasing the timeout to 10ms gives ample time.
BUG=b:188188172, b:188935533
TEST=Boot guybrush and no longer see channel enable errors
Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib6db577bf06175ceb17b446af706ad8c9f891481
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54788
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The default of CBFS_MCACHE_SIZE is increased to 0x4000 in CB:54146 but
we have limited space on the PSP thus cannot afford it.
BUG=b:177091575
BRANCH=none
Signed-off-by: Kangheui Won <khwon@chrmoium.org>
Change-Id: I94dd782ae00d0b18ad6dd2fc061e4318bda88579
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
NCP_ERR is a 1 byte register in I/O-space, so use inb and not inw. The
variable the result gets assigned to is also a uint8_t.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9fd8c139004111d6227c0316ba2a8b0281541654
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
commit ce0e2a0140 (drivers/intel/fsp2_0:
use FSP to allocate APEI BERT memory region) adds a mechanism to reserve
the BERT region inside the coreboot code, so we can get rid of the
workaround to reserve it in the FSP and return the location in a HOB.
mcfg->bert_size defaults to 0 which makes the FSP not generate the
corresponding HOB, but that field is planned to be removed at least on
Cezanne, so don't explicitly set it to 0.
BUG=b:169934025
TEST=BERT table that gets generated in a follow-up patch for Picasso
points to expected BERT region and Linux is able to access, decode and
display it.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaca89b47793bf9982181560f026459a18e7db134
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52584
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When performing an in-band reset the host controller and the
peripheral can have mismatched IO configs.
i.e., The eSPI peripheral can be in IO-4 mode while, the
eSPI host will be in IO-1. This results in the peripheral
getting invalid packets and thus not responding. This causes the
NO_RESPONSE status bit to be set and cause eSPI init to fail.
If the peripheral is alerting when we perform an in-band
reset, there is a race condition in espi_send_command.
1) espi_send_command clears the interrupt status.
2) eSPI host controller hardware notices the alert and sends
a GET_STATUS.
3) espi_send_command writes the in-band reset command.
4) eSPI hardware enqueues the in-band reset until GET_STATUS
is complete.
5) GET_STATUS fails with NO_RESPONSE and sets the interrupt
status.
6) eSPI hardware performs in-band reset.
7) espi_send_command checks the status and sees a
NO_RESPONSE bit.
As a workaround we allow the NO_RESPONSE status code when
we perform an in-band reset.
BUG=b:186135022
TEST=suspend_stress_test and S5->S0 tests on guybrush and zork.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I71271377f20eaf29032214be98794e1645d9b70a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
I'm not 100% sure if this should rather be duplicated from Picasso or
commonized. Checked with the docs and this won't be compatible with
Stoneyridge and one future product's PPR lacked the corresponding
register. Some other chip has a compatible register layout, but a
different number of PCIe GPP clock outputs, so the common code would
need to use some SoC-dependent defines and possibly a SoC-specific
lookup table for the mapping which is also not that great.
TEST=Checked Cezanne PPR
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6b6d0cb8d7eb0288d8a18fcb975dc377b2c6846a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54685
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since this enum is only used for the devicetree settings and not for the
hardware itself, move it from the southbridge header to the chip one.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I0907fc5cba9315fec5fabff67d279c6d95d1c9f0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54684
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This removes the need to include this code separately on each
platform.
Change-Id: I3d848b1adca4921d7ffa2203348073f0a11d090e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
PSP_SOFTFUSE_BITS used to be like this:
15 0 29 "28 6"
It causes internal shell report error:
/bin/sh: -c: line 0: unexpected EOF while looking for matching `"'
/bin/sh: -c: line 1: syntax error: unexpected end of file
/bin/sh: -c: line 0: unexpected EOF while looking for matching `"'
/bin/sh: -c: line 1: syntax error: unexpected end of file
Change-Id: I716f19d37fb57b9ef3fc7259c6dcca7d21022d32
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
By default, FSP disables the GFX HDA. Enable it to support HDMI Audio
functionality.
BUG=b:186479763
TEST=Build and boot to OS in guybrush. Ensure that the GFX HDA is
enumerated in lspci output.
04:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1637
Change-Id: I42cb26c44bbca3d937c5d52736c42468139f7b07
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54100
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also drop unneeded intermediate cast to void * before casting the
address of the struct dptc_input type variables to uint8_t *.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie1e2aa1ec728a4e16d3a587d7400cdfc8962f443
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This adds support for convertible devices to support different maximum
power and thermal configurations. The dynamic power and thermal
configuration (DPTC) via ACPI ALIB calls allows to change the parameters
during runtime. This code contains the assumption that
\_SB.PCI0.LPCB.EC0.TBMD exists when ACPI code calls the DPTC method. At
the moment only chromeec declares EC0.TBMD, but it's also the only code
that calls the DPTC method. The definition of DPTC_INPUTS isn't moved to
the common code directory, since it's currently unsure if we might need
to configure more than those 4 parameters for Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibdfc056cb325a32d87505dd93e01c9af81dfd6c5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Cezanne PSP is missing implementations for some svc apis. Do not
include files related to missing svc apis.
This CL should be reverted after the cezanne PSP supports these
functions.
BUG=b:187906425
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ibaab4e8435624d403ef18e980146ebfd1598b61b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This will change the names of the GPP bridges, but this ok since there
is no hand written ASL that references these names.
BUG=b:184766519
TEST=Boot picasso and dump ACPI
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic09200156e8a37bd1a29ca95a17c8f8ae2b92bd3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54028
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Lowercase characters are not valid ACPI identifiers.
BUG=b:184766519
TEST=Boot picasso to OS and verify ACPI errors are no longer printed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I75aca67f4607e97ced8ac00ac68e51c359aff944
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Cezanne and Picasso can now use the same driver.
BUG=b:184766519
TEST=Boot guybrush and dump ASL. Verified it didn't change.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie4ede82935d6c69b323c1fdceaa61e306aa2820a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54026
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
This is still causing boot errors on zork:
coreboot-4.13-3659-g269e03d5c42f Fri May 7 22:03:11 UTC 2021 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
Set power off after power failure.
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area COREBOOT found @ 875000 (7909376 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I68b4b73670e750207414f0d85ff96f21481be8ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53933
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 6eced03b25.
This prevents zork from booting. We get the following error:
eSPI cmd0-cmd2: 00080009 00000000 00000000 data: 00000000.
Error: unexpected eSPI status register bits set (Status = 0x10000010)
Error: Slave GET_CONFIGURATION failed!
This isn't a pure revert. It is more of a fix that keeps the old
behavior.
BUG=b:187122344
TEST=Boot zork an no longer see eSPI error
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If75a35d3994b0fd23945a450032d3cc81abeb136
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cezanne must use cold resets. Change the warm reset request to always
set TOGGLE_ALL_PWR_GOOD. And, since the bit is sticky across power
cycles, set it early for good measure.
BUG=b:184281092
TEST=Majolica successfully resets using 0xcf9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I7d4ca5665335b20100a5c802d12d79c0d0597ad9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52982
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Loading address and size for the user app has been changed with recent
PSP release.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: If247cdf3413c6a10f4b3c92fb7e43dd1057865d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Verify if transfer buffer is valid before progressing further to catch
invalid transfer buffer early.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I4c470b156944b50e581dcdee47b196f46b0993f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52965
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMDFW tool stores bios dir entry to bios1_entry in picasso but
bios3_entry in cezanne. Separate getting bios_dir_addr into a function
and implement it on each platforms.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie18ed7979a04319c074b9b251130d419dc7f22dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52964
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move all platform-specific code except direct svc calls to chipset.c.
There will be differences between each platforms and we can't put
everything into svc.c.
TEST=build firmware for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ie7a71d1632800072a17c26591e13e09e0269cf75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52963
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
psp_verstage.bin target is already defined at
common/psp_verstage/Makefile.inc, thus removing it here.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ica4b09282d1c4cfc555c18ba50951458b8580826
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52962
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Build amdfw_[ab] and put them into CBFS. We can reuse FW_[AB] position
from zork since we have same flash layout and size.
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb31afa7a513f01593b2af75515a170dfca8d360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52961
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can generate the names, so there is no need to hard code a table.
This will make the code more generic so it can be reused with picasso in
the future.
BUG=b:184766519
TEST=Dump guybrush ACPI table and verify it looks correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5134d1dba4fcb9ce8cc4bfad1c619331a95f3b11
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52870
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We can now use the GNB IO-APIC.
BUG=b:184766519
TEST=Boot guybrush to OS with `pci=nomsi amd_iommu=off noapic`
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4df5a4583f14044d2efcde3a9de9dd85e898a11d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53936
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To configure and enable the IOAPIC in the graphics and northbridge (GNB)
container, FSP needs to write an undocumented register, so pass the GNB
IOAPIC MMIO base address to make it show up at that address.
BUG=b:187083211
TEST=Boot guybrush and see IO-APIC initialized
IOAPIC[0]: apic_id 16, version 33, address 0xfec00000, GSI 0-23
IOAPIC[1]: apic_id 17, version 33, address 0xfec01000, GSI 24-55
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1e127ce500d052783f0a6e13fb2ad16a8e408b0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52905
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the new acpigen_write_PRT to write the _PRT for each PCI bridge.
BUG=b:184766519
TEST=Dump guybrush ACPI table and verify it looks correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idb559335435a95e73640e6d7fb224e16e0592326
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This uses the new FSP PCI methods to pull the routing table and populate
the pirq data structure.
BUG=b:184766519
TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These are helper methods for interacting with the
AMD_FSP_PCIE_DEVFUNC_REMAP_HOB_GUID.
BUG=b:184766519, b:184766197
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Id03d0b74ca12e7bcee11f8d13b0e802861c13923
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We can now delete the picasso specific version.
BUG=b:184766519
TEST=Build zork and verify SSDT has not changed
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ic79014e83c9ff63cc7a6757b16764ae23b36984f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53935
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is loosely based off of picasso/pcie_gpp.c. This version uses the
acpigen_write_PRT_X methods to write the actual records. There are also
two functions, 1 for using the GNB, and one for using the FCH. The FCH
one is useful when the GNB IO-APIC has not been initialized.
BUG=b:184766519
TEST=Dump guybrush ACPI and verify it looks correct
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I926430074acb969ceb11fdb60ab56dcf91ac4c76
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The method now dynamically allocates the pirq structure and uses the
get_pci_routing_table method.
BUG=b:184766519
TEST=Build guybrush and verify picasso SSDT has not changed.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I297fc3ca7227fb4794ac70bd046ce2f93da8b869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows us to use the common get_pci_routing_info and
pci_calculate_irq. The IRQ field in the struct was also filled in from
the PPR.
BUG=b:184766519
TEST=Boot ezkinil and verify SSDT table is identical.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I16d90d8c89bfcf48878c0741154290ebc52a4120
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53923
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This struct is similar to `struct pci_routing` defined in
picasso/pcie_gpp.c. It additionally contains the irq used for the bridge
and is structured in a way that the FSP can provide via HOB.
The next set of CLs will migrate the pci routing functions used by
picasso into common and enable pci routing table generation for cezanne.
BUG=b:184766519
TEST=Build guybrush
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1a8d988d125f407f0aa7bc1722d432446aa9aff8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
TEST=Mandolin still boots into Linux and there's no ACPI warning in
dmesg.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7e6d38ebeae5e55a4a65930b989838532ab9c446
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53920
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also add an alib_ prefix to avoid possible name collisions.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib0f220a4cde6da764bb8bc589b5f44ae16496bd7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53918
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parameter IDs are defined in the AGESA Interface specification
#55483. This patch also adds a ALIB_DPTC_ prefix to the IDs and makes
the names more consistent.
TEST=Timeless build for Mandolin results in identical binary.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I75e0504f6274ad50c53faa8fcbde4d6821d85a04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/53917
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
