Remove cross rank/cross channel dependency.
I guess this is a mistake that could lead to instabilities.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I899db907cd2d2197fd81eda4c4656fb1e570c18f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17610
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Tested-by: build bot (Jenkins)
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
Change-Id: I986bb7a88f53f7f7a0b05d4edcd5020f5dbeb4b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18626
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
As we now apply asmlinkage attributes to romstage_main()
entry, also x86_64 passes parameters on the stack.
Change-Id: If9938dbbe9a164c9c1029431499b51ffccb459c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18624
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add 100 Mhz reflock default values for Ivybridge.
Some values are extracted from MRC, those marked as
guessed needs to be verified.
Tested on Lenovo T430 (Intel IvyBridge) and DDR3-1800.
Change-Id: Ife7f899b5fea02827ad998e9e8ab10ecaef61191
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17609
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add support for 100MHz reference clock on ivybridge.
Allows to use more frequencies than sandybridge.
Tested on Lenovo T430 (Intel IvyBridge) on DDR3-1800.
Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17607
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use Ivy Bridge specific magic values on Ivy Bridge instead
of Sandy Bridge values.
The values are extracted from MRC.bin.
Should increase raminit stability.
Tested on Lenovo T430 (Intel IvyBridge).
Change-Id: I49fdfe5ae3e65704d22e083e8446e3f1069869bc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17606
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Producer and consumer of these buffers now appear in same file.
Also add test for uninitialized NonVolatileStorage in SPI.
Change-Id: Ibbf6581a0bf1d4bffda870fc055721627b538b92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19037
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This save/restore facility operates on the same datablock.
Change-Id: I6e1f176adc2addbf2659c724f94c1b8d46d4838f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19026
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Only guard the parts that are problematic for romstage.
Also intention is to move AMD_S3LATE_RESTORE to ramstage in followup
work, it will need OemS3LateRestore.
Change-Id: Ie9c1fb3f3f0ab1951771ed829d4acdd8a59d8fbf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19025
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Specification says to do CAR teardown as part of AmdInitPost().
Move initializing the final AGESA heap storage to AmdInitEnv()
so the buffer is not invalidated without writeback.
Change-Id: I3a5d497d0e25ec291f722e9f089bc8928238c3f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some Chrome OS boards previously didn't have a hardcoded vboot
configuration (e.g. STARTS_IN_BOOTBLOCK/_ROMSTAGE, SEPARATE_VERSTAGE,
etc.) selected from their SoC and mainboard Kconfig files, and instead
relied on the Chrome OS build system to pass in those options
separately. Since there is usually only one "best" vboot configuration
for a certain board and there is often board or SoC code specifically
written with that configuration in mind (e.g. memlayout), these options
should not be adjustable in menuconfig and instead always get selected
by board and SoC Makefiles (as opposed to some external build system).
(Removing MAINBOARD_HAS_CHROMEOS from Urara because vboot support for
Pistachio/MIPS was never finished. Trying to enable even post-romstage
vboot leads to weird compiler errors that I don't want to track down
now. Let's stop pretending this board has working Chrome OS support
because it never did.)
Change-Id: Ibddf413568630f2e5d6e286b9eca6378d7170104
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/19022
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We define AGESA_LEGACY as an implementation of mainboard
that has its romstage main completely under mainboard/
directory. We have learnt from other platforms this approach
has several downsides when it comes to making platform-wide
improvements.
We start by creating per-family romstage.c file, which
boards will gradually take into use by removing the
AGESA_LEGACY Kconfig option we here apply to all of them.
Change-Id: Id01931e185a023039a60af16a678de9966db8d65
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18619
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
This is a cosmetic change.
Change-Id: Iea4dd97e9d83594447427abd9f844e507b805192
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18960
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Currently the `break` further down is called unconditionally as the
brackets for the body of the if statement are missing. Add those.
Change-Id: I34917a9877dcc882d880dedea689e1d72fe52888
Found-by: Coverity (CID 1372941: Control flow issues (UNREACHABLE))
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/18971
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Replace the use of the old device_t definition inside
northbridge/via/vx900.
Change-Id: I04292a6b698a42a5c582eddcef7cf5a235e1a464
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17317
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It makes no sense to read SPDs if the system will reset anyway.
Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17661
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reuses some of gm45 code to set up the panel.
Panel start and stop delays and pwm frequency can now be set in
devicetree.
Linux does not make the difference between 945gm and gm45
for panel delays, so it is safe to assume the semantics of those
registers are the same.
The core display clock is computed according to "Mobile Intel® 945
Express Chipset Family" Datasheet.
This selects Legacy backlight mode since most targets have some smm
code that rely on this.
This sets the same backlight frequency as vendor bios on Thinkpad X60
and T60.
A default of 180Hz is selected for the PWM frequency if it is not
defined in the devicetree, this might be annoying for displays that
are LED backlit, but is a safe value for CCFL backlit displays.
Change-Id: I1c47b68eecc19624ee534598c22da183bc89425d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18141
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Decode DDR2 SPD similar to DDR3 SPD decoder to ease
readability, reduce code complexity and reduce size of
maintainable code.
Rename dimm_is_registered to spd_dimm_is_registered_ddr3 to avoid
compilation errors.
Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/18273
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
A problem around CAR teardown time may result with missing
training results at the time we want to save them.
Record this in the logs for debugging purposes, it will
not be possible to use S3 suspend if this happens.
Change-Id: Id2ba8facbd5d90fe3ed9c6900628309c226c2454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18534
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
No board with binaryPI currently supports HAVE_ACPI_RESUME. For
platforms with PSP the approach is also very different from what
we previously had here.
Furthermore, s3_resume.[ch] files under cpu/amd/pi do not
distinguish between NonVolatile and Volatile buffers of S3 storage.
This means the Volatile buffer that is maintained and available in
CBMEM is unnecessarily copied to SPI flash. This has been fixed on
open-source AGESA directory, so development of S3 suspend support
with binaryPI is better continued with that.
Unfortunately there are further complications and indications that
open-source AGESA may have always had a low-memory corruption
issue. This has to be investigated separately before restoring
or claiming S3 is supported on binaryPI.
Change-Id: I81585fff7aae7bcdd55e5e95bc373e0adef43ef0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18501
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
The file is used for fam15.
Change-Id: I7cdf238a8f7be4bf79546bcfc3c9d05bd8986e3e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18635
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Definitions are not part of ACPI S3 feature, nor do
they require any AGESA headers so move them to a
better location.
Change-Id: I9269e9d65463463d9b8280936cf90ef76711ed4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18616
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
One very long line has to be wrapped to be shorter than 80 characters to
satisfy the lint scripts.
Note, that this gets rid of the brackets ().
Change-Id: Ie98eff360ebc5b68ce496edc15eb2d9fddcac868
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18556
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
These definitions do not require AGESA.h include,
and we will eventually remove agesawrapper.h files.
Change-Id: I1b5b78409828aaf2616e177bb54a054960c3869f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18588
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As we drive both channels with the same speed,
chan0dll and chan1dll are the same.
Change-Id: I7253ea9ea66396c536c82d63c67fecb041681707
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18472
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
AGESA AmdInitEarly() reconfigures the lapic timer in a way that
conflicts with lapic/apic_timer.
This results in an endless loop when printk() is called after
AmdInitEarly() and before the apic_timer is initialized.
This patch forces a reconfiguration of the timer after
AmdInitEarly() is called.
Codepath of the endless loop:
printk()->
(...)->
uart_tx_byte->
uart8250_mem_tx_byte->
udelay()->
start = lapic_read(LAPIC_TMCCT);
do {
value = lapic_read(LAPIC_TMCCT);
} while ((start - value) < ticks);
[lapic_read returns the same value after AmdInitEarly()]
Change-Id: I1a08789c89401b2bf6d11846ad7c376bfc68801b
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/17924
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit fec8872c9d.
The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Signed-off-by: Daniel Kulesz <daniel.ina1@googlemail.com>
Reviewed-on: https://review.coreboot.org/18369
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
This fixes a warning that the new toolchain generates.
Change-Id: Idf46026729a474323e74a5cf7a156bf5bc8cf026
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18485
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This fixes warnings that the new toolchain generates.
Change-Id: I83d2c4c4651a89b443121312a5f36adfc1e4bc48
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18308
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This is more consistent with newer Intel targets.
Change-Id: I52ee8d3f0c330a03bd6c18eed08e578dd6ae284b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18371
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Adds the necessary plumbing for acpi_device_path() to find the LPC
bridge on the AMD Family14 northbridge with an SB800 southbridge.
This is necessary for TPM support since the acpi path to the LPC bridge
(_SB.PCI0.ISAB) doesn't match the built-in default in tpm.c
(_SB.PCI0.LPCB).
Change-Id: I1ba5865d3531d8a4f41399802d58aacdf95fc604
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: https://review.coreboot.org/18402
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins)
Add a test in case we have a DIMM2 not populated but DIMM3 is.
Change-Id: I14f82afe03884740570838e7b2771233356c518d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/18386
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
It rewrites the results of receive enable stored in the upper nvram
region, to avoid running receive enable again.
Some debug info is also printed about the self-refresh registers.
(Not enforcing a reset here, since 0 does not necessarily mean it's
not in self-refresh).
Change-Id: Ib54bc5c7b0fed6d975ffc31f037b5179d9e5600b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17998
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Those are the result from tracing what linux or the option rom do
but are not needed here.
TESTED on Thinkpad X60.
Change-Id: I4297a78c4ab6a19ef6161778c993fc3f3fb08c7e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18294
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Void pointer arithmetics are forbidden in standard C but GCC has
an extension that allows it.
Change-Id: I43029b2ab2f7709b8e1ba85eb05c31341b8ac16f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18293
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
It's an attempt to consolidate the access code, even if there are still
multiple implementations in the code.
Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18265
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Since it checks for DDR3 style checksums, it's a more appropriate name.
Also make its configuration local for a future code move.
Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/18264
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This also selects RELOCATABLE_RAMSTAGE and
CACHE_RELOCATABLE_RAMSTAGE_OUTSIDE_CBMEM by default on Haswell.
Change-Id: I50b9ee8bbfb3611fccfd1cfde58c6c9f46b189ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18232
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The selection of the SSC reference frequency for LVDS was based on a
completely unrelated clock.
The `ssc_freq` flag should be set when the SSC reference runs at a
different frequency than the general display reference clock (DREF).
For most platforms, there is no choice, i.e. for i945 and gm45 the SSC
reference always differs from the display reference clock (i945: 66Mhz
SSC vs. 48MHz DREF; gm45: 100MHz SSC vs. 96Mhz DREF), for Nehalem and
newer, it's the same frequency for SSC/non-SSC (120MHz). The only,
currently supported platform with a choice seems to be Pineview, where
the alternative is 100MHz vs. the default 96MHz.
Change-Id: I7791754bd366c9fe6832c32eccef4657ba5f309b
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/18186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Ubuntu’s default compiler flags for GCC [1][2] include `-Wformat
-Wformat-security`, causing errors similar like the one below.
```
CC romstage/northbridge/amd/amdht/ht_wrapper.o
src/northbridge/amd/amdht/ht_wrapper.c: In function 'AMD_CB_EventNotify':
src/northbridge/amd/amdht/ht_wrapper.c:124:4: error: format not a string literal and no format arguments [-Werror=format-security]
printk(log_level, event_class_string_decodes[evtClass]);
^
[…]
```
Fix that, by explicitly using a format string.
TEST=Built and booted on ASUS KGPE-D16.
[1] https://stackoverflow.com/questions/17260409/fprintf-error-format-not-a-string-literal-and-no-format-arguments-werror-for
"fprintf, error: format not a string literal and no format arguments [-Werror=format-security"
[2] I tested with gcc (Ubuntu 5.4.0-6ubuntu1~16.04.4) 5.4.0 20160609.
Change-Id: Iabe60deeffa441146eab31dac4416846ce95c32a
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18208
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The results were obtained by comparing the MCHBAR registers of vendor bios
with coreboot at the same dram timings.
This fixes 2 issues:
* 1333MHz fsb CPUs were limited to 667MHz ddr2 speeds, because with
800MHz raminit failed;
* 1067MHz fsb CPUs did not boot when second dimm slot was populated.
TESTED on ga-g41m-es2l on 800, 1067 and 1333MHz CPUs with
DDR2 667 and 800MHz dimms.
Change-Id: I70f554f97b44947c2c78713b4d73a47c06d7ba60
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18022
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
max_cdd_we_delta should be signed to allow for negative CDD.
Found-by: Coverity Scan #1347355
Change-Id: Iaccd1021680296d169c26c25e339f83fbd7cc065
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18162
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The values of highest_rank_count were undefined on DDR2 systems.
Explcitly define these values on DDR2 platforms.
Found-by: Coverity Scan #1347338
Change-Id: Iad7bb00db97b2816fcc44fb5941bd14373451da2
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18078
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The orphaned Tab_TrefT_k causes a failure to build due to
an unused variable warning on GCC 6. Remove this variable.
Change-Id: Ida680a6a3bc2b135755dd582da8c6edb8956b6ff
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
An unintended sign extension warning was thrown by Coverity.
Explicitly state the length of the constant multiplier.
Found-by: Coverity Scan #1347342
Change-Id: Icd42eec13be04fc5fd2ffc85320cbadafc852148
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18077
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Logic inside mct_EnableDimmEccEn_D uses an unintialized variable as
a register address under certain conditions. Refactor mct_EnableDimmEccEn_D
to use the explicit address of the register in all cases.
Found-by: Coverity Scan #1347337
Change-Id: I6bc50d0524ea255aa97c7071ec4813f6a3e9c2b8
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18079
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Malloced resources were not freed in failure branches during
S3 parameter save. Clean up Coverity warnings by freeing
resources in failure branches.
Found-by: Coverity Scan #1347344
Change-Id: I5f119874e52ef2090ca1579db170a49a2a6a0a2a
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing DRAM clock speed to configuration value logic contained
an error resulting in a theoretical out of bounds read. While this
would not be hit on real hardware, it was prudent to clean up the
logic to avoid the associated Coverity warning.
Found-by: Coverity Scan #1347353
Change-Id: Ic3de3074f51d52be112a2d6f2d68e35dc881dd2e
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18073
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing code inadvertently calculated the maximum read
latency for nonexistent channel 2 instead of for channels
0 and 1 as intended. Fix the calls to the maximum read latency
training function.
Found-by: Coverity Scan #1347354
Change-Id: If34b204ac73cd20859102cc3b2f40bc99c2ce471
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18072
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The critical delay delta was incorrectly specified as an
unsigned short. Use a signed short instead.
Found-by: Coverity Scan #1347355
Change-Id: I37d769afb8c8af85a0375ae459e9d4ab0adcca74
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18071
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The existing logic to set up CsMux45 used an incorrect mask
and comparison value due to a copy + paste editing error.
Use the correct mask and comparison value for the last two
values.
Found-by: Coverity Scan #1347385
Change-Id: Ic08a52977df90b9952e434e71cd12dbc6d7e1443
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18070
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing code waiting for northbridge P-state transitions
contained a logical error preventing correct operation. Fix
the logical error and force coreboot to wait for the P-state
transitions per the BKDG.
Found-by: Coverity Scan #1347388
Change-Id: I35f498c836db1439734abe684354c18c8e160368
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18069
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The code to set the igd frequencies is written with the mobile version
of the 945 chipset in mind and seems to cause cause strange igd
related problems on the desktop versions.
Some possible problems are:
* on 800MHz fsb CPUs the igd sometimes has artifacts on the screen;
* on 800MHz fsb CPU memtest results vary a lot;
* since a commit 45e11aa0a5 "Add/Combine Broadwell Chromebooks using
variant board scheme" that does not affect this northbridge, the
display shows garbage as soon as Linux (4.8) modesets the display.
A fix is to hardcode the core display and render clocks to their
maximum, potentially also improving graphical performance.
Vendor bios on all boards in coreboot with this northbridge have the
same value in this PCI config address.
TESTED on P5GC-MX (display works fine again in Linux) and
user reports of it making GA-945GCM-S2L run more stable.
Change-Id: I8b046edbc952631d9b79023e3d385160ff682c24
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
On AMD DDR3 platforms, the upper DQMask was incorrectly
calculated, leading to undefined behaviour and possible
DRAM training faults. Use the correct calculation for
the upper DQMask.
Found-by: Coverity Scan #1347394#1347393
Change-Id: If3190eb7c30f1f00d6fd8b751bc1761c9d119782
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18068
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Several members of DCTStatStruc are designed to persist across resets of
all other members. Move the persistent members into a substructure in
order to simplify the reset logic and avoid compiler warnings / UB.
Change-Id: I1139b7b3b167d33d99619338d42fcd26e2581a5d
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18058
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some PCI peripherals, such as FPGA accelerators, require a great amount
of memory mapped IO. This patch allows the user to select at build time
the bottom IO to leave enough space for such devices.
We cannot calculate this value at runtime because it has to be set
before the PCI devices are enumerated.
Change-Id: Ic590e8aa8b91ff89877cbff6afd10614d33dcf8d
Credit-to: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@gmail.com>
Reviewed-on: https://review.coreboot.org/17980
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Nothing from that header is used or even declared since
CONFIG_HYPERTRANSPORT_PLUGIN_SUPPORT is not selected on Intel
hardware.
Change-Id: I9101eb6ffa6664a2ab45bc0b247279c916266537
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18044
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Values based on vendor bios and suggested by Arthur Heymans for FSB1067.
FSB1067:
The ratio 1067/800 is proportional to the ratio of EPBAR32(0x2c) bits:
0x1a / 0x14 ~ 1067/800
EPVC1IST:
The ratio is also proportional to FSB ratios: 0x9c / 0xf0 ~ 533/800.
Change-Id: Ib90e8ea1b82f2fcc3b5c199cace32a7f0aff4b5c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/17198
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently only there is only one eaglelake board in coreboot
(ga-g41m-es2l) featuring a G41 variant northbridge.
Adding boards with a different variant (Q43, Q45, G43, G45, B43) will
require this change for graphic initialisation.
Change-Id: Ida32c563a99576b66685dfdadf9a534fd6e197dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17900
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add custom files for Sandybridge and IvyBridge functions.
Move only the minimal required functions into separate files.
Both files' functions are going to call raminit_common functions.
No functionality is changed.
Sandybridge code path tested on Lenovo T420.
Change-Id: I1b1dfbd0857b59d3ae4392b73c033ee7a5aed243
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17605
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is a follow-on patch to commit 10141c30 -
(nb/intel/gm45: Use LAPIC udelay instead of custom version)
which removed the custom udelay from everywhere except SMM.
This patch removes it from SMM as well, and gets rid of the
gm45/delay.c file.
Change-Id: I7970bb5205f4aa10b38172ab5b9f8bcd6766c4e7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17330
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17676
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.
This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.
This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.
Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This makes CHIPSEC happy. We don't enable PAVP, but it shouldn't hurt
to lock it nevertheless.
Change-Id: I9428f0b6e8868832eb79f7aea24cbc7961c2aa8f
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Reviewed-on: https://review.coreboot.org/17352
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Resource is actually stored even before read_resources, but
that's where we currently log this resource.
For Intel, use PCI config register offset as the resource
index, while AMD side uses MSR address.
Change-Id: I6eeef1883c5d1ee5bbcebd1731c0e356af3fd781
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17696
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.
Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.
Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Resource allocator and 64-bit PCI BARs will need it and
PCI use is not really restricted to x86.
Change-Id: Ie97f0f73380118f43ec6271aed5617d62a4f5532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17733
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
I liked the style of code in pci_mmio_cfg.h more, and used those to
replace the ones in io.h.
Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17689
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code originates from times before __SIMPLE_DEVICE__ was
introduced. To keep behaviour unchanged, use explicit PCI
IO operations here.
Change-Id: I44851633115f9aee4c308fd3711571a4b14c5f2f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17720
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access
being non-atomic and/or need to access 4kiB of PCI config space.
All these platforms now have MMCONF_SUPPORT_DEFAULT.
Change-Id: I943e354af0403e61263f1c780f02c7b463b3fe11
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17529
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Boards with this chipset do not have any reference of
MMCONF_BASE_ADDRESS being written to chipset registers.
Either board support is already broken or FSP takes
care of this early and Kconfig lacks the notice that
this parameter must match with the chosen FSP binary.
CPU bootblock associated with this chipset uses
exclusive PCI IO access already.
Untested.
Change-Id: I07d20d81266ff6aaa6384d20a806d52fd4568e08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17547
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Split raminit.c into smaller parts. Move all functions that will
be used by chip-specific code into raminit_common.c.
The chip-specific changes includes new configuration values
for IvyBridge and 100Mhz reference clock support, including new
frequencies.
No functionality is changed.
Tested on Lenovo T420.
Change-Id: If7bb5949f4b771430f3dba1b754ad241a7e8426b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17604
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The same pattern was being used throughout the code base
for initializing the romstage handoff structure. Provide
a helper function to initialize the structure with the S3
resume state then utilize it at all the existing call sites.
Change-Id: I1e9d588ab6b9ace67757387dbb5963ae31ceb252
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17646
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17534
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Vendorcode always does PCI MMCONF access once it is
enabled via MSR.
In coreboot proper, we don't give opportunity to make
pci_read/write calls before PCI MMCONF is enabled via MSR.
This happens early in romstage amd_initmmio() for all cores.
Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17533
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Building an image for the Lenovo X60 on Debian 8.5 (jessie) with GCC 4.9.2,
compilation fails with the error below.
```
$ gcc --version
gcc (Debian 4.9.2-10) 4.9.2
[…]
$ make # lenovo/x60 with native graphics initialization
[…]
CC ramstage/northbridge/intel/i945/gma.o
src/northbridge/intel/i945/gma.c: In function 'probe_edid':
src/northbridge/intel/i945/gma.c:570:2: error: 'for' loop initial declarations are only allowed in C99 or C11 mode
for (int i = 0; i < 8; i++) {
^
src/northbridge/intel/i945/gma.c:570:2: note: use option -std=c99, -std=gnu99, -std=c11 or -std=gnu11 to compile your code
Makefile:316: recipe for target 'build/ramstage/northbridge/intel/i945/gma.o' failed
make: *** [build/ramstage/northbridge/intel/i945/gma.o] Error 1
```
Fix this by declaring the count variable outside the 'for' loop.
Change-Id: Icf69337ee46c86bafc4e1320fd99f8f8f5155bfe
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17623
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code won't allow anything beyond CL11 due to short
CAS Latency mask and a bug in mr0 which had the wrong
bit set for CL > 11.
Increase the CAS bitmask, fix the mr0 reg to allow CAS Latencies
from CL 5 to CL 18.
Use defines instead of hardcoding min and max CAS latencies.
Tested on X220 with two 1866 MHz, CL13 memories
Tested-By: Nicola Corna <nicola@corna.info>
Change-Id: I576ee20a923fd63d360a6a8e86c675dd069d53d6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17502
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This allows to set the backlight PWM frequency and the
duty cycle in the devicetree instead of using a plain BLC_PWM_CTL
value.
Change-Id: I4d9a555ac7ea5605712c1fcda994a6fcabf9acf3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17597
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix-up for 696abfc
nb/intel/x4x: Fix and deflate `dimm_config` in raminit
It didn't fix the channel-number shifting issue as intended.
The channel index is either 0 or 1. DIMMs are counted from 0
to 3 where 0..1 covers channel 0, and 2..3 covers channel 1.
Since we have two DIMMs per channel, we have to multiply the
channel index by 2 (or shift it left by 1) to get the index
of the first DIMM in the channel. Finally, to get the offset
of a DIMM in the channel we take its index modulo 2 (again,
the number of DIMMs per channel).
Change-Id: I2784b0cb655bfe823bf5fa48b722623dfca1ddc3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17612
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We kept this value at it's default on the native graphics init path.
Maybe the Video BIOS path, too, I don't know if the VBIOS sets it.
The panel power sequencer uses the core display clock (CDCLK). It's
based on the HPLLVCO and a frequency selection we made during raminit.
The value written is the (actual divisor/2)-1 for a 100us timer.
v2: Fix unaligned mmio access inherited from Linux.
v3: Use MCHBAR8() instead. Also, the unaligned access might have
worked after all.
Change-Id: I877d229865981fb0f96c864bc79e404f6743fd05
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17619
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Some methods like discover_402x assume an clear state.
Should fix fallback attempt raminit failures.
Change-Id: I7a6fe044c17f5e0dbfa0e9b9d2aed0c3b6ae3972
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
By shifting the `chan` right instead of left, values were always taken
from the DIMMs of the first channel. The diff-stat also looks like an
improvement.
Change-Id: I605eb4f9b04520c51eea9995a2d4a1f050f02ecc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17587
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
If smbus_read_byte returned an error when reading the DIMM size,
this value would be used as an offset into an array.
Check for the error, and set the DIMM size to 0 if there's
a problem.
Addresses coverity issue 1229658 - Negative array index read
Signed-off-by: Martin Roth <martinroth@google.com>
Change-Id: I6461a0fae819dd9261adbb411c4bba07520d076d
Reviewed-on: https://review.coreboot.org/17485
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
RW flag was added to spi_slave structure to get around a requirement on
some AMD flash controllers that need to group together all spi volatile
operations (write/erase). This rw flag is not a property or attribute of
the SPI slave or controller. Thus, instead of saving it in spi_slave
structure, clean up the SPI flash driver interface. This allows
chipsets/mainboards (that require volatile operations to be grouped) to
indicate beginning and end of such grouped operations.
New user APIs are added to allow users to perform probe, read, write,
erase, volatile group begin and end operations. Callbacks defined in
spi_flash structure are expected to be used only by the SPI flash
driver. Any chipset that requires grouping of volatile operations can
select the newly added Kconfig option SPI_FLASH_HAS_VOLATILE_GROUP and
define callbacks for chipset_volatile_group_{begin,end}.
spi_claim_bus/spi_release_bus calls have been removed from the SPI flash
chip drivers which end up calling do_spi_flash_cmd since it already has
required calls for claiming and releasing SPI bus before performing a
read/write operation.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Idfc052e82ec15b6c9fa874cee7a61bd06e923fbf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17462
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Time spent in printk() is highly unpredictable, depending of the
enabled consoles. If only CBMEM console is enabled, debugstring
is repeated tens of times, consuming preram_cbmem_console storage.
Change-Id: I2b0d9bd11c294d988a0eb84b90e77d5cc7f1f848
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17516
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make MMCONF_SUPPORT selected with MMCONF_SUPPORT_DEFAULT.
Platforms that remain to have explicit MMCONF_SUPPORT are
ones that should be converted.
Change-Id: Iba8824f46842607fb1508aa7d057f8cbf1cd6397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17527
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When MRC cache is available, first read only the SPD unique
identifier bytes required to detect possible DIMM replacement.
As this is 11 vs 256 bytes with slow SMBus operations, we save
about 70ms for every installed DIMM on normal boot path.
In the DIMM replacement case this adds some 10ms per installed DIMM
as some SPD gets read twice, but we are on slow RAM training boot path
anyways.
Change-Id: I294a56e7b7562c3dea322c644b21a15abb033870
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17491
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
For S3 resume path SPD is only used for DIMM replacement detection.
As this detection already fails in the case of removal/insertion of
same DIMM, we can rely on cbmem_recovery() failure alone to force
system reset in case someone accidentally does DIMM replacements while
system is suspend-to-ram stage.
Skipping DIMM replacement detection allows skipping slow SPD loading,
thus reducing S3 resume path time by 80ms for every installed DIMM.
Change-Id: I4f2838c05f172d3cb351b027c9b8dd6543ab5944
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17490
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Take the timestamp before SPD loading takes place, for easier
comparison against MRC blob performance and followup changes
will optimize some of the slow SPD/SMBus operations.
Change-Id: I50b5a9d02d2caf4c63e1a4025544131a085b8fb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17489
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Switch to use CRC of unique identifier section SPD[117..127],
remaining area of SPD data is ignored.
Change-Id: If4b43183f99f5f911ae6c311b43c29a72b9922e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17487
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Also memset info.dimm as it contains decoded SPD timings
used to calculate common timings.
Tested manually on Lenovo T420.
Change-Id: I659e5bc2a6cbadd9539931ee00ddea0a5253295f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17473
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
No need to find the same CMD rate for all channels.
Allow different CMD rates for every channel.
Tested on Lenovo T420 with different modules on each channel.
No regressions found.
Change-Id: I7036275ae89335dd3549ec392fa64824355b3cbf
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use register names found on forums.corsair.com.
No functionality changed.
Change-Id: Ibaede39a24e8df1c4d42cb27986ab66174b7d45b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17400
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Locking the PLL again once it's locked doesn't work.
The MRC doesn't do this, for some reason.
Remove fallback attempts of lowering DDR frequency.
Change-Id: Iccb54fa7d7357a22182dd26bd5b49c4073c04dc9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17399
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
As documented in DDR3 spec for MR2 the CWL is based on DDR frequency.
There's no to little difference for most memory modules operating at DDR3-1333.
It might fix problems for memory modules that operate at a higher frequency and
memory modules with low CL values should work even better.
Tested on Lenovo T420 with DDR3-1333 CL9 and DDR3-1600 CL11.
No regressions found.
Change-Id: Ib90b5de872a219cf80b4976b6dfae6bc02e298f4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/17389
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I5b218ce3046493b92952e47610c41b07efa4d1de
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17455
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.
Also fixes regression of slower S3 resume path after commit
9b99152 intel/sandybridge: Use common ACPI S3 recovery
Skipping low memory backup and using stage cache for ramstage decreases
time spent on S3 resume path by 50 ms on samsung/lumpy.
Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15790
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Replace the use of the old device_t definition inside
northbridge/via/vx800.
Change-Id: I14a2b4d847f8aeb327d90f385dea998779fae24f
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17316
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/via/cx700.
Change-Id: I6e25f898ab55ee959f1b3b8aba9616c3ba18986d
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17315
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/i855.
Change-Id: Iae66d1ef838095a560868d9c9ff81f4208f814f1
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17314
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/agesa/family10.
Change-Id: I5723e217fc739ab576cbe3a1ee6d92023190267c
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/17313
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is more consistent with other Intel GMCH code.
Change-Id: I7bfaa79b9031e2dcc5879a607cadacbdd22ebde7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17405
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Have a common romstage.c file to prepare CAR stack guards.
MTRR setup around cbmem_top() is somewhat northbridge specific,
place stubs under northbridge for platrform that will move
to RELOCATABLE_RAMSTAGE.
Change-Id: I3d4fe4145894e83e5980dc2a7bbb8a91acecb3c6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15762
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fix regression, S3 resume not working on sandy/ivy after commit
9d6f365 ACPI S3: Remove HIGH_MEMORY_SAVE where possible
There is some 20ms delay with ACPI S3 wakeup time due to MTRR setup
being done after the backup copy. Moving to RELOCATABLE_RAMSTAGE fixes
this delay by removing need of this backup entirely.
Change-Id: Ib72ff914f5dfef8611f5f6cf9687495779013b02
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15248
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change may slow down the raminit by maximum 200usec,
but reuses the lapic udelay definition.
Change-Id: I60a68f8a7911b257c0eecda96f7c5bf302bb51ed
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17152
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
No boards left in the tree for this northbridge.
Change-Id: Id45da11b9d78cbd6bd50acb5a3c6c3c270f9020e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17281
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Carrizo (00660F01), Merlin Falcon (00660F01), and Stoney Ridge (00670F00)
locate the HD audio controller on the northbridge root complex at 9.2
instead of the FCH. This duplicates the existing ASL into the northbridge
directories and reports the correct address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit f68206c2b42c90076efd968a99f4d3a49e403438)
Change-Id: I6d42bb40ad58c7f35e8c88ff27ebd327d656c021
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17216
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Adjust the names to match AMD's convention for family and model.
This patch is relevant for:
Trinity & Richland: Family 15h Models 00h-0Fh
Carrizo: Family 15h Models 60h-6Fh
Mullins & Steppe Eagle: Family 16h Models 30h-3Fh
Change-Id: I613b84ed438fb70269d789c9901f1928b5500757
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17169
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
The Stoney device supports only a single channel of DRAM with
two DIMMs. Correct the dimmensions of the SPD lookup array.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: <marcj303@gmail.com>
(cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8)
Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17145
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Remove the language associated with the Carrizo Gfx PCIe bridges.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748)
Change-Id: I8b67a646f98667d500fcee5da8389c10483488da
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17144
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Modify the new Stoney support files to match the APU's IDs and codename.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit de626730758def76e558294762a06d8ec9950cb9)
Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17143
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Prepare for new 00670FF00 (StoneyRidge) support.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Tested-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce)
Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17142
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These settings should be always made by the firmware, no matter if we
set up graphics or not. It looks like Linux doesn't even know these
registers.
The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1,
2]. They match the settings that were done in the native graphics path
for Ivy Bridge. I expect the differences to be an update (i.e. the set-
tings we did on the Sandy Bridge path were just outdated). Also, these
settings affect the PCH and not the CPU which are independent from each
other.
[1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
Volume 3 Part 3: PCH Display Registers (SandyBridge)
Doc Ref #: IHD-OS-V3 Pt3 – 05 11
https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf
[2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM)
Volume 3 Part 4: South Display Engine Registers (Ivy Bridge)
Doc Ref #: IHD-OS-V3 Pt 4 – 05 12
https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf
Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17073
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17111
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Those registers are only used on more recent Intel platforms featuring a
PCH. The DP registers on G4X hardware are at a different offset.
Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17110
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Also drop an odd comment about the resource allocator which seems to
work fine, with the right id.
Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17095
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This fixes an instability on 945gc where the IGD completely locks
up the system, when for instance tasked to do something with
compositing (like GNOME or GDM).
TESTED on ga-945gcm-s2l and d945gclf
TEST: launch GDM (gnome display manager)
Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17094
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect.
The result is that 800MHz FSB CPUs now properly work with 667MHz RAM.
Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas
Elyes.
Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17038
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Previously the 945gc raminit only worked for 533MHz FSB CPUs.
This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are
taken from the vendor bios of Gigabyte ga-945gcm-s2l.
The result is that 1067MHz FSB CPUs now boot without problems.
800MHz FSB cpus still don't get past romstage.
Change-Id: I13a6b97d2e580512155edf66c48405a153121957
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17034
Tested-by: build bot (Jenkins)
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This removes writes to FDI related registers since there is no FDI
link on these targets. This is likely a remainder from copying code from
later targets.
TESTED on Thinkpad x200 (gm45)
Change-Id: Id67fdc999185fa184a9ff0e5c3fc9bced04131ad
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16993
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This issue was found by Coverity Scan, CID 1364118.
Change-Id: Iba3c0f4f952729d9e0987d928b63ef8b8fe8841e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16992
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
According to: "Intel ® 965 Express Chipset Family and Intel ® G35 Express
Chipset Graphics Controller PR" the p2 divisor needs to be 10 when the
dotclock is below 225MHz and 5 when its above 225MHz.
Change-Id: I363039b6fd92051c4be4fdc88788f27527645944
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16991
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
According to "G45: Volume 3: Display Register Intel ® 965G Express
Chipset Family and Intel ® G35 Express Chipset Graphics Controller" the
VSYNC end should start at bit 16. This is also how Linux (at least 4.4)
sets this register, which can be seen with intel-gpu-tools.
TESTED on Lenovo thinkpad X60 (it does not change anything).
Change-Id: Ie222ac13211a91c4fbc580e2bf9de0d973ea9a3a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17015
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Some devices have no LVDS output but if no VGA is connected or
no EDID can be found, it will try to init LVDS.
This patch detects the presence of an LVDS panel and makes sure that
LVDS is not initialized when it is absent.
Change-Id: Ie15631514535bab6c881c1f52e9edbfb8aaa5db7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16513
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This reuses linux code (at least 4.1) to compute the graphic clock
divisors for LVDS displays on the gm45 northbridge.
The divisors m1, m2, n, p1, p2 need to be such that
"BASE_FREQUECY * (5 * (m1 + 2) + (m2 + 2)) / (n + 2)
/ (p1 * p2)" is as close as possible to the target_frequency.
On g4x hardware the BASE_FREQUENCY is 96000kHz.
This potentially increases LVDS display compatibility.
Change-Id: I2323af5756431e89769f95059790f5a922af14b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
MHCBAR(CLKCFG) was previously incorrectly written by the
sdram_program_memory_frequency function which required falsely
limiting the max dram frequency for 945GC.
TESTED on Intel d945gclf (memclock 667 and fsb 533) and
Gigabyte ga-945gcm-s2l (memclock 667 and fsb 1067)
Change-Id: I520efd69fa09fc9fde87c5301fd81121fde6a700
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
An epic battle to fix Nehalem finally ended when we found an odd mask
set in SMRR. This was caused by a wrong calculation of TSEG size. It
was assumed that TSEG spans the whole space between TSEG base
and GTT. This is wrong as TSEG base might have been aligned down.
TEST: On X201, copied 1GiB from usb key to sd-card and verified.
Change-Id: Id8c8a656446f092629fe2517f043e3c6d0f1b6b7
Found-by: Alexander Couzens, Nico Huber
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/16939
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch implements native resolution, VESA mode, on the VGA output of
x4x.
It relies on EDID to modeset, but has a fallback-mode (640 x 480 @
60Hz) if this is no EDID could be found. This fallback mode only works
in textmode since in VESA mode some payloads (grub2) rely on VBE info,
which is being generated from an EDID.
Change-Id: I247ea7171ba3c5dc3b209d00e4dcb2d2069abd75
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16498
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family"
mention the possibility of having 352M ram preallocated for the
integrated graphic device. This only worked fine if the amount of ram in
the system was 3GB or less. When 4G or more is installed, memory is
remapped to create a 1GB large pci mmio hole which is not enough and
creates conflicts when 352M vram is used.
This patch increases the pci mmio hole size on Lenovo x200 to allow
352M vram to work.
TEST: build and flash on target with 4GB ram or more, use nvramtool to
set gfx_uma_size to 352M and reboot.
Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16831
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/via/cn700.
Change-Id: Ib7761697daad3c459f3568e5158f925199bcd919
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16689
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add PCI device id to native graphic init and add the Native graphic init
option in Kconfig.
Change-Id: I136122daef70547830bcc87f568406be7162461f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16512
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This reuses the Intel Pineview native graphic initialization
to have output on the VGA connector of i945 devices.
The behavior is the same as with the vendor VBIOS BLOB.
It uses the external VGA display if it is connected.
Change-Id: I7eaee87d16df2e5c9ebeaaff01d36ec1aa4ea495
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16511
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The code to compute n, m1, m2, p1 divisors is not correct in coreboot and
on some targets hits a working mode at lower refresh rate, which is why
display is working on some targets.
The divisors must be such "refclk * (5 * (m1 + 2) + (m2 + 2))/ (n + 2)
/ (p1 * p2)" is as close as possible to the target frequency (which
is defined by the resolution and refresh rate).
This patch also fixes the reference frequency.
This patch reuses linux (4.1) code from drivers/gpu/drm/i915/intel_display.c
to correctly compute divisors.
The result is that some previously not working displays, like many
displays found on the Lenovo T60 might work now.
Some examples of T60 displays that were known to not work (in payload):
Samsung LTN141XA-L01 (14.1" 1024x768)
LG-Philips LP150X09 (15.1" 1024x768)
IDtech N150U3-L01 (15.1" 1600x1200)
IDtech IAQX10N (15.1" 2048x1536)
Samsung LTN154X3-L0A (15.4" 1280x800)
LG-Philips LP150E06-A5K4 (15.1" 1400x1050)
Tested on T60 with 1024x786.
Change-Id: I2c7f3bb0024ac005029eaebe3ecdc70c38ac777e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16504
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Compilation (w/o native raminit) fails due to missing include
Change-Id: Ic79a77006257b32e0181c88c4e24d7c1f5c5f7ce
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/16735
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This generates a fake VBT for the Intel i945 graphic device. i945
supports both the mobile chipset 945gm (calistoga) and the desktop
chipset 945gc (lakeport), which is why a VBT with a different id string
needs to be created for each target.
The VBT id string is obtained from the vbios blob in the following way:
"strings vbios.bin | grep VBT".
Change-Id: I8245b12b16a4426efbe1f584d4163fc257231a98
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16530
Tested-by: build bot (Jenkins)
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Padding the VBT id string is now done automatically.
Change-Id: I8f9baf7b1585026bc29b82d07e451aa11e284ffb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16740
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
The correct id string for gm45 is "$VBT CANTIGA ".
This can be found in the gm45 option rom:
"strings vbios.bin | grep VBT".
Change-Id: Icd67a87dac774b4b3c211511c784c4fb4e2ea97c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16551
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This implements "Keep VESA framebuffer" behavior on VGA output of gm45.
This patch reuses Linux code to compute vga divisors.
Change-Id: I2db5dd9bb1a7e309ca763b1559b89f7f5c8e6d3d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16338
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The intel x4x and gm45 have very similar integrated graphic devices.
Currently the x4x native graphic init enables VGA, while gm45 can output
on LVDS.
This patch reuses the x4x graphic initialisation code
to enable output on VGA in gm45 in a way that the behavior is similar to vbios:
If no VGA display is connected the internal LVDS screen is used.
If an external screen is detected on the VGA port it will be used instead.
Change-Id: I7e9ff793a5384ad8b4220fb1c0d9b28e6cee8391
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16295
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Replace the use of the old device_t definition inside
northbridge/intel/nehalem.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I6da4e0a9ef21b3285f4a369c8ddfbdb32a7a3801
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16406
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/gm45.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I87754799f922cf241fb456071bac04e6fe1eab34
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16402
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdht.
Change-Id: I7dfb8f001504c691aeddf1bfbc3be05cc7d31ce4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16468
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdk8.
Change-Id: I5209dd309f0685f83d8a468c50309d5fda77973a
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16467
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/amd/amdfam10.
Change-Id: I5037feb31c51d06ccc672b0771d5d6e8c0dac949
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16466
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Move the funtion to find most significant bit set(fms)
and function to find least significant bit set(fls) to a common
place. And remove the duplicates.
Change-Id: Ia821038b622d93e7f719c18e5ee3e8112de66a53
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/16525
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
northbridge/intel/x4x.
Change-Id: I65cd02eacf57cb41ded434582ca6e9d9f655e6ea
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16472
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/i5000.
Change-Id: Ic049d882ef22f117ee52ba497351f548e2355193
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16471
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/e7505.
Change-Id: Ie819f380ec06667e11bcff3e9e993126a86b2c89
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16469
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/fsp_rangeley.
Change-Id: I4c1e6af64fe70211db2fafdba9f39182dfea66fc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16470
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Previously the ME PCI interface (HECI) was being reported as present in
the DMAR ACPI table even when ME firmware was missing or the PCI device
was hidden and HECI would be unresponsive.
Now we check via the PCI config space itself to verify if the HECI
is present or not.
Note that this test could fail if ME firmware is present but
HECI is disabled in devicetree, because it would not advertise that the HECI
exists even though there is a running ME. Perhaps this behaviour is desirable
because in this case you won't see the HECI in the lspci tree anyway.
Change-Id: Ib692d476d85236b4886ecf3d6e6814229f441de0
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16330
Tested-by: build bot (Jenkins)
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This is necessary for PCI express graphics card add-ons,
otherwise the pci allocator cannot fit the mmio for the
add on card into the space it has available and the OS
turns off the card. Old value was 1GiB.
Change-Id: I606994501b15e636fe209d1ed4b3d3f73b42bf5c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
No more hang on DMI init when wait for DMI is re-enabled.
Previously the virtual channel arbitration table was not being
set up in the south/north bridges causing invalid DMI state.
This has been tested on GA-G41M-ES2L with patches following.
An NVIDIA GT218 card was detected by the OS and displayed using
the nouveau driver with no blobs.
Change-Id: I35e03c40f5f7aa4915afd5d26db7ab053abcf0cd
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/16491
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
According to "G45: Volume 3: Display Register
Intel ® 965G Express Chipset Family and Intel ®
G35 Express Chipset Graphics Controller" some registries
are set incorrectly in gm45/gma.c.
Some values are changed after comparing them with the values
the i915 linux kernel (3.13 was used) module sets while modesetting.
The values were obtained using 'intel_reg' from intel-gpu-tools,
during a normal boot and with 'nomodeset' as a kernel argument.
Some registers that don't exist on gm45 are set in gma.c, which is
probably the result of copying code from a more recent intel
northbridge.
The result is that that gm45 laptops with wxga displays still work as
before. gm45 laptops with wxga+ or higher resolution now just work,
where previously a black screen was shown.
TEST: build with native graphic init and flash on a gm45 target, like
lenovo x200.
Change-Id: If66b60c7189997c558270f9e474851fe7e2219f1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16217
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Remove an unusued function declaration that caused problems while
compiling the target.
Change-Id: Idfd73693e9b0e1777cafa4706113fde394e95795
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16435
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Replace the use of the old device_t definition inside
northbridge/intel/i945.
The patch has been tested both with the arch/io.h definition of
device_t enabled and disabled in order to ensure compatibility
while the transaction takes place.
Change-Id: I041c150a7b50261e26955ad9287ef05b9a06e412
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16371
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replace the use of the old device_t definition inside
northbridge/intel/sandybridge.
The patch has been tested both with the arch/io.h definition of device_t
enabled and disabled in order to ensure compatibility while the
transaction takes place.
Change-Id: I35cc76ec7b6baa216666d06f6f325f43ac69067e
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/16409
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
