Now that microcode has been added to blobs, use that one instead of
the one included in the tree. Microcode from the tree will be
removed in a subsequent patch. Since the microcode updates are blobs,
they belong in the blobs repository.
This change may introduce a build failure if the "Generate from tree"
microcode option is selected, but the blobs repository is not
enabled. We have to live with this for now, until microcode is moved
to blobs for all CPUs, at which point we may adjust Kconfig
accordingly.
Leave the FSP cpu alone for now, as that will need approval from
SAGE.
Change-Id: Ia77ba2e26c083da092449b04ab2323b91a2ca15b
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4530
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
During the development of commit bde6d30 (x86: Change MMIO addr
in readN(addr)/writeN(addr, val) to pointer), there were several iterations
and patterns tried. An intermediate pattern was the use of u32 pointers,
and division by sizeof(u32). Some of these did not get properly
changed to pointer types of length 1, causing a regression in
the Intel Ibex Peak SATA driver, fixed in commit 9b5f137
(Intel ibexpeak: Fix SATA configuration).
Other regressions of this pattern are fixed here. I audited all changes
to u32 types, and the other ones are safe.
Change-Id: I9e73ac8f4329df8bf0cdd1a14759f0280f974052
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Reviewed-on: http://review.coreboot.org/8530
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The Winbond W83793 fan controller is not automatically
configured correctly on power application, leading to
abnormal, and in some cases random, fan behaviour.
This commit enables the controller and sets sane default
values.
TEST: Booted mainboard and verified that the correct number
of fan speed sensors were visible from hwmon under Linux.
Also verified that, unlike before, the CPU fans were running
at a high enough speed to properly cool the CPUs. Verified
the 8 fan outputs under direct control of the W83793 device.
Verified voltage and temperature sensors and limits via output
of the 'sensors' command.
Change-Id: Ie3753bd3111d9d9eb46826da410c132caec4d9fe
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8503
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The version field for t132 cpus is 0x00130001. Update it to
the correct version.
BUG=chrome-os-partner:29882
BRANCH=None
TEST=Built and was able to see serial with subsequent changes.
Original-Change-Id: I39d560307261fdfc34e071f5c35a4397c134e03c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205435
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 14916b3ba5545ab2cb35b6a4a7fa231b895ede46)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I785069d3eb82ed24bafd52ef627d53505a35c09a
Reviewed-on: http://review.coreboot.org/8467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
CONFIG_CONSOLE_SERIAL_UART has been updated to
CONFIG_DRIVER_UART. The UART may be used for more than serial console.
Change-Id: Ife6e6861d210126b2b9ba5eee9ff72e8a447c47f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8516
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The early_console.c file isn't used or built. It has been replaced
by the generic uart and console drivers.
Change-Id: I505b4e48d2369dbbfd92ef1dab364c5f2ed924df
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8529
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix up commit ce7ecf9c (baytrail: enable monotonic timer), which
selected `HAVE_MONOTONIC_TIMER` explicitly, although it is already
selected by `TSC_MONOTONIC_TIMER` (cf. `src/cpu/x86/Kconfig`).
Therefore remove the explicit selection of that Kconfig option.
Change-Id: I8964771947a6f7457dcdefe7a17be623ae0ef900
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8471
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
No real harm done (thanks to our free() implementation),
but let's do it right.
Change-Id: Ib98d28aabc043dff5c288728c33490a79f09f35a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8511
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Add a new driver for Intel i210 MACPHY with the goal to
update the MAC address in i210 if it is found
during PCI scan.
Change-Id: I4d4e797543a9f278fb649596f63ae8e1f285b3c3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8404
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
DEFAULT_CONSOLE_LOGLEVEL_* is supposed to be selected by the user, and
should not be overriden by any other part of the tree. As such, remove
the selection of DEFAULT_CONSOLE_LOGLEVEL_7 from these two boards.
Change-Id: I194a71b371b184e81a16fec2bd21f1b0deb4ebbf
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8486
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This option is already defined in console/Kconfig, and is intended
to be controlled by the user. Only six boards in the entire tree
redefined it, so remove the definition from those boards.
Change-Id: I3a65444f63c93c01d78569a9a7eb01158fb290bd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8457
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
SUPPORT_CPU_UCODE_IN_CBFS is a deprecated option now that all CPUs
with updateable microcode (except AGESA) load microcode from CBFS.
CPU_MICROCODE_ADDED_DURING_BUILD is a state variable that is set
based on user's choice in the microcode menu and should not be changed
directly.
Eliminate INCLUDE_MICROCODE_IN_BUILD variable, whose use directly
interferes with the microcode mechanism, remove selection of
CPU_MICROCODE_ADDED_DURING_BUILD, and do not depend
SUPPORT_CPU_UCODE_IN_CBFS on anything. This makes usage of the
microcode mechanism consistent with other CPUs in the tree.
This incorrect usage of the Kconfig variables was hiding the fact that
some of the microcode files present in fsp_baytrail/microcode_blob.c
were not present in the tree.
Change-Id: I71cb3f834c22c0363a20bd469797a9f51c215371
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Change gpp_configuration to GPP_CFGMODE_X1111 (was X4000), this is done
to only advertise x1 lane width for PCIe link 0:15.0.
Hide functions of PCIe links that have no slots connected. Our PCI
infrastructure does not support bridge devices that are set off
in devicetree but remain visible in the PCI hardware tree.
Change-Id: If90919634995076ab0f029baece3ba9cb8f3f3b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8388
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Remove functions 0:12.1 and 0:13.1 that do not exist in the hardware.
Disable 0:14.1 IDE controller, as it would only be used with SATA ports
4 and 5 that are not populated with connectors in the hardware.
Disable 0:14.2 HD audio, as it is not implemented in the hardware
Disable 0:14.5 OHCI controller, as ports behind this USB1.1 -only controller
are not populated in the hardware.
Fix some alignment and whitespace.
To my knowledge these changes are not included with SAGE release
pcengines.apu_139_osp.tar.gz, but that tarball does not contain
either devicetree.cb or a pre-compiled static.c file so I cannot tell
for sure.
Change-Id: Idcb8e76645fce7e89a37ff7007531b668f472131
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8328
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Interrupts from USB controllers 0:16.0 and 0:16.2 were not routed
in PIC mode. The only affected peripheral was the SD card reader.
This patch is not included with SAGE release pcengines.apu_139_osp.tar.gz.
Change-Id: Ie7f0fa3751b46cca0132bd6dcada3628c6a45efb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8327
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Some GPIO pins are shared with (disabled) PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, we cannot mark 0:14.4
disabled in devicetree just yet.
Change-Id: Ibc5d950662d633a07d62fd5a5984a56d8e5f959d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8326
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
While we cannot recreate exact copies of PC Engines APU1 firmware images,
I shall upstream the vital changes for coreboot from the following tarballs
SAGE has published to meet GPL:
SageBios_PCEngines_APU_sources_for_publishing_20140405_GPL_package.tar.gz
md5sum: ce5f54723e4fe3b63a1a3e35586728d4
pcengines.apu_139_osp.tar.gz
md5sum: af6c8ab3b85d1a5a9fbeb41efa30a1ef
The patch here adds Kconfig, Makefile.inc and devicetree.cb files to
match 2014/04/05 release tarball config.h and static.c files.
Change-Id: Id61270b4d484f712a5c0e780a01fc81f1550b9ad
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8325
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Some GPIO pins are shared with PCI bridge 0:14.4.
As our PCI subsystem currently does not configure PCI bridges that are
marked disabled, but remain visible in the hardware, simply setting 0:14.4
disabled in the devicetree does not work here yet.
Change-Id: Ib9652e12a888e1d797d879d97737ba4101b7029a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8495
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Tested-by: build bot (Jenkins)
The goto statement skipped all the code that is necessary
to fill in the data structures that are read right after
the jump.
Since there doesn't seem to be useful data, why write these
ACPI objects in the first place?
Change-Id: I1d06c11a7a31517b81e54159355d5c27e3cc3735
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8507
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
xgifb_probe() doesn't own the object it tries to free
in its error code path, potentially leading to a
double-free in xgi_z9s_init().
Since we don't actually implement free, it doesn't matter
too much, but let's keep things proper.
Change-Id: I70c8f395fd59584664040ca6e07be56e046c80fc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Found-by: Coverity Scan
Reviewed-on: http://review.coreboot.org/8506
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The change in commit 5636237 allows */cpu/amd/agesa/* to be removed.
TEST: Booted the amd/parmer board.
Change-Id: I8d2d2639f8e5f3b1dd58be96be98db0eff7b268f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8505
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This copies a change made in commit 1cc3338 that allows alloc_cbmem()
to be called only in ramstage. This will allow the */cpu/amd/agesa/*
field to be removed from the list of illegal_globals EXCLUDE_FILEs.
TEST: Booted the amd/parmer board.
Change-Id: I2d4b5352815aae090ffce7b83e487f7c0a4d0c88
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8504
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
That's just how we roll.
Change-Id: I47ef62476703fdf2544d9cd77c30ae12452afeae
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/8514
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If function cmos_init() was called with parameter invalid
set, this indicates, that the caller has found a power
loss event in the RTC registers. In this case, we need to
load the default date and time because it can be corrupted.
Change-Id: Ib8d58a14da0182ceb8167e67440a0f1ea2a20eb7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8373
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Fan 2 and Fan 3 were inexplicably set to zero after device
setup.
Change-Id: I37945745dbfaf33eb28808d85cdf75dca401e44b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8520
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Without this change the builder would fail with the complaint
that there was a global static variable in romstage. alloc_cbmem()
is only called in ramstage. The alternative was to add
*/cpu/amd/pi/*.romstage.o to the list of illegal_globals
EXCLUDE_FILEs in arch/x86/init/romstage.ld.
TEST: Booted the amd/lamar board.
Change-Id: I5167910ff790a3152a4ad8e5af0a4a3b17894f0f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8256
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This adds the AMD Family 15h model 30 CPU.
S3 suspend/resume currently is not supported.
Tested on the amd/lamar platform.
Change-Id: Ifef55747a5d715b17937fc75ab9d35945b59f0e6
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The coreboot I²C API was completely reworked in commit
* cdb61a6 i2c: Replace the i2c API.
For the allwinner I²C driver, wrappers to the old API were provided
on a "best guess" basis. Replace these wrappers with proper
transaction handling based on the i2c_seg API.
Change-Id: Ibdda3b022ce4876deb2906e17a5a0ca9e939aada
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8431
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Originally, axp209_(read|write) accessors relied on i2c_(read|write)
to return the number of bytes transferred. This was changed in
* cdb61a6 i2c: Replace the i2c API.
to return an error code or 0 on success. This caused the AXP209 check
to fail. Fix the accessors to account for this new behavior.
Change-Id: Ib0f492bd52260d224d87f8e8f2d3c1244d1507df
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8432
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
We only need one of devx and dev. This function should be called
with dev already adjusted if link_num > 3.
Change-Id: I7166bbb88143bc28802c9530c4da16db67868d8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8351
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These settings are specific to the SteppeEagle SOC and should
be made in its northbridge code rather than the CPU code.
Change-Id: I1a231f95225e1414b0cbc026a2a7b7797bd91fca
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8254
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
They seem to have been copy-pasted during the backport from sandybridge.
Change-Id: I2277bb90e6da2676b31eb2665b7c15f074e3d4bf
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8295
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
It's not very useful to try to link a host tool into
the bootblock image.
Change-Id: Id3b6496c061d41184fbb516d56746855b455b0c3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/8473
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Note that the limit is not set in the devicetree.cb which use native
sandybridge raminit, as it is not needed. When that isn't set, it's
automatically set to zero, and when we find that, we automatically
return the default limit. Thus behavior isn't changed for any board.
Change-Id: I447399eea71355612b654710a56f3a0077c2f7f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8476
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
We can successfully bring up systems if timC calibration fails, as has
been demonstrated with google/butterfly. As a result, do not die(),
but simply print a message and continue in the hope that we may be
able to boot.
Change-Id: I49ec80324f63b2d45ae8f61c5c26454acb9c232f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8475
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Builds with cbootimage.
BUG=None
BRANCH=None
TEST=build test
Original-Change-Id: I796f171031bacf17106878d4a554e8f1cbfe93f8
Original-Signed-off-by: Furquan Shaikh <furquan@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203145
Original-Tested-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 4778ae4d08a25306407f0fd2fe47976d63463f9d)
Increase the bootblock area for the larger BCT that is generated by
the coreboot version of the cbootimage tool.
Change-Id: I42b8208504bf4936a9fa14f820d665590f6a3754
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8413
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Changes might be required for .bct files as we get to know more.
Pulling in files from mainboard nyan for now
BUG=None
BRANCH=None
TEST=Compiles successfully for rush
Change-Id: Iaf81a384af0469c77940cf7309ba68018110b5eb
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/203144
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit d3633f8cf8c01a07b54ceef2dd7bf7a64afd7c76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8412
Reviewed-by: Aaron Durbin <adurbin@google.com>
This patch is to perform software triggered RAM re-repair in
the warm boot path.
"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.
Also, note that this file isn't built in coreboot proper, but is a
companion binary for kernel. It resides here for safe keeping.
BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run suspend_stress_test on nyan.
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I540f8afbffa323d1e378cb6ba6a20be4afd08339
Original-Reviewed-on: https://chromium-review.googlesource.com/207422
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit f06c413c42819f8f75d9b0fecde02b82583f1d2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I151ce943ce8623e46cc55f890bbd6fc641cc2b98
Reviewed-on: http://review.coreboot.org/8416
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch is to perform software triggered RAM re-repair in
the cold boot path.
"RAM" actually refers to the CPU cache here (yeah, I know, but that's
how the manuals call it). This is some magic hardware thing that must be
done every time after applying power to the main CPU cores or their
cache may have random failures in some very rare cases.
BUG=chrome-os-partner:30430
BRANCH=nyan
TEST=run cold reboot test on nyan.
Original-Signed-off-by: Yen Lin <yelin@nvidia.com>
Original-Change-Id: I87869431e80e7bc66948a7f67f35e5b907993765
Original-Reviewed-on: https://chromium-review.googlesource.com/207362
Original-Tested-by: Yen Lin <yelin@nvidia.com>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Yen Lin <yelin@nvidia.com>
(cherry picked from commit d999f5ecc31d90c8dce1dd91533bc34ffd3c03f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iaee1d7f9fa8856f26d7ead70eaeeff9d80dbb181
Reviewed-on: http://review.coreboot.org/8415
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Based on TRM, cpu clock enabling and reset vector setting should
all be done properly before ungating cpu power partition. Otherwise,
with current code, a race condition could occur where cpu starts but
reset vector has not been set.
BUG=chrome-os-partner:30064
BRANCH=none
TEST=run nyan_big reboot test. No issue is experienced.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I571e128693bb2763ee673bd183b8cf60921dc475
Original-Reviewed-on: https://chromium-review.googlesource.com/206682
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 106480ff32406c899a24544fdfab858db5afd1d9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3da6018dd68e4c15d2c58db566a9745b0b26c365
Reviewed-on: http://review.coreboot.org/8414
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All code must agree on PCI enumeration for the CK804 device,
define these only once. The definition in enable_usbdebug.c was
different and was assumed incorrect.
Change-Id: I7d25c145afbad41db81a6b9b4f3956ad50fcb9f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8339
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This reverts commit b871687991.
Use of #ifndef here makes it error-prone and hides errors.
Change-Id: I13a999250c80adedb6b3fd4963a862ff106750f0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8338
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This patch allows the user to set a maximum HT link frequency in
NVRAM, paralleling a similar option available in the proprietary
BIOS on some mainboards.
Change-Id: Iba3789262eefa52421e76533cbf14d9da2ef1de8
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8462
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The existing code generated invalid ACPI processor objects
if the core number was greater than 9. The first invalid
object instance was autocorrected by Linux, but subsequent
instances conflicted with each other, leading to a failure
to boot if more than 10 CPU cores were installed.
The modified code will function with up to 99 cores.
Change-Id: I62dc0eb61ae2e2b7f7dcf30e9c7de09cd901a81c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8422
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
All settable memory controller options are now controlled by NVRAM,
making the Kconfig options irrelevant.
Change-Id: I9b2c8798d830e5c41bb9a108514e60d784d2ebc5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8452
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
K10 processors cannot operate at full memory speeds when more than a
certain number of DIMMs are installed on a specific channel. The
allowed DIMM numbers and speeds are listed in the BKDG; this patch
implements the appropriate frequency reduction to ensure stability.
Change-Id: I8ac5b508915e423d262ad36c49de1fe696df2ecd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8435
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These values were originally hard-coded in the AMD MCT wrapper.
Change-Id: I12056d38d5348e70a44c192385e22e715e207792
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8454
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In specific configurations, such as homogeneous supercomputing systems,
changeable NVRAM parameters are more of a liability than a useful tool.
This patch allows a coreboot image to be compiled that will always set
the NVRAM parameters to their default values, reducing maintainance
overhead on large clusters.
Change-Id: Ic03e34211d4a58cd60740f2d9a6b50e11fe85822
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8446
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This fixes errors of the form:
error: 'Dct0MemSize' may be used uninitialized in this function
Change-Id: Ifc853aea9050994f5641c57a081aa0667331c995
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8455
Tested-by: build bot (Jenkins)
TEST: Boot with corrupted CMOS and make sure console level defaults
to SPEW, instead of 0, and that cbmem console is not empty.
Change-Id: I8ab2423e99bbe116f52ad27f4b20427d8557f6ff
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8379
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch allows the following memory controller settings to be overridden in NVRAM:
Memory frequency limit
ECC enable
ECC scrub rate
Change-Id: Ibfde3d888b0f81a29a14af2d142171510b87655e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8438
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Currently the coreboot console log contains messages in the following
form.
Show all devs...Before device enumeration.
[…]
Show all devs...After init.
Add a space after the ellipse, so it’s better readable and it does not
look like a newline is missing.
Show all devs... Before device enumeration.
[…]
Show all devs... After init.
Change-Id: Ifa2a37b8d60c433c219df7533a79fced03b6271a
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8424
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.
Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
The default linking behavior of ramstage was changed in commit
* 8f99378 ARMv7/Exynos: Fix memory location assumptions
However, that commit failed to address the issue of maintaining
linking behavior on non-Exynos chips. As a result we ended up
linking ramstage at address 0, which is outside of SDRAM.
Explicitly link ramstage at SDRAM base for A10. This patch does not
address the issue on other chips that were broken by commit 8f99378.
Change-Id: I90fa41d3eabf110b5ab24c31b78ac6d0474e4083
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8443
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
PCIe root ports on devices 0:15.0 to 0:15.3 should at first all
appear visible in hardware. The real configuration will be done by
vendorcode once we call sb_Before_Pci_Init().
Change-Id: I01a46c630aa6d55a94af45da6b78c97df7553e4f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8387
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This has nothing to do with SATA controller. We only need to
fill the table with defaults before we parse devicetree for
changes to device configuration.
Change-Id: Ic4b28b5992ec9bfdf252f61b1c86b0162243cc95
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8386
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If devicetree.cb has GPP port off, really disable it before even
trying to do link training.
Change-Id: I810945da28d86768e88249dc4d29a50ad9f9959b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8385
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
A set of pins can be configured for GPIO or (parallel) PCI bridge use.
When requested configuration is 0:14.4 enabled, register programming
must be done before attempting to enumerate devices behind the bridge.
When requested configuration is 0:14.4 disabled, we must not even
temporarily enable pins for PCI use to avoid spurious GPIO state changes.
As our PCI subsystem currently does not configure visible PCI bridges
that are marked disabled, we cannot mark 0:14.4 disabled just yet but
need to handle pcengines/apu1 as a special case.
Drop related dead code.
Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8329
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These sb800_enable() messages without newline mess up the log.
Change-Id: I1689b68702e08e2a287083835f310f52f495c451
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8384
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Kconfig variable is not implemented.
Change-Id: I546a1001847e7b1002f96baf49ed3301852a6894
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8345
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Keep the slower HyperTransport configuration for a possible reference
in fam15 boards.
Change-Id: Ifcdedc6385fec80f7d02c55c2aac10e5e2429a18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8344
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Probing is done by reading the ID register and comparing it to a known
value. When there is a mismatch, print an error.
Change-Id: I36fb1fe9b56e97660556dcb27be25bfe5129ad73
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The actual key values were not added in commit 17ace8255.
TEST: amd/lamar shows the correct result.
Change-Id: I8f20e3d0ce83dd87b6c233ee98c3e77a6b7c1b03
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8375
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Marc Jones <marc.jones@se-eng.com>
This combines the Avalon and Bolton tables of text descriptions
of the IRQ assignments. It also corrects the text string for
the SD controller on Bolton.
Test: This was verified on amd/lamar.
Change-Id: Ibc74641eb4e1f7581f26d260ba3d33201bcbf5e7
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8374
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Verstage isn't included yet, but we need to have
the Kconfig option for toolchain.inc to pass.
Change-Id: I7fae73cd3b77fd347398221489caf745274701eb
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/8409
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add two macros to gpio.h which allow to setup 20K
pull-up or pull-down resistor for a given GPIO.
Change-Id: Ie3bc4d40df588ed682cc692e2a80527b9e62a483
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8402
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Two source files were accidently marked executable. Switch them back to
mode 644 (rw-r---r--)
Change-Id: Ic96f6e5e9a05cbffb65cdfb627023d04d3866dc9
Signed-off-by: Stefan Reinauer <stepan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8426
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
SeaVGABIOS supports both the coreboot linear framebuffer and native EGA
text mode. To use SeaBIOS interactively on standard VGA hardware a VBIOS
is needed; SeaVGABIOS is one such option.
TEST: Booted KFSN4-DRE with XGI Volari Z9s and SeaVGABIOS. Was able to
interact with SeaBIOS and comboot menu, then booted Linux successfully.
VGA display was continuously usable from power on to Linux login.
Change-Id: Id4bd4cb5cece9114457633832c5f0e5280c02b47
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8368
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I92e6e7f1292f66642aa0336064a4eccba104dd08
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5101
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The core count identification code in the PowerNow! _PSS
ACPI object generation code was incorrectly copied from the
model_fxx code. This code has been rewritten to properly
return the number of cores installed in the system.
Change-Id: I19567486f2de9dc2c43970addf4d91fa3d233a99
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8421
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
The PCI id defaults to 1106,3230 -> via chrome 9 ...
Tested on the board.
Change-Id: I5ad91faec9c97f34c8ca48eee9198237e9ea8336
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8177
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
microcode updates are extracted from: www.amd64.org/microcode.html
Mircocode versions of 1020h and 1022h are more recent in coreboot
than inside the AMD archive.
Change-Id: I9f52accc1ebc7057890a769a059048e9982109d2
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8354
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This resolves an issue on Shanghai dual CPU configurations where
the APs on node 0 would not start. Single CPU configurations are
unaffected by this issue.
TEST: Booted KFSN4-DRE with dual Opteron 8389 CPUs and verified
proper BSP/AP start and microcode patch levels.
Change-Id: I0f5d4e0e356c6bd64e324b4399ef43b400ecab0c
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8397
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Improve documentation of lock down MSRs in finalize().
Most of these aren't documented in public MSRs.
Change-Id: I4fc47bb9b71bdd7907aae65fc18b419a17ae8547
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/8294
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
There is no auto-detection for AGP type and we have no hardware that
selects this. Furthermore, we treat AGP bridges just like PCI bridges,
there is no optimisation for higher bandwidth.
Change-Id: I4fe87c83411643cb9b8d3216f2af07bf098174d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8367
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
By adding a description to ME_PATH it becomes visible
and editable in menuconfig.
Change-Id: I8c2f6a30c10f16b19f3667263db02c93688c9f8f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/8398
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The original firmware has a 2 MiB BIOS region in both 4 MiB and 8 MiB
flash variants. Let's allow using the whole region instead of the
gm45 default of 1 MiB.
Change-Id: I2d8a04bcb992bf2e8e15890a5c6719810b1cf405
Signed-off-by: Michał Masłowski <mtjm@mtjm.eu>
Reviewed-on: http://review.coreboot.org/8392
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fix a mistake that led to an invalid 0ms latency in the automatically
generated PowerNow! ACPI _PSS objects.
TEST: Booted FreeBSD and Linux and verified correct latency values.
Found-by: Coverity Scan
Change-Id: I03cecab694708136dc555ca2af7ee9a0bf9be5af
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8376
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Because the pointer to the FSP HOB list is now being saved, we can
use that to find the top of usable memory. This eliminates the need
to hardcode the size of the FSP reserved memory area.
Tested on minnowboard max for baytrail.
The HOB structure used does not seem to be present for the rangeley
or ivybridge/pantherpoint FSPs. At the very least, the GUID is not
documented in the integration guides.
Change-Id: I643e57655f55bfada60075b55aad2ce010ec4f67
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8308
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
The "used" attribute was added in commit 27cf2472 which caused these
warnings to start appearing when using the standard coreboot GCC
toolchain:
{standard input}: Assembler messages:
{standard input}:96: Warning: ignoring changed section type for .car.global_data
{standard input}:96: Warning: ignoring changed section attributes for
.car.global_data
The # at the end of the section name causes the assembler to
ignore everything following the name. I verified that the resulting
binaries are the same with and without the #.
Change-Id: Iaac8042533842ed887f33895f083b613a18f496a
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8301
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Now that BROKEN_CAR_MIGRATE is fixed we can stash these in CAR.
Change-Id: I49c31b91f34d415778797d08a347a51dbef797e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8024
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
The port is based on the x230 / t530.
Tested - is in active use.
Change-Id: Ic5ccfe70343e8aef3465690edce9cdebf153a44d
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8359
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
cmos_init() had layers of preprocessor directives, which resulted in
a complete mess. Refactor it to make use of the IS_ENABLED() macro.
This improves readability significantly.
One of the changes is to remove in inline stub declaration of
(get|set)_option. Although that provided the ability for the compiler
to optimize out code when USE_OPTION_TABLE is not selected, there is
no evidence that such savings are measureable.
Change-Id: I07f00084d809adbb55031b2079f71136ade3028e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8306
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This macro is controversial for arches where the bits are numbered
MSb first, though we don't support such an arch. We've seen this macro
creep into our tree in different places, so provide it in one place.
Change-Id: I86cd8a16420f34ef31b615aec4e0f7bd3191ca35
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8280
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
TEST: Booted KFSN4-DRE with on-board XGI Volari Z9s
Initial text from coreboot appeared, and the Linux
console was displayed immediately at the start of
kernel initialization. After boot was complete
the text mode console continued to behave normally.
SeaBIOS does not currently make use of the legacy
VGA text-mode display.
Change-Id: I2177a1d00e6f07db661dd99fe0184e2c228404d1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8360
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The indentations of #define are not consistent in chip.h. Update to make
all #define indentations being aligned and put them after the variable
declaration.
Change-Id: I37550acac18bac3efddb580ef6b956be0e2b357a
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8333
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
1) Save the pointer to the FSP HOB list to low memory at address 0x614.
This is the same location as CBMEM_RESUME_BACKUP - the two aren't used
in the same platform, so overlapping should be OK. I didn't see any
documentation that actually said that this location was free to use, and
didn't need to be restored after use in S3 resume, but it looks like
the DOS boot vector gets loaded juat above this location, so it SHOULD
be ok. The alternative is to copy the memory out and store it in cbmem
until we're ready to restore it.
2) When a request for the pointer to a CAR variable comes in, pass back
the location inside the FSP hob structure.
3) Skip the memcopy of the CAR Data. The CAR variables do not
get transitioned back into cbmem, but used out of the HOB structure.
4) Remove the BROKEN_CAR_MIGRATE Kconfig option from the FSP platform.
Change-Id: Iaf566dce1b41a3bcb17e4134877f68262b5e113f
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8196
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add native XGI Z9s framebuffer support to coreboot
XGI initialization code largely taken from Linux 3.18.5
TEST: Booted KFSN4-DRE with XGI Volari Z9s into SeaBIOS
with SeaVGABIOS enabled. Text appeared correctly on screen
and interaction with graphical comboot menu was successful.
However, Linux cleared the framebuffer on boot, rendering the
screen useless until Linux loaded its native xgifb driver.
Change-Id: I606a3892849fc578b0c4d74536aec0a0adef3be3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8331
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This copies what was done in southbridge/amd/agesa in:
commit 56f46d8 agesa/family15tn: Switch to per-device ACPI
TEST: amd/lamar.
Change-Id: Id8890ccd4a1ea783ad4740333ae6b061b6bbd7fc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8288
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This adds the PCI and interrupt related definitions
for the bolton specific features.
Change-Id: Ia6530c57ec5a4a5c4525bfbae0eb5db04c0bef9e
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8286
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tests on CPUID are valid regardless of revision.
Change-Id: I5a3a01baca2c0ecfb018ca7965994ba74889a2e2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8337
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Keep the value that is listed first, it also the one with a more
recent change.
Change-Id: I0336c962544d75f94512563c08f280aa43c7a175
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8336
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The amd/lamar mainboard is the first mainboard to use the f81216h.
These changes are needed to fix up commit 27a63d77 so the
Super I/O builds and functions correctly.
- Wrong #include name
- Removed global variable in romstage
- Missing "case" in switch()
Change-Id: I1b2058a915b776664fba14e4341e8a410b50330f
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8255
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Include microcode updates in CBFS for every CPU revision the platform
can support, as changing to different CPU revision should not require
a coreboot rebuild.
This increases CBFS usage from 2 kB to 14 kB.
Change-Id: I6bf90221a688f1a54e49641ce3ba378c5bf659f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4521
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
This option is now deperecated by loading microcode updates from cbfs.
Remove this option in anticipation of implementing CBFS loading for
AMD cpus. Removing it beforehand results in less patch overhead.
Change-Id: Ibdef7843db686734e2b6b1568692720fb543b240
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8322
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Use HT MSI Mapping capability register at 0xe0 in CK804 HT device to enable
HT MSI Mapping so that MSIs work. Prior to this change PCIe devices
downstream of the CK804 with MSI enabled would fail to actually assert
their interrupt. Tested on msi/ms7135 and winent/mb6047 running Debian
GNU/Linux 7.0 (wheezy).
Change-Id: I5e0dc8b352f3d04e3b16b899af11d2b908a82850
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/8276
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Although bool normally belongs in stdbool.h, for our use cases,
providing these definitions in stdint.h is acceptable.
Change-Id: I1d0ca1018efacc27d7a4a72aa452912e004401f9
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8279
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Rangeley POST-GOLD 2 FSP added PCIe ports de-emphasis configuration
by UPD input. Update UPD_DATA_REGION structure for matching up this
FSP change.
PcdCustomerRevision is a debugging aid that will be output to debug
message in FSP. When needed, it can be customized by BCT tool for tracking
BCT configurations.
Change-Id: I6d4138c9d8bbb9c89f24c77f976dbc760d626a9b
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/8107
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
This patch clears the CAR area. The FSP loads the entire CAR area with a
pattern instead of clearing it. At least the cbmem area needs to be
cleared or cbmem will not use it.
Change-Id: I829ddc26133353a784dfc01729af9b3bf427e889
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8195
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Test:
Single Opteron 2419 with 1GB RAM in slot A1
Booted Ubuntu Linux 14.04 and verified all 6 cores were visible
Brief stress test of all 6 cores simultaneously
Verified proper ACPI power states for all 6 cores
Change-Id: I1e598e36f9eaed5ba8a18b9c62ceedee16870f15
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8311
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Move mapping tables to struct and prevent OOB array
access that was crashing the APs during CAR initialization.
Change-Id: I9e2554b50ad60a8d02ef4bd3fbee6fddb238d83f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8310
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Some magic numbers are documented in the PCH datasheet so use them.
Change-Id: I15b58ff99b3bc11ac437e5ea74f4f01b7c02032a
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8307
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
OC2 at port 4 was missing. Verified with RCBA dump.
Change-Id: Ide5701d53aeee28619204c7ac408662626aa11e4
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8304
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
thinkpad_acpi checks that BIOS version matches some pattern.
Report version in this form.
same as http://review.coreboot.org/4650 /
63acd22dc5
Change-Id: I82d7a2b9f2ec56557b3a9c26d1af57ed39e31850
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/8302
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add a function to retrieve the location of the CAR temporary memory
that was saved by the FSP into the HOB structure.
Change-Id: I2635de5207cd699740721d333a7706425b837651
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8194
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Status:
Tested with KFSN4-DRE PCB v1.04G
Booted Ubuntu Linux 14.04 and all onboard peripherals appear to work.
Dual Opteron 8347 CPUs tested with 8GB RAM (4GB per bank).
Dual Opteron 8356 CPUs tested with 1GB RAM in slot A1.
AMD PowerNow! functions correctly via ACPI.
Video, network, USB, SATA, and serial have received thorough testing.
Tested with KFSN4-DRE PCB v1.05G
Single Opteron 2419 CPU tested with 1GB RAM in slot A1.
Booted to PXE configuration menu; not tested further.
Known issues:
RAM initialization is a bit flaky with multiple high-density modules;
this could be a generic MCT training issue but is probably bad hardware.
The XGI Volari option ROM crashes SeaBIOS v1.7.5, but the video device
works after Linux boots and initializes the device.
Suspend/resume functions at the S1 level but sometimes hangs on resume.
Wake on LAN can be flaky; the strap(s) needed to have WoL work on power
application were not physically installed by ASUS so the board needs to
boot at least once after power application before it will work.
Change-Id: I0709f822eea8ed877f55db9443143028a5400472
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8270
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This fixes the resource allocator locating the PCI register
space below 0xe0000000 thereby causing corruption with more
than ~3.5GB physical RAM on AMD Family 10h systems.
Change-Id: I66d1bfa1e977a6b492c1909079087a801c7e6a3a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8261
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Skeleton and ACPI generator interface taken from
model_fxx powernow_acpi.c
Small portions of FIDVID MSR code taken from
model_10xxx fidvid.c
Nearly completely rewritten for the P-state-based K10 CPU
TEST: KFSN4-DRE with dual Opteron 8356 CPUs
Verified CPU per-core dynamic state change with system load
Verified reported P-state count and frequencies
Stress-tested each CPU (all cores simultaneously) to verify
proper P0 transition and configuration.
Change-Id: Icf620ec96a3f163b62d96b5988184996641dd439
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8284
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The build failure stems from a missing function being called via a chain
including setup_ss_table(), set_ht_link_ck804(), and
st_ht_link_buffer_counts_chain(); the latter function is only available
in the AMD K8 code.
It appears that a bunch of K8-specific code snuck into the CK804 and MCP55
southbridge code in GIT commit 968bbe89 and GIT commit d4b278c0.
Change-Id: I85d005edba44c503c49917d4b928e5c9c5900059
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8269
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
On the ASUS KFSN4-DRE initializing CK804 0x78 causes an almost
immediate soft reset. Leaving the register at its power-on
default value appears to have no ill effect on that same board.
Change-Id: I833603adea580cb3f4441e35044d1e17d2d67852
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8272
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Fix three IASL warnings in ASL utility code by making the
methods `GWBM`, `GWEM` and `GIOR` serialized.
TEST: Built and booted on ASUS KFSN4-DRE.
Change-Id: Ia98088bea7e3e21c33252c98a675799d52edb809
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8264
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Drop the implementation of statically allocated high memory
region for CBMEM. There is no longer the need to explicitly
select DYNAMIC_CBMEM, it is the only remaining choice.
Change-Id: Iadf6f27a134e05daa1038646d0b4e0b8f9f0587a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7851
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
We can now create CBMEM with dynamic allocation even if CBMEM
location is resolved late in ramstage.
Change-Id: I8529ccbcd4a0e567ebe0a46232ac5d16476e81a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7861
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
The name was always obscure and confusing. Instead define cbmem_top()
directly in the chipset code for x86 like on ARMs.
TODO: Check TSEG alignment, it used for MTRR programming.
Change-Id: Ibbe5f05ab9c7d87d09caa673766cd17d192cd045
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7888
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Move the CAR migration call to arch -specific part of CBMEM init,
it is truly a x86 specific thing.
Change-Id: I715417e54f197b8745e0670d6b900a5660178141
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7860
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
In preparation to remove the static CBMEM allocator, tag the chipsets
that still do not implement get_top_of_ram() for romstage.
LATE_CBMEM_INIT also implies BROKEN_CAR_MIGRATE.
Change-Id: Iad359db2e65ac15c54ff6e9635429628e4db6fde
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7850
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Use the value of CONSOLE_PRERAM_BUFFER_SIZE to determine if we can
do CBMEM console in bootblock and romstage. Kconfig forces it to zero
if _BASE is unset or we cannot do CAR migration on x86.
Add CBMEM console to bootblock, except for x86. Only one of bootblock
and romstage clears the pre-RAM buffer.
To start with empty console log on S3 wakeup, ramstage now clears
previous contents of CBMEM buffer if there was no pre-RAM buffer.
Unify Kconfig variable naming.
TODO: ARM configurations do not define PRERAM_BUFFER_BASE values.
Change-Id: I70d82da629529dbfd7bc9491223abd703cbc0115
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This avoids the need for separate timestamp_reinit() calls made
via CAR_MIGRATE() that is not implemented for ARM.
Change-Id: Ia683162f3cb5d3cb3d4b7983a4b7e13306b0cfc8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8033
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
This replaces need for separate cbmemc_reinit() calls made
via CAR_MIGRATE() and in ramstage.
Change-Id: If7b4d855c75df58b173f26ef3c90a4a7563166d3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7859
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
With the change it becomes irrelevant if memcpy() car.global_data or
cbmemc_reinit() is done first.
Change-Id: Ie479eef346c959e97dcc55861ccb0db1321fb7b2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8032
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Until we completely can unify early_variables, use these to
handle CBMEM update hooks for both romstage and ramstage.
For x86, CAR_MIGRATE serves the purpose of romstage hooks.
Change-Id: I100ebc0e35e1b7091b4f287ca37f539fd7c9fa7a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7876
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Add new functions to:
- Compare two GUIDs
- Find a hob based on its GUID
- Print information about GUID_EXTENSION type HOBs
- Print a GUID's address and value
Change-Id: I89377ec8ab7d98fe7dc129097e643aac061ab3a3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.
Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
These were probably accidentally missed when the move
from southbridge/amd/agesa/hudson to amd/pi/avalon occured.
Change-Id: I4cf6e2f8b25899d6d342452cb1b15e694dae35c8
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add all of the PI source that will remain part of coreboot to
build with a binary AGESA PI BLOB. This includes the gcc makefiles,
some Kconfig, and the AGESA standard library functions.
Change vendorcode Makefile and Kconfig so that they can compile
AMD library files and use headers from outside the coreboot/src
tree.
This fix changes the makefile so that the AGESA dispatcher is
built using its own rules rather than generic library generation
rules in coreboot/Makefile and coreboot/Makefile.inc. The AGESA
source files are initially copied from whereever they live into
coreboot/build/agesa. They are compiled from there. The binary
PI directory now has a mandatory structure that places the AGESA
BLOB into the same directory as the support headers. These will
nominally be placed in the amd directory in SageBIOS or the
3rdparty directory in coreboot.org.
Change-Id: I56788cd197159939b64c7d16c1d32418f8cc2197
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5967
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Fix multiprocessor support not being compiled in when selected
via Kconfig on AMD systems.
Change-Id: I44c22f2e11096247285b0fb469ccf51963eace2b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8268
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
vboot2 abtracts tpm storage as some 'secure' space. Thus, it's firmware's
responsibility to handle vboot specific operations with tpm. This CL just copies
related files from vboot_reference so that we can see how code was modified in
the next CL. Note rollback_index.c/h were renamed to antirollback.c/h.
TEST=none
BUG=none
Branch=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I1792a622058f70a8fcd3c4037547539ad2870420
Original-Reviewed-on: https://chromium-review.googlesource.com/206462
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 2ae188b29242bf09c5e79e31f98b330a30bf7b93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5fa5a636003e8472127194e961fea4309489b1d9
Reviewed-on: http://review.coreboot.org/8164
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Doing reset while VBERROR_TPM_REBOOT_REQUIRED occured.
BUG=chromium:389568
TEST=Manual force VBERROR_TPM_REBOOT_REQUIRED returned from VbInit()
and system will reboot.
Original-Change-Id: I9d7c4b3a380a931a728f792b4013b3b9bf65dfae
Original-Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206337
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 32728dd9fc43a95d6f763a85f9cc7a660a66b175)
Original-Reviewed-on: https://chromium-review.googlesource.com/206948
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1ea5e233386d236ce20f3d1695fac3a1bc49d4bd)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib93fdf7b22918f563d3e29207a75fc831bee186a
Reviewed-on: http://review.coreboot.org/8163
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch has a basic structure of vboot2 integration. It supports only Nyans,
which have bootblock architecture and romstage architecture are
compatible from linker's perspective.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I4bbd4d0452604943b376bef20ea8a258820810aa
Original-Reviewed-on: https://chromium-review.googlesource.com/204522
Original-Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit a6bce0cbed34def60386f3d9aece59e739740c58)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I63ddfbf463c8a83120828ec8ab994f8146f90001
Reviewed-on: http://review.coreboot.org/8160
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This reverts the revert commit 5780d6f387
and fixes the build issue that cuased it to be reverted.
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains,
compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the
boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with
verstage_.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a83b87c29d98d97ae316091cf3ed7b024e21daf
Reviewed-on: http://review.coreboot.org/8224
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Control bits located by changing tristate power
restoration value in proprietary BIOS, booting into
Linux, dumping the entire CK804 configuration space,
then comparing values against those dumped earlier.
"Last state" control bit(s) are unknown at this time.
TEST: Boot ASUS KFSN4-DRE with both coreboot power on
and power off after power failure settings, then
pull power plug / reinsert power plug and verify
mainboard behaviour matches setting.
Change-Id: I737bdd35632fe786968a1cb8458e56c785363cfa
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: http://review.coreboot.org/8258
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
There were a number of issues with the ARM64 build files. This
patch ports the following changes from ARMV4/V7 to ARMV8:
- make armv8 Kconfig options consistent with armv4/v7
- fix build include issues in boot.c, tables.c,
and early_variables.h by matching armv4/v7.
Change-Id: I57359a96821d88c50f48dc0bb6ad226cacb0c2ec
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iacd95d336559c45458784d1da67bde62a0956620
Reviewed-on: http://review.coreboot.org/8236
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The length of the memcpy is incorrect and this will cause the
destination buffer to corrupt the following 2 bytes of data.
BUG=none
BRANCH=All
TEST=build and boot on rambi, system boot up without error
Change-Id: I96adf2555b01aa35bb38a2e0f221fc2b2e87a41b
Signed-off-by: Zhuo-Hao Lee <zhuo-hao.lee@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/237510
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
[Remove usage of macro `FIELD_SIZEOF(t, f)`.]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8227
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This must be committed at the same time as the corresponding
depthcharge change which updates the fmap.
BUG=chrome-os-partner:30079
BRANCH=none
TEST=Build samus firmware.
dump_fmap -h /build/samus/firmware/image.bin shows PD_MAIN_A and
PD_MAIN_B sections.
Boot samus. 'crossystem mainfw_act' -> A
As root, 'crossystem fwb_tries=1'
Reboot samus. 'crossystem mainfw_act' -> B
CQ-DEPEND=CL:208984,CL:*169850,CL:208989
Original-Change-Id: Ibccec8b82ba22c61248a79023f42b92e4763403e
Original-Signed-off-by: Randall Spangler <rspangler@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208899
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit d241e1dddaf8a435e49e08e60e4ad998735d2137)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida8f7bd68d71e2a4a47e304b8f8283b566c52837
Reviewed-on: http://review.coreboot.org/8219
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
In order to ensure that we meet timing requirements for the SSD
power sequencing delay bringing the SSD out of reset until after
memory training.
BUG=chrome-os-partner:29914
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: I807e3d3698255287c3fe7219f44e8ec9a0985df1
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208155
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 1cf557049c49e1ba11ade1eee7a45fc2b075ff3d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib39a14a03e04a167fab45b58b3bc840eb4bcf317
Reviewed-on: http://review.coreboot.org/8215
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
- Turn on keyboard backlight early in boot (not resume) path
as a sign of life for the system
- Add ACPI device for keyboard backlight so the kernel can find
and make use of it
BUG=chrome-os-partner:30586
BRANCH=None
TEST=build and boot on samus
Original-Change-Id: Iecaef0ec5c814774e19d7c4a14cb92dc236cfee3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/208152
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e166f76f9bd167468c7637dcce2b9eabf7dce8f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I47927d97c1586ec09310d014d8fba7d7a3d773c4
Reviewed-on: http://review.coreboot.org/8213
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Configuration for GNB GPP was incorrect, only PCIe x1 cards worked.
Change-Id: I369bf6382080e6034ff138ac664c76b03280ca69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8229
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Due to some projects don't have the correct settings in devicetree.cb
so put this change in case those projects without are setting in devicetree.cb
BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
checked the USBPHY_COMPBG is configured properly
even there is no setting in devicetree
Original-Change-Id: Iaf8155497c41f10c81d1faa7bb0e3452a7cedcc6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/209051
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 713f809952a2d8da434d619d48cb7ddce1991925)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I86f9b77e703d2b844fa636678499c47ffaffeede
Reviewed-on: http://review.coreboot.org/8218
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
USBPHY_COMPBG needs to be configured by project
BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
checked the USBPHY_COMPBG is configured properly
CQ-DEPEND=CL:208557
Original-Change-Id: I8f2714644e1ef5d790d7ef1f574ebb998abbdac6
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208731
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 1e9aeebb769e30940175cf3c38afe7ecfa69b5b4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I28aa445ccb4506db65784e30253dd16161b2bc75
Reviewed-on: http://review.coreboot.org/8217
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
USBPHY_COMPBG needs to be configured by project
BUG=chrome-os-partner:30690
BRANCH=none
TEST=emerge-rambi coreboot without problem
checked the USBPHY_COMPBG is configured properly
Original-Change-Id: I05eee384d94cf5deeec14418bd78816df0b26a92
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/208557
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 20a9c0ab7ab180596821751110f0c0a35d3ff3a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8bed3fa4e74e4bb4c93fa522d9df631bac2d9795
Reviewed-on: http://review.coreboot.org/8216
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The correct type-signature of 'do_smbus_write_byte' is:
int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
and so storing the return type in a 'u32' is inappropriate, leading
to a tautological compare of 'ret < 0' and 'err < 0'.
Change-Id: I65486df7156c70af84fa00c336142d9a45998620
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8209
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
It's not a SPI related macro, hence move it to stddef.h where
other similar macros live.
Change-Id: I1008894af7a272f1bc36d3ae6cee3881132b6ba9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8109
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
No reason to carry timestamps on CAR stack, as implementation
of timestamps internally stashes on CAR_GLOBAL table and migrates
those to CBMEM.
Change-Id: I5b3307df728b18cd7ebf3352f7f7e270ed1e9002
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8022
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This reverts commit 320647abda, because it
introduced the following regression.
$ LANG=C make V=1
Warning: no suitable GCC for arm.
Warning: no suitable GCC for aarch64.
Warning: no suitable GCC for riscv.
/bin/sh: --: invalid option
Usage: /bin/sh [GNU long option] [option] ...
/bin/sh [GNU long option] [option] script-file ...
GNU long options:
--debug
--debugger
--dump-po-strings
--dump-strings
--help
--init-file
--login
--noediting
--noprofile
--norc
--posix
--rcfile
--restricted
--verbose
--version
Shell options:
-ilrsD or -c command or -O shopt_option (invocation only)
-abefhkmnptuvxBCHP or -o option
make: -print-libgcc-file-name: Command not found
It also introduced trailing whitespace.
Change-Id: I50ec00a38e24c854fa926357cd24f9286bf4f66f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/8223
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Verstage will host vboot2 for firmware verification.
It's a stage in the sense that it has its own set of toolchains, compiler flags,
and includes. This allows us to easily add object files as needed. But
it's directly linked to bootblock. This allows us to avoid code
duplication for stage loading and jumping (e.g. cbfs driver) for the boards
where bootblock has to run in a different architecture (e.g. Tegra124).
To avoid name space conflict, verstage symbols are prefixed with verstage_.
TEST=Built with VBOOT2_VERIFY_FIRMWARE on/off. Booted Nyan Blaze.
BUG=None
BRANCH=none
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: Iad57741157ec70426c676e46c5855e6797ac1dac
Original-Reviewed-on: https://chromium-review.googlesource.com/204376
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit 27940f891678dae975b68f2fc729ad7348192af3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I42b2b3854a24ef6cda2316eb741ca379f41516e0
Reviewed-on: http://review.coreboot.org/8159
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Allow for reading from cbfs media without having a handle
to a non-CBFS_DEFAULT_MEDIA cbfs_media. In conjunction with
cbfs_locate_file() one can locate and cbfs_read() a file
without bringing the entire file through a potentially
temporary buffer (non-memory-mappable cbfs media platforms).
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built.
Original-Change-Id: Ib5d965334bce1267650fc23c9e9f496675cf8450
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205991
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 85200f28863e5ea8888322f5787dc6de9a2999f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I25e3221beefd0155305ad63da6be9f47e756f7d0
Reviewed-on: http://review.coreboot.org/8181
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
cbfs_locate_file() can be used to locate the data within the
cbfs file. Based on the offset and length of the file it can
then be read into any address without bringing the contents
into another buffer (platforms without memory-mapped access
to entire contents of cbfs at once).
BUG=chrome-os-partner:29922
BRANCH=None
TEST=Built and booted rush into romstage (stage load still works).
Original-Change-Id: I2932f66478c74511ec1c876b09794d9a22a526b3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/206000
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
(cherry picked from commit 56c958facd379ca0eeebe1b689e3b80d5e692699)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c4964132af615a069258c0eb37153bd84fbbfae
Reviewed-on: http://review.coreboot.org/8180
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When included for the CAR transition, this was causing the error:
error: invalid storage class for function 'DebugDeadLoop'
Change-Id: Idf37a8104b4468b40c29c8cbe9a40f7a357a4f17
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8193
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Put functions in appropriate pre-processor sections to avoid
false-positive 'unused function' compiler warnings.
Change-Id: Ie4955ee9df6904c38848f46226b53be37d9fa239
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8157
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Put function under same guard as its call site so that the
compiler does not emit a warn about unused functions upon
a false branch of the guard.
Change-Id: I899d539ec5fbb87e7469415cc8d15837ba8e63f3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8156
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
I would appear from commit a6354a1 that this is now dead code.
Change-Id: I0f74183c9a5d8cc6ff5a11409d487cc45d9ed2df
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8168
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
These boards don't have Super I/O's, rather they use Embedded
Controllers instead. No need to confuse with Super I/O related
stuff showing up in menuconfig.
Change-Id: I4922319daf7920bf5331b5bce05ded0d9a31a69b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7986
Tested-by: build bot (Jenkins)
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Function was orginally used for reverse engineering.
Change-Id: I646dddd39e61b59358b29a49239c0a1de77c7e55
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8158
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
This just fixes name members of mainboard_ops for daisy and
peach_pit, which were never officially supported but used for
development and proof-of-concept.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Change-Id: Ia1f9b62bc9d91ed634ec1eaa7f907e8aed977f96
Reviewed-on: http://review.coreboot.org/8184
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Place the mrc.cache file at top of CBFS. There is no real requirement
for it to have a fixed location though.
Change-Id: Ibebe848a573b41788c9d84388be8ced68957f367
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7962
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Due to the CST entries the machine uses less power running
GNU/Linux-libre. This can be seen by monitoring CPU temperature
and time left the machine can run on battery. CPU temperature
measurements have been done with lm_sensors, battery querying
with acpi. Tests have been done before applying this patch and
after. In both cases the battery was fully loaded and the machine
powered up on battery, without AC. In both tests the machine was
idleing for more than 1 hour.
Without this patch battery was predicted to last 01:52:30 hours,
CPU temperature first measurement showed 38 degrees. After 15 min
idle, temperature has reached its maximum value in this test of
61 and 62 degrees (Core 0 and 1). Fan speed begins to increase
shortly after 15 min. From its minimal value 1800 rpm it reaches
3100 rpm after 40 min. CPU temperature did not increase any further.
After 60 min idle, the battery was predicted to still last 57 min.
With this patch battery was predicted to last 02:22:40 hours. That
is plus 30 min. CPU temperature begins at 35 degrees. After 15 min
temperature has reached 45 degrees; after 30 min it has reached
the maximal temperature during this test of about 50 degrees.
That is 10 degrees improvement. The fan stayed at minimal speed.
After 60 min idle, the battery was predicted to still last 01:22:48
hours; a 25 minute improvement.
Change-Id: I6b2173df1dc09300329b61b51b79f4b9f4a8fb13
Signed-off-by: Axel Holewa <mono@posteo.de>
Reviewed-on: http://review.coreboot.org/7923
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This adds a generic primitive memory test. We should look into
using tests in src/lib/ramtest.c, but they seem to rely too heavily
on x86 asm and this test has been useful on multiple ARM platforms.
BUG=none
BRANCH=none
TEST=builds and runs on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ia0fb4e12bc59bf708be13faf63c346b531eb3aed
Original-Reviewed-on: https://chromium-review.googlesource.com/186309
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e7625c15415eaf6053ce32b67d9d6ab18d776f5f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Conflicts:
src/lib/Makefile.inc
Change-Id: I34e7aedfd167199fd5db4cd4a766b2b80ddda79b
Reviewed-on: http://review.coreboot.org/8150
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
In the original fix for the 'Lost arb' we were seeing on
Nyan* during reboot stress testing, I had the name of
BC_TERMINATE's bit setting wrong. Fix this to use the
IMMEDIATE (1) setting. The setting didn't change, just
the name. According to Julius this is the optimal
setting for bus clear in this instance. Also widened
the SCLK_THRESHOLD mask to 8 bits as per spec.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I19588690924b83431d9f4d3d2eb64f4947849a33
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/206409
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 76e08d0cb0fb87e2c75d3086930f272b645ecf4e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If187ddf53660feaceab96efe44a3aadad60c43ff
Reviewed-on: http://review.coreboot.org/8152
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
We assume that the clock rate of SCLK/HCLK/PCLK was 408MHz which was same
as PLLP. But that is incorrect, BootROM had switched it to pllp_out2
with the rate 204MHz. So actually the warm boot procedure was running at
the condition of SCLK=HCLK=PCLK=pllp_out2 with the rate 204MHz.
And the CPU complex power on sequences were different with what we used
in kernel and Coreboot. Fix up the sequence as below.
* enable CPU clk
* power on CPU complex
* remove I/O clamps
* remove CPU reset
Update the time of the CPU complex power on function for record.
* power_on_partition(PARTID_CRAIL): 528 uSec
* power_on_partition(PARTID_CONC): 0 uSec
* power_on_partition(PARTID_CE0): 4 uSec
Finally, removing the redundant routine of a flow controller event with
(20 | MSEC_EVENT | MODE_STOP).
BUG=chrome-os-partner:29394
BRANCH=none
TEST=manually test LP0 with lid switch quickly and make sure the last
write to restore register successfully
Original-Change-Id: Ifb99ed239eb5572351b8d896535a7c451c17b8f8
Original-Signed-off-by: Joseph Lo <josephl@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/205901
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit 4194a9af3999da4b061584cda9649944ec0fdfb1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If21d17dc888b2c289970163e4f695423173ca03d
Reviewed-on: http://review.coreboot.org/8151
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Propagate commit 9107e53 from amd/agesa and fix some
related #includes under cpu/amd/pi.
Change test to return true on S2 wakeup too. In S2 CPU would
have been powered down so MTRR recovery is required.
Change-Id: I18cb31c1124da53e5fcba2610f6b02d755feb092
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8171
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial; Use tab over space for indent.
Change-Id: Iba0e006197a020157b11746dd4999d87a8ca8d97
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8015
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This serves as supplemental patch to CL:197732. After clearing bus, we
should also redo controller init (because controller has been reset
before bus clear). On the upper layer, upon receiving error return status,
it should just retry instead of simply call cpu_reset().
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Built and tested on nyan and nyan_big.
Original-Change-Id: Ib526bc730cb73ffef8696fc2a6a2769d6e71eb9e
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202784
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 06f8917c70ddca88c847d0f15ebe7f286a3f6338)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1d8bc43d730b53fe7f2dad8713831311e96e3984
Reviewed-on: http://review.coreboot.org/8145
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This makes it so that we always log the generic "system boot" event.
If boot count support has not been implemented, fake it.
BUG=chrome-os-partner:28772
BRANCH=nyan
TEST=booted on Big, ran "mosys eventlog list" and saw
"System boot" event logged with boot count == 0
Original-Change-Id: I729e28feb94546acf6173e7b67990f5b29d02fc7
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204525
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2598dc63ddc0d76bcdf9814cadd4c75653fd9832)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieb4e2e36870e97d9c5f88f0190291863a65a6351
Reviewed-on: http://review.coreboot.org/8142
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- SPD GPIO table was changed from earlier builds and GPIO67 needs to be
swapped with GPIO69
- Hynix 8GB DRAM is actually x16 and needs updated geometry in the SPD
- Broadwell LPDDR3 at 1333 is not working in P2, remove the workaround
- In order to support both P2A and P2B with one firmware image we need
to read the EC board version and use the right SPD GPIO for bit3
- Touchpad I2C address changed to 0x4a/0x26
BUG=chrome-os-partner:29502
BRANCH=None
TEST=boot on P2A and P2B boards
Original-Change-Id: I4af4161449d904b8dd69c1c4f984b2f41f0dbbbc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/204818
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9cc71b68be556dab154fdf3f86914129e5f7a6dc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic5ca71dbfd9b9d413b86b2ae2786f39fd78ace1d
Reviewed-on: http://review.coreboot.org/8135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a block in the SMI handler to call init functions for
drivers which may be used in SMM. A static variable is used to
ensure the init functions are only called once.
BUG=chrome-os-partner:29580
BRANCH=mccloud
TEST=Built and booted on mccloud, system no longer hangs when
pressing power button at the dev mode screen. Also tested on parrot.
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I225f572f7b3072bec2bc06aac3fb50d90a2e30ee
Original-Reviewed-on: https://chromium-review.googlesource.com/204764
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 9315c485deb5f24df753e2d69f4819b2cb6accc2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8d2b21765c35c7ac7746986d5334dca17dcd6861
Reviewed-on: http://review.coreboot.org/8134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Enable the ACPI Device for the EC ALS.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Original-Change-Id: I9e957464f835d5bd96d4806f896ac60db9dea5dc
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a4f78b0b78c53bc0397d9a21dd8f3fa040f41616)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib83d6211d323770c9498180a7721d45e4aefca9d
Reviewed-on: http://review.coreboot.org/8133
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC can export ALS information if the sensor is attached
to it directly rather than to the host. This adds a basic
ACPI ALS device and implements the required information.
The kernel does not use the _ALR tuple set but it is required
by the ACPI spec so this just adds the sample two point
response curve defined in ACPI 5.0 section 9.2.5.
The EC does not currently send events for lux value changes so
a polling interval of 1 second is defined.
BUG=chrome-os-partner:24208
BRANCH=None
TEST=build and boot on samus, add acpi-als driver to the kernel
and read /sys/bus/iio/devices/iio:device0/in_illuminance_raw
Original-Change-Id: Id29b72a68aa21c1a7c71d5f87223ac010cef0377
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 81f44b33b87a6ee3079b8ef6efffacd0eeb0283f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5a0ccd30e8b453675beaf7d0363dbfa162bd5b3f
Reviewed-on: http://review.coreboot.org/8132
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This marks the bottom chunk of memory, which is used by various IP
blocks, as reserved so that Depthcharge does not attempt to wipe it.
BUG=chrome-os-partner:30067
BRANCH=storm
TEST=Built and booted for storm, depthcharge shows:
Wipe memory regions:
[0x00000041500000, 0x00000051000000)
[0x000000510006a0, 0x00000053000000)
[0x00000054141260, 0x0000007fffd000)
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8f782f16d13620b705e1b3fbeca21dc8705b7e77
Original-Reviewed-on: https://chromium-review.googlesource.com/206516
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit f66f553f1594c481a74b7f40b4b1088600b1a70a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I82d118abc86052f5e32f6195a4efd04fe315be5a
Reviewed-on: http://review.coreboot.org/8149
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The actual storm device has a single USB interface, which needs to be
explicitly turned on using GPIO51.
BUG=chrome-os-partner:29871
TEST=verified that depthcharge finds and boots a kernel from USB stick
Original-Change-Id: Iaf868812c96e1e3289b9403855c4cc8f87c1e368
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205329
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit aa22376ffac22309a298dfa844e7f61c97d57d3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic0f34622e61a65a0540c0f3fca26fb057fa85fb7
Reviewed-on: http://review.coreboot.org/8147
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Storm devices use more recent Spansion flash, add its description to
the table of supported devices.
BUG=chrome-os-partner:29871
TEST=the updated firmware boots all the way to depthcharge
Original-Change-Id: I81661c01ae679d49918e40d940b8d348f3081f9a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205182
Original-Reviewed-by: Stefan Reinauer <reinauer@google.com>
(cherry picked from commit ea7bb1cf65b7130164b869fef09c55138100206b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1e0136a5c575951b4e464aab0f380f19e886a84f
Reviewed-on: http://review.coreboot.org/8146
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*.
Back in the day, like more than half a decade ago, we migrated a lot
of boards to printk, but we never cleaned up the existing code to be
consistent. Instead, we worked around the problem with a very messy
console.h (nowadays the mess is hidden in romstage_console.c and
early_print.h)
This patch cleans up the generic code pieces to use printk() on all
non-ROMCC boards.
Our two remaining ROMCC boards are fixed up in this commit:
bifferos/bifferboard and dmp/vortex86ex.
Change-Id: I16676eeabe5c892c8e3c9f3c0cd3bae2e8fd74b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8115
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Remove @param command for #define - this isn't valid.
- Rename duplicate @section names - All of the renamed @sections
have other @section names in the same file.
- Remove blank @brief and @param commands - Doxygen seems to REALLY
dislike this...
- Add a missing @param name.
Change-Id: Iba99ec68b37bbb5c375b7256363d16228031d771
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8175
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Join doxygen file command with the file description
- Give extended file location so doxygen knows which early_sbmus.h
the file is. (I don't get this either, but it fixes the warning)
Change-Id: Ia91fb1ac1e9687e1a5a5cb5234696b3c24d4cd24
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8174
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Take unused reverse eng function out of build by wrapping in #if 0.
Change-Id: I816b3ea08a8858fc03e4455c1d7711265e63cba4
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8167
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove 'read_mchbar8_bypass()' as 'read_mchbar8()' does the same
thing and 'read_mchbar8_bypass()' is unused.
Change-Id: I0dc2325e6205c38b63e5200c408ece65e4f938dc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8166
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This convenience API was never used.
Change-Id: If2a99967e7f8c02e9029f7766aeef1e1a1f3dd16
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8108
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Missing base may have enabled SMI for all GPI inputs.
Change-Id: I1157afaccccb17d325a4efdb1f270a27f9a299ab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8169
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- @todo has to be lowercase for doxygen
- Fix some parameters that had changed in the code.
- The @file entries needed to be more specific.
Change-Id: Icdce08735f581609cd25cce41e986c71435368a4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8154
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
- Add missing parameter names in several files
- remove parameter types in several files
- remove lines from doxygen documentation. These should be outside the
doxygen comments.
- Some of the comments shouldn't have been doxygen style. Turn these
into regular non-doxygen comments.
Change-Id: Ieccfe237385efee007b48308d58eb0a6a12f5bfa
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: http://review.coreboot.org/8153
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Remove useless comment pretaining to abusing pragma's for old
GCC/GDB interaction issues.
Change-Id: Ic83a0285ac947a23699a81a82b89de08a47ab052
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8017
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This file will have CBMEM init hooks API one day.
Change-Id: I0c31495d4217a5eb235b13e6d8e8c99a87a3b840
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8031
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the mainboard code to use printk() on all non-ROMCC
boards.
Change-Id: I2383f24343fc2041fef4af65d717d754ad58425e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8111
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the cpu code to use printk() on all non-ROMCC
boards.
Change-Id: I233c53300f9a74bce4b828fc4074501a77f7b593
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8114
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the southbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I312406257e66bbdc3940e206b5256460559a2c98
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8110
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the northbridge code to use printk() on all non-ROMCC
boards.
Change-Id: I4a36cd965c58aae65d74ce1e697dc0d0f58f47a1
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7856
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Because we had no stack on romcc boards, we had a separate, not as
powerful clone of printk: print_*. Back in the day, like more than
half a decade ago, we migrated a lot of boards to printk, but we never
cleaned up the existing code to be consistent. instead, we worked around
the problem with a very messy console.h (nowadays the mess is hidden in
romstage_console.c and early_print.h)
This patch cleans up the superio code to use printk() on all non-ROMCC
boards.
Change-Id: I23fc307f1346cdb7adaaeccfafe17d9205e909ac
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8113
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This code is unused, and the same functionality is in superiotool
already.
Change-Id: I7bf667e2e2bfc8fdedcdbe09bf420abf47b1ee97
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8112
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
console_tx_byte() is defined in stream.h, not console.h. This will cause
problems later, when untangling more ROMCC and console code. Hence, fix
the issue beforehand.
Change-Id: If4e04bd6c69b630912414676950157d06c364d74
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/8121
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Somewhere along the line, the sb_cfg parameter name was changed to
config, but this wasn't carried into the documentation or the function
prototypes everywhere.
Change-Id: Iccb0829c2f50370dddb70af915a6759316c4727a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8098
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Doxygen gives an error when processing #defines inside doxygen comments.
Normal comments are ignored. The choice for this fix was to make this
a standard comment starting with '/*' instead of '/**', or to make the
comment not a #define.
Change-Id: I97fbbcea6f045d80ec7c0ab5e196d57e5da16d86
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8099
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
These files were trying to document the parameters, but didn't have
the syntax quite right. Change the comments from @varname to
@param varname as required by doxygen.
Change-Id: I63662094d3f1686e3e35b61925b580eb06e72e28
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8100
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The doxygen parameter names in the comments no longer matched the
functions they were attached to. Doxygen complains about extra
parameter comments and uncommented parameters in the functions.
Change-Id: I21b8a951f8d8d04b07c3779000eeaf1e69fed463
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8101
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
These comments are left over and are not relevent in the coreboot
code, but created a new section titled "Release Content" in the
doxygen documentation produced by the coreboot code. In an effort
to clean up the output, I'm removing these doxygen comments.
Change-Id: I4d7be3313a2ab6c140b4f3afe70dffc4abba7bca
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8069
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The FSP uses a lot of UEFI HOB (Hand Off Block) functions for reporting
and passing information to coreboot. These seem to me like they should
be in their own file, so I'm splitting them out of fsp_util.c. I'll
be adding a couple more functions in the next patch.
These functions should all be compliant to the Hand Off Block spec.
Change-Id: Ie8bbc0a9277b9484f13dd077b3a52e424a8600fe
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8065
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Re-factor to_flash_offset() into 'spi_flash.h' header. Motivated by
Clang complaining that the function 'to_flash_offset' is unused.
Change-Id: Ic75fd2fb4edc5e434c199ebd10c7384d197e0c63
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7519
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
As `#ifndef` and not `#if` is used in the check for
include guards, setting it to 1 is not needed.
Change-Id: Iaa6c0f807b9e99ad3c9551abe4ab1627e5505d67
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8103
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
Use 'delay.h' header rather than directly including 'delay.c'
source. N.B. Some amdfam10 and K8 boards are not included in
this changeset since unrelated issues are woven in there.
Change-Id: Ibc0c0e560d8eedaf5c3150f95ba72fe5dd8d6f3a
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8086
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Fix system include paths to be consistent. Chipset support is
part of the Coreboot 'system' and hence 'non-local' (i.e., in
the same directory or context). One possible product of this, is
to perhaps allow future work to do pre-compiled headers (PCH) on
the buildbot for faster build times. However, this currently just
makes mainboard's consistent.
Change-Id: I2f3fd8a3d7864926461c960ca619bff635d7dea5
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8085
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Provide proper Makefile and Kconfig components so
that this superio is built as object code. Select
superio component in mainboard Kconfig's to bring
in the link-time symbols and thereby removing the
need for .c inclusion.
N.B. The LPC47N207 Super I/O does not physically exist
on these boards. The Super I/O is found on external LPC
debug card hardware and so should really be made selectable.
However, this is beyond the scope of this specific fix, that
rids us of .c inclusions in romstage.c
Change-Id: I451c3a81c4b5beca1ed65e27467a7393d2521dae
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8084
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Cherry-pick from chromium and adjusted for added boards
and changed directory layout for arch/arm.
Timestamp implementation for ARMv7
Abstract the use of rdtsc() and make the timestamps
uint64_t in the generic code.
The ARM implementation uses the monotonic timer.
Original-Signed-off-by: Stefan Reinauer <reinauer@google.com>
BRANCH=none
BUG=chrome-os-partner:18637
TEST=See cbmem print timestamps
Original-Change-Id: Id377ba570094c44e6895ae75f8d6578c8865ea62
Original-Reviewed-on: https://gerrit.chromium.org/gerrit/63793
(cherry-picked from commit cc1a75e059020a39146e25b9198b0d58aa03924c)
Change-Id: Ic51fb78ddd05ba81906d9c3b35043fa14fbbed75
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8020
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The hp/abm board is used in network/server applications.
Notes:
- The hp/abm board is headless and therefore does not define
CONFIG_GFXUMA, and does not require a video bios.
- The micro USB connector on the board edge is connected to COM4
(i.e. I/O=2E8h). Coreboot needs to be configured to use Index=3.
- If you are using SeaBIOS it would also need to be configured to
use the UART at I/O=2E8h.
- This board has been tested with headless installed versions of
Ubuntu 12.10 and Fedora 19.
Change-Id: I60bde98411c40a184c8d053199bac8d04df8ab07
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6116
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This is just bit-rotting and its likely this will continue to rot
by the time someone notices it exits it will be too late (i.e., today).
Change-Id: I40ef2cd8e3d563079b086f51dabab0960a0a13b3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8087
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
- Remove types from the param declarations.
- list needed to be uppercase.
Change-Id: I8b9ed78908e5d3e1d99e7ba2ea9013be109b8e27
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8072
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Remove PeiServices param for OemInitEarly - it doesn't exist in the
function.
Change-Id: I338aeb4128126f6e541815dc09bf8d23678081c8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8073
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
- Move @def BIOS_SIZE description to the next line
- SB_GEN2 changed to SB_GPP_GEN2
- Move the SIO_HWM_BASE_ADDRESS description to the next line
Change-Id: Ia3496b0108484f557627304553461932a100dfa5
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8071
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Correct the param to match the functions.
Change-Id: Id002c549a6ba6a7be4fa5eee396769eaa2510698
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8074
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
- @v & @i need to be @param v & @param i
- add the @file command
Change-Id: Ib4fb609629bc2dfcf1869bdf7a4d4cd9fea283cc
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8075
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
This doxygen directive was creating a top level modules section, which
had the vx900_int15 code as its only member. I do think that breaking
the code into documented sections is a good plan, but in an effort to
clean up the output, I'm removing this for now.
Change-Id: I3f7e2f704136ebbd1961c5946bac4c2edbd6a371
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/8070
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: I44272b4e30a2bc8c3a719df17b837432cd38429c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8083
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Remove dead debug code, we have superiotool for this reason.
Restructure file to be consistent with other superio's thereby
avoiding forward declarations of functions.
Change-Id: Ief60d3f54c508cbb7795b284b59710d2c0e3018b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8082
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This brings mainboard up to being consistent tree-wide now for
all superio header path inclusions.
Change-Id: I00a806ce209ba363c62e3ddd49db9bf599f32149
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/8052
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This explicitly casts CONFIG_SYS_SDRAM_BASE to an unsigned type so
we don't get compilation errors when increasing CONFIG_DRAM_SIZE_MB.
BUG=chrome-os-partner:29871
BRANCH=storm
TEST=compilation no longer fails with DRAM_SIZE set to 1024
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9717c39d87682d43ec4e7a4042d9b559a1d7eedb
Original-Reviewed-on: https://chromium-review.googlesource.com/206010
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 178db896346ae8cbc5ddec5373a83688f32c62ba)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I68c11d398820684ad928bdfdd74f7a6885247333
Reviewed-on: http://review.coreboot.org/8059
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
When the IPQ SPI driver was ported to coreboot, a few GPIO related
definitions ended up in a wrong include file. Move them to the proper
place and get rid of duplicated definition of GPIO_OUT.
BUG=chrome-os-partner:27784, chrome-os-partner:29871
TEST=proto0 still boots with the new firmware
Original-Change-Id: I4b06067a71c85efaf0e48f29e232f83fd1f725a8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/205328
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit df73bb0023f5eaf5594ef41b3632c4402ebf126c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I109e62e3bfc9bd15640ff697be7634f42435a3e4
Reviewed-on: http://review.coreboot.org/8058
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Depthcharge clears up all unused DRAM before starting Linux, and does
not know the translation table location. Instead of adding an
exclusion term to the memory wipe descriptor let's move the table to
the top of IMEM, it is also likely to be a good location in the
future, when EFS is introduced.
BUG=chrome-os-partner:27782
TEST=manual
. built and ran firmware on ap148
Original-Change-Id: I76546438d243076dda4d0eb3f784e0b5a8a1fa22
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203624
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 4250f8574d6cc0bbec5ba0411f22d801f034afb8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I12cd74e3d318b878e7703414a7ddaaed0812cb7a
Reviewed-on: http://review.coreboot.org/8057
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This patch adds code to initialize the two DWC3 USB host controllers and
their associated PHYs to the IPQ806x SoC (closely imitating the existing
DWC3 implementation for Exynos5), and uses them to initialize USB on the
Storm mainboard.
BUG=chrome-os-partner:29375
TEST=Hack up netboot to get around missing SPI flash, load a file over
TFTP. Hack a storage read into the storage attach function, dump the
data and confirm that it looks right. Enable USB debugging and confirm
3.0 devices get enumerated at SuperSpeed (mostly).
Original-Change-Id: Iaf7b96bef994081ca222b7de9d8e8c49751d3f1d
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202157
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
(cherry picked from commit 6349e7281d5accb1247acb0537a48fa3a5e1bf97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I749d265d45c6a807a7559bd4df2490a6eb8067af
Reviewed-on: http://review.coreboot.org/8056
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Hynix 2GB/4GB configs have been fine-tuned.
Kingston 2GB config is new, uses RAMCODE 0x6.
BUG=none
TEST=emerge-nyan_big coreboot-nyan_big OK. Flashed to my
Big 2GB system (PVT1/SKU1) and it booted OK.
BRANCH=nyan_big
Original-Change-Id: I8a23a5568ef84d5befc13623f78bce664130f314
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203305
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit e47d18d8cff50f46d0a14715b6750f7aa6d0da82)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I363db37d6a63d9f5c578e68a0149259657e1ebfd
Reviewed-on: http://review.coreboot.org/8045
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For some panels, the plld can't provide the pixel clock that
the panels wants, so we give it a good enough one. And we
should calculate the dp/dc settings by the real pixel clock.
BRANCH=nyan
BUG=chrome-os-partner:29489
TEST=Verified the panels N116BGE-EA2(Nyan) and N133BGE-EAB(Big).
No screen flicker is observed. No sor dp fifo underflow found.
Original-Change-Id: I037b2bd5f5e9bb8b15ab6f47a84ac7ef2e207779
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/203358
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d320f0c6b54ea8ca84206447b223da76ac5f771b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I772bb8e7a40cc462c72ba0fb9657c63ed2e0d0ac
Reviewed-on: http://review.coreboot.org/8044
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add XN/PXN bits to prevent cpu from fetching speculative instructions
on noncacheable region.
BUG=chrome-os-partner:28568
BRANCH=nyan
TEST=Build and run reboot tests on nyan_big
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I0cd2ad5a47a467ef609d30d42cd300b5ca45b77b
Original-Reviewed-on: https://chromium-review.googlesource.com/203447
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Commit-Queue: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c3d585bdfcbe9330e5c6f51d1fcf45aec9f26755)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf552e2f1ba20255915b24b4f96a179a2e7d08fe
Reviewed-on: http://review.coreboot.org/8043
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
CrOS devices with Chromeos EC need only use hostevent to communicate
recovery assertion to the BIOS. This CL removes wired GPIO from
determining recovery as it appears under certain conditions (cold
reset) the internal PU on the AP isn't strong enough and therefore the
value is sometimes seen as asserted.
BRANCH=none
BUG=chrome-os-partner:29333
TEST=compiles & BIOS no longer responds to rec_mode GPIO during boot.
Original-Change-Id: Ib220cfa5f5bfe7193d555bfd32c0444b063d00f2
Original-Signed-off-by: Todd Broch <tbroch@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202996
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit d9927bcd67b0fb069fde231314e654d727092282)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6e086cbabc884f18deb2791a0f897e332b31032f
Reviewed-on: http://review.coreboot.org/8042
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Put SSD into reset on transition to S3/S5 to prevent leakage
- Fix GPIO number for wlan disable used in smihandler
- Enable generic hub driver in libpayload
- Fix comment in devicetree about S0ix
BUG=chrome-os-partner:28502
BRANCH=None
TEST=Build and boot on samus
Original-Change-Id: Idce566d0f22622d36697be54ab51cacb576c5d6d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/203185
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c0dd822babee3d766eff1735687d14e63380f702)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idc2da99fce817aaf893f031ffbb4ac4a2ade31b0
Reviewed-on: http://review.coreboot.org/8048
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
XHCI driver was not enabled in libpayload and some ports were
disabled that should be enabled.
The Chrome OS GPIOs also need to be reported as 0xFFFFFFFF to
properly indicate unused so crossystem does not attempt to
export GPIO number 255 in the kernel and trigger a warning.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2
Original-Change-Id: Ib5727ef6e618c959640b200757cfa13f95c7cb0f
Original-CSigned-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-CReviewed-on: https://chromium-review.googlesource.com/203184
Original-CReviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 328362469b00c9467908a7d18a031fee73753def)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I91ef865c44d3c73b0d74c9eaf1fbf2fb5e894434
Reviewed-on: http://review.coreboot.org/8047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Both DDI ports may be used on this board so it needs to be
able to detect a device on either port.
BUG=chrome-os-partner:28234
TEST=None (needs hardware)
Original-Change-Id: I5fc5ec3fe887fb51e7bdeae43c8297580e0ba6d6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202358
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 574bb6ac5d33c98f0214d6c738af24172164f4a1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I57613fcea10af0fecaf0f2ad6a83ca011c650099
Reviewed-on: http://review.coreboot.org/8046
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Update GPIO map
- Update SPD for new memory and 4-bit table decode
- Enable USB3 port 3 and 4 (shared with PCIe port 1)
- Enable PCIe port 3 and disable port 1
- Enable SerialIO ACPI mode for devices
- Disable S0ix for now to prevent use of C10
- Special handling for memory with broadwell CPU
BUG=chrome-os-partner:28234
TEST=Boot on P1.9
Original-Change-Id: If6adcc2ea76f1af7613b715133483d7661e94dd8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201083
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 35835eaed3e098597e46f602fbd646cfbb899355)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icb03808da6d92705bbc411d155c25de57c4409c6
Reviewed-on: http://review.coreboot.org/8007
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Put all the SPD related information in one place including
the onboard SPD sources and the board specific parsing.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
Original-Change-Id: If5cd826ecc9cc856008b7c29aa3cfade5ae7f685
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201082
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit f40e447cee84ebd04ab8a57250d0f56f508d52f2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9c10b08c3e640642e3c75696a233051bb34a2123
Reviewed-on: http://review.coreboot.org/8006
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Convert wtm2 board to use the broadwell soc chipset.
BUG=chrome-os-partner:28234
TEST=Build and boot on wtm2 with haswell and broadwell
CQ-DEPEND=CL:201067
CQ-DEPEND=CL:*164226
Original-Change-Id: Ifb0db15cc23a3b66430b32b2ad3f8ab2fb03c4c3
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201070
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e1073c6e34ab2d436faf46dde5f6b3bf99692866)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I925b91a8de980b1768f03eaee915a7fd91fbdbda
Reviewed-on: http://review.coreboot.org/8001
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The driver as it was copied from u-boot provided a function to
transmit multiple characters in one invocation. This feature was not
ported to coreboot, there is no need to maintain the complexity when
only one character at a time is transmitted. It is also very desirable
to get rid of a 1024 byte array allocated on the stack.
The array was necessary to allow to convert multiple newline
characters in the transmit data flow into two character sequences
CRLF. Now just a single word is enough to keep one or two characters
to transmit.
[EDIT km: newline translation is now part of printk]
BUG=chrome-os-partner:27784
TEST=verified that coreboot with the new code prints generates console
output.
Original-Change-Id: I73869c5f4ca87210b34811b583386554bafff1e7
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/201782
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit eab3dc9d30c7e8355a2563e18ada78e4070e6151)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4274b8f7188bf9636906b39bcd9ec7adf0e1222e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8011
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The static allocator only worked for x86 anyway.
Change-Id: Ibe4e172bb654f6414949bd11787c9407d091a858
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8028
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The static allocator only worked for x86 anyway.
Change-Id: I0d2b63465620512e62334d7aa0c885fc5ab3e589
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8030
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The recently introduced page table location value is wrong, it
overlaps with other areas of the code. This patch fixes the location,
a more robust scheme is needed for memory layout management.
BUG=none
TEST=manual
. occasional random failures disappear after this patch is applied
Original-Change-Id: Idc9047d38712736c5e8197e933c373488b333649
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202641
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit d26bb18e506680a1f481c3950007b2ea6a48e54d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7afcab42db259e53541fb991b36d680fc2186304
Reviewed-on: http://review.coreboot.org/8019
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This is an interim change (before EFS is enabled), align ROM and RAM
stages so that they have enough room and do not step over each other.
BUG=chrome-os-partner:27784
TEST=manual
. booted coreboot successfully on ap148
Original-Change-Id: I6e1710ac7ca494a69aea5ba3b117bfd882aded26
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/202046
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Trevor Bourget <tbourget@codeaurora.org>
(cherry picked from commit f1fd4e3f9d699cc694cf7840c169db9bbe9193b6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9861d34a8bdd6963afbeed7fca7fda8a891ec481
Reviewed-on: http://review.coreboot.org/8012
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Define a base address for page table entries. Place it 64KB below the
bootblock loading address.
BUG=chrome-os-partner:28467
TEST=verified that the page tables are being populated at this
address. Also observed that the SPI driver takes 900 ns to
process a byte as opposed to 1.5 us in case caching is not
enabled.
Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7
Original-Signed-off-by: Deepa Dinamani <deepad@codeaurora.org>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200332
(cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068
Reviewed-on: http://review.coreboot.org/8009
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The main benefit of adding this skeleton is the addition of the
correct memory map to CBMEM. Attempts to load depthcharge do not fail
because of unavailability of the bounce buffer.
BUG=chrome-os-partner:27784
TEST=boot updated firmware on AP148, observe
CPU: Qualcomm 8064
in the ramstage console output as well as not failing to load
depthcharge any more.
Original-Change-Id: I56c1fa34ce3967852be6eaa0de6e823e64c3ede8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199675
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit a8fdbdd268a2bba1405d585881eb95510ad17a2a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7b982f222ac3b93371fe77961f18719c5d269013
Reviewed-on: http://review.coreboot.org/8000
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Squashed the correction patch with the original to avoid confusion in
coreboot.org review.
All what's needed apart from configuring the feature is to provide a
function which would report the top of DRAM address.
BUG=chrome-os-partner:27784
TEST=manual
. with all other patches applied, the image proceeds all the way to
trying to download 'fallback/payload'.
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3
Original-Reviewed-on: https://chromium-review.googlesource.com/197897
(cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
storm: initialize dynamic cbmem properly
Dynamic cbmem support has been enabled on storm, but the proper
initialization at romstage is missing.
Proper DRAM base address definition is also necessary so that CBMEM is
placed in the correct address range (presently at the top of DRAM).
BUG=chrome-os-partner:27784
TEST=build boot coreboot on ap148, observe the following in the
console output:
Wrote coreboot table at: 5fffd000, 0xe8 bytes, checksum 44a5
coreboot table: 256 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
Original-Change-Id: I74ccd252ddfdeaa0a5bcc929be72be174f310730
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199674
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit e2aeb2f4e7f3959d5f5336f42a29909134a7ddb7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74
Reviewed-on: http://review.coreboot.org/7996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is based on x220 and t520. Tested on i7 model with usb3.
There is no support for nvidia gpu and optimus.
Change-Id: I6ca9436ccec3024095d02078e5e450147841e463
Signed-off-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-on: http://review.coreboot.org/7974
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
This change updates the cfg file for Hynix/Micron/Samsung 4GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I7621e60d8dcc568e0bb400a6c96b7f8909a15aa6
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/202059
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit 04e74d2fb0fefa6a1786225638380c8831bd9481)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6615e34a17bb372eda9dd0844ecddbcde902ad7c
Reviewed-on: http://review.coreboot.org/8008
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
This change forces storm platform to use the common CBFS SPI wrapper,
which makes the SOC specific CBFS code unnecessary and requires
including SPI controller support in all coreboot stages.
BUG=chrome-os-partner:27784
TEST=manual
. with this change and the rest of the patches coreboot on AP148
comes up all the way to attempting to boot the payload (reading
earlier stages from the SPI flash along the way).
Original-Change-Id: Ib468096f8e844deca11909293d90fc327aa99787
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197932
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 794418a132b5be5a2c049f28202da3cec7ce478d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I751c51c91f29da4f54fcfe05e7b9a2e8f956c4f2
Reviewed-on: http://review.coreboot.org/7994
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This service is required by various coreboot code modules. It looks
like the 8064 SOC does not provide anything better than a 32 KHz free
running counter (it is used in u-boot for us timer as well). Let's use
this for now.
BUG=chrome-os-partner:27784
TEST=manual
. with the rest of the patches applied AP148 boots all the way to
trying to start the payload.
Original-Change-Id: I98b91ce179f7388d59c769a59caf49ca7640e047
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197896
(cherry picked from commit d526830f9d9618e4ca3460165d7b9ecc8ab268cf)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id37ed21193db67ceee11a795713c34ef26383380
Reviewed-on: http://review.coreboot.org/7993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
ARM processors save the PC value in the Link Register when they handle
and exception, but they store it with an added offset (depending on the
exception type). In order to make crashes easier to read and correctly
support more complicated handlers in libpayload, this patch adjusts the
saved PC value on exception entry to correct for that offset.
(Note: The value that we now store is what ARM calls the "preferred
return address". For most exceptions this is the faulting instruction,
but for software interrupts (SWI) it is the instruction after that. This
is the way most programs like GDB expect the stored PC address to work,
so let's leave it at that.)
Numbers taken from the Architecture Reference Manual at the end of
section B1.8.3.
BRANCH=none
BUG=chrome-os-partner:18390
TEST=Provoked a data abort and an undefined instruction in both coreboot
and depthcharge, confirmed that the PC address was spot on.
Original-Change-Id: Ia958a7edfcd4aa5e04c20148140a6148586935ba
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199844
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
(cherry picked from commit 4a914d36bb181d090f75b1414158846d40dc9bac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib63ca973d5f037a879b4d4d258a4983160b67dd6
Reviewed-on: http://review.coreboot.org/7992
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This adds a generic helper function for adding boot reason in the
ChromeOS case. If vboot is enabled, it will use information passed
in via the vboot handoff table in cbmem to determine mode and
reason in the case of recovery.
BUG=chromium:373467
BRANCH=nyan
TEST=built along with follow-up CL and booted on Big under various
modes, verified entry was added to eventlog with "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I50a7aa6d55eb46413fe9929e732d6eb18c758d4b
Original-Reviewed-on: https://chromium-review.googlesource.com/199690
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 961c0bd1dd5512b1c2feb2ed4391bf507900eb7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6ae4e2a891966d2d1de7d37dcc551383e94e4d75
Reviewed-on: http://review.coreboot.org/7991
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The static allocator only worked for x86 anyway.
Change-Id: Iadaab225fea04b455c559c25b918a2a842b9faca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/8029
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Change-Id: I9210241c902ad8a88980a7c9cdb0d52c460b2541
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8025
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
It was showing up as a menu item and it should not.
Change-Id: I448f683fbf4187b11821381332f971b1daea29f8
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/8027
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix a trivial tab/space indent inconsistency while here.
Change-Id: I819d85293e1a070817cd13349a220ba85ba89951
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7984
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Combine four patches dependencies. These will not build
individually, so combine them for coreboot.org upstream.
samus: Move SPD handling to separate file
The code to find the SPD data for the mainboard based on GPIOs
is moved from romstage.c into spd.c.
It relies on the updated pei_data structure from broadwell instead
of the haswell interface.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I5bd56f81884dae117b35a1ffa5fb6e804fd3cb9c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199920
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 0bd2de4ba5eb8ba5e9d43f8e82ce9ff7587eab62)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Move PEI data structure init to separate file
This needs to be executed in both romstage and ramstage
for the different PEI binary stages.
It uses the broadwell interface now instead of haswell.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ida05bd17b9e54f08ed0e2767361c9301a2e97709
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199921
(cherry picked from commit 89f98a27ea561ec63e716b1f6446d92822a6a5de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Convert mainboard to use soc/intel/broadwell
Switch from the haswell cpu/northbridge/southbridge interface
to the soc/intel/broadwell interface.
- Use new headers where appropriate
- Remove code that is now done by the SOC generic code
- Update GPIO map to drop LP specific handling
- Update INT15 handlers, drop all but the boot display hook
BUG=chrome-os-partner:28234
TEST=Build and boot on samus
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199923
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: I56f3543612e89e2cdb4256b1bcd4279f5546b918
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199922
(cherry picked from commit 715dbb06e9f79d1ec3647330311c45aa29362375)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
samus: Add some code to print basic info from SPD
The handling of LPDDR is a bit messy in Intel platforms. There
is no traditional SPD so instead one is created by hand from the
provided datasheets.
These have varying (and sometimes unexpected) geometry and it can
be important during bringup to know what configuration is being
passed to the memory training code.
This could in theory be put in a more generic location, but for now
this is the only board with LPDDR3 where I have found it valuable.
BUG=chrome-os-partner:28234
TEST=Build and boot on samus, look for SPD details on the console.
CQ-DEPEND=CL:199920
CQ-DEPEND=CL:199921
CQ-DEPEND=CL:199922
CQ-DEPEND=CL:199943
CQ-DEPEND=CL:*163751
Original-Change-Id: Ibce0187ceb77d37552ffa1b4a5935061d7019259
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199923
(cherry picked from commit 3f36348dd7abc67048407f181065f1a99b3d0dab)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1d19dffbd0b2e838d1946670a0bee9f8e121869d
Reviewed-on: http://review.coreboot.org/7943
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Hook the soc/intel/broadwell directory into the configuration
and build system so it can be used by mainboards.
BUG=chrome-os-partner:28234
TEST=build and boot on wtm2
Original-Change-Id: Ia48ac644a8cefb2cf9c64efaa1bd9737ddfb8b1f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ee290d7f6e541999e077bcf871cd6c7b6504f3d6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iea5f37a839b516ac98227cc1737ce0d03f7e7e3b
Reviewed-on: http://review.coreboot.org/7940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Updated Intel Broadwell for differences in the source based on
the chromium tree. It is missing most of the recent updates
on coreboot.org.
- makefile changes for Elog and IDF tool
- kconfig changes for ME, ucode, and other updates
- update oprom flag
- update timestamp mechanism
- cbfs payload function is now generic
Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7939
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
A typical SPI operation consists of two phases - command and data
transfers. Command transfer is always from the host to the chip (i.e.
is going in the 'write' direction), data transfer could be either read
or write.
We don't want the receive FIFO to be operating while the command phase
is in progress. A simple way to keep the receive FIFO shut down is to
not to enable it until the command phase is completed.
Selective control of the receive FIFO allows to consolidate the
receive and transmit functions in a single spi_xfer() function, as it
happens in other SPI controller drivers.
The FIFO FULL and FIFO NOT EMPTY conditions are used to decide if the
next byte can be written or received, respectively. While data is
being received the 0xFF bytes are transmitted per each received byte,
to keep the SPI bus clocking.
The data structure describing the three GSBI ports is moved from the
.h file into .c file. A version of the clrsetbits macro is added to
work with integer addresses instead of pointers.
BUG=chrome-os-partner:27784
TEST=not yet, but with the res of the changes the bootblock loads and
starts the rombase section successfully.
Original-Change-Id: I78cd0054f1a8f5e1d7213f38ef8de31486238aba
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197779
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit c101ae306d182bbe14935ee139a25968388d745a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7f3fd0524ec6c10008ff514e8a8f1d14a700732f
Reviewed-on: http://review.coreboot.org/7983
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
The original patch from chromium was a bit of a mishmash.
Between that, rebasing and using the coreboot.org UART infrastructure,
the patch has changed a bit from the original. It seems reasonable to
keep these changes together.
- build in the ipq UART and turn on bootblock console
- sets LPAE and ROM header address
- adds cpd.c to storm
The original commit:
ipq8064: make UART driver work in bootblock
This patch it the last one in the chain adapting the ipq9064 UART
driver for use in coreboot. A new config option
(CONSOLE_SERIAL_IPQ806X) is being introduced to control inclusion of
the driver.
The previously introduced uart_wrapper.c is now included in the build
to provide the console driver structure used by ramstage.
Necessary configuration options are added to allow use of UART in the
bootblock.
BUG=chrome-os-partner:27784
TEST=with this change the coreboot image on AP148 prints a banner on
start up:
coreboot-4.0 Wed Apr 23 16:24:51 PDT 2014 starting...
Original-Change-Id: I129ee30ba17a5061b30cfee56c135df31eba98b5
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196663
(cherry picked from commit 42ca8994361327c24e7a611505b21534dd231f30)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1175e74ed639cdc27a1a677fba65de2dd2b13a91
Reviewed-on: http://review.coreboot.org/7875
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
We relocate GDT to CBMEM, this can be done late in ramstage.
Note: We currently do this for BSP CPU only.
Change-Id: I626faaf22f846433f25ca2253d6a2a5230f50b6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7858
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
GPIO init marcos are not enough to initialize different gpio attributes
BUG=none
TEST=emerge-rambi coreboot works well
Original-Change-Id: I193fa7b3e22632cacb555e726e3dd3991f4f4faa
Original-Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200531
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5e0fcbcd7cefcfccb5b565003336d197bb29e4cc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6bf4db9397733a003dfdedc6eb63b82127917851
Reviewed-on: http://review.coreboot.org/7953
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The VDDIO to GEN2 I2C SCL/SDA pins is 1.8V and the external
pull-up voltage is 3.3V (the external 3.3V > I/O 1.8V) thus
the pinmux E_OD bit of these two pins needs to be set to
ensure GEN2 I2C pads work fine on 3.3V.
BRANCH=nyan
BUG=none
TEST=observed voltage drop from 3.3V to 2.36V on gen2 i2c
on blaze w/o this change. the waveform looks good on both
scl/sda pins w/ this change.
Original-Change-Id: I1b97f0c9c7580d1e532c3bdf7ac8690241ee7ee3
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200996
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 2db39166ec525e56a19746f38a867305a2687365)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0c84eade89311baf0a6f180cb5cc9e2145f6b7ea
Reviewed-on: http://review.coreboot.org/7952
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The kernel will not track wakeup events for devices unless they have
a defined _PRW. There is no EC output of the lid signal coming to
a GPIO and instead it pulses PCH_WAKE#.
BUG=chrome-os-partner:27631
TEST=Manual on Rambi.
- Run lidclose + lidopen on EC console, verify that wakeup_count
increments.
- Run lidclose + lidopen in rapid succession, verify that suspend
request is aborted.
BRANCH=Rambi.
Original-Change-Id: I8d4c58a7bb37d7e474ec094fe96e46e1bfd980de
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200289
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
(cherry picked from commit 08c6b42f1ed1af7fff6217e6b71469edd7ff4b2e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iee813ed6f39cd3d5e0a2bdd395c740f82a1cf01a
Reviewed-on: http://review.coreboot.org/7945
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Add the empty weak function clear_recovery_mode_switch().
Problem:
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC is set,
the following will happen:
1. Boot device in recovery mode with Esc + F3 + Pwr.
2. Turn device off with Pwr button.
3. Turn device on with Pwr button.
Device still boots to recovery screen with
recovery_reason:0x02 recovery button pressed.
If GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC isn't set, turning the
device off and on again with the Pwr button does a normal boot.
Solution:
Unconditionally clear the recovery flag.
BUG=chromium:279607
BRANCH=TOT
TEST=Compile OK.
Original-Change-Id: Ie1e3251a6db12e75e385220e9d3791078393b1bf
Original-Signed-off-by: Sheng-Liang Song <ssl@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197780
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Randall Spangler <rspangler@chromium.org>
Original-Commit-Queue: Sheng-liang Song <ssl@google.com>
Original-Tested-by: Sheng-liang Song <ssl@google.com>
(cherry picked from commit 18908bb64cef34ca41812814817ef887961bed34)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I71ca9f3ea8d816c865375ec66a0603ca211f23ae
Reviewed-on: http://review.coreboot.org/7895
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Length arguments for VbExTpmSendReceive have type uint32_t but it calls function
which expects size_t. This change converts uint32_t to size_t on call and
size_t to uint32_t on return.
BUG=None
BRANCH=None
TEST=Booted Nyan Big to Linux
Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Original-Change-Id: I1971488baae2d060c0cddec7749461c91602a4f9
Original-Reviewed-on: https://chromium-review.googlesource.com/198016
(cherry picked from commit 6830747eb47568f2a2b494624522d37d8945c030)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I20741759e7bbd60dd7044c532287d6b55047e19a
Reviewed-on: http://review.coreboot.org/7894
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
To avoid LCD_VCC glitch on cold reset, set SOC_DISP_ON as GPIO output high.
After gfx initialize is done, set it to native function 2.
BUG=chrome-os-partner:25159
BRANCH=firmware-rambi-5216.B
TEST=Tested on Rambi and squawks, no LCD_VCC glitch anymore.
Original-Change-Id: If16af498e910a8da1d77a9a66456eb767286a61a
Original-Change-Id: Icf62588fa0338f89fafb3fe9246c26f16bcdaa60
Original-Signed-off-by: Kein Yuan <kein.yuan@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197985
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Tested-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 6f7d621678f22133c9825565fedc77d19198b08c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibaf547b8d1c27811a1bec9fa3254d559c505a361
Reviewed-on: http://review.coreboot.org/7893
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
If the kernel does not properly handle the TPM and send it a
TPM_SaveState command before suspend then it will not be in
the correct state on resume. In order to easily detect this
case add a new post code for TPM failure and use it in the
vboot resume path.
BUG=chromium:371105
TEST=Build and boot on wtm2.
Original-Change-Id: I412520b521387a8e18ad1c6f5a64b39cdd5c88ec
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199371
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit ff2f0dc56c1a783295710f81567af02729fe1da2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5baf894fd72922acd79d191e5485ae8ef7e0d559
Reviewed-on: http://review.coreboot.org/7936
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.
BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan
Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4fad296ecfeff8987e4a18054661190239245f32
Reviewed-on: http://review.coreboot.org/7891
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The AS3722 PMIC, like many PMICs, has an RTC built into it. This change adds a
driver for it which implements the new RTC API.
BUG=None
TEST=Built and booted with the event log code modified to use this interface.
Verified that events had accurate timestamps.
BRANCH=nyan
Original-Change-Id: I400adccbf84221dcba8d520276bb91b389f72268
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197796
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 011e49beba3a99abbd122866891e3c20bf1188d2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibc1d342062c7853a30d195496c077e37a02b35b0
Reviewed-on: http://review.coreboot.org/7890
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch has a rather twisted history. It was originally split off
from a chromium patch, which moved ALTCENTURY to Kconfig. However,
since we have no user without ALTCENTURY, we've agreed that the best
way to proceed is to eliminate the non-ALTCENTURY case entirely.
The old commit message and identifiers are kept below for reference:
The availability of "ALTCENTURY" is now set through a kconfig
variable so it can be available to the RTC driver without having to have a
specialized interface.
BUG=None
TEST=Built and booted on Link with the event log code modified to use the RTC
interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the second half the following patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8e871f31c3d4be7676abf9454ca90808d1ddca03
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7987
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
This brings in the banana_cs version of the SPI driver.
BUG=chrome-os-partner:27784
TEST=none
Original-Change-Id: Ie93ec8c962c26fff1f0a235516cd8a4062cab40b
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194225
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 3cada6e4ed51a6d4f637aa31a1a836352a99d13d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0a58a4ddaf9375c22c9b2b249a2baa2c5538ba6c
Reviewed-on: http://review.coreboot.org/7982
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
There is a hub in USB port2 downstream.
BUG=chrome-os-partner:28964
BRANCH=None
TEST=emerge-nyan_blaze coreboot depthcharge chromeos-bootimage and verify usb
port2 is workable
Original-Change-Id: I0e698970729911f401f89594232f9d49e4da93cc
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200417
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 9316acfe8791585f778eecead95943e6422ca419)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I76e4331ea6e803bfbbddefab449310421c0c1d9c
Reviewed-on: http://review.coreboot.org/7949
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Our tests with the I2C bit clear mechanism (recovering from "lost
arbitration" errors) show that the bit clear hardware does not work
correctly in some situations. When a wedged slave device tries to send
more than one 0-to-1-to-0 transition to the host (e.g. leftover bits
from an aborted read), the controller never transitions the BC_ENABLE
bit back to zero.
This patch adds a long timeout to the bit clear code that waits for
register transitions as a safeguard. This way, We will still eventually
exit the function (probably followed by a reboot). Our tests show that
this will recover from all conditions after at most a few reboots.
BRANCH=nyan
BUG=chrome-os-partner:28323
TEST=Ran wedge_ack and wedge_read tests with software_i2c patch, system
recovered as expected in all cases.
Original-Change-Id: I6c37119130e1240e1ef3a5944582abbcd2e39ff0
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/200265
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4c8d0af25cf107a38c856b38067b8f2f74384f22)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I600d5c9a8e68719cf8795c083c5fac63f626f5bf
Reviewed-on: http://review.coreboot.org/7948
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This patch adds I2C emulation in software through raw toggling of the
SDA/SCL lines. Platforms need to provide bindings to toggle their
respective I2C busses for this to work (e.g. by pinmuxing them as GPIOs,
currently only enabled for Tegra).
This is mostly useful as a debugging feature, to drive unusual states on
a bus and closely monitor the device output without the need of a bus
analyzer. It provides a few functions to "wedge" an I2C bus by aborting
a transaction at certain points, which can be used to test if a system
can correctly recover from an ill-timed reboot. However, it can also
dynamically replace the existing I2C transfer functions and drive
some/all I2C transfers on the system, which might be useful if a driver
for the actual I2C controller hardware is not (yet) available.
Based on original code by Doug Anderson <dianders@chromium.org> and
Hung-ying Tyan <tyanh@chromium.org> for the ChromeOS embedded
controller project.
BRANCH=None
BUG=chrome-os-partner:28323
TEST=Spread tegra_software_i2c_init()/tegra_software_i2c_disable()
through the code and see that everything still works.
Original-Change-Id: I9ee7ccbd1efb38206669a35d0c3318af16f8be63
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/198791
Original-Reviewed-by: Doug Anderson <dianders@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8f71503dbbd74c5298e90e2163b67d4efe3e89db)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id6c5f75bb5baaabd62b6b1fc26c2c71d9f1ce682
Reviewed-on: http://review.coreboot.org/7947
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When doing DP attach, we need to make sure the register change to
take effect immediately, otherwise it may fail to catch the attach
timing.
BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big
Original-Change-Id: I569dc435a1aa4aac0d5ecd0655d2ad87a791246d
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200414
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 47b86e2893fa667bebada6a0e0b443886dd5ee02)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Icf809b46e675bbdb8633d9a4f31d005d6644bd2a
Reviewed-on: http://review.coreboot.org/7951
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
We initialized the dc before the plld's initialization. So some
of the dc init settings did not took effect. This patch moves
the clock_display() before the dc init call.
BRANCH=None
BUG=chrome-os-partner:28128
TEST=Display works and system boots up on Nyan and Big
Original-Change-Id: If2c40e2526fdf7a6aa33a2684ba324bd0ec40e90
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/200413
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit dc3cc253c319c21772c30962d963ec9dfc4944a7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I021290f4293c740666d460f73fecbe79146896a4
Reviewed-on: http://review.coreboot.org/7950
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=nyan
TEST=built and booted on Big under various modes, verified that
expected boot mode showed up using "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8d98487a2cb910874c8d741008ae59a6c89102e7
Original-Reviewed-on: https://chromium-review.googlesource.com/199691
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 9f4b2574c1af23dcdc01706e9a118441f46a0f97)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ibbf264a1e05323dfddb7cdb270ee6f2d49e83eff
Reviewed-on: http://review.coreboot.org/7946
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Provide elog stub functions so eventlog support can be omitted
without littering code with "#if CONFIG_ELOG".
This makes it so coreboot can be built without eventlog support for
these platforms for debugging purposes.
BUG=none
BRANCH=none
TEST=compiled for Nyan and Rambi with CONFIG_ELOG unset
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Ibf56d29a09234068773378f99ad9bffd5480dc9c
Original-Reviewed-on: https://chromium-review.googlesource.com/198647
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 8e83dd460647972c4f46c19f8dc3d3ad7baeb550)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3c0803ceb7a1c06da717416c42b6b7730c029ed0
Reviewed-on: http://review.coreboot.org/7901
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The IO accessor wrappers are used to allow integer register addresses.
A structure defining UART interface configuration is declared and
defined. A few long lines are wrapped. Interface functions are renamed
to match the wrapper API.
cdp.c is edited to fit into coreboot compilation environment, and the
only function required by the UART driver if exposed, the rest are
compiled out for now.
BUG=chrome-os-partner:27784
TEST=after all patches are applied the serial console on AP148 becomes
operational.
Original-Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196662
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 5e9af53a069cd048334a3a28f0a4ce9df7c96992)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I80c824d085036c0f90c52aad77843e87976dbe49
Reviewed-on: http://review.coreboot.org/7874
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
These patch modifies .h files to match the coreboot API. A few more
significant changes are:
- UART specific fields removed from common board structure in cdp.h.
These fields are set at compile time in u-boot (where this
structure comes from), they will be set in a different structure in
the UART driver in an upcoming patch.
- an inline wrapper is added in gpio.h to provide GPIO API the UART
driver expects.
- the ipq_configure_gpio() is passed the descriptor placed in ro data.
BUG=chrome-os-partner:27784
TEST=none
Original-Change-Id: Id49507fb0c72ef993a89b538cd417b6c86ae3786
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196661
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit ea400f1b720eb671fa411c5fd1df7efd14fdacd6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2c7be09675b225de99be3c94b22e9ee2ebb2cb9a
Reviewed-on: http://review.coreboot.org/7873
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Make sure it is initialized at different stages.
BUG=chrome-os-partner:27784
TEST=manual
. not much at this point, just verified that it compiles
Original-Change-Id: I343e7a6648e2ca935606cd76befd204aabd93726
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on:
https://chromium-review.googlesource.com/196592
(cherry picked from commit aedc41924313e5c21aef97b036f5a0643d59082d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I4a90ae5ba6c9a561b7d5c938d18b6ea2b855855f
Reviewed-on: http://review.coreboot.org/7981
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The following patches had to be squashed
to properly build all the different ARM boards.
ipq8064: storm: re-arrange bootblock initialization
The recent addition of the storm bootblock initialization broke
compilation of Exynos platforms. The SOC specific code needs to be
kept in the respective source files, not in the common CPU code.
As of now coreboot does not provide a separate SOC initialization API.
In general it makes sense to invoke SOC initialization from the board
initialization code, as the board knows what SOC it is running on.
Presently all what's need initialization on 8064 is the timer. This
patch adds the SOC initialization framework for 8064 and moves there
the related code.
BUG=chrome-os-partner:27784
TEST=manual
. nyan_big, peach_pit, and storm targets build fine now.
Original-Change-Id: Iae9a021f8cbf7d009770b02d798147a3e08420e8
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197835
(cherry picked from commit 3ea7307b531b1a78c692e4f71a0d81b32108ebf0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
arm: Redesign mainboard and SoC hooks for bootblock
This patch makes some slight changes to the way bootblock_cpu_init() and
bootblock_mainboard_init() are used on ARM. Experience has shown that
nearly every board needs either one or both of these hooks, so having
explicit Kconfigs for them has become unwieldy. Instead, this patch
implements them as a weak symbol that can be overridden by mainboard/SoC
code, as the more recent arm64_soc_init() is also doing.
Since the whole concept of a single "CPU" on ARM systems has kinda died
out, rename bootblock_cpu_init() to bootblock_soc_init(). (This had
already been done on Storm/ipq806x, which is now adjusted to directly
use the generic hook.) Also add a proper license header to
bootblock_common.h that was somehow missing.
Leaving non-ARM32 architectures out for now, since they are still using
the really old and weird x86 model of directly including a file. These
architectures should also eventually be aligned with the cleaner ARM32
model as they mature.
BRANCH=None
BUG=chrome-os-partner:32123
TEST=Booted on Pinky. Compiled for Storm and confirmed in the
disassembly that bootblock_soc_init() is still compiled in and called
right before the (now no-op) bootblock_mainboard_init().
Original-Change-Id: I57013b99c3af455cc3d7e78f344888d27ffb8d79
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/231940
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 257aaee9e3aeeffe50ed54de7342dd2bc9baae76)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id055fe60a8caf63a9787138811dc69ac04dfba57
Reviewed-on: http://review.coreboot.org/7879
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: If883ff6eb14dd49a06f57a01ca61661854ded78d
Original-Reviewed-on: https://chromium-review.googlesource.com/198324
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 536c34c2d92178f4e62b8ca7cfffceaf80a305f6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I199451ed2b29c55bfb5e1487afa8cf3b9978e63e
Reviewed-on: http://review.coreboot.org/7935
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
The Eon SPI25 code had a number of issues:
- fix page write calculation
- fix erase segment
- fix id check
- fix sector size
- make commands EN25 generic
This makes the code similar to other SPI25 devices used in coreboot.
BUG=chrome-os-partner:25907
BRANCH=baytrail(rambi)
TEST=Read and write MRC and ELOG on Glimmer with Eon device.
Original-Change-Id: I7667eab28b850790d92a591c869788d51c26a56c
Original-Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198323
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Marc Jones <marc.jones@se-eng.com>
Original-Tested-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2ee0da695bf6a6c6aedc0dd2b3a3b7c9c3165bca)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8917e778cd62f3745189336d23c0c6118887d893
Reviewed-on: http://review.coreboot.org/7934
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Since the same driver is going to be used at all coreboot stages, it
can not use malloc() anymore. Replace it with static allocation of the
driver container structure.
The read interface is changed to spi_flash_cmd_read_slow(), because of
the problems with spi_flash_cmd_read_fast() implementation. In fact
there is no performance difference in the way the two interface
functions are implemented.
BUG=chrome-os-partner:27784
TEST=manual
. with all patches applied coreboot proceeds to attempting to load
the payload.
Original-Change-Id: I1c7beedce7747bc89ab865fd844b568ad50d2dae
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197931
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 57ee2fd875c689706c70338e073acefb806787e7)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I9d9e7e343148519580ed4986800dc6c6b9a5f5d2
Reviewed-on: http://review.coreboot.org/7933
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Coreboot has all necessary infrastructure to use the proper SPI flash
interface in bootblock for CBFS. This patch creates a common CBFS
wrapper which can be enabled on different platforms as required.
COMMON_CBFS_SPI_WRAPPER, a new configuration option, enables the
common CBFS interface and prevents default inclusion of all SPI chip
drivers, only explicitly configured ones will be included when the new
feature is enabled. Since the wrapper uses the same driver at all
stages, enabling the new feature will also make it necessary to
include the SPI chip drivers in bootblock and romstage images.
init_default_cbfs_media() can now be common for different platforms,
and as such is defined in the library.
BUG=none
TEST=manual
. with this change and the rest of the patches coreboot on AP148
comes up all the way to attempting to boot the payload (reading
earlier stages from the SPI flash along the way).
Original-Change-Id: Ia887bb7f386a0e23a110e38001d86f9d43fadf2c
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197800
Original-Tested-by: Vadim Bendebury <vbendeb@google.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 60eb16ebe624f9420c6191afa6ba239b8e83a6e6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I7b0bf3dda915c227659ab62743e405312dedaf41
Reviewed-on: http://review.coreboot.org/7932
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Add the device ID definitions and properties for the SPI chip used on
the AP148 board (Google Storm).
BUG=chrome-os-partner:27784
TEST=manual
. with the rest of the patches applied AP148 boots all the way to
trying to read the payload.
Original-Change-Id: I5a0e5c9d3cc9ea81bc5227c0fbc1d0a5fc7bec27
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/197895
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit a7c69981b18ac6b1158273596b94df0def65963d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I14e2f4f8f691a7db6ed596a3440914e08680867b
Reviewed-on: http://review.coreboot.org/7931
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This CL adds an API for RTC drivers, and implements its two functions,
rtc_get and rtc_set, for x86's RTC. The function which resets the clock when the
CMOS as lost state now uses the RTC driver instead of accessing the those
registers directly.
BUG=None
TEST=Built and booted on Link with the event log code modified to use
the RTC interface. Verified that the event times were accurate.
BRANCH=nyan
Original-Change-Id: Ifa807898e583254e57167fd44932ea86627a02ee
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197795
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
This is the first half of the patch.
(cherry picked from commit 9e0fd75142d29afe34f6c6b9ce0099f478ca5a93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I159f9b4872a0bb932961b4168b180c087dfb1883
Reviewed-on: http://review.coreboot.org/7889
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CBMEM IDs are converted to symbolic names by both target and host
code. Keep the conversion table in one place to avoid getting out of
sync.
BUG=none
TEST=manual
. the new firmware still displays proper CBMEM table entry descriptions:
coreboot table: 276 bytes.
CBMEM ROOT 0. 5ffff000 00001000
COREBOOT 1. 5fffd000 00002000
. running make in util/cbmem still succeeds
Original-Change-Id: I0bd9d288f9e6432b531cea2ae011a6935a228c7a
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/199791
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 5217446a536bb1ba874e162c6e2e16643caa592a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0d839316e9697bd3afa0b60490a840d39902dfb3
Reviewed-on: http://review.coreboot.org/7938
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Always build CBMEM for romstage, even for boards that will not use it.
We further restrict car_migrate_variables() runs to non-ROMCC boards without
BROKEN_CAR_MIGRATE.
This fixes regression of commit 71b21455 that broke CBMEM console support
for boards with a combination of !EARLY_CBMEM_INIT && !HAVE_ACPI_RESUME.
Change-Id: Ife91d7baebdc9bd1e086896400059a165d3aa90f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7877
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When using fixed MTRRs for CAR setup, CONFIG_DCACHE_RAM_BASE is ignored
and was not correctly set on affected sockets and boards. It was still
referenced in romstage linker script. This was discovered by clang builds
failing for cases where DCACHE_RAM_BASE = 0, while gcc builds passed.
The actual DCACHE_RAM_BASE programming is base = 0xd0000 - size, as taken
from intel/cpu/cache_as_ram.inc.
Change-Id: Ied5ab2e9683f12990f1aad48ee15eaf91133121c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7887
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Disable Super I/O related topics showing in menuconfig.
Change-Id: I246bc935147baf6ff2dfcb306079cc2d4c7cb153
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7985
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If it's a 4 byte format (as per documentation), there
are some reserved bits, so let's mark them as such...
Unfortunately undone while upstreaming changes.
Change-Id: I50f12cfff2c9bb9d082a5f3c3ac54c0d514d862c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Originally-Reviewed-on: http://review.coreboot.org/7674
Reviewed-on: http://review.coreboot.org/7964
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The "((1ull << (sizeof(modules) * 8)) - 1)" statement evaluates to
0xffffffff, but there's no need to AND with that value, as 'modules'
is already 32-bit. The '&&' is most likely a typo, which meant bitwise
and, as indicated by the structure of thus operation.
Remove this superfluous statement. This also fixes a clang warning.
Change-Id: Ie55bd9f8b0ec5fd41e440f56dcedd40c830bf826
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7965
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
CPU_MICROCODE_CBFS_LOC used a non-existing dependency variable
CPU_MICROCODE_IN_CBFS. This broke alignment of microcode in CBFS.
Remoce CPU_MICROCODE_CBFS_LOC from global namespace as it is only
used with PLATFORM_FSP.
CPU_MICROCODE_CBFS_LEN was no longer used at all.
Change-Id: I0454397924d2526d97b1f095cc371ba962873c99
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7957
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbol map_oprom_vendev is no longer NULL.
Always have empty stub function defined.
Change-Id: I5b1bdeb3f37bb04363cf3d9dedaeafc9e193aaae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7956
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
After relocation the weak symbols are no longer NULL.
Always have empty stub function defined.
Change-Id: I6cb959c1fa10b4b63018e400636842e2a15d6e81
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7955
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
We had NULL reference with cache_loaded_ramstage() if
CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM was not set so boot never
proceeded to ramstage.
Cache implementation outside CBMEM provides means for platform-specific
location so there is no need of weak attributes here.
Change-Id: I1eb1a713896395c424fde23252c374f9065fe74d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7954
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It's not needed, as we can use a simpler macro instead.
Change-Id: Ib96f5cfa434d0383ee3bfe49995a8f8830987f20
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7925
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This change updates the cfg file for Micron/Samsung 2GB,
792MHz DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I840cdd967c3b38479946a497a91da89bef5a98ad
Original-Signed-off-by: Jerry Wang <jerryw@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/199296
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
(cherry picked from commit cb70674c6551c8c36d2fd2d220e0f677ed2c6b24)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I11222bc1453a76cc27c2be169be5d3481ed7cfe7
Reviewed-on: http://review.coreboot.org/7902
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. That puts the machine in a funny state and may prevent it
from booting properly.
BUG=chrome-os-partner:28559
TEST=Built for nyan, nyan_big and nyan_blaze. Booted normally, through EC
reset, software reset ("reboot" command from the terminal), and through watch
dog reset. Verified that the new code only triggered during the watchdog reset
and that the system rebooted and was able to boot without going into recovery
mode unnecessarily.
BRANCH=nyan
Change-Id: Id92411c928344547fcd97e45063e4aff52d2e9e8
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/198582
Reviewed-by: Tom Warren <twarren@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit b298be41c0959c58aeb8be5bf15141549da2504c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7900
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
When a watchdog reset happens, the SOC will reset but other parts of the
system might not. In order to detect those situations we can check the
rst_status register in the PMC.
BUG=chrome-os-partner:28559
TEST=With this and a change which uses the new function in the nyan boards,
built for nyan, nyan_big and nyan_blaze. Booted normally, through EC reset,
software reset ("reboot" command from the terminal), and through watch dog
reset. Verified that the new code only triggered during the watchdog reset and
that the system rebooted and was able to boot without going into recovery mode
unnecessarily.
BRANCH=nyan
Original-Change-Id: I7430768baa0304d4ec8524957a9cc37078ac5a71
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/198581
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 5fdc0239fc2960167dd9c074f3804bf9e4ad686a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5845d3a4d819868f5472c758e83e83b00e141b72
Reviewed-on: http://review.coreboot.org/7899
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The original sdram-hynix-2GB-792.inc was just copied from nyan
bct file. This change updates the cfg file for Hynix 2GB, 792MHz
DRAM based on the data generated by t124_emc_reg_tool.
BUG=none
BRANCH=blaze
TEST=emerged coreboot, booted successfully into kernel.
Original-Change-Id: I9534b4df6d35193179de124309df12ed830098a0
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197660
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 797dabe54f2679bb5717961dda1947df453eb0f1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie67bedb29d5d9c3a3b58d949ddf9600716c385ec
Reviewed-on: http://review.coreboot.org/7898
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
This is a fix for the 'Lost arb' we're seeing on Nyan* during
reboot stress testing. It occurs when we are slamming the
default PMIC registers with pmic_write_reg().
Currently, I've only captured this a few times, and the bus
clear seemed to work, as the PMIC writes continued (where
they'd hang the system before bus clear) for a couple of regs,
then it hangs hard, no messages, no 2nd lost arb, etc. So
I've added code to the PMIC write function that will reset the
SoC if any I2C error occurs. That seems to recover OK, i.e. on
the next reboot the PMIC writes all go thru, boot is OK, kernel
loads, etc.
BUG=chrome-os-partner:28323
BRANCH=nyan
TEST=Tested on nyan. Built for nyan and nyan_big.
Original-Change-Id: I1ac5e3023ae22c015105b7f0fb7849663b4aa982
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197732
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
(cherry picked from commit f445127e2d9e223a5ef9117008a7ac7631a7980c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I584d55b99d65f1e278961db6bdde1845cb01f3bc
Reviewed-on: http://review.coreboot.org/7897
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reduce difference with exynos5420/clock.c by fixing some whitespace
and an include directive.
Change-Id: Ifbdd61c8300f3988f5f729fe7d6124ac8a9b7821
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7926
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use 'd' instead of 'hhd' when printing absolute year of manufacture. This
is the correct type in this case, as the result is autoatically promoted
to int.
Change-Id: Ice4155bb1a04f206ae55c45c260089d6971b77d1
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7885
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Callout FCH_OEM_CONFIG is made during AMD_INIT_RESET, so it was required
to provide GetBiosCallOut here too.
Change-Id: I0eab858677d14536293385ca37daab3e538132e6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7826
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
We should potentially provide an OEM platform hook to manipulate parameters
around any entry point to AGESA. Use structure for such ops to avoid weak
functions and lots of empty function stubs.
Change-Id: I99bf7de8a1e2f183399d2216520a45d0c24fd64c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7824
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
It does not really matter if we continue or return after a failed
assertion, system configuration is invalid anyway.
Change-Id: I5ba47ee3fd6c5ff97b9229f8bfc9db08873b08ca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7823
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Not part of wrapper to AGESA, but workaround for enable_resources().
Also remove remains of comments in non-fam14 wrappers.
Change-Id: I2526821ca283feb6a506b602b86f817f8b03b341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7816
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
These are not wrappers for AGESA as they do not enter vendorcode at all.
We expect most of the added fixme.c file to be written without use of AMDLIB.h
and parts relocated as northbridge enable_resources().
Change-Id: Iba6d59e2a7672349208e9a65fcd2cb1094ab7d50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7815
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Increase to max 64 buses, as there are no benefits of limit 16.
NOTE: It appears there is no matching (early) programming of the
region to non-posted MMIO.
Change-Id: I664789f7bd90992840e5817555cd3621c2d1e86c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7813
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
MMIO for non-posted region used hard-coded setting for 64 buses
while MSR programming was for 256 buses.
Change-Id: I690237dd459f7b7b4da68ae55ae9d22b79e5f255
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7812
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Minor style fixes to avoid future bikeshedding.
- Opening brace for functions go on their own lines.
- use fixed-length types where appropriate.
BUG=none
BRANCH=none
TEST=it compiles
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: If9855d32c8ed1f5977937806c8c4cce65dd7d450
Original-Reviewed-on: https://chromium-review.googlesource.com/196955
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit e2bfeed18636af6b532e2e8f118de22a658fe41b)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Conflicts:
src/mainboard/emulation/qemu-armv7/uart.c
Change-Id: I8e09db53534802262168e65ec4cd47b96386490a
Reviewed-on: http://review.coreboot.org/7867
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
When across warm reset, if VDD_3V3_SD_CARD gets power-cycled but VDDIO_SDMMC3
does not, we will get ~1.5V leakage on VDD. To fix that, we reset VDDIO_SDMMC3
to 0 along with VDD_3V3_SD_CARD in Coreboot. Payloads must turn on VDDIO_SDMMC3
explicitly before accessing SD card.
Note the warnings of "VDD_SDMMC must set early" in comment seems only happens on
U-Boot and can be removed.
BUG=chrome-os-partner:27053
BRNACH=nyan
TEST=Ctrl-U to boot from SD card, login and type "reboot", then Ctrl-U to boot
again. Without this patch, system will fail in loading kernel.
Original-Change-Id: I7f85995317d18587d514ea3afcff3bfea0a33e93
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196961
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 2cfdb78d9dc229a3c06f19bbe137d59d923908a4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie7d814e0424478c35a56fbc959437ee6a555684a
Reviewed-on: http://review.coreboot.org/7866
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When warm booting, SD card reader on Tegra 124 needs to be reset by setting
power GPIO to zero. Since we don't really access SD card in Coreboot, set it to
zero and let payloads enable power when they need to access SD cards.
CQ-DEPEND=CL:196783
BRANCH=nyan
BUG=chrome-os-partner:27053
TEST=emerge-nyan coreboot depthcharge chromeos-bootimage
# With related changes in depthcharge, boots SD card successfully.
Original-Change-Id: I2d368eb9480c978e9e343648b58a729028c94622
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196774
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Andrew Bresticker <abrestic@chromium.org>
(cherry picked from commit 62bb7d04dff1a87474a8557f144b24e6b7d006ae)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3429535d0d032f9db89d8e70a525a6281102537a
Reviewed-on: http://review.coreboot.org/7865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some panels (including those on Big DVT) cannot work fine without link training
before sending the video signals, especially multi-lane Full HD panels. We need
to use the fast link training functions from kernel to support them.
BRANCH=Nyan
BUG=chrome-os-partner:28128, chrome-os-partner:28129
TEST=tested on nyan, nyan_big dvt.
Vince verified on Full HD panels.
Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ifde8daf0ebdc6fb407610d3563f3311b2a72dbc4
Original-Reviewed-on: https://chromium-review.googlesource.com/196162
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 992132ff3431fc7abba10cc8e910e36d4f3a3f7a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5ed091ae7a872fd674ab21f9f80267052fcd24b1
Reviewed-on: http://review.coreboot.org/7864
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Board has no chance of working without a cache_as_ram.inc, but without
a specified CAR region we also break builds.
Change-Id: I98e9db38c5e0a7bf4a1b8d2f8a693cc8d0c773b9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7863
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It is implied by DYNAMIC_CBMEM.
Change-Id: I6859c4950ce568fb76c7604e9e994031a3d94d78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7857
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
commit 8b685398 (ARM: Overhaul the ARM Makefile.)
changes config flags for cpu and mainboard bootblock initialization.
Tested on beaglebone black.
Change-Id: I70cbe3abad8443c5dc71c8ba76a35973a5284477
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: http://review.coreboot.org/7189
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Only used for AMD K8 siemens/sitemp_g1p1 with southbridge rs690.
Change-Id: Ie98a77ce190b1bd35996c7f25da0a0fe9819c9c3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7809
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Only used on non-AGESA board siemens/sitemp_g1p1 and already dropped
from other AGESA families.
Change-Id: Ifa726d38216c8b684af06af26b701daa99c42e8c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
"SPD has a invalid or zero-valued CRC" is not a very useful message,
so show the actual and expected values.
Change-Id: I31a1cdacc82240c699627769d490b94f5d378e86
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/7393
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The new AMD PSP and SMU BLOBs currently have fixed sizes in the
southbridge Makefile. Future PSP and SMU updates may require more
space and thereby cause the make to fail with cryptic error messages.
Change the makefile to compute CBFS locations and the corresponding
PSP pointer table entry values based on the actual file sizes.
Additionally, the FWM directory has expanded to 4096 bytes. The
Avalon makefile is modified to zero-pad the FWM directory using
the "dd" system command.
There is dead code in the makefile to allow hardware validated boot
ROMs, but the option is hard-coded to be disabled. Remove the HVB
dead code.
Change-Id: I4705cede8ed001a71bb4f49598444255c9609d52
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/7726
Reviewed-by: Marshall Dawson <marshall.dawson@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Along with the spelling fixes, it was requested that I correct this
comment. Updating "LocateImage() take minutes" to
"LocateImage() takes minutes" everywhere that comment occurs.
Change-Id: I28cd47476cb42ba3e404e064695a7fd97d581834
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7848
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Port 80h codes were coming out of bootblock and romstage scrambled, or
were not coming out at all. Initializing the LPC signal pads as LPC
fixes that issue.
Change-Id: I16943513f2eb6fe8fa58766aaa82dac182440c34
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7802
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GPIO_NC1 #define was added to handle GPIOs that are not on func0.
This is already handled elsewhere in the GPIO code, so is not needed.
- Remove the single GPIO_NC1 from platforms using fsp_baytrail
- Revert the GPIO_INPUT_PU_10k #define to remove the _func argument.
Update everywhere this macro is called.
- Remove GPIO_NC1
Change-Id: I32f337af7bc88eab821d9a8c375145b45718275f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7849
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The GPIO_OUT_LOW #define was missing an internal comma in both
soc/intel/baytrail and soc/intel/fsp_baytrail.
Thanks to Werner Zeh for pointing this out.
Change-Id: I2e5507058739e5fdc2c0e43e0380058458870e46
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7801
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
The variable 'halt' is not useful and results in a compile error
because of:
1b2f2a07 Introduce halt()
build error:
src/mainboard/amd/olivehillplus/romstage.c: In function 'cache_as_ram_main':
src/mainboard/amd/olivehillplus/romstage.c:43:15: error: declaration of 'halt' shadows a global declaration [-Werror=shadow]
In file included from src/include/cpu/x86/lapic.h:6:0,
from src/mainboard/amd/olivehillplus/romstage.c:29:
src/include/halt.h:31:32: error: shadowed declaration is here [-Werror=shadow]
cc1: all warnings being treated as errors
make: *** [build/mainboard/amd/olivehillplus/romstage.pre.inc] Error 1
Change-Id: Id67a0dcb192fb6478115e489f46bfb07021afd90
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/7847
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
This one is special because qemu is really far from anything real but
shares some common features.
Change-Id: Ia1631611724a074780e1fece50166730b2ee94ae
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6939
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
.. and also drop the northbridge and southbridge used by the board.
This is one of the last boards to not use ROMCC for romstage. Let's
get rid of it.
Change-Id: I0a864b2c4ce3eeb7d3e199944eedef0cd71a85e6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7853
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
There is no Cache As Ram for these boards, let's get rid of them.
Also drop unused dependencies
Change-Id: I94782da521c32ade7891ada29d3013cbab32a48b
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7836
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The first dword in FirmwareTN has been changed from 0xa0009 to 0xa000e.
The FirmwareTNHeader is not called by any one in latest PI. It seems to
be useless for now.
Change-Id: Ic7a20e0bcca8de0b56c7bc5d01e0ce86347bde21
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/7844
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This allows the chromeos header and functions to be included
without needing to guard with #if CONFIG_CHROMEOS.
BUG=chrome-os-partner:28234
BRANCH=None
TEST=emerge-rambi coreboot
Original-Change-Id: I523813dc9521d533242ae2d2bc822eb8b0ffa5e2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196265
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit b78ccada9a01f54a60993dfc2c618201d31df9ad)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic2f7127966da716e114336c30829a6403d82e180
Reviewed-on: http://review.coreboot.org/7843
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This cleans up a mis-merge in elog.c and puts the following
change back:
drivers/elog: Unmangle header include out of pre-proc cond
commit a3119e5835
Change-Id: Iafbbd381efdb103717022d2a3c342da376a9428f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7838
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to protect ourselves from the kernel driver not honoring or
placing the correct frequency in the backlight register always set one.
This code path picks 200Hz as the default if nothing is specified in
device tree. It's somewhat arbitrary but that frequency is valid for all
the eDP panel specs we've seen being used on baytrail devices.
BUG=chrome-os-partner:28267
BRANCH=baytrail
TEST=Built and booted in normal mode. Noted register write stuck.
Original-Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196821
Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 2eaa650860ebbc838dbf8c1c1ca2259ac64141ac)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifec29f0671e9f14ba57b9643c29d8bb2cd07eef5
Reviewed-on: http://review.coreboot.org/7845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the normal mode case these settings aren't overwritten by
the VBIOS because the VBIOS does not run. Therefore, the settings
need to align with what the VBIOS programs so that there is a
consistent panel power sequencing.
BUG=chrome-os-partner:28267
BRANCH=baytrail
TEST=Built and booted. Noted settings set by firmware for both dev
and normal mode match.
Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196822
Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf
Reviewed-on: http://review.coreboot.org/7846
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This ensures that SPI is ready when eventlog code is used.
x86 platforms which use eventlog invoke elog_clear() in GSMI and
elog_add_event_raw() when deciding the boot path based on ME status.
For the SMM case spi_init() is called during the finalize stage in
SMM setup. For the boot path case we can call spi_init() at the
beginning of BS_DEV_INIT and it will be ready to use when the boot
path is determined from the ME status.
BUG=none
BRANCH=none
TEST=tested on Link (bd82x6x), Beltino (Lynxpoint), and Rambi
(Baytrail) with follow-up patch
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id3aef0fc7d4df5aaa3c1c2c2383b339430e7a6a1
Original-Reviewed-on: https://chromium-review.googlesource.com/194525
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 173d8f08e867bab8c97a6c733580917f5892a45d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ifaed677bbb141377b36bd9910b2b1c3402654aad
Reviewed-on: http://review.coreboot.org/7756
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Set VB_INIT_FLAG_SW_WP_ENABLED according to the status returned by an
optional platform / mainboard function vboot_get_sw_write_protect().
BUG=chrome-os-partner:26777
TEST=Manual on Rambi with all patches in sequence:
`crossystem sw_wpsw_boot` prints 0
`flashrom --wp-enable` and reboot
`crossystem sw_wpsw_boot` prints 1
BRANCH=Rambi
Original-Change-Id: Ifb852d75cc106d10120cfee0a396b0662282051a
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190096
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c4668fc8a9ab31d9cf876b3d9ad3405756d4d683)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Idace325439958f6b490d2e6705d55e95305c4b2a
Reviewed-on: http://review.coreboot.org/7750
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The call was after the call to vboot_verify_firmware and so would only be
called when falling back to RO, aka recovery mode. This change moves it to
before vboot_verify_firmware so we'll always have the cbmem console.
BUG=None
TEST=Built and booted on nyan and verified that the cbmem console was the same
as the serial output. Built for big and blaze.
BRANCH=nyan
Original-Change-Id: I02d01110659689b08d32777dae384ac3e01b3b9f
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/196158
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d3e4a778e4a0f5ade7d633d8ce7e72ef06c44086)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id14a19a78bcb21cb0c4030c2e41195e491f690d5
Reviewed-on: http://review.coreboot.org/7777
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Panel datasheet defines some delay between PWM signal out and
backlight enable. This change fixes the current sequence
and makes the delays adjustable by dt setting.
BRANCH=none
BUG=chrome-os-partner:28008
TEST=Verified on Big DVT and Nyan/Norrin panels.
Panel works fine with dev mode, and the measurement
of power on sequence meets panel requirements.
Original-Change-Id: If6015bbb6015a3b203d425f5e90f676ad786b5e8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/196183
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 2bbcaa7281222ffc0b4026e8b1eb4c210a8e308a)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id6424f66eb8dc6adeb70eaa33df742f4e57983c3
Reviewed-on: http://review.coreboot.org/7776
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Enable pinmux clamp function to avoid pinmux conflict.
For pins which are configured to tristate enabled, the inputs to the
controller will be clamped to zero. This can be used to avoid pinmux
conflicts since the tristate bit is set to 1 in the power-on-reset
pinmux setting.
With pinmux clamp enabled, we need to configure all the input pins
to tristate disabled.
BUG=chrome-os-partner:27091
BRANCH=None
TEST=built and booted successfully, display worked fine.
Original-Change-Id: Id79a717f2025c812908c7152d439351208aee8d2
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194060
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c95d6fe79810612cfad721667657cdcb87068d23)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1b23df8b90f83ea2b2c08c4364d90fe71533a5a0
Reviewed-on: http://review.coreboot.org/7775
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This enables event logging support for Nyan platforms.
Right now this doesn't do a whole lot. We can add events in
later CLs.
BUG=none
BRANCH=none
TEST=built and booted for Nyan Rev. 1, eventlog gets initialized
if necessary and can be printed by "mosys eventlog list"
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Id77a78f55c8bff9ef0ffc7109c8b03c270e8b6b1
Original-Reviewed-on: https://chromium-review.googlesource.com/191200
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1bb1a00863a63e53379b02f2b466d4d8ae3cef50)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3a5d896d97dfc66ec37114bd3bac3f34e1c22bf7
Reviewed-on: http://review.coreboot.org/7774
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This reverts commit 474313d1b6.
This reverted commit was applied out of sequence and there are a number
of dependencies that need to be in place prior to adding it. Remove it
for now.
Change-Id: If80c40867098dee2feff2b9a1d824558f4d7028d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The length modifiers for unsigned char were accidentally changed from
'hh' to 'h' with commit:
* 1c8ee21 edid: Change static variables to auto variables.
Change-Id: I4b3e63cbcde7635b842894f776373f7946bd0df8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4477
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
SSUS GPIO 5 reflects the Minnowboard Max SKU:
--- GPIO 5 low is a 1GB board
--- GPIO 5 high is a 2GB (or 4GB in the future) board.
This allows us to determine the board type at runtime and configure
the FSP appropriately.
Change-Id: I9f75df5413d23d63280b601457ea9a1ff020d717
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7797
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
- Build gpio.c into romstage
- Add functions to translate the GPIO # to a pad #, then return the
value read from the GPIO.
- Add functions to configure the GPIO - Function, Pull up/down, pull
strength, Input/Output, and Output level.
Change-Id: Ic37dfc9a74a598023bdf797d31087428adec176a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7796
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@gmx.net>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5a5af71ea49152accd92dc331a19e57f3717e4ff
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7841
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I5d2d4ba098d2a95f7643f000f4b48b3349a8e6cf
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7839
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: Ice5d8ce9408356c866a9a2ee5a03f704f55ddc2a
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7842
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Trivial fixes, but the editor highlights them, and it's easy to go
through a bunch of files while I'm otherwise idle.
Change-Id: I31333742d9c90cf6d7ae3d2f324880ed53807d7f
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7840
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This change introduces LPAE for virtual address translation. To enable it, set
ARM_LPAE. Boot slows down about 4ms on Tegra124 with LPAE enabled.
TEST=Booted nyan with and without LPAE. Built nyan_big and daisy.
BUG=None
BRANCH=none
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Daisuke Nojiri <dnojiri@google.com>
Original-Change-Id: I74aa729b6fe6d243f57123dc792302359c661cad
Original-Reviewed-on: https://chromium-review.googlesource.com/187862
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
Original-Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
(cherry picked from commit 6d8c8b2bbdc70555076081eb3bfaabde7b4a398f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8980375c14758af35f7d5ec5244be963e5462d8a
Reviewed-on: http://review.coreboot.org/7749
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This consolidates all calls to spi_claim_bus() and spi_release_bus()
to a single location where spi_xfer() is called. This avoids confusing
(and potentially redundant) calls that were being done throughout the
generic spi_flash.c functions and chip-specific functions.
I don't think the current approach could even work since many chip
drivers assert /CS once and then issue multiple commands such as page
program followed by reading the status register. I suspect the reason
we didn't notice it on x86 is because the ICH/PCH handled each
individual command correctly (spi_claim_bus() and spi_release_bus()
are noops) in spite of the broken code.
BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I3257e2f6a2820834f4c9018069f90fcf2bab05f6
Original-Reviewed-on: https://chromium-review.googlesource.com/194510
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit d3394d34fb49e9e252f67371674d5b3aa220bc9e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieb62309b18090d8f974f91a6e448af3d65dd3d1d
Reviewed-on: http://review.coreboot.org/7829
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a wrapper function and a Kconfig variable to differentiate
between SPI controllers which use atomic cycle sequencing versus
those where the transaction sequence is controlled manually. Currently
this boils down to x86 vs. non-x86.
Yes, it's hideous. The current API only worked because, for better or
worse, x86 platforms have been homogeneous in this regard since they
started using SPI as an alternative to FWH for boot flash. Now that
we have non-x86 platforms which use general purpose SPI controllers,
we should overhaul the entire SPI infrastructure to be more adaptable.
BUG=none
BRANCH=none
TEST=tested on nyan and link
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: If8ccc9400a9d04772a195941a42bc82d5ecc1958
Original-Reviewed-on: https://chromium-review.googlesource.com/195283
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 4170c59d06206667755402712083452da9fcd941)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I54e2d3d9f9a0153a56f7a51b80f6ee6d997ad358
Reviewed-on: http://review.coreboot.org/7828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In last clean-up commit, the detailed_blocks parsing has been merged to one
for-loop and combining return values in each iteration instead of assignment.
As a result, has_valid_detailed_blocks should now be initialized as 1.
BRANCH=none
BUG=none
TEST=Tested AUO 1080p and InnoLux 720p panels on nyan_big
Original-Change-Id: Ie4b6e25de63c0e216ae5de9bde20eed1fe3e59a6
Original-Signed-off-by: Vince Hsu <vinceh@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/195803
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 21ac533d17c892c39532c263cc6ec15e4507ed3e)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I23111efb902c7e5994a4dbdfe77242c13ef5a70e
Reviewed-on: http://review.coreboot.org/7835
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To support parsing multiple EDID blobs, the static "decode results" flags should
be changed to auto variables inside decode_edid.
This is done by packaging static variables into a structure inside decode_edid.
We also revised some functions (manufacturer_name, do_checksum) to avoid
accessing global variables directly. Extension (and detail block) parsing may
need to access and return all parsed context so we pass the whole structure to
it.
BRANCH=none
BUG=none
TEST=emerge-nyan coreboot chromeos-bootimage
# See EDID parsed correctly on Nyan.
Original-Change-Id: Ieca93d446bacf655c145dffdfa6cc6f5dc87ac26
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/195372
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ed45909df24c05a0cb8b2ff662fdd2d7a39012f0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I17cdfa770181a6eaac9d1050d340c8e052572b4a
Reviewed-on: http://review.coreboot.org/7834
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Use the RTC driver interface to find the timestamp for events instead of
reading the CMOS based RTC directly on x86 or punting on ARM. This makes
timestamps available on both architectures, assuming an RTC driver is
available.
BUG=None
TEST=Built and booted on nyan_big and link and verified that the timestamps
in the event log were accurate.
BRANCH=nyan
Original-Change-Id: Id45da53bc7ddfac8dd0978e7f2a3b8bc2c7ea753
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/197798
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 493b05e06dd461532c9366fb09025efb3568a975)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8481adde86d836b5f0b019c815bada6d232a4186
Reviewed-on: http://review.coreboot.org/7833
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This attempts to isolate/fix some x86-isms:
- Translate flash offset to memory-mapped address only on x86.
- Guard ACPI-dependent line of code
- Use a Kconfig variable for SPI bus when probing the flash rather
than assuming the bus is always on bus 0.
- Zero-out timestamp on non-x86 until we have a better abstraction.
(note: this is based off of some of Gabe's earlier work)
BUG=none
BRANCH=none
TEST=needs testing
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I887576d8bcabe374d8684aa5588f738b36170ef7
Original-Reviewed-on: https://chromium-review.googlesource.com/191203
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1fc7a75f8c072098e017104788418aeed0705e93)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida4b211cf21ecdde9745d4dbef6a63ffb9fbba8d
Reviewed-on: http://review.coreboot.org/7832
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This severs a dependency the eventlog code has on initializing
chipset/SoC SPI controller. Currently elog_init() calls spi_init()
as a catch-all. This worked for x86 since the SPI controller is only
used for one thing on existing platforms. As we add eventlogging
support to non-x86 platforms we need to consider the more generalized
case where the assumptions about how SPI works on x86 are no longer
valid.
BUG=none
BRANCH=none
Signed-off-by: David Hendricks <dhendrix@chromium.org>
TEST=built and booted on Link, Beltino and Rambi. See below for
"mosys eventlog list" output on Link showing boot and suspend/resume
events (including lid close/open) added successfully.
localhost ~ # mosys eventlog list
0 | 2014-04-14 13:52:44 | Log area cleared | 4096
1 | 2014-04-14 13:52:44 | System boot | 50
2 | 2014-04-14 13:52:44 | EC Event | Power Button
3 | 2014-04-14 13:52:44 | SUS Power Fail
4 | 2014-04-14 13:52:44 | System Reset
5 | 2014-04-14 13:52:44 | ACPI Wake | S5
6 | 2014-04-14 13:53:25 | ACPI Enter | S3
7 | 2014-04-14 13:53:35 | ACPI Wake | S3
8 | 2014-04-14 13:53:35 | Wake Source | RTC Alarm | 0
9 | 2014-04-14 13:53:49 | ACPI Enter | S3
10 | 2014-04-14 13:54:00 | EC Event | Lid Open
11 | 2014-04-14 13:54:00 | ACPI Wake | S3
12 | 2014-04-14 13:54:00 | Wake Source | GPIO | 15
Original-Change-Id: I26e25c0a856f7b8db5ab6b8e7e1acae291d2eadc
Original-Reviewed-on: https://chromium-review.googlesource.com/194526
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 2971d20b6ebdd9803b05ccbbaeefe1bde1a21af4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia5f2913fd8e4fee6e741e6d1e39d32bb86525cb3
Reviewed-on: http://review.coreboot.org/7831
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The current algo sets dc shift clock divider to 5 and PLLD DIVP
to 0, this is causing VCO out of the characterized range for some
panels.
This CL changes the dc shift clock divider to 1 and calculates a
proper DIVP to have the VCO inside the characterized range, i.e.,
500MHz ~ 1000MHz.
BRANCH=none
BUG=none
TEST=Verify on below panels the pixel clock frequencies are correct.
1. AUO B133XTN01.3 (69.5 MHz)
pixelclk(MHz), pll_d(MHz), m/n/p
without: 69.5 695 12/695/0
with: 69.5 139 3/139/2
2. AUO B140HTT01.0 (141 MHz)
pixelclk(MHz), pll_d(MHz), m/n/p
without: VCO (1410000000) out of range. Cannot support.
with: 141 282 2/94/1
3. LG LP140WH8 (76.32 MHz)
pixelclk(MHz), pll_d(MHz), m/n/p
without: 76.32 763.2 5/381/0
with: 76.3125 152.625 8/407/2
4. N116BGE-EA2 (76.42 MHz)
pixelclk(MHz), pll_d(MHz), m/n/p
without: 76.40 764 3/191/0
with: 76.375 152.75 12/611/2
Original-Change-Id: Id4b3a4865acde37a97d7346ec88406f5237304eb
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/195534
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 1b56566786aa86c14f691fa3858b878f27b6b4de)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia9de93420e60323f143a42db842febdd3706fe44
Reviewed-on: http://review.coreboot.org/7773
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Similar to the W25Q64DW, the W25Q32DW has basically the same
attributes as the earlier W25Q32 parts but with a different
value in the MSB of the ID.
BUG=none
BRANCH=none
TEST=tested on nyan, now SPI flash commands actually work.
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I697768a443c98515d893f9cf8f8b4258ae0f159d
Original-Reviewed-on: https://chromium-review.googlesource.com/191205
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 35f03f4f4f21c470d172ce7cce257517b959346d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I73606737835e4f8ea00d2c331ca37957e4abd953
Reviewed-on: http://review.coreboot.org/7755
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The old print simply said "Got idcode". This makes it actually
display what it got.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I8f1c8fde6e4ac00b12e74f925b7bcff83d1f69f3
Original-Reviewed-on: https://chromium-review.googlesource.com/191204
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 5f13789be77d038d3c1602037afe29a0351f72ee)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I65d0d51c17b3bda62351532aac1756b630433ea3
Reviewed-on: http://review.coreboot.org/7754
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
hynix-2GB-204MHz/hynix-4GB-204MHz are not workable with Samsung RAMCODE.
To replace them by samsung-2GB-204/samsung-4GB-204 for bring up purpose.
BRANCH=none
BUG=chrome-os-partner:27682
TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and
boot to kernel successfully with all the RAMCODE
Original-Change-Id: I7c2a96e84e6988dd739a9621ff93edc01703306a
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/195396
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
(cherry picked from commit dc028c408be58f036fe125abc2e49e2c0cde0aa8)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ieeb0250e42fb48c6089bc8dc95550c9b1694d7f8
Reviewed-on: http://review.coreboot.org/7772
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The pixel clock for some panel (ex: CMN N116BGE-EA2: 76420000) cannot be matched
by our PLLD params finding algorithm, after VCO/CF limitations are applied.
To support these panels, we want to allow "best matched" params.
BRANCH=nyan
BUG=none
TEST=emerge-nyan_big coreboot chromeos-bootimage;
emerge-nyan coreboot chromeos-bootimage;
# Successfully brings up display on Nyan_Big EVT2 and Nyan Norrin.
Original-Change-Id: If8143c2062abd2f843c07698ea55cab47bf1e41a
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/195327
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 8aa66e659e3c60296f05e59b4343496a850ea019)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I623db44de35fecee5539e4d72f93f28b5fa0b59c
Reviewed-on: http://review.coreboot.org/7771
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
We found that without enabling DC in tegra_dc_sor_enable_dc, kernel would have
problem showing the text console before graphics interface is initialized, for
example "chromeos factory install shim (text only)" or the "splash screen".
BRANCH=none
BUG=chrome-os-partner:28082
TEST=emerge-nyan coreboot chromeos-bootimage
Boots factory install shim and see text console.
Original-Change-Id: I6fce963ceddd125dd52789d2ec843cc2ee05f1f5
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/195388
(cherry picked from commit 375a86be9b23650cd96e46b07c7a0b5c10970797)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib75e3ffac9b216c7486845cb8459dd8952d51fe6
Reviewed-on: http://review.coreboot.org/7770
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Dump all SOR registers for debug purpose. By default, this function
is not being built in.
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I7f44709b8572b9eac33c2193b92a65bf2b22aa76
Original-Reviewed-on: https://chromium-review.googlesource.com/194738
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Commit-Queue: Tom Warren <twarren@nvidia.com>
Original-Tested-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit d08c0f7c5e8ac094987b09fae96e8133ed9c08c5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I1341bbbd0ea6277e5a1b286d6f088f2961070416
Reviewed-on: http://review.coreboot.org/7769
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch adds some documentation to the additional PLL divisor
constraints on the intermediary VCO and CF values that we just found out
about. PLLC divisors for some oscillators had to be adjusted
accordingly.
It also adds a new clock_get_pll_input_khz() function to replace
clock_get_osc_khz() in cases where you want to factor in the built-in
predivider for 38.4 and 48 MHz oscillators.
BUG=None
TEST=Still boots.
Original-Change-Id: Ib6e026dbab9fcc50d6d81a884774ad07c7b0dbc3
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/194474
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 3f1f565baf100edcd486055e4317c675c882396f)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I091f42bf952a4b58ef2c30586baa5bf7496fa599
Reviewed-on: http://review.coreboot.org/7768
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This register needs to be set properly during display init.
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display works as well. However, the mode setting
needs to be based on either devicetree or EDID.
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I93c69d8042a3f3c19f4e24801423b73246e37031
Original-Reviewed-on: https://chromium-review.googlesource.com/194739
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ee9a3c472c5621edebefcc8882582c6fc01255e2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie642a008eaf6c4ab68ede1dde98ff4268f51fc9c
Reviewed-on: http://review.coreboot.org/7767
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display still does't work until all related
patches are built in. (CL:194739)
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: Ic5d977f695be127693f1ecc3ba52d478f524d20f
Original-Reviewed-on: https://chromium-review.googlesource.com/194737
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit ef3208d8ff3c3dcfaeda9c0146bf1ae920682dea)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ide1cd28ecc0ae1cd4d8603a52975592daee4bce8
Reviewed-on: http://review.coreboot.org/7766
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Correct SOR attaching sequence.
https://chromium-review.googlesource.com/190300
BRANCH=none
BUG=chrome-os-partner:27413
TEST=build nyan and nyan_big. nyan display works fine.
nyan_big display still doesn't work until all related
patches are built in. (CL:194737 and CL:194739)
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Change-Id: I8aaf65db90e5e45bd9097c9d38b231bd7d41d997
Original-Reviewed-on: https://chromium-review.googlesource.com/194403
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit fea9d288b98dcc6fc32dc93212fa7c4185603646)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6646816809e29c63de65caa7e7146cd3d02902cf
Reviewed-on: http://review.coreboot.org/7765
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Tegra124 family products may want to use many different display panels with
various timing settings. To support them, we should initialize display panel by
EDID instead of hard-coded values.
BUG=none
TEST=emerge-nyan coreboot chromeos-bootimage
BRANCH=none
Original-Change-Id: Ib125a7f9cb1e6c8cf2d79e0baab525acfd1b7a6e
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/192730
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 43ecd473419aa0fbdd22487416b0b6cfea6a20d1)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6af47db113035e9440e663a769318776c7b6b70b
Reviewed-on: http://review.coreboot.org/7764
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
First, we don't want floats in our code base.
Second, the calculation of the aspect ratio was wacky,
using a value guaranteed to be 0 for aspect ratio calculation.
While at it, define the aspect_* fields to be in tenths, to
provide some additional resolution. They were like that already
but we now also commit to that.
Change-Id: I5511adf4bf76cdd6a69240491372f220ef1aa687
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: http://review.coreboot.org/7803
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins)
There is no Cache As Ram for these boards, let's get rid of them.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ia70befc59708c360ad02ed7e3a49d3b0f95dc707
Reviewed-on: http://review.coreboot.org/7119
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Drop two SuperIOs that were only used by GX1 systems, and are not used anymore.
* winbond/w83977f
* nsc/pc87351
Change-Id: I8a8eacb0f862b5d08ccfd87f8db503b0ab3c5700
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7118
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There is no Cache As Ram for these boards, let's get rid of them.
Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: http://review.coreboot.org/7117
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There is no need to call cbmemc_reinit() exclusively in romstage,
that is done as part of the CAR migration of cbmem_recovery().
CBMEM console for romstage remains disabled for boards flagged with
BROKEN_CAR_MIGRATE, but with this change it is possible to have it for
ramstage.
Change-Id: I48c4afcd847d0d5f8864d23c0786935341e3f752
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7592
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <gaumless@gmail.com>
Flag the boards with BROKEN_CAR_MIGRATE, as testing for EARLY_CBMEM_INIT
is not enough to disable CBMEM console for romstage on these platforms.
To have CBMEM early in ramstage, define get_top_of_ram() on sandy/ivy.
Change-Id: Ieefc12099a0e043eb1a7e14bdc7c6e3d209b3d8f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7468
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <gaumless@gmail.com>
As is the case in commit:
3312ed7 amd/agesa/f1?/Lib/amdlib.c: Integer overflow in loop construct
The semantics of this loop relies on an integer overflow in Index >=0
that implies a return value of (UINT8)-1 which around wraps to 0xFF, or
VOLT_UNSUPPORTED.
Also fix an infinite loop.
Change-Id: Iced3eff3ae7b8935db3bdd6147372cf3b540883c
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7676
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
It appears the decimal value was used instead of the hexadecimal value.
Apply commit 59919ad1 (southbridge/amd/agesa/hudson: Correct incorrect
#define) to AMD Avalon, whose `pci_devs.h` was copied from AMD Hudson.
The incorrect define was introduced in commit 2093c4f7 (AMD/agesa: Add
functions for AMD PCI IRQ routing).
Change-Id: I7ccc060e8fa032080375259c3b11d39e2deb8e9e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/7800
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
The new API is in use in depthcharge and is based around the "i2c_transfer"
function instead of i2c_read and i2c_write. The new function takes an array of
i2c_seg structures which represent each portion of the transfer after a start
bit and before the stop bit. If there's more than one segment, they're
seperated by repeated starts.
Some wrapper functions have also been added which make certain common
operations easy. These include reading or writing a byte from a register or
reading or writing a blob of raw data. The i2c device drivers generally use
these wrappers but can call the i2c_transfer function directly if the need
something different.
The tegra i2c driver was very similar to the one in depthcharge and was simple
to convert. The Exynos 5250 and 5420 drivers were ported from depthcharge and
replace the ones in coreboot. The Exynos 5420 driver was ported from the high
speed portion of the one in coreboot and was straightforward to port back. The
low speed portion and the Exynos 5250 drivers had been transplanted from U-Boot
and were replaced with the depthcharge implementation.
BUG=None
TEST=Built and booted on nyan with and without EFS. Built and booted on, pit
and daisy.
BRANCH=None
Original-Change-Id: I1e98c3fa2560be25444ab3d0394bb214b9d56e93
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193561
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Tested-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 00c423fb2c06c69d580ee3ec0a3892ebf164a5fe)
This cherry-pick required additional changes to the following:
src/cpu/allwinner/a10/twi.c
src/drivers/xpowers/axp209/axp209.c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I691959c66308eeeec219b1bec463b8b365a246d7
Reviewed-on: http://review.coreboot.org/7751
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BOOT_MEDIA_SPI_BUS is a Kconfig variable used on some ARM-based
platforms to set up CBFS media. It turns out it can also be helpful
for setting up the eventlog which is intended to reside on the same
SPI flash as CBFS. Setting it for x86 will allow us to remove an
assumption about which SPI bus is used for this flash device.
Long term this can go away as we come up with a better abstraction
for the eventlog's backing store. This is only intended to help us
get from here to there.
BUG=none
BRANCH=none
TEST=built and booted on Link
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I1d84dc28592fbece33a70167be59e83bca9cd7bc
Original-Reviewed-on: https://chromium-review.googlesource.com/191202
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 200aa7c5b1b1f4c74412893cf7231a12e2702463)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: If988bcff5244ec6a82580203471b25fac49c45ef
Reviewed-on: http://review.coreboot.org/7752
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This replaces a hard-coded bus number of 0 with a Kconfig variable,
CONFIG_BOOT_MEDIA_SPI_BUS. This removes an assumption made for x86
where this value is always 0 and makes it easy to add support for
other platforms where the bus number for the backing SPI flash is
more arbitrary.
BUG=none
BRANCH=none
TEST=tested on Nyan (bus=4) and Link (bus=0)
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I1e878a1628af7f4ccc2f39a70b2190192767e536
Original-Reviewed-on: https://chromium-review.googlesource.com/194854
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 371c6c14d8d4b98004eebce7049a88a219682bc4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ie105b4654e028098f2137c96e4309b8d85f096df
Reviewed-on: http://review.coreboot.org/7753
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This symbol is set using a config variable which can be set to something
appropriate by the SOC. If it isn't, the symbol is set to 0 which should be
caught by checks in the cbmem console itself.
BUG=None
TEST=Built for nyan with a cbmem buffer location set. Built for peach_pit
without a location set.
BRANCH=None
Original-Change-Id: I92cd65bb6767a67637faf1dd3cdbe03e433724a9
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193165
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4f38c073bfe469a753e168391787fdd7bc5c34d9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I979037fe8cda885cc516d79f3151ca1fc77adca3
Reviewed-on: http://review.coreboot.org/7746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Turns out that when you clear 28 bits starting with bit 3, you leave bit
31 standing. Ooops...
This shouldn't really matter since that bit is reserved/SBZ in CLIDR
anyway, but it's still nice to fix it. This whole thing should really be
an AND for clarity anyway in my opinion.
Bug found in upstream NetBSD (who would've thought...).
BUG=None
TEST=Still boots.
Change-Id: Ic826e82d58fd1ce984971afea3dfa9296f746d9f
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/193300
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d270c0ec18b74b272451c456cbf07e99d95896cb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/7745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In order to build rmodules for armv7 boards, the default
compiler options need to be set so the assembler sources
can correclty compile. For now assume rmodules for arm
devices use the ramstage compiler options.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vboot as rmodule for nyan.
Original-Change-Id: I8d12a2a57944b187cbdff2f22176de5b4de87a54
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190926
(cherry picked from commit cd091ae8ced30e6e2543f36bdb5c14518e7879c3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I24706f7d72a53f71abd2770f0d12de8c6ed31f63
Reviewed-on: http://review.coreboot.org/7744
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
According to DP version 1.2a, The MOT (Middle-of-Transaction) bit
must be set when the I2C transaction does not stop with the current
AUX transaction.
Thus the correct steps for an I2C read shall be:
1. I2C command write with MOT set to 1
2. I2C command read to the same address with MOT set to 0
BUG=chrome-os-partner:27679
TEST=EDID data read from LP140WH8 panel is correct while it's a
repeated pattern of the first 16 bytes without this CL
BRANCH=none
Original-Change-Id: I0526beffb8852fbbe0eb5bb80e370261617a59b8
Original-Signed-off-by: Ken Chang <kenc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194915
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 466ab0e00744f79ae3720474140d95e5f0828de9)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ic8ad38b4b08989dd7178d59151e1e276b8a58439
Reviewed-on: http://review.coreboot.org/7763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
PLLD, the clock for display, was previously hard-coded to 306MHz. To support
more different panels, we should calcualte PLLD by panel pixel clock
configuration.
Note existing pixel clock configurations for nyan* boards won't work (they used
to rely on hard-coded approximated values) so the device trees are also
modified.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan_big coreboot chromeos-bootimage
See panel correctly initialized and got DEV screen.
Original-Change-Id: I8d592f0cc044e7c4e4803c45955642e791210ad3
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/193565
(cherry picked from commit 4f9b793633ebb2d104b0544e3b72fa0d105951c4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ib2cabbad60af010e872505e888eab485ba8c2916
Reviewed-on: http://review.coreboot.org/7762
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds a missing dma_release() at the end of DMA transfers. It
probably doesn't matter since we don't do many DMA transfers, though
I wouldn't want to hit some corner case with EFS and eventlog.
BUG=none
BRANCH=none
TEST=tested on nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I79b30455babe75a13aac827caac88bf7053ec9e4
Original-Reviewed-on: https://chromium-review.googlesource.com/194479
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit dc7dc1d25bd88873b4c1198a6f3723d27c914ddc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I8c5da4e104328fd8bce71942e6eda458a37bfe06
Reviewed-on: http://review.coreboot.org/7761
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It worked earlier since the APB and AHB bus widths occupy the same bits
in their respective registers.
BUG=none
BRANCH=none
TEST=tested on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7
Original-Reviewed-on: https://chromium-review.googlesource.com/194478
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e
Reviewed-on: http://review.coreboot.org/7760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GPIO_PU4/PH1 and _PU5/PH2 were set to use the same PWM1/2 SFIO.
Even though no problems were caused by this, correct it here
so we get a conflict-free pinmux map.
BUG=chrome-os-partner:27091
BRANCH=none
TEST=Built and booted on Nyan, ran TegraShell "pinmux check"
and saw no conflicts.
Original-Change-Id: Ib16341aa0c92b9a078d7f3254d4151e9592f40b0
Original-Signed-off-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/194582
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit e06a5a62d381f803dd6574787795a51ce1f1fe74)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I055359dc80c0c878ba5f5faac17884a5506a826c
Reviewed-on: http://review.coreboot.org/7759
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
href_to_sync and vref_to_sync are chip specific settings. Currently
they are set to 1/2 of hfront_porch and vfront_porch respectively.
However, to support EDID (CL192730), per David Ung, the safe
values for both are 1 (the same settings as in kernel).
BUG=none
BRANCH=none
TEST=built and booted on nyan.
Original-Change-Id: Ifb8898e720a160ba044e2b526de2a4d17bc63672
Original-Signed-off-by: Jimmy Zhang <jimmzhang@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193504
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit a7128a533ba6083ddfeeca3ba0828962cc2c8ab6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6954a5b49c798ebdffb20e3ebc9099cd17591b79
Reviewed-on: http://review.coreboot.org/7758
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change takes about 8K of space away from the cbfs cache and repurposes
it for the cbmem console buffer. This is a little more than twice the space
we currently need for the bootblock and ROM stage to give us some room to grow
and for extra debug output if needed.
BUG=None
TEST=Built and booted on nyan. Checked the cbmem output.
BRANCH=None
Original-Change-Id: I6543bf5efddcf2377528a273f846b8090cd8be55
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193169
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 32e9ea6f9ecaa9b5441c91acab96514222f3af2c)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia9e5cc7a4b561bd89137cdc8b594584b272d9fab
Reviewed-on: http://review.coreboot.org/7757
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Set the appropriate config options and make the appropriate calls
to perform vboot verification. The flashmap offset as well as the TPM
information needs to be properly set. Lastly, call into
vboot_verify_firmware() to perform the vboot verification when it is
enabled.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built vboot verification on nyan.
Original-Change-Id: I6113badd6143008ceb2b80f0ec0832e1addd03d7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/190928
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit 8c6c48c7823738bf9b029a467b077d2ee20d04e5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I2a442b1b0fff55e737df2e96740c05c1726502d5
Reviewed-on: http://review.coreboot.org/7743
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
RAM module for RAMCODE 0010 (K4B4G1646Q) does not work with
hynix-2GB-204MHz configuration. We need to replace it by
hynix-2GB-792MHz. Also updated hynix-2GB-792MHz configuration
from Nyan board folder. This commit is only for bring up stage.
Once finish dram stress test, will update it again.
BRANCH=none
BUG=chrome-os-partner:27682
TEST=emerge-nyan_blaze coreboot builds OK; flash to blaze board and
boot to kernel successfully
Original-Change-Id: Idfc503c944ac6120c92a4cf329f3fbe63b2c2a1c
Original-Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193737
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit 91f21aa0cf9251b825e42d946d8cd41849c57447)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I6293fa638c5b2577e502ba34a3cc6e6d5b7f2fdb
Reviewed-on: http://review.coreboot.org/7742
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There are some unexpected symbol at the end of each line in the
generated .inc file when the config file is in DOS format (CR+LF).
Modify cfg2inc to support DOS format cfg file by removing carriage return symbols from the end of each line.
BUG=chrome-os-partner:27614
TEST=sudo cfg2inc.sh XXX.cfg # make a expected inc file
BRANCH=nyan
Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Change-Id: I68b0f4b3805fcb5a6b633653c95afbafcb880a93
Original-Reviewed-on: https://chromium-review.googlesource.com/192697
Original-Tested-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Neil Chen <neilc@nvidia.com>
(cherry picked from commit 38e90ab0d9110d3ede39c70e27961b833813a7d4)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I30737600fa8ac12a45ad0fbc6086a624993794e7
Reviewed-on: http://review.coreboot.org/7741
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
For some UART hardware registers are 32 bits wide, so we will need
base_port + reg << 2 instead. Prepare for that change and unification of
MMIO between ARM and x86.
Change-Id: I5fa2c2f7ee4872499a01754c1ba872a8addf499c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/7793
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
To set the 8 different BCT as hynix-2GB-204 first. Once the
corresponding BCT release from AE, change it.
BRANCH=none
BUG=None
TEST=emerge-nyan_blaze coreboot builds OK
Signed-off-by: Neil Chen <neilc@nvidia.com>
Original-Change-Id: Ia42a4a5b85c561421ab8ae9aaf21c46a3c0a3513
Original-Reviewed-on: https://chromium-review.googlesource.com/191682
Original-Tested-by: Neil Chen <neilc@nvidia.com>
Original-Reviewed-by: Artiste Hsu <chhsu@nvidia.com>
Original-Reviewed-by: Katie Roberts-Hoffman <katierh@chromium.org>
Original-Commit-Queue: Neil Chen <neilc@nvidia.com>
(cherry picked from commit 27792db4a90ae00e066bb0b88968cf5f187edb1d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia648c8bdbbbc82bbc8508bead6ab24d8d0aa3fb2
Reviewed-on: http://review.coreboot.org/7740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EC doesn't seem to be able to handle its bus running at 4 MHz or higher.
To avoid it not being able to keep up, we reduce the frequency of that bus on
all nyan derivatives to 3 MHz. Because PLLP can't be divided that low, we
switch the clock source to CLKM.
BUG=chrome-os-partner:22849
TEST=Built and booted on nyan.
BRANCH=None
Original-Change-Id: I8f31b41098d64634427b4686f5333012f643fada
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193349
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit c215c50a5bb982b0e671c951e2fe8df06db85db2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia60513d118aed8881927e9d52f170e27655ea8e7
Reviewed-on: http://review.coreboot.org/7739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Consolidate the register setting clrsetbits_le32 call to simplify the macros.
Add a check for bits of the divisor being dropped. The clock source registers
will throw away bits that aren't supported, so we can check for divisor
overflow by checking for dropped bits.
BUG=None
TEST=Purposefully tried to set a clock to a rate which overflows its divisor.
Verified that the check triggered. Booted on nyan. Verified the TPM i2c bus
frequency was still correct.
BRANCH=None
Original-Change-Id: I3b1b6ba57f6b7729f303d15a16b685a48751d41f
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193348
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 9cd79dd974d8a3c31398f8fbd62750b194867891)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id4d8ecfeff52737cdd68999028b37cbdedb0d116
Reviewed-on: http://review.coreboot.org/7738
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To ensure that the command1 write which sets the "go" bit completes before
other reads to the device. Otherwise, there's a race condition where those
register values might still have their values from the last transfer. With
different SPI clock frequencies, that could lead to spi_delay being told there
were negative bytes still to send. Its expected delay would wrap to a negative
value, that was passed to udelay, and the system would sit there for 4 seconds
not doing anything.
BUG=None
TEST=Built and booted on nyan. Set the SPI bus frequency to a value which was
causing the 4+ second delay and verified that it no longer happened.
BRANCH=None
Original-Change-Id: I8b4090efc69f34d0413e3f63c59c1825dd151cec
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193347
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit d7ea9febdf2c5942f81607ee6ded786c9a8954bb)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I095bfc745eda37b8e666475ceb41684152f3709a
Reviewed-on: http://review.coreboot.org/7737
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes two problems with the clock configuration on tegra124. First, the
macro which set up the i2c clocks tried to account for the fact that the i2c
divisor's lsb represents 1.0 where it normally represents 0.5 by multiplying
the target frequency by 2. That doesn't work, unfortunately, because the
divisor is actually n + 1, and what n + 1 means depends on where the one's
place is in the divisor.
Also, when calculating the divisor, the standard C division operator uses
truncation to deal any remainder which tends to make the divisor smaller. That
has the effect of making the output frequency higher than what was requested.
Since it's usually safer to undershoot a frequency than overshoot it, this
change makes those divisions round up instead.
Finally, the hand tuned temporary UART clock configuration was adjusted so
that it still ends up with the same divisor. Without that, very early output
from the bootblock is garbled, specifically the coreboot welcome banner,
build timestamp, etc.
BUG=chrome-os-partner:27220
TEST=Built and booted on nyan. Used a logic analyzer to verify that the TPM
i2c bus ran at 400KHz instead of 660KHz, and that the divisor was the expected
value. Measured boot time with and without EFS and verified that there was no
change. Spot checked the output for errors and verified that none of the
bootblock output was garbled.
BRANCH=None
Had to add the stdlib.h from 89ed6c that hadn't been merged correctly.
Original-Change-Id: I7e948c361ed4bf58c608627d32f2e3424faea1fb
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/193362
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 164f7010a47d3bbdbc8bb572106140ae186f3807)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I317b66eda929c0e5a5832adca267b8b54c6aae34
Reviewed-on: http://review.coreboot.org/7736
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
To read EDID, we need to access I2C via DP AUX channel.
BRANCH=none
BUG=chrome-os-partner:25933
TEST=emerge-nyan coreboot chromeos-bootimage
Original-Change-Id: I2666b5d46843485b79265a537f19bd8eab5e1a26
Original-Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/188858
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 8f8e98ff5038b57f89332aee75573095c3933dd2)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I5b1b6ab2940c8265483059fd94a2c4db2a41144a
Reviewed-on: http://review.coreboot.org/7735
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If EFS is enabled and vboot didn't tell us it's going to use the display, we
can skip initializing it and save some boot time.
BUG=chrome-os-partner:27094
TEST=Built and booted on nyan without EFS in recovery mode and normal mode.
Built and booted on nyan with EFS in recovery mode and normal mode. Verified
that in normal mode with EFS the display initialization was skipped and boot
time was essentially the same as when display initialization was simply
commented out.
BRANCH=None
Original-Change-Id: I1e2842b57a38061f40514407c8fab1e38b75be80
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192544
Original-Reviewed-by: Tom Warren <twarren@nvidia.com>
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit a672d18c3570e6991a1c1c0089697112a4cd71d0)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I95e8bd7a447876174305f755cc632365ed6f5a30
Reviewed-on: http://review.coreboot.org/7734
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It appears the decimal value was used instead of the hex value.
Change-Id: I04acde9e5b2a9e08ed01b0564c3d561b0385a392
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/7799
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
For some of the boards using AMD processors, the Agesa Makefile.inc
is processed twice, causing the list of obj files passed to the ar
command to be added twice. This does not break the build, but does
make the ar command line unnecessarily long.
Change-Id: I02a7e6fc617e337ca2e2dceeff3d4db9995bfe16
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7787
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
powernow_acpi.c array TDP has 20 entries, yet the loop that reads it
processes 21 entries. This causes a gcc 4.9.2 build failure. Limit
processing to 20 entries.
Change-Id: Ice173b276293184386cd8943a3213f3154f86458
Signed-off-by: Scott Duplichan <scott@notabs.org>
Reviewed-on: http://review.coreboot.org/7791
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Remove '__attribute__((optimize("Os")))' as it is unlikely to be
necessary as it is not used in other families that have the same
code and only hides deeper issues.
Change-Id: Ica890812ebc2fb659b9c3e46b40cf3f6534b3cf2
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/7689
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
The updated KaveriPI binary, upgrading to v1.1.0.7, requires changes
to define the PSP device (PCI 0:08.0) and the IOMMU device (PCI 0:00.2).
In the new AGESA binary, the IOMMU device is enabled and must be
disabled in devicetree.cb and agesawrapper_amdinitenv() to maintain
the same level of functionality.
Change-Id: I3f47e0bd5a75729ec1e4b7b11885d0622c474342
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/7727
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Clang complains:
"implicit truncation from 'int' to bitfield changes value from -1 to 15"
-1 is define in 'c11std 6.3.1.3p2' as:
[Signed and unsigned integers] Otherwise, if the new type is unsigned,
the value is converted by repeatedly adding or subtracting one
more than the maximum value that can be represented in the new type
until the value is in the range of the new type.60)
FOOTNOTE.60 The rules describe arithmetic on the mathem...
This is "0xFF" on Mullins and "0xF" in this case. Clang seems to
complain about this two's complement in a bitfield as being truncated.
As the bitfield is 4 bits wide, (a maximum of 15 decimal), we set the
field as '0x0F'. Ideally this field /should/ be set to 'UINT8_MAX' however
we still have silly truncation warnings.
Change-Id: Ib7476d453ffd932bb911e638117cf9f56f71f269
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7719
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Clang complains that a signed shift result (0x210000000)
requires 35 bits to represent, but 'int' only has 32 bits.
However, we write the high bits separately and so this is
a spurious warning.
Change-Id: I3e1c57334077feb50004d7b39abff4bd84ca095b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/7673
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
They were only used internal to the SPI drivers and, according to the comment
next to their prototypes, were for when the SPI controller doesn't control the
chip select line directly and needs some help.
BUG=None
TEST=Built for link, falco, and rambi. Built and booted on peach_pit and nyan.
BRANCH=None
Original-Change-Id: If4622819a4437490797d305786e2436e2e70c42b
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192048
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 1e2deecd9d8c6fd690c54f24e902cc7d2bab0521)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ida08cbc2be5ad09b929ca16e483c36c49ac12627
Reviewed-on: http://review.coreboot.org/7708
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
spi_set_speed was never implemented, and spi_cs_is_valid was only implemented
as a stub and never called.
BUG=None
TEST=Built for rambi, falco, and peach_pit.
BRANCH=None
Original-Change-Id: If30c2339f5e0360a5099eb540fab73fb23582905
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/192045
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 98c1f6014c512e75e989df36b48622a7b56d0582)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iebdb2704ee81aee432c83ab182246d31ef52a6b6
Reviewed-on: http://review.coreboot.org/7707
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
The SPI drivers for tegra and exynos5420 have code in them which waits for a
frame header and leaves filler data out. The SPI driver shouldn't have support
for frame headers directly. If a device uses them, it should support them
itself. That makes the SPI drivers simpler and easier to write.
When moving the frame handling logic into the EC support code, EC communication
continued to work on tegra but no longer worked on exynos5420. That suggested
the SPI driver on the 5420 wasn't working correctly, so I replaced that with
the implementation in depthcharge. Unfortunately that implementation doesn't
support waiting for a frame header for the EC, so these changes are combined
into one.
BUG=None
TEST=Built and booted on pit. Built and booted on nyan. In both cases,
verified that there were no error messages from the SPI drivers or the EC
code.
BRANCH=None
Original-Change-Id: I62a68820c632f154acece94f54276ddcd1442c09
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/191192
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit 4fcfed280ad70f14a013d5353aa0bee0af540630)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Id8824523abc7afcbc214845901628833e135d142
Reviewed-on: http://review.coreboot.org/7706
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <gaumless@gmail.com>
Depending on the platform the underlying regions vboot requires
may not be accessible through a memory-mapped interface. Allow
for non-memory-mapped regions by providing a region request
abstraction. There is then only a few touch points in the code to
provide compile-time decision making no how to obtain a region.
For the vblocks a temporary area is allocated from cbmem. They
are then read from the SPI into the temporarily buffer.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted a rambi with vboot verification.
Original-Change-Id: I828a7c36387a8eb573c5a0dd020fe9abad03d902
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/190924
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
(cherry picked from commit aee0280bbfe110eae88aa297b433c1038c6fe8a3)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Ia020d1eebad753da950342656cd11b84e9a85376
Reviewed-on: http://review.coreboot.org/7709
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The arm architecture currently exports cache_sync_instructions()
in <arch/cache.h>. In order for rmodule loading to work on arm
architectures the cache_sync_instructions() needs to be called to
sequence the instruction cache. To avoid sprinkling #ifdefs around
just add an empty cache_sync_instructions() definition.
BUG=chrome-os-partner:27094
BRANCH=None
TEST=Built and booted nyan and rambi.
Original-Change-Id: I1a969757fffe0ca92754a0d953ba3630810556e3
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/191551
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit fda20947b928ee761d5ed15e414636af419970a6)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I3e8ca12e1d82ccedf1ff9851ae3c5c80cda2dd5f
Reviewed-on: http://review.coreboot.org/7710
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To find the coreboot tables, the payload has historically searched for their
signature in a predefined region of memory. This is a little clumsy on x86,
but it works because you can assume certain regions are RAM. Also, there are
areas which are set aside for the firmware by convention. On x86 there's a
forwarding entry which goes in one of those fairly small conventional areas
and which points to the CBMEM area at the end of memory.
On ARM there aren't areas like that, so we've left out the forwarding entry and
gone directly to CBMEM. RAM may not start at the beginning of the address space
or go to its end, and that means there isn't really anywhere fixed you can put
the coreboot tables. That's meant that libpayload has to be configured on a
per board basis to know where to look for CBMEM.
Now that we have boards that don't have fixed amounts of memory, the location
of the end of RAM isn't fixed even on a per board level which means even that
workaround will no longer cut it.
This change makes coreboot pass the location of the coreboot tables to
libpayload using r0, the first argument register. That means we'll be able to
find them no matter where CBMEM is, and we can get rid of the per board search
ranges.
We can extend this mechanism to x86 as well, but there may be more
complications and it's less necessary there. It would be a good thing to do
eventually though.
BUG=None
TEST=Built and booted on nyan. Changed the size of memory and saw that the
payload could still find the coreboot tables where before it couldn't. Built
for pit, snow, and big.
BRANCH=None
Original-Change-Id: I7218afd999da1662b0db8172fd8125670ceac471
Original-Signed-off-by: Gabe Black <gabeblack@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/185572
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Commit-Queue: Gabe Black <gabeblack@chromium.org>
Original-Tested-by: Gabe Black <gabeblack@chromium.org>
(cherry picked from commit ca88f39c21158b59abe3001f986207a292359cf5)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: Iab14e9502b6ce7a55f0a72e190fa582f89f11a1e
Reviewed-on: http://review.coreboot.org/7655
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Alexandru Gagniuc