so it's possible to use the LCD panel connector. Values are hard coded instead
of read from CMOS but it's a start.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.
Fix intel/d945gclf build, which was missing some ACPI component.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
smart iasl will segfault.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5038 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://www.roda-computer.com/en/products/notebooks/rocky-iii-rk886ex.html
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5031 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and guard SMI specific parts of the ACPI code.
(trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* drop debug.c files from 945 mainboards (and share it in the northbridge code)
* adapt the mainboard and auto.c files for above changes.
Rather trivial
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of the equivalent copy in src/cpu/emulation/qemu-x86/northbridge.c.
Also, delete the copy.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5006 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- via/epia-cn is a romcc board, not a CAR board. (Thanks Kevin, for the report)
- Make emulation/qemu-x86, dell/s1850, via/epia-cn use Makefile.romccboard.inc
- New flag: BIG_BOOTBLOCK, which is always the inverse of tinybootblock
Suitable for Makefile.inc rules (foo-$(CONFIG_BIG_BOOTBLOCK) += ...)
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5005 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch also aligns the configuration of a couple of
boards more closely to what newconfig does.
Also, the romstrap inc/lds files are declared in the
Makefiles of the southbridges they belong to, instead of
some global file.
AMD CPUs have their own timer functions, so disable UDELAY_IO
for them and set HAVE_INIT_TIMER as appropriate, same for
emulation/qemu-x86.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for tinybootblock
- move asus/m2v-mx_se to tinybootblock
- Add romstrap for via southbridge to tinybootblock-bootblock
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Don't implicitly add __PRE_RAM__ in romcc.
Fixes intel/xe7501devkit
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4998 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(defaults to UDELAY_IO again, like newconfig)
- Use UDELAY_TSC on Via C7 [kconfig]
- Support Tinybootblock on Intel CPUs
- set XIP location correctly for Tinybootblock on Intel
- provide correct XIP location in Tinybootblock configuration
- Make kontron/986lcd-m use Tinybootblock
- Some kconfig fixes to kontron/986lcd-m [kconfig]
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4997 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Set __PRE_RAM__ define per default
- Properly handle ignored (#ifdef'd out) #include lines
amd/serengeti_cheetah_fam10:
- write ACPI files to $(obj) instead of the top dir (alias $(CURDIR))
tinybootblock:
- provide a way to define code that should be added to the bootblock,
to map the entire ROM for use by CBFS
amd/model_fxx, amd/model_10xxx:
- add CONFIG_SSE
walkcbfs.S:
- eliminate the use of two registers, to make space for romcc to wiggle
amd/serengeti_cheetah_fam10:
- use the enable_rom framework. not entirely functional yet
Boot-tested on emulation/qemu-x86
Build-tested on amd/serengeti_cheetah_fam10
amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4990 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Introduce the tiny bootblock infrastructure and use it on QEmu.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fully). Also fix the kconfig build for HAVE_ACPI_RESUME.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4985 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
which is normally set to 0x10 (the current default) and set to 0x80 (the current alternative)
where necessary (if romstraps get in the way).
For Kconfig, the special case is set per southbridge (as these define the necessity for this
workaround), for newconfig it's added to each single board.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4962 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Usually, this means adding values to Kconfig, but in a few cases, adding values
to newconfig, too (which doesn't hurt).
Also really hook up tyan/s2850 and tyan/s2875 to kconfig, and have them still
build.
Trivial and stupid kconfig changes, just lots of them.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I forgot to svn add the speaker.c and speaker.h.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change EARLY_STAGE into __PRE_RAM__.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove all remaining warnings from qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Libra Li <libra.li@technexion.com>
Added object reference to Config.lb, too and
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
now handled more generically using CBFS.
Simplify the option ROM code in device/pci_rom.c, since there are only two ways
to get a ROM address now (CBFS and the device) and add an exception for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."
There are probably some places where both are tested, but only one is needed.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Of course, the user can still override those defaults, if needed.
Add defaults for VIA pc2500e, Kontron 986LCD-M/mITX, MSI MS-6178.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ram init fails, as the i945 driver currently only supports the mobile version
of the chipset..
Not sure how much sense it makes to check this in, but since it's a nice and
cheap board, maybe someone wants to work on this.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4879 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fixes booting for Hugh.
Various white space fixes as well.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4870 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Make more boards use both of them.
Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VIDEO_MB is a variable that defines how many MB of RAM will be used
for onboard graphics frame buffer. It's northbridge-dependent which
values for CONFIG_MB are valid (but not board-dependent).
This patch adds choices for menuconfig to select the VIDEO_MB value for:
- Intel 82810
- Intel 82830
- VIA CN400
- VIA CN700
Note: CN400 and CN700 are based on the CX700 datasheet, not sure if they're
correct. If somebody has CN400 and CN700 datasheets, please verify.
We drop all per-board VIDEO_MB variables in per-board Kconfig files as
there's a northbridge-specific option/default now (plus the user can override
the value if needed in menuconfig).
As CONFIG_MB is chipset-specific but not board-specific (and never was), filter
it in util/compareboard/compareboard, we don't need to match those values.
Finally, put "CPU", "Northbridge", "Southbridge", "Super I/O", and
"Devices" sections into the "Chipset" menu, where NB-specific
options will appear if you select a board using a certain NB,
SB-specific options would appear in the "Southbridge" section etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4866 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- run ACPI code through preprocessor so we get the same values
as the C code
- fix PCIe x16 slot
- fix ICH7 Azalia/HDA driver
- SMI/GNVS update security fix (only allow struct pointer update once)
- ACPI updates
- IDE driver fixes
- add cmos options for disabling onboard ethernet and controlling system fan
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4861 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
any of the CPUs might be used.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4858 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Do kbuildall then grep not.defined kbuildall.results/*
The interesting ones were GENERATE_* I had to put them in twice to make it work
correctly: once outside the menu setting the defaults, and once inside the menu.
Now they show up when they should, and are always defined
Define HAVE_INIT_TIMER to only exclude the three boards that define it to be 0
in newconfig.
Define MEM_TRAIN_SEQ to be an integer and set it correctly.
Remove CAR_FAM10 and just depend on NORTHBRIDGE_AMD_AMDFAM10
MOVNTI is a performance enhancement, and should default to 0 so it doesn't break
boards that forget to define it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4856 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
RAM is initialized, and no one does it. Trivial.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4830 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ppc port, some ambiguous use of CONFIG_IDE and an unused ide driver (we dropped
the filesystems already to be used with it) (somewhat trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4828 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
does not need any handling in software.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also add pci_rom entries (commented) to targets/hp/e_vectra_p2706t/Config.lb
for the same reason. They have to be uncommented to be used.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Boot-tested by Paweł Stawicki <stawel@gmail.com>.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Paweł Stawicki <stawel@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4820 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
selected in sockets, and they aren't used yet.
Add a couple of variables to src/Kconfig for lack of a better place so that
their selects work.
Add select statements according to newconfig for some variables that were
defined but never selected in mainboard configs.
Fix #if CONFIG_VGA==1 -> #if CONFIG_VGA.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change HAVE_FAN_CTL to be specific to the SuperIO that supports it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4809 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
with the respective board.
Of course, the user can still override the size in menuconfig.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4790 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It was added by rsmith in r2273 on 20060424, when pci_locate_device() in
src/arch/i386/include/arch/romcc_io.h in fact scanned all busses:
- for(; dev <= PCI_DEV(255, 31, 7); dev += PCI_DEV(0,0,1)) {
+ for(; dev <= PCI_DEV(CONFIG_MAX_PCI_BUSES, 31, 7); dev += PCI_DEV(0,0,1)) {
Today this looks like:
for(; dev <= PCI_DEV(255|(((1<<CONFIG_PCI_BUS_SEGN_BITS)-1)<<8), 31, 7); dev += PCI_DEV(0,0,1)) {
and CONFIG_MAX_PCI_BUSES is never used anywhere.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4789 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add/drop Kconfig variables as needed.
In Makefile.inc just include Makefile.romccboard.inc with -mcpu=c3.
Build- and runtime-tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom
to make the final image with vga bios.
The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.
## Index: src/southbridge/amd/rs690/chip.h
## ===================================================================
## --- src/southbridge/amd/rs690/chip.h (revision 4782)
## +++ src/southbridge/amd/rs690/chip.h (working copy)
## @@ -23,7 +23,6 @@
## /* Member variables are defined in Config.lb. */
## struct southbridge_amd_rs690_config
## {
## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */
## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
##
Don't apply above patch about rs690/chip.h before every board has been fixed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to build, but by default all the tables that are available are built.
Make PIRQ table build for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reset the s2891 so the HT speed gets updated.
Remove some PANTA comments.
Add SATA init from non-CAR version.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4771 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU.
Issues with this port:
- hangs early during "Starting Windows" with Windows 7, after loading all the
drivers
- sound is untested and probably not working
- powernow seems to be not working
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild-tested for the boards that are touched.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4760 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add "select HAVE_ACPI_TABLES" for boards which need it.
- Drop sections which set HAVE_ACPI_TABLES to 'n', that's the default.
- Convert sections which set HAVE_ACPI_TABLES to 'y' to the
shorter "select HAVE_ACPI_TABLES".
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4759 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on QEMU.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4757 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
There is an i2c mux out there. We found it using a user level program
that, as usual, began by inverting all gpios until we found out
what we needed to know. In the end, we just set up the GPIOs as
the factory bios does.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4755 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
or not still depends on how close the configuration
options are to what they should be.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4751 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for amd/socket_AM2R2, amd/socket_939, drivers/ati/ragexl
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4750 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use "default n" for all components that shall be "select"ed.
- Use "0x0" instead of "0" for hex variables for clarity and to reduce
the risk of people passing integer instead of hex values to such variables.
- Add TODO comments for boards that have irq_tables.c but don' set
CONFIG_HAVE_PIRQ_TABLE = 1. Someone with the hardware should test enabling.
- ASUS M2V-MX SE doesn't have irq_tables.c so don't define
IRQ_SLOT_COUNT in its Kconfig file.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
failover.inc MUST come after enable_sse or your CPU will hang.
> Can you say why?
yes. if you compile failover.c with romcc options that include sse,
then you'll see code like this in failover.inc:
mov eax, %xmm0
This will hang if you have not first enabled sse.
Verified yesterday on the dell s1850.
>
> Does it hang in the SSE code or in the failover code?
It will hang in failover code, if that code was compiled with sse enabled
AND if the sse registers are used.
>
> Does this mean that failover requires SSE in order to work?
It may or it may not.
But if you compile it with romcc options that include sse,
and it uses sse without sse being enabled, it will hang.
This is a particularly nasty bug in that the failover code is not
guaranteed to compile in a way that sse is used, even if sse is
enabled; hence, this could be very hard to catch.
I'm lucky this bug appeared as soon as it did.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4746 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
their own vgabios.c
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4744 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fam10 doesn't build due to size constraints at this time.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4741 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to be run AFTER SSE is set up. I just had this problem cause a failure
today.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4740 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and PIRQ tables were actually wrong, I cannot imagine they ever
worked properly.
- Use CONFIG_IRQ_TABLE_COUNT in all irq_tables.c files instead of
hard-coded numbers.
- Make all CONFIG_IRQ_TABLE_COUNT values in irq_tables.c match Options.lb.
- Make all CONFIG_IRQ_TABLE_COUNT values match the actual number of entries
in the irq_tables.c file.
- Set all CONFIG_IRQ_SLOT_COUNT values in src/.../Options.lb for those
boards where they were set to 0 (in order to be overridden in
the respective targets/.../Config.lb).
This is mainly done to aid Patrick's scripts for kconfig conversion.
- Fix a number of comments in irq_tables.c files.
- Drop CONFIG_IRQ_SLOT_COUNT usage from boards that don't have irq_tables.c:
- tyan/s1846
- asus/a8v-e_se
- asus/m2v-mx_se
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4737 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add some more enables to the s1850.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4736 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, drop per-board CONSOLE_VGA/PCI_ROM_RUN while I'm at it, they're
global options in kconfig.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4735 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Add helps texts to multiple user-visible Kconfig options.
- Improve some menu and option names.
- PAYLOAD_NONE should come before PAYLOAD_ELF, so that you scroll down
(instead of up) when changing "no payload" to "ELF payload" (more
intuitive, IMHO).
- s/cbfs/cbfstool/.
- Add some TODO items where needed.
- Put GDB_STUB in a "Debugging" menu, no options should be top-level.
There'll be more debug options later, I'm pretty sure.
- Start converting help texts which are not user-visible to #-comments.
- Re-order some options for more intuitive menus.
- Set ARCH_X86 and ARCH_POWERPC to "default n", each boards selects them.
- "Maximum reboot count" should proabably not be user-selectable, or at
most if CONFIG_EXPERT (yet to be added) is enabled. It does definately
not need its own "Misc options" menu.
- Set PCI_ROM_RUN and VGA_ROM_RUN to "default y", most users will want to
run option ROMs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4734 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ROMCCFLAGS, so boards can override it where necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
select UDELAY_TSC
select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
for all 440BX and i810 boards as per Options.lb.
The UDELAY_IO / TSC / LAPIC / HPET setup will probably be checked
and improved later when the kconfig transition is done. For now
we keep the same values as in Options.lb.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
complete set of variables now, though they might still have
the wrong values.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4728 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
should not be set in per-mainboard Kconfigs.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4722 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in very early stages, otherwise the boot may hang like this because
the CBFS headers cannot be found/accessed:
Uncompressing coreboot to RAM.
Jumping to image.
Check CBFS header at fffedfe0
magic is ffffffff
ERROR: No valid CBFS header found!
CBFS: Could not find file fallback/coreboot_ram
Jumping to image.
This patch enables full ROM access on all 440BX boards right after the
serial init (and before CBFS headers are parsed).
Build-tested and runtime-tested on ASUS P2B-F.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4721 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both were only really used in pre-cbfs, as the payload's size isn't
relevant for the build process anymore.
Various calculations in {no,}failovercalculation.lb are adapted
accordingly.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4716 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Whitespace fixes to devicetree.cb
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4715 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
boards to global. It's not a per-board value, but
compatibility stuff.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4713 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- CONFIG_CBFS
- anything that's conditional on CONFIG_CBFS == 0
- files that were only included for CONFIG_CBFS == 0
In particular:
- elfboot
- stream boot code
- mini-filo and filesystems (depends on stream boot code)
After this commit, there is no way to build an image that is not using
CBFS anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4712 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
per discussion on the mailing list.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
for years.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4708 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
it is a P4 and it needs SSE for romcc not to go into infinite loop.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4701 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4700 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some of this trickery was determined with serialice.
There are several lovely undocumented features to the chipset.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4698 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
fam10 and h8dmr k8 targets.
Many, many thanks to Marc, Myles, Patrick and Stepan for all their help with
this, and to Arne for doing the s2912 fam10 port.
Build and boot tested. Abuild tested.
There are a number of outstanding issues and caveats - see src/mainboard/supermicro/h8dmr_fam10/README.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4693 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, simplify the M2V-MX SE Kconfig file a bit while I'm at it.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4688 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kconfig development.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4675 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also enable building individual boards with kbuildall for
debugging.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4666 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's only three files. Also fix up all the paths (Gotta love included C files)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
kconfig_s2892.dif: Add support for Tyan s2891, s2892, and s2895 to Kconfig.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig_bools.diff: Change some more ints to bools, change some default values.
xip_size.diff: Make XIP_SIZE + XIP_BASE add up to 4GB.
smp.diff: set CONFIG_SMP based on MAX_CPUS.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
copy any comment lines before the start of the device tree.
Fix up amd/pistachio and technexion/tim8960.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4648 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This allows us to change
dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary,
sm_dev->path.pci.devfn, 0x64);
to the much more readable
dword = pci_read_config32(sm_dev, 0x64);
Clean up all PCI operations in mainboards based on AMD 690:
amd/pistachio
amd/dbm690t
technexion/tim8690
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4647 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
out of the way of the serial port. Tested extensively in user mode.
Works and gets the BMC out of my way, which is good, because there
are few more useless things than IPMI and the BMC.
The BMC, all by itself, is the cause of most of our problems in booting
and talking to these nodes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I don't know what else to do for files generated by programs ...
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4639 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
let it build.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested. I also addressed questions raised by Uwe:
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
UDELAY_TSC
Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in
the mainboard Kconfig. The remaining question of Uwe's is a deeper
problem:
---
We'll have to check if this works. From a quick glance
the Rumba does not have the mmx related lines (which _are_ in
Makefile.romccboard.inc, though):
crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
---
We're going to need a whole variant of this standard mainboard OR
we're going to have to make (some) of the unconditional includes above
conditional.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
remove Config variables now defined elsewhere.
add rumba Kconfig and Makefile.inc
rumba won't build until my earlier patches are acked.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4617 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch tries to improve the pcie portA configuration.
The Matrox G550e PCIe gfx card shipped along with the dev board is supported.
Signed-off-by: Arnaud Maye <arnaud.maye@4dsp.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4615 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
copy any comment lines before the start of the device tree.
Copy over the comments for amd/dbm690t.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4614 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In amd/serengeti_cheetah there were duplicates, and USE_DCACHE_RAM is a
boolean value, so make it so.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4596 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This includes:
soyo/sy-6ba-plus-iii
a-trend/atc-6240
a-trend/atc-6220
gigabyte/ga-6bxc
biostar/m6tba
azza/pt-6ibd
tyan/s1846
abit/be6-ii_v2_0
compaq/deskpro_en_sff_p600msi/ms6119
msi/ms6147
asus/p2b
asus/p2b-d
asus/p2b-ds
asus/p3b-f
The Makefile.inc for all of them are _exactly_ the same, so I made a common
src/mainboard/Makefile.romccboard.inc (maybe needs a nicer name). I also suspect
that many other romcc-based boards will be able to re-use this Makefile.inc.
Apart from the board name, most boards only differ in the Super I/O that's
being used and the IRQ_SLOT_COUNT value. The Tyan S1846 is a bit different
as it doesn't have an irq_tables.c.
I also dropped the broken MS-6178 kconfig stuff for now, I'll submit a
proper config in another patch.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4587 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Any whitespace or dashes are replaced with underscores.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is the correct choice. Avoids type problems in kconfig
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only build-tested so far, not tested on hardware.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
important corrections to the Kconfig and Makefile.inc that were there. I
would like to go ahead and get this in, because I don't want anyone to
continue using what is in the upstream tree as it now exists.
I also tested old-style build with this and it did not break anything.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CBFS uses sprintf, which requires vtxprintf, which requires (in the
current design) a nested function. That works on x86, but on PPC this
requires a trampoline. In the ROM stage, this is not available, so
remove the single use of sprintf and replace it with a direct string
handler - it's only used to fill in fixed-length hex values.
20090819-3-more-noreturns-in-romcc:
Mark two more functions in romcc as noreturn. Helps clang's scan-build a
bit
20090819-4-cbfsify-ppc:
Make PPC use CBFS. Support big endian ELF in cbfs-mkstage. Untested and
not complete yet.
20090819-5-fix-ppc-build:
The CBFS build system requires ROM_IMAGE_SIZE to have a somewhat
plausible value.
With fixes to tohex* functions as discussed on the list, and correct
function names.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4558 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This eliminates 56kb of padding in the bootblock.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4554 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on Via EPIA-NL8000EG with FILO payload booting FC9 (2.6.25
kernel) from SATA HDD.
ACPI is working for PCI interrupt routing, some memory stuff and
Soft-Off.
USB/SATA Working
VGA Console Working
X Working via Onboard AGP
Removed dsdt.c, fixed some whitespace.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Remove the normal/* files from the image. they're just
copies of fallback/* anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4541 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Keeping identical files around will only bite us eventually, when they
get out of sync. See coreboot-v2 history for examples.
Trivial and build tested.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
when Patrick's tree and mine got out of sync.
Link stage still fails.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and we will fix issues as they appear.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
certain configuration options are disabled. The strings were just
at the wrong place.
Two boards fix up some variables for romstream. This isn't necessary (or
possible) when CBFS is active, as there is no romstream. It would be
nicer to have them depend on CONFIG_ROM_PAYLOAD, but there isn't any
invariant that forces that to be inactive if CBFS is active, and this
patch is supposed to be small, esp. as the stream loaders are on the way
out.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4494 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code
and through the general vga infrastructure i committed a month or two ago.
Add videoram_size option for k8m890 and the Asus M2V-MX SE.
Now the Asus M2V-MX SE will magically come up with a working standard VGA
80x25 textmode.
Many thanks to the people who worked hard on the Asus M2V-MX SE, and all
of its components; this vga bringup was a breeze thanks to your hard work
for this excellently supported board. And separate thanks to Rudolf Marek
for spurring me on and for providing a register dump.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
linux out of the box. There were two problems. First was that the
mmconfig ACPI structure was empty because of cut and paste (PCI ID of
K8M890 is different).
Second problem is now nicely solvable by add_region. Linux expects that
the mmconfig region is found as reserved memory. Otherwise it does not
trust it.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* acpi_add_table requires a pointer to the RSDP, not the RSDT anymore, in order
to properly support XSDT generation.
* fix compilation the DSDT on gigabyte/m57sli
* drop a remaining, forgotten HPET_NAME for "HPET"
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4461 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Move interrupt routing to mainboard specific code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
soon as there's an ACPI 2.0 or later table)
* add XSDT support
* add more table types
This patch will break at least the kontron (and possibly some new boards I
missed)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4453 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add the respective Super I/O config in Config.lb (Winbond W83697HG),
enable COM1 on the board, fix irq_table.c, as well as the PCI
devices listed in Config.lb (based on lspci output).
This has been tested by Jakob Bornecrantz <wallbraker@gmail.com>
on hardware, i.e. there is serial output. It does not yet boot
to a Linux console successfully, more fixing will be needed.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Jakob Bornecrantz <wallbraker@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4423 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Change the parallel port from polling to interrupt-driven.
This was tested by Andreas Mundt with a parallel port printer.
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
i810 chipset. Not all hardware has been tested, but my test PC boots Linux
(via FILO) without any problems.
Also: Add support for the SMSC LPC47U33X to the generic 'smscsuperio' driver.
Signed-off-by: Michael Gold <mgold@ncf.ca>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware with the patch from r4398 and works fine as soon
as Linux boots (no VGA in FILO for some reason, will investigate).
In order to make the 'i810.vga' VGA blob from the vendor BIOS work
you have to make the check for PCI device ID mismatches non-fatal
(for now) in the src/devices/pci_rom.c file like this:
Index: src/devices/pci_rom.c
===================================================================
--- src/devices/pci_rom.c (Revision 4393)
+++ src/devices/pci_rom.c (Arbeitskopie)
@@ -87,7 +87,7 @@
if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
rom_data->vendor, rom_data->device);
- return NULL;
+ // return NULL;
}
printk_spew("PCI ROM Image, Class Code %04x%02x, Code Type %02x\n",
The reason is that the VGA blob thinks the proper VGA device ID is 0x7123
whereas it really is 0x7121 on hardware. There are multiple ways to work
around this (there have been many discussions in the past), we'll see which
method will be used in future...
Note: This has been tested against r4393 only for now to make sure there
are no problems because of the recent resource allocator changes, see
http://www.coreboot.org/pipermail/coreboot/2009-July/050486.html.
Tests with trunk will follow.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Turn on Parallel Port and Floppy in Config.lb
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Andreas B. Mundt <andi.mundt@web.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
targets/supermicro/h8dmr/Config.lb and Config-abuild.lb.
Importantly, this also sets
default CONFIG_AP_CODE_IN_CAR=0
in
src/mainboard/supermicro/h8dmr/Options.lb
which is required to make this box boot since the changes that went in in
r4315.
At Myles' suggestion, this patch also sets
default CONFIG_USE_FAILOVER_IMAGE=0
default CONFIG_USE_FALLBACK_IMAGE=0
default CONFIG_XIP_ROM_SIZE=CONFIG_FAILOVER_SIZE
in src/mainboard/supermicro/h8dmr/Options.lb to simplify
targets/supermicro/h8dmr/Config.lb a bit further.
Build tested with abuild, boot tested on physical hardware.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4393 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4389 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
didn't build before, and it still doesn't)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4387 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Attached is the third revision of the CN400/EPIA-N(L) patch for CB V2.
Patch should work against r4381 (or later ?)
This version now boots all of the way through to attempting to launch a
payload (I'm trying FILO right now), where it falls over with exception
6 (invalid opcode)
The coreboot_table issue seems to have been automagically resolved by
the latest core files.
It may still be that the reason for the payload not starting is down to
some issue with the tables initialising, I'll look closer at that.
Signed-off-by: Jon Harrison <bothlyn@blueyonder.co.uk>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Kconfig)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested on hardware by Andrew Morgan <ziltro@ziltro.com>, boots
Linux fine. Detailed status at:
http://www.coreboot.org/Soyo_SY-6BA_Plus_III
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Andrew Morgan <ziltro@ziltro.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4369 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, enable HIGH_TABLES support for this board.
The HIGH_TABLES failed with:
No matching ram area found for range:
[0x00000000000f0000, 0x0000000000100000)
Ram areas
[0x0000000000000000, 0x0000000000001000) Reserved
[0x0000000000001000, 0x00000000000a0000) RAM
[0x0000000000100000, 0x000000000fff0000) RAM
[0x000000000fff0000, 0x0000000010000000) Reserved
SELFBOOT RETURNED!
Boot failed.
The fix was to change northbridge.c as follows:
- ram_resource(dev, idx++, 1024, tolmk - 1024);
+ ram_resource(dev, idx++, 768, tolmk - 768);
This is build-tested and tested on hardware by me. It boots fine,
for instace with SeaBIOS and the standard GRUB1 from my disk.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add initial ACPI support for M57SLI.
Activates/Enables:
* native Coreboot ACPI for M57SLI
* Soft-Power-Off
* PowerNow!
* High Precision Event Timer
* Windows booting with ACPI support
Signed-off-by: Harald Gutmann <harald.gutmann@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
ways superior to v3, while lacking its completeness. But, one nice
thing: no more included .S or .c files. It's all separate compilation.
That should allow our Makefiles to work much better.
Note that the current non-CAR implementation is the default and
continues to work (tested FILO boot to Linux on both CAR and non-CAR).
Index: src/mainboard/emulation/qemu-x86/Config.lb
Change this to be sensitive to USE_DCACHE_RAM. All settings etc. that
depend on this variable are grouped in one if, and the other parts
(romcc etc.) are in the else. This change is a model of how we should be
able to do other motherboards.
Index: src/mainboard/emulation/qemu-x86/Options.lb
add needed options.
Index: src/mainboard/emulation/qemu-x86/failover.c
remove code inclusion from this not-yet-used file.
Index: src/mainboard/emulation/qemu-x86/rom.c
This is the entry point for the rom-based code. Called stage1.c in v3.
Index: src/lib/Config.lb
change initobject to a .o from a .c; this fixed a build problem.
Index: src/pc80/serial.c
make uart_init non-static.
Index: src/pc80/Config.lb
add initobject
Index: src/arch/i386/init/entry.S
Entry point. Unify a bunch of files that were fiddly lttle includes. From v3.
Index: src/arch/i386/init/ldscript.ld
new file. The goal is to hang all init changes for CAR here, to minimize other changes to any
other ldscript. Besides, putting this in init makes sense; entry and car are manage init.
Index: src/arch/i386/init/car.S
generic i386 car code from v3.
Index: src/arch/i386/init/ldscript_fallback_cbfs.lb
Fix what looks like a bug: this was not including the init.text section.
Index: targets/emulation/qemu-x86/Config.lb
push up the console loglevel. qemu is for debugging so we might as well
get all the debugging we can.
Index: targets/emulation/qemu-x86/Config-car.lb
For CAR bullds.
Signed-off-by: Ronald G. minnich <rminnich@gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4357 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Abuild tested and boot tested on s2895 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
gets us through config, but it fails during build because the original patch
duplicated some files for VIA systems.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Make get_dsdt script executable.
- Rename DrivingClkPhaseData.c to driving_clk_phase_data.c.
- Set proper IRQ_SLOT_COUNT value in the hope that the '14' from irq_table.c
is correct.
- Fix broken or incorrect #include names to increase likelyhood of a
successful compile.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4350 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
files for targets without failover:
src/config/nofailovercalculation.lb (64 kB XIP)
src/config/nofailovercalculation128.lb (128 kB XIP)
Targets with other XIP sizes were ignored.
This patch moves XIP size back into mainboard code.
Benefits from this patch:
- src/config/nofailovercalculation128.lb is no longer needed
- Targets with XIP sizes besides 64k and 128k benefit from refactoring
- Conceptually, this makes the include files pure calculation files
without settings.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4348 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same. The errata need some extra room in failover.
Trivial and abuild tested
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4347 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
instead of coreboot.strip. That fixes the normal
image because the calculations for its offset in
the ROM match reality again.
This requires changes in CBFS configurations to
minimize the bootblock size. These are also done
for CBFS boards.
Other than this a couple of minor fixes are in this
patch:
- make asus/m2v-mx_se build with abuild with a
crosscompiler
- move CONFIG_CBFS for hp/dl145_g3 to Options.lb
as it's done everywhere else
- change the default config of abuild to not
provide ROM_IMAGE_SIZE values for the images
in a CBFS configuration
- change abuild's crosscompile autodetection to
not try to use "i386-elf-i386-elf-gcc" (which
is bogus)
Except for the latter two abuild changes (both
in util/abuild/abuild), they're available as
patch set on the mailing list in a mail from
2009-06-05 titled
[PATCH]es to get normal image to work again with CBFS
The changes in util/abuild/abuild are trivial and
abuild tested.
As discussed on the list,
targets/hp/dl145_g3/Config-abuild.lb is
deleted, now that Config.lb works again.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4344 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The patch has been submitted by bari <bari@onelabs.com> and written
by OLPC.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code, specifically the difference between pre_f and f code.
The only functional changes are in printk statements. The rest is white space.
1. Remove some #if 0 and #if 1 blocks
2. Remove #if USE_DCACHE_RAM blocks. All K8 boards use CAR.
2. Correct typos (canidate -> candidate)
3. Try to minimize the differences between amdk8_f.h and amdk8_pre_f.h
4. Try to minimize the differences between raminit.c and raminit_f.c
5. Make boards that have rev_f processors include the correct raminit code
There is much more that could be done, but it's a start.
Abuild tested and boot tested on s2892 and serengeti_cheetah.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4337 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit c03527377db5951f0d3228e2a93b4c57dd81b8ec.
Stepan pointed out that 's' means string, and that therefor strings do exist.
Marking this as reserved breaks some payloads.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4334 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The kontron 986lcd_m cmos.layout had a 512bit area claimed for "boot_devices".
The changes to the cmos code no longer allow usage of values larger than
32bits. Since this option was completely unused, mark it as reserved.
Fixes build after the get_option change (r4332)..
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4333 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
directory just with one common file.
Changes to FADT: move to rev4, fix the generic register descriptors, detect additional VT8237S features.
Change the compiler to CORE , its revision to 42.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4327 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4325 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4324 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Replace $(PWD) with $(CURDIR) in Makefiles. I don't know why
the Solaris version behaves differently, but CURDIR is a safe
choice on gnu make (and we require gnu make already)
- Use tail -1 instead of tail -n1 in a file that already relies on
tail -1 support in another place
- Use tail -1 as alternative to tail -n1 in another place
- Use #define for ulong_t in romcc, as that name is used on Solaris
- Avoid fprinting a null pointer. The standard doesn't mandate that
this is a special case, and Solaris doesn't implement it that way.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4305 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
out in the mainboard config file. (trivial)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tree it was copied from.
This is a trivial patch.
Signed-off-by: Ward Vandewege <ward@gnu.org>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4295 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4289 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
register setting for all FAM10 processors.
This does not include new errata for FAM10 C2.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Vincent Lim (vincent.lim@amd.com)
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Vincent Lim <vincent.lim@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4286 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I would like to remind you that this firmware enables the hardware
virtualization on the AMD cpu's on the machine. That feature was
explicitly disabled by the factory BIOS.
Due to an error in the VGAROM no other rom loader (YABEL or X*^BIOS)
than SeaBIOS manages to load the VGA rom. The VGA ROM tries to read
config space of a device that is actually not present.
Because SeaBIOS does not support AHCI SATA it can not start the
bootable drive of the machine so i had to add filo to seabios to
manage booting:
./cbfstool coreboot.rom add-payload filo.elf img/FILO
Signed-off-by: Samuel Verstraete <samuel.verstraete@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4277 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/northbridge/intel/i440bx/ but not to
src/cpu/emulation/qemu-x86/northbridge.c
It also adds a driver for the ISA device that is found when using
0.9.1 If you look in a log without this patch you won't find the RTC
init lines.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4269 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
because it was not working anyway (it was hardcoded) and because it allows me to
fix the XIP base to something sane (and use generic computation and approach)
This board is bit tricky because until now it required the VGA BIOS on the flash
start. XIP will work with 64KB aligned base, therefore the VGA ROM image must be
aligned too to 64KB.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4265 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4260 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4249 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joseph Smith <joe@settoplinux.org>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
I didn't try to remove "defined but not used" warnings because there are too
many ifdefs to be sure I wouldn't break something.
For shadowed variable declarations I renamed the inner-most variable.
The one in src/pc80/keyboard.c might need help. I didn't change the
functionality but it looks like a bug.
I boot tested it on s2892 and abuild tested it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4237 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
3 (with one of them way too much assembler code).
On the way, I had to make some changes to the way the code is built,
which is an effort I want to expand over time.
Right now, large portions of the in-ROM part of coreboot is compiled as
a single file, with lots of .c files including other .c files.
That has its justification for pre-raminit code, but it also affects
lots of post-raminit code (memcpy doesn't really make sense before
raminit, or at least CAR)
The coreboot_apc code (AMD boards) gained some .c includes because I
don't know that part of the code enough to really rework it and only
have limited possibilities to test it. The includes should give an
identical situation for this part of the code.
This change was posted as set of 6 patches to the list, but they
were mostly split for review purposes, hence commit them all at once.
They can still be backed up using the patch files, if necessary.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
support for it.
The related mainboards don't need to activate it
themselves anymore.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
this generic code could be added to the caller of
add_mainboard_resources (wrapped in HAVE_HIGH_TABLES, of course).
That way, boards that really need it (for other things) can use this
function, while others don't have to do anything to use
HAVE_HIGH_TABLES.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested, incl. optionrom-in-cbfs for kontron, and compressed payloads
for both.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the appropriate mainboard sources.
Signed-off-by: Mondrian nuessle <nuessle@uni-hd.de>
Acked-by: Samuel Verstraete <samuel.verstraete@gmail.com>
I updated some whitespace and the Config files. - Myles
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4184 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(scan-build chokes on this)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4181 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
combined socket_mPGA604. No other sockets come with clock rates, and there is
no difference in code, except for the number of microcode patches included in a
build.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4169 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
refactoring Config.lb became possible.
Factor out ROM size calculation from Config.lb.
This patch converts 87 boards (with and without USE_FAILOVER_IMAGE),
but it has to work around a parser bug.
89 files changed, 209 insertions(+), 2415 deletions(-)
A total of 2206 removed lines.
Abuild works for all changed boards on khepri.
Myles writes:
I've tested serengeti for the failover portion and s2892 for the
nofailover portion. ldoptions are exactly the same and they both boot
the same.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4147 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is a pretty standard "yet another 440BX" target, so the code
is pretty straight-forward. It's a dual-CPU machine, which might need
some fixing, I'm booting with 'maxcpus=0' for now. It does boot
successfully up to a Linux login prompt, though.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4133 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4126 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
HAVE_MP_TABLE=0
It also removes the artifacts from the Asus m2v-mx_se that were
necessary before the change.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Repeat: Cosmetic patches shall not break the tree for 20 revisions.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4116 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This also has the config tool changes in v2/util.
Rename romfs.[ch]->cbfs.[ch] and sed romfs->cbfs romtool->cbfstool ROMFS->CBFS
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4113 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
It should fix the build break introduced in r4101
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4105 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code just blinks the leds. The motherboard resources are use to reserve coreboot
used memory.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4103 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
In file included from
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:93:
src/northbridge/amd/amdk8/raminit.c: In function ‘sdram_set_spd_registers’:
src/northbridge/amd/amdk8/raminit.c:2123: error: implicit declaration of
function ‘activate_spd_rom’
In file included from
src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c:101:
src/cpu/amd/model_fxx/init_cpus.c: In function ‘init_cpus’:
src/cpu/amd/model_fxx/init_cpus.c:319: error: implicit declaration of
function ‘soft_reset’
In file included from
src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c:98:
src/northbridge/amd/amdk8/raminit_f.c: In function ‘sdram_set_spd_registers’:
src/northbridge/amd/amdk8/raminit_f.c:2848: error: implicit declaration of
function ‘activate_spd_rom’
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4098 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
now all have the same parameter order.
action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS)
-I$(TOP)/src -I. -nostdinc -nostdlib -fno-builtin -Wall -Os -c -S
$(MAINBOARD)/$(CACHE_AS_RAM_AUTO_C) -o $@"
The idea behind this parameter order is:
- *FLAGS at the beginning.
- Use a common set of *FLAGS.
- Include files and directories listed afterwards.
- nostdinc, nostdlib, no-builtin tell the compiler this is standalone
code.
- Warnings. They do not influence source or compilation.
- Compilation strategy (small) and output mode (asm or binary).
- File to be compiled.
- Output name.
- $(DEBUG_CFLAGS) and -S are only used for asm output.
Other changes in this patch:
- src/supermicro/h8dme/Config.lb now uses $DEBUG_CFLAGS instead of
hardcoding the respective flags.
- $DEBUG_CFLAGS was added to asm outputting $CC calls:
supermicro/h8dme/Config.lb
lippert/roadrunner-lx/Config.lb
- $DISTRO_CFLAGS was added to some $CC calls in:
iwill/dk8_htx/Config.lb (CAR AP code)
supermicro/h8dmr/Config.lb (CAR AP code)
supermicro/h8dme/Config.lb (CAR AP code)
gigabyte/m57sli/Config.lb (CAR AP code)
gigabyte/ga_2761gxdk/Config.lb (CAR AP code)
amd/serengeti_cheetah_fam10/Config.lb (everywhere)
msi/ms7135/Config.lb (everywhere)
nvidia/l1_2pvv/Config.lb (CAR AP code)
-$CFLAGS was added to all $CC calls in:
amd/db800/Config.lb
amd/dbm690t/Config.lb
amd/norwich/Config.lb
amd/pistachio/Config.lb
amd/serengeti_cheetah/Config.lb
amd/serengeti_cheetah_fam10/Config.lb
arima/hdama/Config.lb
artecgroup/dbe61/Config.lb
asus/a8n_e/Config.lb
asus/a8v-e_se/Config.lb
asus/m2v-mx_se/Config.lb
broadcom/blast/Config.lb
digitallogic/msm800sev/Config.lb
gigabyte/ga_2761gxdk/Config.lb
gigabyte/m57sli/Config.lb
ibm/e325/Config.lb
ibm/e326/Config.lb
iei/pcisa-lx-800-r10/Config.lb
iwill/dk8_htx/Config.lb
iwill/dk8s2/Config.lb
iwill/dk8x/Config.lb
kontron/986lcd-m/Config.lb
lippert/roadrunner-lx/Config.lb
lippert/spacerunner-lx/Config.lb
msi/ms7135/Config.lb
msi/ms7260/Config.lb
msi/ms9185/Config.lb
msi/ms9282/Config.lb
newisys/khepri/Config.lb
nvidia/l1_2pvv/Config.lb
pcengines/alix1c/Config.lb
sunw/ultra40/Config.lb
supermicro/h8dme/Config.lb
supermicro/h8dmr/Config.lb
technexion/tim8690/Config.lb
tyan/s2735/Config.lb
tyan/s2850/Config.lb
tyan/s2875/Config.lb
tyan/s2880/Config.lb
tyan/s2881/Config.lb
tyan/s2882/Config.lb
tyan/s2885/Config.lb
tyan/s2891/Config.lb
tyan/s2892/Config.lb
tyan/s2895/Config.lb
tyan/s2912/Config.lb
tyan/s2912_fam10/Config.lb
tyan/s4880/Config.lb
tyan/s4882/Config.lb
- Use $@ wherever appropriate.
- Kill that evil CACHE_AS_RAM_AUTO_C variable.
- Trailing whitespace fixups on lines which were touched anyway.
We now only have 6 remaining different calls to $CC whereas before there
were 20.
If I am allowed to rename src/mainboard/kontron/986lcd-m/auto.c to
src/mainboard/kontron/986lcd-m/cache_as_ram_auto.c, we're down to 4
different calls.
If we can decide on the use of $CPU_OPT, we are down to 3 different
calls.
One additional point I'd like to clear up:
if ASSEMBLER_DEBUG
makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm
end
"-dA -fverbose-asm" is only useful for asm output. For these flags,
DEBUG_CFLAGS is a total misnomer. What about calling them
DEBUG_ASMCFLAGS or somesuch?
"-g" should be controllable by a separate switch. It is useful even for
object code.
The following targets are broken by this patch because they contain
implicit declarations, but the error did not trigger due to missing
CFLAGS:
amd/serengeti_cheetah
asus/a8v-e_se
asus/m2v-mx_se
digitallogic/msm800sev
pcengines/alix1c
supermicro/h8dme
supermicro/h8dmr
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use $(CACHE_AS_RAM_AUTO_C) instead of cache_as_ram_auto.c
- Compile apc_auto.c with $(DISTRO_CFLAGS)
- Clean up whitespace
If anyone can explain the remaining differences in Config.lb which are
NOT caused by the K8/Fam10 switch, I'd be glad to hear them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Lots of Config.lb files still have "if USE_DCACHE_RAM" sections although
USE_DCACHE_RAM is always set for them. Such checks are not only
pointless, they actively make the files hard to read.
A full abuild run confirmed that compilation did not change with this
patch applied.
The patch does not change whitespace of the remaining code to ease
review and svn blame.
With this change, it should be possible to have two or three Config.lb
variants in total (except the actual hardware config). Right now, some
Config.lb have comments, some don't, some have empty lines for better
readability, some don't, some have leading whitespace, some don't. This
is an utter mess and unifying these files would certainly reduce the
headaches I have when looking at them.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4093 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(trivial)
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
working. Given all the limitations of PIRQ routing we keep it simple
and just set the IRQ directly. Most BIOSes are doing setup this way anyways,
since there are so many errors in PIRQ tables.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4080 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- don't make users pick the name. Names for option roms are in the v3-defined
format of pci%04x,%04x.rom with the vendor and device id filling in the
%04x.
- users pass in vendor and device id.
- users pass in a dest. If the dest is 0, the address of the ROM image in
FLASH is returned. If the address is non-zero, then the decmpressor is called,
and it will make sure the ROM image is copied to the destination (even
in the uncompressed case).
move qemu over to always using ROMFS
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4078 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As I mentioned a few weeks ago, I am in the process of porting this board:
http://www.technexion.com/products/embedded_boards/tim-8690-mt.html
This board has a dual BIOS , choosable with a jumper - much like the BIOS
savier from before - so it is a pleasure to work with as a linuxbios developer.
It is still a work in progress, however , I already submit the patch.
All on board devices and slots work as expected, only need some more stress
testing with the RAM, acpi, etc..
Signed-off-by: Daniel Toussaint <daniel@dmhome.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4075 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4058 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in their Config.lb but never use it. There's no point in keeping
dead code around.
This patch removes ROMCC remainders from Config.lb and kills orphaned
auto.c and failover.c in the affected mainboard directories.
arima/hdama
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms9282
newisys/khepri
sunw/ultra40
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882
Abuild log is completely identical with and without the patch.
With this patch, the last ROMCC remainders for K8 boards are gone.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4055 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tyan/s2735
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895
Abuild log is completely identical with and without the patch.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4050 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in their Config.lb but never use it. There's no point in keeping dead
code around. Kill it.
This patch removes ROMCC remainders from Config.lb for tyan/s2735 and
tyan/s2850.
Abuild build log with and without the patch is completely identical.
More patches of the same type can be done, hopefully making
ROMCC dependencies a bit more clear for v2.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4048 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
be used unconditionally, and the names don't hurt.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4042 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Trivial fix, just add the defaults as with all other boards.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4041 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Tested under abuild, causes no trouble.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4035 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4025 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot to 1MB and tries to cache whole range for XIP. The UMA part colide a
bit with the HAVE_HIGH_TABLES region. I solved that by relocation of the region.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4024 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The one issues is the SPD address switch for the second CPU. That means that
the memory must be an exact match on each CPU.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Ward Vandewege <ward@gnu.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
DSDT and use the dynamic TOM2 variable instead.
- The DSDT needs to be revision 2 or above to handle 64 bit variables.
This will require a recent (not older than 2007) iasl (ACPI compiler).
- Fix an incorrect comment.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code expecting too old binutils(?).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4007 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
address of the RTC is 0x70, you need to write 0x400 to it. Now the dump from
superiotool matches the factory except 0xf0 of the keyboard. When you boot with
the factory BIOS that is 0x04, but with coreboot it is not set.
It's trivial because it is reverts.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4002 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
directories and use the global (v3) one in util/x86emu instead. It also fixes
the breakage introduced by 4000
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4001 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3999 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
be required for a series of later patches. Roughly it contains:
* fixed SMBus driver (was not compiled in before)
* fixed S-ATA/P-ATA combination
* Added warnings to drivers being called with a NULL dev->chip_info
* Set subsystem ids for those boards that have none specified in Options.lb
* Fix license headers. The code was originally released under GPL v2 but
some files sneaked in with a v2 or later header.
* some attempts to fix azalia/Intel HDA.. not working yet
* clean up and fix pci bridge handling code
* Add Config based GPI handling to LPC driver
* Add HPET enable function
* Enable clock gating where appropriate
* first attempt at USB debug console support (not working yet)
* Add required options to kontron board
* many other minor changes
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3991 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a problem with IRQ 9, but besides that Linux is happy. BSOD in Windows still.
changes by file:
src/mainboard/tyan/s289X/Options.lb:
Add options and defaults for ACPI tables and resources.
src/mainboard/tyan/s289X/mainboard.c:
Add high_tables resource ala Stefan's code for the Kontron.
src/mainboard/tyan/s289X/acpi_tables.c:
Fill out the ACPI tables, using existing code where possible.
Only the madt is different between the boards, to be combined later.
src/mainboard/tyan/s289X/Config.lb:
Compile in acpi_tables.c and dsdt.dsl.
Turn on the parallel port and the real-time-clock.
src/mainboard/tyan/s289x/dsdt.dsl:
The board layout (thanks Rudolf) and interrupts from mptable.c
src/mainboard/tyan/s289x/mptable.c:
Minor formatting changes to make them diff better.
src/superio/smsc/lpc47b397/superio.c:
Correct the size of the real-time-clock so it can be where it belongs.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3989 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
whitespace differences between this file and the amdk8_util.asl from
asus/m2v_mxe.
It also enables SLIT filling if you have one, zeroes the unused fields in the
srat_lapic structure, and adds some declarations in acpi.h.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3986 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
(in addition to their low locations)
This adds the kontron 986LCD-M and the i945 as a sample.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3960 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
removes the ugly binary DSDT patching and all other related stuff. Stick to
infrastructure in previous patch.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3955 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This patch converts mainboard_$VENDOR_$BOARD_ops to mainboard_ops and
mainboard_$VENDOR_$BOARD_config to mainboard_config.
Ron's part:
The config change that makes the naming change not break every build.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3954 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
on some platforms.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
M2V-MX SE as example how to do that. It is based on AMD code and mine code for
ACPI generation.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The company is dead.
It causes builds to fail, and that is not a problem we need to have.
Removing it to remove the problems it causes.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3945 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
clause.
An ITE87427 Super I/O does not exist. Use the real name (IT8712F) of
the chip on the DBM690T board.
Use decimal values for KELV, THOT and TCRT on the Pistachio board for
better readability.
Tested by Maggie Li on DBM690T and Pistachio.
Tested by Carl-Daniel Hailfinger on Asus M2A-VM.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3939 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix reference to documentation.
Use __FUNCTION__ instead of hardcoding function names in printk
messages.
No functional changes.
I'm slowly getting to the point where adding another RS690 board is
really easy and needs almost no changes to the existing target.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3938 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
new AML code generator. Compile-tested on all changed targets. I think it should
work because it works for Asus M2V-MX SE.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3929 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generate run-time ACPI ASL code.
Moreover it demonstrates its use on Asus M2V-MX SE where the SSDT table is
generated by new function k8acpi_write_vars (technically similar to
update_ssdt). But lot of nicer.
x
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3925 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- use new features of the ich7 update
- move rambase above 1M to avoid memory trashing through SMM relocation
- enable superio HWM
Update ICH7 driver
- minor smi cosmetics (in progress)
- add real ac97 driver
- add real azalia driver
- fix some interrupt issues
- fix some sata issues
- include Patrick's fix for _lpc.c
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cause problems with certain toolchains. This patch will also safe some hard
disk space for those of us working on laptops or netbooks with always too small
disks.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3876 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
bit 10 is part of NewVID. That means the resulting VID is wrong and
causes the processor to crash.
The Pistachio code has the same bug.
This patch fixes the wrong setting and changes control from a magic and
incorrect unexplained value (0xE8202C00) to a combination of explained
values and shifts which has the right value (0xE8202800).
It is tested on my machine and it survived 200 changes from minimum to
maximum frequency every 100 ms under heavy load and under no load.
In the long term we want to consolidate all AMD FIDVID code into one
generic library file.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Maggie Li has tested it on her DBM690T board. It is ok.
Acked-by: Maggie li <Maggie.li@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3868 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
revF CPUs. The 100MHz/200MHz stepping is already handled in the FID setting
and doesn't need to be checked to set the fid_multiplier. The multiplier is
always 100.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: zheng bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The attached patch adds missing bits to ACPI to make Windows XP and Windows Vista happy.
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3842 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-By: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3841 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The FADT bootarch flags
Blacklists MSI for this chipset (maybe not needed)
Adds modified amdk8_util.asl
Adds the SSDT table to chain of tables
Aligns the FACS correctly (this should be done for other boards)
Adds the _CRS method to Asus M2V-MX SE acpi DSDT.
Fixes the FACS table length.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3840 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
debug code to src/northbridge/amd/amdk8/incoherent_ht.c.
However, printk is not available for all boards at that stage.
I have changed the following boards:
agami/aruma
arima/hdama
asus/a8n_e
broadcom/blast
ibm/e325
ibm/e326
iwill/dk8s2
iwill/dk8x
msi/ms7135
newisys/khepri
sunw/ultra40
tyan/s2850
tyan/s2875
tyan/s2880
tyan/s2881
tyan/s2882
tyan/s2885
tyan/s2891
tyan/s2892
tyan/s2895
tyan/s4880
tyan/s4882
abuild works fine for all of them.
agami/aruma needs a Config-abuild.lb which doesn't have fallback and
normal due to size problems.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3829 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
in the VT8237R, and a card interrupting at Pin-A on either PCI slot.
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3826 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
different ROM chip sizes (trivial, tested with 256 KB chip).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
implemented (It just prints "hard_reset not implemented. FIX ME!" This patch
defines HAVE_HARD_RESET 1 and adds a #warning hard_reset not implemented.
The net effect is that hard_reset prints something instead of just entering an
infinite loop.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3823 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
worked or not, but my board doesn't have COM1, and those function don't
support using COM2, so I've changed auto.c to use the fintek f71805f
functions, the fintek is the onboard super io. I also cleaned up a
whitespace issue and unused variable.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
specific changes based on the DBM690T code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3813 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This should hopefully make the "too few registers" error pop up less often.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3810 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The following ACPI features are supported:
1. S1, S4, S5 sleep and wake up (by power button).
2. Thermal configuration based on ADT7475.
3. HPET timer.
4. Interrupt routing based on ACPI table.
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Michael Xie <michael.xie@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Joe Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3801 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
See details at:
http://support.necam.com/mobilesolutions/hardware/Desktops/pm2000/celeron/
Thanks to Quentin RAMEAU <quentin.rameau@gmail.com> for providing the
required information and for testing the patch.
This boots into a Linux console just fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The patch changes the LDTSTOP length as well mostly default content of 0xec,
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
0xe4 and 0xe5 registers. I'm suspecting that the documentation may be wrong.
Furthermore this fix for powernow may not work on CPUs hit by errata #181.
Workaround should be implemented. The powernow may not work on pre-A2 revisions
of VT8237S silicon, revision reg is unknown.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3795 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add AMD dbm690t ACPI support.
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.
Signed-off-by: Joe Bao <zheng.bao@amd.com>
Reviewed-by: Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3788 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The following ACPI features are supported.
1. S1, S5 sleep and wake up (by power button or PS/2 keyboard/mouse).
2. AMD powernow-k8 driver.
3. Thermal configuration based on ADT7461.
4. IDE timing settings.
5. HPET timer.
6. Interrupt routing based on ACPI table.
Signed-off-by: Joe Bao <zheng.bao@amd.com>
Reviewed-by: Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
With this patch it's possible to
- determine the according source code line for each asm statement
(objdump -dS)
- determine the source code file for each asm statement
(objdump -ddl)
This isn't exactly trivial because cache_as_ram_auto.c gets compiled to
assembly and converted by a perl script afterwards.
This patch solves the problem
- by extending cache_as_ram_auto.inc with debug information and line
numbers
- by correcting the perl calls (".text" --> "\.text")
- by creating a disassembly with source code and line numbers.
(ctr0.disasm and
coreboot.disasm)
There's one minor downside to the patch: A complete abuild run takes up
around 1.6G instead of about 700MB now. But I'm sure this is quite
reasonable for the benefits.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Please commit while this is being worked out.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
memory controller.
Also, drop some unused '#if 0' code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3773 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Intel 810 chipset (and all boards using it). This isn't required for this
chipset as there's only one memory controller.
This also helps a lot with romcc register usage, you should see the dreaded
"too few registers" less often.
Build-tested with all three boards using the Intel 810 chipset.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is a school book example of why trivial indent patches just suck
big time.
This error was introduced by a trivial self-acked indent patch and was
never detected (because of a missing Config-abuild.lb)
So, indenting the code for no reason can make it a lot worse (read:
break it) instead of improving it.
I ask everyone to keep this in mind when going on indent-frenzy again.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3762 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the Lippert Cool SpaceRunner LX which is already in svn).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3761 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
enable may do printk()s which result in a 2 minute delay on some boards.
Fix this on all boards which currently do smbus_enable() before enabling
the serial console.
Thanks to Elia Yehuda <z4ziggy@gmail.com> for tracking this bug down.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3742 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3727 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Not tested, builds, derived from getpir. Definitely better than what was there.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Bari Ari <bari@onelabs.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3724 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Both regular and abuild images have been boot tested successfully.
Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3711 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
built in the normal image, not fallback.
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Corey Osgood <corey.osgood@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3667 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* Add a function to change the 24/48Mhz clock input selector on the Winbond
W83697 superio to 48Mhz, used by the WinNET P680
Signed-off-by: Alex Mauer <hawke@hawkesnest.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3661 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This is abuild-tested by me.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3654 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Stefan Reinauer