Under certain conditions when the APs are still executing during
MCT setup the system can hang. This was the root cause of most
of the S3 resume failures on this platform; waiting for AP stop
before MCT setup allows for reliable S3 resume.
Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13169
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Under certain conditions, such as when microcode updates are
being performed, it is important to make sure all APs have
finished updates and are halted before continuing with the
boot process.
Add a new wait_ap_stopped() function to allow for this
functionality to be added to the appropriate mainboard
romstage source files.
Change-Id: Ib455c937888a58b283bd3f8fda1b486eea41b0a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13168
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active. Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.
Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The IOMMU/HT device was not routed correctly; add the proper APIC
mappting to the mptable generation code. Also clarify comments
surrounding the pin mappings.
Change-Id: I72ceb0f22dabdfa71a1f6231ccb841face08ff7a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13163
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The existing code did not allow for the second core of the BSP to
reside on an APIC ID other than 1, leading to a boot hang on Family
15h processors when APIC_ID_OFFSET was set to anything other than 0.
Furthermore, insufficient AP stack space was allocated for AP start.
Change-Id: I4ded3cfb3736149e2265848014352d7622d5042a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13158
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Since this code is pulled in through commonlib, it will break compilation
of cbfstool on OSX.
Change-Id: I342bfa7e755aa540c4563bb5cd8cccacee39d188
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13525
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is the very very minimum needed to compile the code.
Change-Id: I7f9e5f564181071591a4640019f59f91a4c456c6
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/13297
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some newer x86 systems can boot from non-memory-mapped boot media
(e.g. EMMC). The bootblock may be backed by small amounts of SRAM, or
other memory, similar to how most ARM chipsets work. In such cases, we
may not have enough code space for romstage very early on. This means
that CAR setup and early boot media (e.g. SPI, EMMC) drivers need to
be implemented within the limited amount memory of storage available.
Since the reset vector has to be contained in this early code memory,
the bootblock is the best place to implement loading of other stages.
Implement a bootblock which does the minimal initialization, up to,
and including switch to protected mode. This then transfers control
to platform-specific code. No stack is needed, and control is
transferred via a "jmp" such that no stack operations are involved.
Change-Id: I009b42b9a707cf11a74493bd4d8c189dc09b8ace
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/13485
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
bootblock.S was used strictly for setting up the system so that the
assembly generated by ROMCC could be executed. Since the
infrastructure now exists to run a bootblock wihtout ROMCC, rename
this file accordingly. this is done to prevent any future confusion.
Change-Id: Icbf5804b66b9517f9ceb352bed86978dcf92228f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/11784
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
since commit f1e321001d, the UART init
should be in bootblock_mainboard_early_init() which runs before
console init. (see src/lib/bootblock.c)
Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71
Reviewed-on: https://review.coreboot.org/13448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move the default select of "Use native graphics initialization" for
Peppy to the ChromeOS section as SeaBIOS (default payload) requires a
vBIOS and takes twice as long to load with this option enabled. For the
same reasons, this option shouldn't be enabled by default (def_bool y).
Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/13493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
TEST=Boot to OS
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I9b43eb4f6f7af62a8a0bbe7bfa08feee1eaca24e
Reviewed-on: https://review.coreboot.org/13506
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Now coreboot should do BIOS CAR setup along with NEM
mode setup.
This patch also provides a mechanism to use 16MB code caching
benefit although LLC still limited to 1M/1.5M based
on SOC LLC limit.
Here with unlimited cache line gets replaced. Now we could use
unlimited cache size along with well defined data size
[pg: updated to current upstream #defines]
BUG=chrome-os-partner:48412
BRANCH=glados
TEST=Builds and Boots on FAB4 SKU2/3.
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: pchandri <preetham.chandrian@intel.com>
Signed-off-by: Dhaval Sharma <dhaval.v.sharma@intel.com>
Change-Id: I96a9cf3a6e41cae9619c683dca28ad31dcaa2536
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2ec51f15c874ad2f1f4fad52fa8deced7b27a24b
Original-Change-Id: Id62c15799d98bc27b5e558adfa7c7b3468aa153a
Original-Reviewed-on: https://chromium-review.googlesource.com/320855
Original-Commit-Ready: Subrata Banik <subrata.banik@intel.com>
Original-Tested-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13138
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
If coreboot's build process is reproducible (eg. using the latest git
timestamp as source), bl31 is, too.
This requires an arm-trusted-firmware side merge first (in progress) and
an update of our reference commit for the submodule, but it also doesn't
hurt anything because it merely sets a variable that currently goes
unused.
Change-Id: If139538a2fab5b3a70c67f4625aa2596532308f7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13497
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
The KGPE-D16 and KCMA-D8 use a Winbond W83667HG-A SuperIO. While
the Nuvoton NCT5572D is effectively the same core, and a close
enough match to get things working initially, the W83667HG-A
has a different LDN mapping and several extra features that
require a separate support driver.
Clone the Nuvoton NCT5572D and modify according to the W83667HG-A
datasheet, version 1.4.
Change-Id: I707ba2e40a22d41cd813003d84a82cb20304f55b
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13156
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The KGPE-D16 supports an optional MIO audio card, which connects
to the on-board HDA interface of the SP5100.
Enable the HDA interface for use with the MIO card.
Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13152
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
The existing code used an incorrect macro name to check for mainboard
DRAM voltage set support, and as a result no voltages were actually
set. Furthermore, the existing code did not contain a centralized
voltage assumption for boards that did not have a DIMM voltage set
implementation.
Use the correct macro name to test for boards with voltage set
implementation, and provide a basic fallback to 1.5V operation
for boards without a voltage set implementation.
Change-Id: I638c65fe013a8e600694d8cbedf6a10b33b0ef95
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13150
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The existing code generated an incorrect boot APIC ID from node and
core number for single node packages, leading to a boot failure when
the second node was installed.
Properly generate the boot APIC ID from node and core number.
Change-Id: I7a00e216a6841c527b0a016fa07befb42162414a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13149
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Previously with errors in the ram init, early cbmem was disabled.
Now that the ram is working correctly, set as early cbmem platform
and update all (1) boards to use it.
Tested on GA-G41M-ES2L
Change-Id: I5925c28821537f0e326b4f5a2ac39778e4724a3c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13131
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tidy up the code and move vga_textmode_init() later
Change-Id: I49967e7197416c955ae6c8775eac7d1a60c92d1c
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13128
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
- Fix bug with msbpos, it was not returning the correct result
due to typo in logic, and unsigned value needed to be negative.
- Add reclaim above 4GiB
- Fix to ME related registers near the end of raminit
Change-Id: I04acd0593a457437ee4a42e14b287b2b17a160af
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13127
Tested-by: build bot (Jenkins)
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Previously, 0xa0000000 to 0xc0000000 needed to be reserved as
a non-usable memory hole because it would hang on memory i/o.
Memtest86+ now passes with no errors on both channels populated.
Tested on GA-G41M-ES2L with 2x2GiB sticks of ram.
Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13125
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Just rename the two scripts that are in the src/ tree to give them
a .sh extension. Since we generally expect files in the src directory
to be source files, this allows to identify these as scripts easily.
Change-Id: I0ab20a083880370164488d37a752ba2d5a192fdc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13432
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This eliminates all "ud2" instances from romstage disassembly.
Change-Id: I3b0c8322a4ca4a851b0cce8f3941425d9cb30383
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/13488
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
zeroptr is a linker object pointing at 0 that can be used to thwart
GCC's (and other compilers') "dereferencing NULL is undefined"
optimization strategy when it gets in the way.
Change-Id: I6aa6f28283281ebae73d6349811e290bf1b99483
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: https://review.coreboot.org/12294
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add interface to program USB2_COMPBG register to set
HS_DISC_BG and HS_SQ reference voltage for each project.
TEST=Get build success and do EFT test
Original-Reviewed-on: https://chromium-review.googlesource.com/300846
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: shkim <sh_.kim@samsung.com>
Change-Id: If2201829e1a16b4f9916547f08c24e9291358325
Signed-off-by: Kenji Chen <kenji.chen@intel.com>
Signed-off-by: shkim <sh_.kim@samsung.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12739
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
DPTF should update the charger cooling device state during
boot time and every 3 seconds after boot. But 3 seconds polling
doesn't seems to be working with current version of DPTF.
This impacts charging since DPTF writes states 4 when charger
is not connected at boot time. On connecting the charger,
DPTF doesn't write 0 to enable charging. This issue is addressed
by calling the PPPC function to read cooling device state and passing
the value to SPPC to set cooling device state. This doesn't
compromise safety since DPTF can override this value
later based on the platform thermal condition. Also this provides
additional safety measure in the unlikely event that DPTF crashes
and is not re-spawned by OS. With this patch even after DPTF crashes,
if the power adapter is plugged it would still allow the system to
charge correctly.
Original-Reviewed-on: https://chromium-review.googlesource.com/288460
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Jenny Tc <jenny.tc@intel.com>
Change-Id: I50c7666b86e45d5ab537a9d4149e6c71eba04e50
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12729
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fish bowl HTML5 graphics benchmark with 250 fish
is not reaching 60 FPS. This change will update
the DPTF parameters to accommodate this test.
TEST=Run fish bowl benchmark with 250 fish
and check for 60 FPS.
Change-Id: I6b6827199cb0f5ab44c354abc477ea73e4de9ec5
Original-Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302208
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13484
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Disabling S5 wake from touch panel and trackpad
TEST=Build and boot the platform.
TEST=Poweroff platform -> enter PG3 -> remove AC -> close Lid
Plug AC in -> EC boots up and AP will shutdown the platform
and open Lid -> platform boots to OS.
Change-Id: I7b661a9f1327b97d904bac40e78612648f353e39
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/288970
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Reviewed-on: https://review.coreboot.org/13425
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The GPIO mapping was incorrect for wpsw_cur. The GPIOs for East
community are in two ranges - 0: INT33FF:02 GPIOS [373 - 384]
PINS [0 - 11] and 12: INT33FF:02 GPIOS [385 - 396] PINS [15 - 26]
The discontinuity was not accounted for, hence the error.Original
offset was 0x16 whereas it should be 0x13
TEST=Run crossystem and test wpsw_cur entry. If screw is present,
it should be 1 and if not present, it should be 0
Change-Id: I29e19589b3a358a42818afbc6d017d6cbc6a9c4c
Original-Signed-off-by: Kumar, Gomathi <gomathi.kumar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/291572
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com>
Reviewed-on: https://review.coreboot.org/13424
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Read GPIO to get the status
Change-Id: Id2d56ce4b47c4cccba2de3f113afaee6c49885c9
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13186
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is enabled
on this board
CQ-DEPEND=CL:13038
Original-Reviewed-on: https://chromium-review.googlesource.com/309190
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12749
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In set_max_freq, instead of using ratio from IA_CORE_RATIOS, using
ratio from MSR_IACORE_TURBO_RATIOS
Also, punit_init needs to be called before enabling this frequency.
Original-Reviewed-on: https://chromium-review.googlesource.com/295268
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iabdab9ec45f8eef0a105a5a05dbcdb997b6764b0
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12736
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Cleaning up code to remove support for early revs of Strago board
Change-Id: Ic0647a17d78164fd7dfadc731c9395a8ba08c235
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13434
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Set up the GPIO(MF_ISH_GPIO_4) to read WP status.
TEST=Use crossystem to read the WP status
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I17cbcba013e2a11c2527731df985aa1243065eff
Original-Reviewed-on: https://chromium-review.googlesource.com/302424
Original-Tested-by: John Zhao <john.zhao@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13185
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configuring Native Mode enables the card present bit in
sd card controller register.
TEST=Sd Card Plug/Unplug should work in OS and DepthCharge.
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I2f017bdd7125f324fb58a88485cd83110851fbc5
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12741
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The unused lines leads to spurious interrupts
on few of the systems.
TEST=run suspend_stress test and make
sure that kbd is working.
Change-Id: Ie539e1debc15dd1fd8707f8866c65714fc43e44b
Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313417
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13176
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The codec clock frequency was incorrectly set to 25MHz.
The only available frequency is 19.2MHz through external clock and PLL.
Original-Reviewed-on: https://chromium-review.googlesource.com/295768
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I9bef334a5a3aaee28fcc4937180896ff49969bc5
Signed-off-by: Felix Durairaj <felixx.durairaj@intel.com>
Reviewed-on: https://review.coreboot.org/12732
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
VGA grub console works but display wobbles left/right
drm/i915 driver reports one error:
- [drm:i915_irq_handler] *ERROR* pipe A underrun
- Monitor does not display 1920x1080 after modeset
- Other resolutions look out of sync
Cause: suspect single bug in raminit (chipset init)
Change-Id: I2dcf59f8f30efe98f17a937bf98f5ab7221fc3ac
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12921
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Remove include references to the soc include directory which are not
required to build the FSP driver. Remove "duplicate" include file
definitions from file that include fsp/romstage.h. Move the definition
of fill_power_state into soc/pm.h to ensure it is still available.
TEST=Build and run on Galileo
Change-Id: Ie519b3a8da8c36b47da512d3811796eab62ce208
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of tagging object files with .<class>, move them to a <class>
directory below $(obj)/. This way we can keep a 1:1 mapping between
source- and object-file names.
The 1:1 mapping is a prerequisite for Ada, where the compiler refuses
any other object-file name.
Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.
Change-Id: Idb7a8abec4ea0a37021d9fc24cc8583c4d3bf67c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13181
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
There were several spots in the tree where the path to a per class
object file was hardcoded. To make use of the src-to-obj macro for
this, it had to be moved before the inclusion of subdirs. Which is
fine, as it doesn't have dependencies beside $(obj).
Tested by verifying that the resulting coreboot.rom files didn't change
for all of Jenkins' abuild configurations.
Change-Id: I2eb1beeb8ae55872edfd95f750d7d5a1cee474c4
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
LPC_CLKRUNB pin needs to be set to PU_20K to prevent leakage
TEST=Test on Strago and make sure the leakage is gone
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: Id2bf7511806cdc52b505bb469238a9465b356352
Original-Reviewed-on: https://chromium-review.googlesource.com/317020
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Tested-by: Kane Chen <kane.chen@intel.com>
Original-Commit-Queue: Kane Chen <kane.chen@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13175
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Configure EC_IN_RW signal as gpio input.
TEST=Boot to Chrome OS in normal mode and enter recovery mode
use ctrl-d to switch to Dev mode.
Change-Id: I835a1c70d89ef2ab75c35233f889124b60bb64a3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/304040
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Gomathi Kumar <gomathi.kumar@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/13124
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This change includes following changes:
- Clean up the DDR configuration and flow.
- Removing support for non LPDDR3 boards.
- Supporting only LPDDR3 and PMIC config.
TEST=Build/flash CB and boot the platform to OS.
Change-Id: I8369443da728a4c07e0c1a82040d94034c3542da
Signed-off-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297941
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Jenny Tc <jenny.tc@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13122
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Fix GPIO config for this board:
- SD card detect to GPI
- SATA GPI to not used
- GPIO_SUS1 and GPIO_SUS11 to GPI with pull up (1K and 20K)termination
- I2C4 SDA and SCL from not used to Native
Change-Id: Iecb23df465a540a71f7268c5aac48617dc74ebf2
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13431
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Properly use the CONFIG_CACHE_MRC_SETTINGS value to determine when to
cache the MRC settings.
TEST=Build and run on Galileo
Change-Id: Ibc76b20b9603b1e436a68b71d44ca1ca04db7168
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13437
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The Intel Skylake RVP3 mainboard is not building, and according
to Intel, there is no plan to continue working on it for coreboot.
The intel/kunimitsu board is the Skylake reference design for
coreboot.org.
Change-Id: Icb4e42fdb560cc3188ca29c465674f5e0b11569b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13469
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This patch adds a check to the VPD parsing code to avoid reading the
whole thing if the first byte ('type' of the first VPD entry) is 0x00
or 0xff. These values match the TERMINATOR and IMPLICIT_TERMINATOR types
which should never occur as the first entry, so this usually means that
the VPD FMAP section has simply never been initialized correctly. This
early abort avoids wasting time to read the whole section from SPI flash
(which we'd otherwise have to since we're not going to find a Google VPD
2.0 header either).
BRANCH=None
BUG=None
TEST=Booted Oak, confirmed that VPD read times dropped from 100ms to
1.5ms.
Change-Id: I9fc473e06440aef4e1023238fb9e53d45097ee9d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 20a726237e03941ad626a6146700170a45ee7720
Original-Change-Id: I09bfec3c24d24214fa4e9180878b58d00454f399
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322897
Original-Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/13467
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds three timestamps to coreboot and the cbmem utility that
track the time required to read in the Chrome OS Vital Product Data
(VPD) blocks (RO and RW). It's useful to account for these like all
other large flash accesses, since their size is variable.
BRANCH=None
BUG=None
TEST=Booted Oak, found my weird 100ms gap at the start of ramstage
properly accounted for.
Change-Id: I2024ed4f7d5e5ae81df9ab5293547cb5a10ff5e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b97288b5ac67ada56e2ee7b181b28341d54b7234
Original-Change-Id: Ie69c1a4ddb6bd3f1094b3880201d53f1b5373aef
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322831
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13139
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
It's unused, so get rid of it.
Change-Id: I28c6dc0208686edc3aabaf624773ea70350c1c8f
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13177
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Added GPIO library code to allow all BSW board specific code
to use memory configuration GPIOs in GPIO Input mode and read
them to determine which memory type is on the board.
Also added other GPIO related APIs to support GPIO access
in BSW.
Original-Reviewed-on: https://chromium-review.googlesource.com/294893
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Idd65136c0449f0cdebfae12a510985e29889fa2b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12735
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
For the coreboot license header, we want to use two paragraphs.
See the section 'Common License Header' in the coreboot wiki
for more details.
Change-Id: I4a43f3573364a17b5d7f63b1f83b8ae424981b18
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13118
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This allows the native VGA to be disabled for debug, or if someone wants
to use the vbios.
Change-Id: I59a94fa0d02bfe254c8a598e15d3d9d73ecfe650
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12848
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
It ended up in .data, and that doesn't seem to be actually necessary.
Change-Id: Ib17d6f9870379d1b7ad7bbd3f16a0839b28f72c8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13134
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Use CBFS_AUTOGEN_ATTRIBUTES for mc_tcu3 to enable position
and alignment attributes in cbfs.
Change-Id: I6c39bb02ab641d7e22e20e77a72a577f159549dd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13123
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
The existing code accidentally truncated the MSB from the MR0
WR value. While this probably had a minimal effect in reality,
it should be configured correctly for maximal system stability.
Change-Id: Ifb8a39c6ca47b32b44d33735e5c6c39f1dc5a44e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13147
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The existing drive strength calibration code did not strictly
follow the BKDG-defined setup process. Bring the calibration
code in line with the BKDG recommendations.
Change-Id: I122eeb93958d88de59d0c3b2979f607afa2c52c3
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13145
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When an Extended Temperature Range DIMM is installed on a channel
the refresh rate should be increased per the BKDG recommendations
to allow correct operation at higher temperature ranges.
Set fast refresh on a channel if an ETR DIMM is installed on that
channel.
Change-Id: I7a085d34efc78f3f0794a5cb33b88f27a5e6d54e
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13144
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing CBMEM TOM calculations did not account for the CC6 save region
(when enabled); this resulted in CBMEM storage being placed on top of the
CC6 save region, which resulted in corrupt CBMEM data and a boot hang.
Change-Id: I32399da0438d7b16e05192449be625f9aa675b18
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13143
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing code unconditionally cleared the LDT tristate enable bit,
which was incorrect for C32 sockets. Update the code to be in line
with the BKDG recommendations.
Change-Id: I8095931973ea10f1467a6621092e88c6c494565a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13142
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The existing MCT initialization code was largely missing C32 socket-
specific configuration data. Add C32 socket-specific timing and ODT
values as specified in the BKDG.
Change-Id: I8eef8d5c8581f03d269663a338d5542744c5cdd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13141
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The existing code applied G34-specific speed limits to all socket
types. Update G34 and C32 specific speed limits to be in line with
BKDG recommendations.
Change-Id: I958ad333c47948ae741a56de5866af3e636fd24d
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13140
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was misspelled as EC_PURISM_LIBEM, causing the EC to not
get included in the build.
Change-Id: Iffbfb504926e1b90070c2dbf61c0c44ca8fb46bc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13178
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
When C_ENVIRONMENT_BOOTBLOCK is selected link bootblock using the
memlayout.ld scripts and infrastructure. This allows bootblock on
x86 to utilize all the other coreboot infrastructure without
relying romcc.
Change-Id: Ie3e077d553360853bf33f30cf8a347ba1df1e389
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13069
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Instead of solely relying on malloc for building up an address space
for the range_entry objects allow one to supply a list of free entries
to memranges_init_empty(). Doing this and only calling malloc() in
ramstage allows a memranges oboject to be used in a malloc()-free
environment.
Change-Id: I96c0f744fc04031a7ec228620a690b20bad36804
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13020
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.
Change-Id: Ibdc024ad90c178c4846d82c5308a146dd1405165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13133
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Replace with the more familiar AT&T syntax.
Tested by sha1sum(1)ing the object files, and checking the objdump that
the code in question was actually compiled.
Change-Id: Ie85b8ee5dad1794864c18683427e32f055745221
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13132
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=chrome-os-partner:47609
TEST=remove servo board connection and insert/remove an empty SD card
in recovery mode.
Change-Id: I89a1cb6914d634f07ff71b9793eb29b711381524
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d21bf091a576574cb9e976447ee2b9a69748d2b6
Original-Change-Id: I2083605c9ad88841885dfaad48dcd27e6fb5161d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313073
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13099
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Support memory range querying to above/below 4GiB.
Enable PRERAM_CBMEM_CONSOLE.
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: If12ab2e9b8a129e2c82dd97b0493d9abdd6985a9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 139a3163ca867ec5676c6cb81fdec724c99a4a99
Original-Change-Id: Ie190f86f49ae88671f0738e2d6ceafdad58a93cc
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292559
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13098
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=boot to kernel
Change-Id: I0630d7c172e97f81abb1722afe028542e9e7f106
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 608c66df0543c76be7e811b06718464776631b55
Original-Change-Id: I03426085121bfa44c99c351d63db28f567d0ee1d
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/313969
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13097
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Mimicking change I7037308d2, always compile mdelay for romstage.
The boards that #included delay.c in the romstage now rely on the linker
instead, which is a desirable cleanup.
Change-Id: I7e5169ec94e5417536e967194e8eab67381e7c98
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13115
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
BRANCH=none
BUG=none
TEST=build pass and verified on rev3
Change-Id: I3849342e59c2b022db723ef0281cdd5153ae27cb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 495e978cd7381bd393099315ac6d60fe4446dd9f
Original-Change-Id: I9626d06746e5d0bf6698a9b8e7594c58e7ff213a
Original-Signed-off-by: Ben Lok <ben.lok@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292689
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13096
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=build pass and test it ok on oak
Change-Id: Ib3d3f420dd576a63d7504dd0949040a3d430c675
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b17b03ed40b562a520185fa243bc4458daed6f23
Original-Change-Id: Ib9346f7913433ca82e8123feaf34fd0d6c071047
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292687
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13095
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=test it ok on oak-rev3
Change-Id: I05233c5b9aa237dce1e6667ed09fe6d56f8e6350
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb3efe8d0d1199ab836af01dc012cc97257b4fd4
Original-Change-Id: Ie1ab9421052dbd6aea8fbd762143cec0ce0d88f5
Original-Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297942
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13094
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Since backlight is controlled in depthcharge, we only configure
control pins as output pin and set them power-off in the coreboot
stage.
BRANCH=none
BUG=none
TEST=Saw DEV screen during boot process.
Change-Id: I3ed95e133417194ec8e774f42770bc61d879295f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e9628781801943903ba99ba1071aa374c6fc0754
Original-Change-Id: Ifd101f3e08698561d8516d83bc7d502d210e3b66
Original-Signed-off-by: YH Huang <yh.huang@mediatek.com>
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292686
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13093
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: I01eb059a3525bbbc5d17335cf43bc01be4355142
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13092
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=build and verified pass on oak board
Change-Id: I2680f6b87614362dffb27490bdeedf7125006c3f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bc2bb9f5b461ec848df8aba07940b895401004f8
Original-Change-Id: I848468cec04a36659fbb4b898dff9368305d72ac
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292683
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13091
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add a new function mt_pll_set_aud_div() to set APLL for audio I2S.
The function is called by mainboard's configure_audio().
BRANCH=chromeos-2015.07
BUG=chrome-os-partner:41507
TEST=build and verified pass on oak board
Change-Id: Ia3c2f250627028422a7427b93d78d49545eb7a75
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: bb18943f5e74af7723bd4e01d4da96c0b153a0f6
Original-Change-Id: I7996a8048f2e54ab09093cca3c8bc7447b61170f
Original-Signed-off-by: Koro Chen <koro.chen@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297225
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13090
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
BRANCH=none
BUG=none
TEST=none
Change-Id: Ic046c66c8e314bd61f96c2edbc5d832260590afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 84de3a6f1a726938e2318814d6faaf6a7dd29ac0
Original-Change-Id: If29f28a092617532dd73e71e0dbe24fd930c3bf8
Original-Signed-off-by: CC Ma <cc.ma@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292677
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12617
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
The mt8173 boot rom expects the bootblock to be in a certain format.
gen-bl-img wraps our bootblock appropriately.
BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I7486e548d356c5bd27261851f1f1bed620715e91
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbcd7959e0fda595de91899ace7236037ac833d3
Original-Change-Id: Ib9df440bfa95cf06e8041491ecdb34c357047acd
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292664
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12613
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for verstage
[pg: split original commit into multiple commits]
Change-Id: I8c9fe02f26bf8fa8381a7502a778bed300684986
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for verstage
[pg: split original commit into multiple commits]
Change-Id: Ia43bc72a1fb36c6fad5be5654abee5fc19fc4093
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13051
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
[pg: split original commit into multiple commits]
Change-Id: I0dc8d9855c98c077d4a47227de0c504c3a846953
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13050
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add more code to verstage
[pg: split downstream commit into multiple commits]
Change-Id: I578a69a1e43aad8c90c3914efd09d556920f728e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2827aa08ff8712c0245a22378f3ddb0ca054255d
Original-Change-Id: I94a9ee2c00e25a37a92133f813d0cd11a3503656
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292662
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/12612
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
We just had a user who spent a fair amount of time debugging a
failing build due to this option being enabled. Add a little
guidance that it probably shouldn't be enabled in the help text.
Change-Id: I9339e442876c1fcd18ea564041c6cc1201c18ae5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13066
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a new Kconfig variable to enable the generation of
position and alignment attributes for cbfs files which
has constraints on this parameters.
In addition, modify Makefile.inc to support that option.
Change-Id: Ibd725fe69a4de35964bdb2dde106d9a7c37ffb47
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12968
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This adds support for booting the Purism Librem 13 mainboard
with coreboot, using binaries extracted from the original BIOS
and from a Broadwell Chromebook.
The following features have been tested on Ubuntu 15.10:
- Input: Keyboard and Trackpad
- SATA: Internal HDD and M.2 NGFF
- Network: WiFi and Ethernet
- USB: Bluetooth, Camera, SD Card, Ports (1xUSB2 and 1xUSB3)
- Video: Internal panel and HDMI port
- Internal speakers and microphone (headphones do not work)
- EC handling for battery, AC, lid, special keys
These binaries are extracted from the original BIOS:
- VGA BIOS
- Management Engine
- Intel Firmware Descriptor
These binaries are extracted from a Broadwell Chromebook BIOS:
- MemoryInit reference code binary
- SiliconInit reference code binary
This was developed and tested on an Librem 13 device. For those
who may want to do more development you can use EHCI debug and the
right USB port to get coreboot output.
Change-Id: Ia72e2d7ddc8ba5eef63819e5677122a5a5c705d8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13026
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Platforms that need to initialize WRDD package with the regulatory domain
information should implement function wifi_regulatory_domain.
A weak implementation is provided here.
Original-Reviewed-on: https://chromium-review.googlesource.com/314384
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: I84e2acd748856437b40bbf997bf23f158c711712
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12744
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Get the WRDD domain code from VPD and put it in global nvs.
WRDD method in wifi.asl returns this value from global nvs.
This wifi.asl should be included in dsdt.asl under the root port where wifi
module resides.
Original-Reviewed-on: https://chromium-review.googlesource.com/314373
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Commit-Queue: Hannah Williams <hannah.williams@intel.com>
Change-Id: I809d28f10e80681471a785e604df102fb943a983
Signed-off-by: fdurairx <felixx.durairaj@intel.com>
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
SVID config set to SVID_PMIC_CONFIG
BUG=none
BRANCH=none
TEST=build, boot to OS and check the register is set properly
Change-Id: If63b8112d4da0347c3a2c4c6d82b12a1f618291c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/308576
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13117
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
WRDD method in wifi.asl returns the regulatory domain code. This value
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.
Change-Id: I6e96bdf0fe93ae30a3afdcb63a0f89ce21023704
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/13055
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
WRDD method in wifi.asl returns the regulatory domain code. This value
is read from VPD in wifi_regulatory_domain() and saved to global nvs if
CONFIG_HAVE_REGULATORY_DOMAIN is enabled. It returns default code if
CONFIG_HAVE_REGULATORY_DOMAIN is not enabled.
Original-Reviewed-on: https://chromium-review.googlesource.com/315131
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I52e0a052d31f36c6dc04e6a0953456350e7d86c3
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-on: https://review.coreboot.org/12746
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We already do this for lines with all zeroes, so it makes sense to
treat all ones the same, for symmetry.
Change-Id: I4b637b07a49e0c649331aa200995b474dd9a2682
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Updating EC+PD takes long enough to update that it is good to
show the "critical update" screen when doing an EC/PD update.
BUG=chrome-os-partner:49650
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.
Change-Id: I436b96b95595b68273e594bdcfe2db0789ee26b2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 08e45decd066f8f57ad103ff8b76cb7a916afa9e
Original-Change-Id: Ie250f4531437e4a0ce14b5aeb0fe564e9461fe4d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322783
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13075
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
In order to support vboot requesting graphics support in normal
mode the VBT needs to be passed to FSP when it is requested
outside of the usual developer/recovery path.
To make this integrate cleaner use the generic bootmode provided
display_init_required() function instead. Also have it print a
message indicating when it does not pass VBT to GOP so it is
easier to see what happened in the console logs.
BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Enable EC_SLOW_UPDATE on chell and test that when vboot
requests graphics support in normal mode FSP will get passed VBT
and bring up the panel.
Change-Id: I07bc54d37d687134b21baa60b5c278b5041241cf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 41efd322951b8f3a8a687944832bfd89fd3014ca
Original-Change-Id: I1b68760eabbf3af1d962cb2a3199e504a7852042
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322782
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13074
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Add flag handling for CONFIG_VBOOT_EC_SLOW_UPDATE to indicate
to vboot that it should show the "critical update" screen during
software sync for EC+PD.
In order to make this work on x86 where we do not run graphics
init in the normal path add handling for CONFIG_VBOOT_OPROM_MATTERS
and indicate to vboot when the option rom has been loaded.
BUG=chrome-os-partner:49560
BRANCH=glados
TEST=Build and boot on chell in normal mode with an EC update payload
and ensure that it reboots to enable graphics, shows the "critical
update" screen, and then reboots to disable graphics init again.
Change-Id: I5ca46457798a22e9b08aa2febfec05b01aa788f9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a1bb8572c3485f64b9f3e759288321b44184e66
Original-Change-Id: I9f66caaac57bb9f05bc6c405814469ef7ddf4d0a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/322781
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13073
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Override the default PL2 values with one recommended by
Intel. Disable PL1 configuration via MMIO register.
BUG=chrome-os-partner:49292
BRANCH=glados
TEST=MMIO 0x59A0[14-0] to find PL1 value (0x78) / 8 Watts = 15W
MMIO 0x59A0[15] to find PL1 enable/disable = Disable
MMIO 0x59A0[46-32] to find PL2 Value (0xC8) / 8 Watts = 25W
Here PL2 is set to 25W and PL1 is disabled.
Change-Id: I10742f91cc7179de1482d42392338976e8082afe
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b7771ccb34bdff92ffa9870733bd641e4644cdf
Original-Change-Id: Iefa93912008c71b41f2b20465e8acfd42bb6c731
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321392
Original-Commit-Ready: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Tested-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-on: https://review.coreboot.org/13070
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is a follow-up to CL:320623 to make veyron DRAM configs
uniform (except for Rialto).
As discussed in chrome-os-partner:43626, the mr[3] value and ODT
are set diffently for Mickey, thus the .inc files for other boards
have mr[3] = 1 and ODT disabled.
BUG=none
BRANCH=veyron
TEST=compile tested for veyron
Change-Id: I61798cfef779b0a3a510fd354ab53ffc63ca6c95
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3b7cea6331bcec8aba09a204060e093d3dd732cb
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab
Original-Reviewed-on: https://chromium-review.googlesource.com/321870
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13109
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Setup an initial rule to make use of the updatable CBFS regions in fmap.
Change-Id: I1fe1c6e7574854b735760c85590da6e297f6e687
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13060
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.
One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.
Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.
Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- While we're working on fixing clang for coreboot, mark it as not
currently working so that it doesn't look like a reasonable choice.
- Add help on how to make the toolchains
Change-Id: Ib37093ca98d0328fad40dd7886c98d00f78bd58e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13053
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We had another one that crept in while the linter was broken.
Change-Id: Ie690e2d7fc7ad31b3b674de1618723bb100ac961
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13056
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
commit a8aef3ac (cbfs_spi: Initialize spi_flash when initializing
cbfs_cache) introduced a bug that makes the rarely-used unified
CBFS_CACHE() memlayout macro break when used in conjunction with
cbfs_spi.c (since that macro does not define a separate
postram_cbfs_cache region). This patch fixes the problem by making all
three region names always available for both the unified and split
macros in every stage (and adds code to ensure we don't reinitialize
the same buffer again in romstage, which might be a bad idea if
previous mappings are still in use).
BRANCH=None
BUG=None
TEST=Compiled for both kinds of macros, manually checked symbols in
disassembled stages.
Change-Id: I114933e93080c8eceab04bfdba3aabf0f75f8ef9
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f270f88e54b42afb8b5057b0773644c4ef357ef
Original-Change-Id: If172d9fa3d1fe587aa449bd4de7b5ca87d0f4915
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318834
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12933
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Update Hynix memory configuration for mickey
so that it can boot on Hynix board.
BUG=chrome-os-partner:48637
BRANCH=master
TEST=Boot on mickey hynix board
Change-Id: Ibbf90cf76793005e23a720b97540b268ebf0864d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 071167b667685c26106641e6899984c7bd91e84b
Original-Change-Id: Id63d74cac36b9fd84bdb88969291982e14fa7d01
Original-Signed-off-by: Lang Zhang <kingsley_zhang@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320623
Original-Commit-Ready: lang zhang <kingsley_zhang@asus.com>
Original-Tested-by: lang zhang <kingsley_zhang@asus.com>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13048
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This provides symbols needed by CBFS and FMAP APIs, and allows running
run_romstage() in an x86 bootblock. Note that console-related files
are not added in this patch, as they are not essential for the
functinality on an x86 environment bootbock.
Change-Id: I36558b672a926ab22bc9018cd51aee32213792c2
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12880
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These files provide symbols needed by console and uart drivers. This
was not an issue in the past, as we were not setting up a C
environment this early in the boot process.
Change-Id: Ied5106ac30a68971c8330e8f8270ab060994a89d
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12869
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of depending BOOTBLOCK_CONSOLE on a set of architectures,
allow the arch or platform to specify whether it can provide a C
environment. This simplifies the selection logic.
Change-Id: Ia3e41796d9aea197cee0a073acce63761823c3aa
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Reviewed-on: https://review.coreboot.org/12871
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This header is only used for the bootblock compiled with ROMCC. As the
follow-on patches introduce a bootblock which does not make use of
ROMCC, rename this header to prevent confusion.
Change-Id: Id29c5bc6928c11cc7cb922fcfac71e5a3dcd113c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/12867
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Migrate google/tidus (Lenovo ThinkCentre Chromebox) from Chromium
tree to upstream, using google/guado as a baseline.
TEST=built and booted tidus with full functionality
Change-Id: I9d7a976345566bee63226d1a44ba7d5ec137a742
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12801
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This adds basic ACPI support for the EC used on Purism Librem laptops.
The EC firmware appears to use the topstar laptop interface that has
support in the linux kernel for handling the special keys.
Supported functions:
- Battery information
- AC presence
- Lid switch
- Special keys (after loading topstar-laptop driver in linux)
- EC events for turbo enable/disable when on AC power
Things it does not do:
- EC SMI handling
- Fan is left under EC control
This was developed and tested on a Librem 13 laptop, and has not
been directly tested on an Librem 15.
Change-Id: Ib85a24e4cc8ab09b14147060043cff372863c2d1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13025
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This driver adds an SMBIOS table for Intel WiFi, but if SMBIOS
table generation is disabled then it should not attempt to
compile or it will fail to find the "get_smbios_data" member
of the device_operations structure.
Tested by compiling and booting on purism/librem13 with
SMBIOS table generation disabled.
Change-Id: Iac6c265da7daae1be4d7585dab7b54561ff4e631
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13046
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This method creates named objects and must be serialized
to prevent a warning from IASL.
Tested by compiling purism/librem13 which includes this ASL.
Change-Id: Ic043ea479e681d2180421fcf8e0583b62e6fcd71
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/13045
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mediatek's bootblock needs mdelay, which depends on a udelay
implementation. Compiling the file for bootblock poses no harm:
Either udelay exists (in which case mdelay is usable) or it doesn't in
which case we see exactly the same kind of build time error (just with
udelay instead of mdelay).
Change-Id: I7037308d2d79c5cb1b05bb2b57a0912ad11cd7a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13049
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This tidies up the setting of the PCS register.
An assumption is made that bit 4 of this register is read-only,
which according to the ICH7 datasheet, it is.
Change-Id: Ia9b7d38a87e26236f6ebc951c169cae12b13139f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13015
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
Selecting Kconfig symbols that were created inside a 'choice' block
have no effect. Remove these so people aren't confused by them.
Change-Id: I7de9131d8d8afb65f86648afb9728f09cb67e122
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12970
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The error informing the user that the CPU device cannot be
allocated has a typo incorrectly spelling "allocate" as
"allocte".
TEST=Compiled
Change-Id: I2a6bad56133e375e2fd6a670593791414bf0dc2c
Signed-off-by: Jacob Laska <jlaska91@gmail.com>
Reviewed-on: https://review.coreboot.org/13030
Tested-by: build bot (Jenkins)
Reviewed-by: Ben Frisch <bfrisch@xes-inc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.
Change-Id: I1e9732e178bb8422b284d80d9f3d34b72f2e2415
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/13040
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Trivial fix for syntax highlighting in editors. Some get confused by
the double quote that doesn't have a close quote and stop highlighting
at that point. This comment closes the quote and the paren pair so
that they can recover.
Change-Id: I2bdb7c953a86905fc302d77eb9ad1200958800b7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The I2C data hold time can be vary on different boards/devices.
So, it needs to be customized by boards/devices
TEST=compile ok and check IC_SDA_HOLD is changed if the hold time
is defined in onboard.h
Original-Reviewed-on: https://chromium-review.googlesource.com/308623
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I66c799de400670916cebbcb529d4f59d5b0f081b
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/12740
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Set "nuvoton,sar-threshold" property to thresholds
based on tuning with the Android Wired Headphone
Compatibility Kit and Chell EVT.
Also set properties nuvoton,sar-compare-time and
nuvoton,sar-sampling-time.
The values of compare and sampling time align with
the ones from this CL:
https://chromium-review.googlesource.com/306372
Signed-off-by: Benson Leung <bleung@chromium.org>
BUG=chrome-os-partner:49333
BRANCH=none
TEST=Run evtest, selecting the input event for sklnau8825adi
Using the Nominal headphones from the kit, check that the
buttons for "KEY_VOLUMEDOWN", "KEY_VOLUMEUP", "KEY_MEDIA",
and code 582 (?) (should be voice search, but evtest doesn't understand)
All of these buttons should work properly.
Change-Id: I43dc1957f7d95744f41039a306d323806e66c56a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2bb545500afeb5b4fa0d1cd02dbf6453f19901ab
Original-Change-Id: I126aae1e5ed1b9e1a2429e8c94fe08b3ba3ca736
Original-Reviewed-on: https://chromium-review.googlesource.com/322243
Original-Commit-Ready: Benson Leung <bleung@chromium.org>
Original-Tested-by: Benson Leung <bleung@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13013
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
After comparing datasheets it appears to have the same geometry
and timings as the K4E6E304EE-EGCF part with just a new part number.
BUG=chrome-os-partner:49357
BRANCH=glados
TEST=build and boot on chell EVT (new part is not used until DVT)
Change-Id: Ia1e67080b1d79600e00c3ea8bee088ecafea2ab2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fb1488ca5ff780b5f1f937dbf0d23610c28204b2
Original-Change-Id: I09e1ce1a45a217afc88f422cf7db7924fad6b6f9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321956
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13011
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: If6955c9ee4f08d1ebc6e98e0ba0786073919856f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7403149299ec2c6c66c2066a5dd8294608e71409
Original-Change-Id: Ia182396ad4eb7a283e183fce7c50c98f6d2de57c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321212
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13009
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Enable serial irq configuration in FSP.
- Set minimum assertion width values for FSP to configure.
- Set I2C4 voltage to 1.8V.
- Enable SaGv feature to dynamically train memory frequency.
- Disable Deep S3 to match chell so DeepSx story is consistent
on skylake-y boards.
BUG=chrome-os-partner:47688
BRANCH=none
TEST=emerge-glados coreboot (tested on chell board)
Change-Id: Ied6bda6a3f2108df7167e0970abe71977d8d2a5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbf353288edc9629ad03b17d0a582e3042d5a5e1
Original-Change-Id: I1619dd5316060793f38b74f8f0bcaf23d8ab2552
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321211
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13008
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The keyboard backlight is very bright at 100% so be more
subtle when turning it on at boot time.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: I3925b94b4a455eb7d3bbb6eee414d21cf6d3bb93
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 52da1456527bfa6e0a3290c87c4886e2b3111e21
Original-Change-Id: Ia3412b4052c96f5de8e8aef59f69f6b346b9aca8
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/321210
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13007
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch adds an UPD/VPD parameter to set voltages to the
I2C ports individually via devicetree.cb
BRANCH=None
BUG=chrome-os-partner:47821
TEST=Tesed by setting voltage via devicetree.cb
and verified voltage level using a DSO probe.
CQ-DEPEND=CL:*242225, CL:*241206
Change-Id: Iaeb1ab3f9724aa1139c876dc63250469661d8439
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fc73b98529ad1eb187f97a4177beda4224f473d1
Original-Change-Id: Ib477ad26667ef59cd298b5e20a68a8c68d85bd8d
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315167
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13006
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Below are the correct RCOMP Target Values:
Samsung K4E6E304EB part = {100, 40, 40, 21, 40}
The rest of the DIMMs should have RCOMP set to
{100, 40, 40, 23, 40}
LARs EVT has new DIMM configurations, and the earlier RCOMP
settings are not correct for the newly added DIMM cards,
causing reboot issues.
With this patch all the DIMMs get the required values programmed.
BRANCH=None
BUG=None
TEST=Built for Lars EVT SKU1/2/3 and verified Boot to OS.
No Reboot after this change.
Change-Id: I5fa5ce47b4b47198b0ae8d0b57f7729cb57d23bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d29cc8a4ad9bc2b7680e4df146ce281738e4a3c4
Original-Change-Id: I15195b748213553907ff22dbc74651d70f3c7bb6
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320527
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13005
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Kingston eMMC can now run under HS400 mode.
BUG=chrome-os-partner:48017
BRANCH=none
TEST=run consecutive boot 100 times on Lars proto Kingston SKU, and
MMC errors didn't happen.
Change-Id: I3c16db6111273fbbabbfba1c315edc780fe23525
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ac474bd7bd33f11904a27691e9eb61bdaf212c6b
Original-Change-Id: I9e47b6ba64ac94acff7673fca86fa62bfb30edd9
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320194
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/13004
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change enables SaGv feature for skylake
platform. As a result of this patch the skylake
platform will train memory at both low & high
frequency points. This will be used to
dynamically scale the work point
(voltage/frequencies).
The value "3" here means enable. Following
is the table for same.
0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled( SaGv Enabled.Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Build and boot lars
Change-Id: I82b1a428d2d3dce47f46de576f677cf2249b6b5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e252123cc73543d0f1b320af9d8873f99a45ab1
Original-Change-Id: I1a545ff2f38df23964378c0d833e29006b2c5557
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/320022
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/13002
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in kunimitsu with SkipMpInit enabled from CB.
CQ-DEPEND=CL:310192
Change-Id: Idd9b1424f23765ce227005a322ac72d9e9fc841a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5c52d0f0cc5d480c87fababc3316009e3ade6e45
Original-Change-Id: I9d92046d0237680b8d562814a9a605a36efb9516
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/312926
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12992
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=none
CQ-DEPEND=CL:319353
Change-Id: I22c1add182b299e2ad9d413bc13c5a5acc6a3179
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ccf89c9d1fe18b74c385e7d12a6aef5b63d7b243
Original-Change-Id: I53b754fd10a140588ad67d9292d9bc04a6d43677
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319194
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13000
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
MP init is already handled in coreboot, but it is also part of FSP
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=Build and booted in Lars with SkipMpInit enabled from CB
CQ-DEPEND=CL:319353
Change-Id: Ib35d9072b883592d22466dfeb1fd45403c0479d4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91cf59ea7865568eca2ce242d81c4c486076d5ac
Original-Change-Id: Ibb46fc6bc7e862c9ea8bc9f9b0d508c3707282a2
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12999
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch disables the SaGv feature in recovery mode. Since the memory
training happens at both low and high frequency points when SaGv is
enabled, recovery mode boot time increases by 5 seconds. To reduce this
5 second increase, the SaGv feature is disabled in recovery mode.
The value "0" here means SaGv disable.
Following is the table for same.
0=Disabled (SaGv disabled)
1=FixedLow (Fixed to low frequency)
2=FixedHigh (Fixed to High frequency)
3=Enabled (SaGv Enabled. Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Results show recovery mode boot time
is not affected (not increased).
Change-Id: I77412a73a183a5dbecf5564a22acc6e63865123e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dc586079052acf9af573b68dff910386cd43484d
Original-Change-Id: Ice3e1a630e119d40d3df52e3a53ca984e999ab0b
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315759
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12998
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change enables SaGv feature for skylake
platform.As a result of this patch the skylake
platform will train memory at both low & high
frequency points.This will be used to
dynamically scale the work point
(voltage/frequencies).
The value "3" here means enable. Following
is the table for same.
0=Disabled(SaGv disabled)
1=FixedLow(Fixed to low frequency)
2=FixedHigh(Fixed to High frequency)
3=Enabled(SaGv Enabled.Dynamically changes)
BRANCH=None
BUG=chrome-os-partner:48534
TEST=Built for kunimitsu.
Tested on D1 silicon.
Change-Id: I2892d631d64495e6aed453af4fd526f4bf5bed68
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8e09d1a22927f5fcddd6c0be3f9edf3dcb8729be
Original-Change-Id: I32a7a53805068a52b381affaf061d69062cd8651
Original-Signed-off-by: haridhar <haridhar.kalvala@intel.com>
Original-Signed-off-by: Somayaji, Vishwanath <vishwanath.somayaji@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315806
Original-Commit-Ready: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Tested-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Haridhar Kalvala <haridhar.kalvala@intel.com>
Reviewed-on: https://review.coreboot.org/12997
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Functions in file pcie.c is not needed.
TEST=Boot and test wifi and video playback
Original-Reviewed-on: https://chromium-review.googlesource.com/298965
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I70337c0fc61c221330836ef17f6cefea8c5f0f11
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/12737
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
SSM4567 smart speaker needs Current and Voltage sensing to be
captured and reported to the algorithm.
This needs 4 CH capture blob.
BUG=chrome-os-partner:48625
BRANCH=none
TEST=Built and booted. Verified CBFS locates
the blob.
CQ-DEPEND=CL:*242635
Change-Id: Ie13622da9a9a8ce5930d32e52ddaf2e0d4862895
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 06f1a501dcb3fa6102eccdb3e24f9011b7869ab0
Original-Change-Id: I7b65b7582b619be53544ebbe4b3ea65398d32a34
Original-Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319020
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12995
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
All of the yabel files are BSD licensed.
Change-Id: Ibe0b3bb67a96c57b5d693676f5e8f19b6bed90fa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12972
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fixes bug that decode_pciebar() function was bypassed due
to PCI_DEV(0,0,0) being detected as zero and function returning 0.
Change-Id: Ia79bcebbe3ba36f479cbb24dbbb163a031d9c099
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13031
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
MP init is already handled in coreboot, but it is also part of FSP.
FSP has a implemented a provision to allow FSP to skip MP init and
let coreboot handle it.
BRANCH=none
BUG=chrome-os-partner:44805
TEST=none
CQ-DEPEND=CL:319353
Change-Id: I81c54582a3c980ecdcf329347bcd5982802d681c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e60ee81acaeb1062a31a3e78ed2ba4ccfe816ec5
Original-Change-Id: I71dd07559dffb7886e489274ffc8e71686ca730f
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319370
Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12994
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Lars has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=none
BRANCH=none
TEST=emerge-lars coreboot
Change-Id: I406b634176dac3f4cf1894e6b386af3306d11ffa
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 37d96458a11c33899f210cc04d3bdab07ec18746
Original-Change-Id: I017aeed1a8684676557e483ffa895dc4bb125d26
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319364
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12990
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The BOOT_BEEP gpio is used to activate the buffer which
isolates the I2S signals from PCH while doing a beep from depthcharge.
It needs to be lo to deactivate the buffer for audio playback from OS.
BUG=chrome-os-partner:47124
BRANCH=None
TEST=boot depthcharge & test beep with devbeep.
Boot OS and test audio playback.
Change-Id: I047513f6cbe9590820dfe3c369161a157864be97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d0e04d6792a4511630b8111d0f4a64226042f3e6
Original-Change-Id: I0fa8f425ac413798740343823d026c6300c8eef1
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319220
Original-Commit-Ready: Rohit M Ainapure <rohit.m.ainapure@intel.com>
Original-Tested-by: Michael Rang <michael.rang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12988
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The timestamps and post codes for the beginning of the FspNotify calls
are out of order. Reverse these entries to fix this error.
BRANCH=none
BUG=None
TEST=Build and run on kunimitsu
Change-Id: Ibfa1ba4b07e31bf3823469ac2dc7deaa8c67deab
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3cd63c56c59337f0ff58fd11a78d08352cf6a04a
Original-Change-Id: I4627860d3ebf446523a5662dbbc8e59153441945
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/318903
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12987
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The GPU panel configuration variables are unused on skylake
and are no longer needed in chip.h.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-chell coreboot
Change-Id: Ie6bfb676b5a32b4d4d39dda91b90fc7e973d38e0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f261d7ca9ec93aae1362975efde11ac9657b7ca6
Original-Change-Id: If64594455754e4dea1f53511861b74ddd880c5b5
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318923
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12986
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.
BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted chell
Change-Id: Ieb014e2a0cee1cb02a1c095da273b5ac1a19ef5d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fcd47a2fb2b369a93d2992fa1c17c2ce91c0e948
Original-Change-Id: Iac197314702fe5897359afc1ad1636bbcdafa204
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317870
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12985
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Use the Kunimitsu settings as baseline, except Psi4Enable set to 0 due
to a known issue (not able to hit S0ix) on glados. The VR settings will
then need to be updated per the board VR design.
BRANCH=none
BUG=chrome-os-partner:48466
TEST=Build and booted glados
Change-Id: I42d360657ab7c47d66043f39b79540b69a9072d1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d06397c1c32136d1b6a1c1346ed722ad6926ce1a
Original-Change-Id: Ib0746cd84c2c8af29f53a65a0a7b85966c918869
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317910
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12984
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
FSP 1.8.0 will do nothing with the VR settings if VrConfigEnable is
non-zero. That behavior is not desired because it's not clear what
the behavior will be for various processor SKUs. Instead provide
default values for the VR config. Note that PSI3 and PSI4 are not
enabled for those defaults.
BUG=chrome-os-partner:48466
BRANCH=None
TEST=Built and booted glados.
Change-Id: I02cb5fbdd4549cc827a0b0e4006bc21da4593b55
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a68c53e0fdf15584270dfafc679a22319f497d17
Original-Change-Id: I82b1d1da2cfa3c83ccc6a981e30ffac6fb6c8c4b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/318263
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12983
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Copy changes from chell to add 20K pull-up to LPC address lines
and setup the PCH_WP signal early so it is set correctly in VBNV.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I3337cb9e5ee445471c7a0b61ee22869f66189b63
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c99dae3729636790c2ad457ec3271d2bd99fb1c4
Original-Change-Id: I7627ec263e710ce186cea15c805203395acf3e99
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317244
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12982
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
There is a UPD setting exposed by FSP that allows the DDR
frequency to be limited. Expose this for devicetree.
BUG=chrome-os-partner:47346
BRANCH=none
TEST=tested by limiting DDR frequency to 1600 on chell EVT
Change-Id: I1f17b221d9fa4c2dd1e8c5f403deb0f2bc0493a7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 91f760ad19823225f7e5bd2dc690164ed253e220
Original-Change-Id: Ibcd4a65a9cfd7d32fbf2ba8843ab25da8e9cf28a
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317243
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12981
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The THERMTRIP status bit is in GBLRST_CAUSE instead of
GEN_PMCON like the EDSv1 indicates. Read this status bit
and add an elog event if THERMTRIP has fired.
BUG=chrome-os-partner:48438
BRANCH=none
TEST=tested on chell EVT after thermtrip fired
Change-Id: Icd52b753c7f3ab0d48095279f1255dd2dd08fd59
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b090c7897a8f99a685f523990235d83fafa063b2
Original-Change-Id: I5a287d7fdae2ba8ae8585cb9a4d4dd873393e1e6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317242
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12980
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
- Add pullup on LPC address lines for leakage
- Configure PCH_WP early so it gets set properly in VBNV
- Disable SD card reader in favor of USB
BUG=chrome-os-partner:47346
BRANCH=none
TEST=build and boot on chell EVT
Change-Id: Ibac79c6cbef0515b1e8a513cfde5fee184e4c70a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ebd0c16a6009b74d3c6c36878c502fda9bb3020d
Original-Change-Id: If2bc4eb546a1aab50d3688b6e92f8c38214c9cca
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/317241
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12979
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Follow kunimitsu setting of
https://chromium-review.googlesource.com/#/c/313068/
BRANCH=none
BUG=chrome-os-partner:48459
TEST=Build and boot in lars
Change-Id: Iffa9e1307f478b1d72befd3e5af71e7d40bb55ef
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6c669014d0773d6790656dd6f957d2c860d00781
Original-Change-Id: I615d53a33ad8e750d4382e2a9ec397c5b6ff55e1
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317222
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12978
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BRANCH=none
BUG=chrome-os-partner:48292
TEST=Build and boot on lars
Change-Id: I28fbbd690ca6efb539422e9ba02f10e07cd35346
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d229ba9d8934dcb5f22b27ce0ad27601ec87d6ff
Original-Change-Id: I64f2497a6bb3a50b0f58c67e2ab6751c4836fd89
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317130
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12966
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The HeciEnabled decides the state of Heci1 at end of boot. Setting to 0
(default) disables Heci1 and hides the device from OS. It internally uses
the FSP Psf Unlock policy to disable the Heci1. It also adds the p2sb
device in the devicetree which is necessary for hiding and unhiding the
device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu.
CQ-DEPEND=CL:*238451
Change-Id: Ieba2ab3b4ac518cce8371069028170ba99aaf079
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: cbefe9d6e9a981594534d346be67a5cd94483d05
Original-Change-Id: I8c95b5b9b28ba8441ca031f4e9ec523d913990d6
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311913
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12977
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This just updates existing guard name comments on the header files
to match the actual #define name.
As a side effect, if there was no newline at the end of these files,
one was added.
Change-Id: Ia2cd8057f2b1ceb0fa1b946e85e0c16a327a04d7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12900
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These were copied from the linux kernel, so get the standard corboot GPL
v2 header.
Change-Id: I27ef3326cc42b7e005f94c8b4fd355012a89561d
Signed-off-by: Damien Roth <yves.r.roth@gmail.com>
Reviewed-on: https://review.coreboot.org/13023
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These files are original to coreboot and get the standard
coreboot GPL header.
Change-Id: I19565b0d2424a6f37a95ab4d7b16742d23122d1e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12919
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Most of these files are original to coreboot and get the standard
coreboot GPL header.
encoding.h and atomic.h are from the riscv codebase and have their
license.
Change-Id: I32506b0ecf88be2f5794dc1e312a6cd9b2a271ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12906
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This was breaking the build on OS X, but also wasn't working correctly
under linux anymore either. It wouldn't print the illegal symbols
when it failed.
- Split the generation of the offenders file from the actual check for
offending symbols and just send all output to /dev/null.
- Rewrite the check for offending symbols in a way that works with OS X.
Tested by adding a global variable to romstage and verifying the
failure is shown correctly. Verified that it works correctly with no
illegal variables.
Change-Id: I5b3ac32448851884d78c3b3449508ffe014119ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch power gates the Kepler module
on skylake kunimitsu board. This is required
to save power since this is consuming over 500mw
of power in all active use cases.
The device can be powered on later by using the
kernel driver as required by setting the
kepler enable gpio high.
BRANCH=None
BUG=chrome-os-partner:45962
TEST=Build and Boot Kunimitsu and check lspci.
The Kepler device should not be listed.
Also power measurement of board should give
approximately 300mW of reduction in power.
Change-Id: I244a23385e20ef1431dc895536c8a47e1f5770d7
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8d4fb7d01f32ac307a351c307b8461628c0e5414
Original-Change-Id: Idafa74d7ff14d67a5b1e635f783efd84b5a7399c
Original-Signed-off-by: Pravin Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302277
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12964
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=chrome-os-partner:46335
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I311cc7d2e70cc52a7e90f3c3c60d422b7b998789
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ad9450c342c752f87e3385a2acd5dd79b65cc75f
Original-Change-Id: Ib7b1b40c296fce80d5366bd19e7ff20d7161db95
Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316287
Original-Commit-Ready: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Commit-Ready: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Original-Tested-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Pravin K Angolkar <pravin.k.angolkar@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12963
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
kunimitsu mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
Kunimitsu does support two audio codec, ADI and MAXIM,
hence use AUDIO_DB_ID to read correct codec and craete
NHLT table, this will also help to load only one amplifier ASL
for machine driver consumption.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted kunimitsu board. Audio worked
with both ADI and MAXIM audio card.
CQ-DEPEND=CL:316352
Change-Id: Ic9b9af83a0229fdf5f1cb019245ae65ad9d2f06c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2db85062d65c5e831da297588aa4abb18d6ed1bb
Original-Change-Id: I3b08f3f23b334799a81cde81a30d6f231cc8583f
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315450
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12959
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds support for disabling the heci1 device
at the end of boot sequence. Prior to this, FSP would have
sent the end of post message to ME and initiated the d0i3 bit.
This uses the Psf unlock policy and the p2sb device to disable
the heci1 device, then lock the configuration and hide the device.
BRANCH=none
BUG=chrome-os-partner:45618
TEST=build for kunimitsu or glados board. set the hecienabled policy
to 0 and check for heci 1 device status in kernel lspci.
CQ-DEPEND=CL:*238451
Change-Id: I26b145231f8ed0c140af42d378b222e857d9aff6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fe184b8baf1bea9bcd0af1841785a4d763af9358
Original-Change-Id: I3b435491aeea0f2ca36b7877e942dc940560e4dd
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/311912
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12976
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
CB used to clear recovery status towards romstage end after FSP
memory init. Later inside FSP silicon init due to HSIO CRC mismatch
it will request for an additional reset.On next boot system resume
in dev mode rather than recovery because lost its original state
due to FSP silicon init reset.
Hence an additional 1 reset require to identify original state.
With this patch, we will get future platform reset info during romstage
and restore back recovery request flag so, in next boot CB can maintain
its original status and avoid 1 extra reboot.
BUG=chrome-os-partner:43517
BRANCH=none
TEST= build and booted Kunimitsu and tested RO mode
Change-Id: Ibf86ff2b140cd9ad259eb39987d78177535cd975
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 40ddc21a97b318510116b7d5c4314380778a40f7
Original-Change-Id: Ia52835f87ef580317e91931aee5dd0119dea8111
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/302257
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12975
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Enable the config option for TPM to use PIRQ instead of SERIRQ
and enable the MAINBOARD_HAS_LPC_TPM option.
BUG=none
BRANCH=none
TEST=tested this patch with TPM ACPI driver(tpm_tis.force=0)
Change-Id: I761d623d1064b8030f2703500d174259bb20ca79
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2f7bdb1091b7dd62a3c0b4a2272ab9f56fd7acc9
Original-Change-Id: Id1a867980d2e28a1f328aa36bed3c846b2137bec
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317471
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12974
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
At S0, S0ix and S3 LPC LAD signals are
floated at 400~500mV.
BRANCH=none
BUG=chrome-os-partner:48331
TEST=Build and boot on lars
Change-Id: I5582007e5caaf444740fa71c9761c27614aafee2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b855fd5834056a3f7d4aef91d634066006990a38
Original-Change-Id: I3a54f9f83f055e433cc1fea38169437ee7f9188f
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317071
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12965
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Count DIMMs on current memory channel instead of all memory channels.
The current code is only able to correctly handle the following memory
configurations:
One DIMM installed in either channel.
Four DIMMs installed, two in each channel.
Two DIMMs installed, both in the same channel.
For systems that have any other configuration the DRAM On-Die-Termination
setting is wrong.
For example:
Two DIMMs installed, one in each channel.
Test system:
* Gigabyte GA-B75M-D3H (Intel Pentium CPU G2130)
Change-Id: I0e8e1a47a2c33a326926c6aac1ec4d8ffaf57bb6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/12892
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
Remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and boot on lars
Change-Id: I48d3b706517b6ea6bda44800f61bb11da64503fb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eab69f2d725df739e5e0e5901a581ad58732cdf9
Original-Change-Id: I42c5a87150638171526ee67f194c1cd9d155203b
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/317080
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12962
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
lars mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted lars board.
Audio worked with MAXIM audio card.
Change-Id: I1b7836c685ebbe1498f3dbaa2eb64d5e0d4faabb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 401f1a7b23dca19712517ed1588e1390769d1271
Original-Change-Id: I6a937872a9e10d2c5ea15d5952d23e98416df092
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316092
Original-Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12961
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This corresponds with the changes that have already gone into the
soc/intel/skylake chip.h file and is needed to get skylake platforms
building again.
Change-Id: I15bfee4eff50d6632659953ec8f97a39d8810db3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13022
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
I don't think the warning is valid, because we already verify
that num_channels is 2 or 4 as soon as we enter the function.
Adding the default case makes the compiler happy.
Fixes warning:
src/soc/intel/skylake/nhlt/dmic.c: In function 'nhlt_soc_add_dmic_array':
src/soc/intel/skylake/nhlt/dmic.c💯2: error: 'formats' may be used
uninitialized in this function [-Werror=maybe-uninitialized]
return nhlt_endpoint_add_formats(endp, formats, num_formats);
^
Change-Id: Idc22c8478ff666af8915d780d7553909c3163690
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Make sure the latest & greatest Intel targets actually
build in our build system.
intel/sklrvp is still failing for reasons unrelated to the rest
of the skylake boards. Leaving that disabled for now.
Change-Id: Ie784628a57257cea30e5e47074648198b884f6db
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12857
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
remove the WakeConfigWolEnableOverride to disable WOL override
configuration in the General PM Configuration B (GEN_PMCON_B) register
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
Change-Id: Ia523e7956c06c9f4a60e0a2296f771cc3c70bc25
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 12a07eebfb8fa4ee8013fbbb12283a0b429cacfd
Original-Change-Id: I2be6c5b0114e4c7d8a7b9ceb59ee32f28f61769f
Original-Reviewed-on: https://chromium-review.googlesource.com/316717
Original-Commit-Ready: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Tested-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12958
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Skylake Core boot should have configurable option to skip
PCH based SD 3.0 Controller from customer/reference design.
Addition to that no unused or unnecessary should list under
device view.
BUG=chrome-os-partner:48190
BRANCH=None
TEST=Build & boot Kunimitsu and LARs.
Change-Id: Ie17fd6db01e0cabcdf605017509d809b54509a0d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 99ac17b723125822368539d0562aa35119e520fb
Original-Change-Id: I98a48f45ef442246227fd54ea021b53f824954c5
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315420
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12946
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Even though the data32 variable was getting written by
pch_pcr_read(), GCC still flagged it as being used while
uninitialized and failed the build.
Note that pch_pcr_read() may only set 1 or 2 bytes of data32 in the
successful path, depending on the size of the read.
Change-Id: Icd6e80d06b9bf4af506d62d55ffe4c5e98634b2b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12860
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Ben Gardner <gardner.ben@gmail.com>
Tested on Intel D510MO
Before this patch, I was unable to get the SATA controller into AHCI
mode. That is, I could never see PCI ID 8086:27c1 appearing on the bus.
With sata_ahci set, controller now goes into AHCI mode and works. 8086:27c1
Tested on X60 with AHCI enabled 8086:27c5 (AHCI mode for mobile ich7)
No regressions detected.
Change-Id: I4a3eabb5773106a0825fa2f30ee400fbfe636c7f
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12923
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Some more PCH Policy UPD Parameters are added in FSP.
Lockdown config moved from FSP to coreboot.
Removing settings in devicetree.cb which are zero.
BRANCH=none
BUG=none
TEST=Build and booted on kunimitsu, verified that CB is doing
the Lockdowns which were previously done by FSP.
CQ-DEPEND=CL:*237842, CL:310191
Change-Id: I3dcf3a5340f3c5ef2fece2de5390cde48db4d327
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8bdb35897b640d271adcaed266030367f060553
Original-Change-Id: Ia201672565c07b2e03d972b2718512cd4fcbb95c
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310869
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12941
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Some MemoryInit UPD parameters have been moved to
SiliconInit in FSP 1.8.0. This patch has the respective
changes in coreboot for this.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu
CQ-DEPEND=CL:*237423, CL:*237424
Change-Id: Ic008d22f96fb5f14965e5b5db15e05fb39dd52d3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 573c1d8325cd504213528030ecf99559402b5118
Original-Change-Id: I71b893aa7788519ed2ef15f3247945ffcbbbcf4d
Original-Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/310191
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12940
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
GPIO ASL APIs to get GPIO Value.
Need such APIs to read GPIO config settings.
Example: Kunimitsu need to read AUDIO_DB GPIO
to identify codec select.
BUG=chrome-os-partner:44481
BRANCH=none
TEST=build and boot on Kunimitsu.
Change-Id: If56bb7b3eae08e1949d372850a6426dfde5aadd0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4983ba835a8da2baf578b035ae482755983c1ecb
Original-Change-Id: Ia40d86c8d4b14857fa8822677b3f7d393a35b677
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316352
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12956
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
DPTF may power off the system when it starts if the CPU temp is >90C.
Since TJmax is 100C set the critical threshold to just below that value.
BRANCH=none
BUG=none
TEST=Build and boot on lars.
Change-Id: I3abf946ae09c3c691480e468d0c1d74730dc6c06
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7c2230009edb840e88a20c2d8a87f942c09b6bf3
Original-Change-Id: Iee1a3596dbbe934f68637f012c02c078c3751eeb
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316102
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12955
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Disable kepler device, it is removed and was not used on proto anyway.
BUG=none
BRANCH=none
TEST=build and boot on lars proto
Change-Id: I137b82b8dca23f5b40adcc6a056e77a4ff54d4d5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 44d63453a9b31331d13d05f8f86d4218af0f0aa1
Original-Change-Id: Ib0892bf93b1d0cda1c0143d2b16cd58aeda83131
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/315950
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12950
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The write protect GPIO is not being configured early enough.
This is leading to coreboot reading incorrect value, and
writing the incorrect value in vboot shared file.
This is leading to "crossystem wpsw_boot" always returning 0
even with the write protect screw in place during boot.
BUG=chrome-os-partner:48292
BRANCH=None
TEST=Boot with the write protect screw in place. Issue
crossystem wpsw_boot. It should show 1.
Change-Id: I3a333a4dcce31be9afe28cf11b127090cc7b9421
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 462dd0229c2d3b81cd34bdd2e36bea844f58586c
Original-Change-Id: Ib7e0539845575b32322e243e89b81ffee077eb81
Original-Signed-off-by: Arindam Roy <arindam.roy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316009
Original-Commit-Ready: Arindam Roy <rarindam@gmail.com>
Original-Tested-by: Arindam Roy <rarindam@gmail.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12952
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=none
BUG=none
TEST=Build and booted on lars.
Change-Id: Ic1313385e0aa1760b473a34c853a95c76257eecf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a47faee53e08da81602b485937621fd49eb2ddbf
Original-Change-Id: I7c91dcdc82525a6d2b706f8f504ba48601097ef7
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316370
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/12953
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
modify the P/N in samsung K4E6E304EE-EGCF SPD from K4E6E304ED-EGCE to
K4E6E304EE-EGCF
BRANCH=none
BUG=chrome-os-partner:48299
TEST=build chell and use gooftool to probe and P/N match
Change-Id: Ie560e5c0d4b9a3cfb34c3856911930fb8159764e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: dabe5eaa8abf54f4e4a5492062adca6ef9b4634d
Original-Change-Id: Ie8d44ac6032e5213928bfae2a2ac5877d4193d62
Original-Signed-off-by: Wisley <wisley.chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316100
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12951
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: Iaf910041453695b7125b254ca5d71e8ccbd0b02f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ea77d326ba1c33b100c34066ed361a55dfa14ce3
Original-Change-Id: I5d93c3a7fa4cf68ba91f1398b4bd04504a28fef2
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/315520
Original-Tested-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12948
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Provide an option for including the NHLT blobs within the
glados mainboard directory while also adding the ACPI NHLT
table generation that the current hardware supports.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built and booted. Headphones, speakers, and mic on camera
emits and creates sound albeit not the greatest.
Change-Id: I6e36c0a99a73cdcb2bf6ccfbfc886a594f989a39
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5b0383a93f054011dd7c18519ece4e6f1944366d
Original-Change-Id: I6f8bd15c72fa89756382af99bddb6cb6abe89905
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313794
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12939
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The use of a NHLT table is required to make audio work
on the skylake SoCs employing the internal DSP. The table
describes the audo endpoints (render vs capture) along with
their supported formats. These formats are not only dependent
on the audio peripheral but also hardware interfaces. As such
each format has an associated blob of DSP settings to make
the peripheral work. Lastly, each of these settings are provided
by Intel and need to be generated for each device's hardware
connection plus mode/format it supports. This patch does not
include the dsp setting blobs.
The current supported connections:
- digital mic array 2 channel
- digital mic array 4 channel
- Maxim 98357 amplifier
- ADI ssm4567
- NAU88L25 headset codec
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Built glados. Speakers, headphones, and mic on camera decently
worked.
CQ-DEPEND=CL:*239598
Change-Id: If1a9be97573b9b160893944661790cac7df26fca
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1f5514e27811c500732de97e1cc7edeced2607e7
Original-Change-Id: Ib42e895f00e7605cb30ce24d9b8dd00bf68a7477
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/313998
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12938
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Intel's SST (Smart Sound Technology) employs audio support
which may not consist of HDA. In order to define the topology
of the audio devices (mics, amps, codecs) connected to the
platform a NHLT specification was created to pass this
information from the firmware to the OS/userland.
BUG=chrome-os-partner:44481
BRANCH=None
TEST=Tested on glados. Audio does get emitted and some mic recording
works.
Change-Id: I8a9c2f4f76a0d129be44070f09d938c28a73fd27
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2472af5793dcffd2607a7b95521ddd25b4be0e8c
Original-Change-Id: If469f99ed1a958364101078263afb27761236421
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/312264
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/12935
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, the Power Limit 1 (PL1) value is 6W which is
low for high performance KPIs. This patch updates PL1
value as TDP. SKL-U has 15W TDP.
BRANCH=None
BUG=None
TEST=Built and boot on kunimitsu. Check for the PL1 value over
sysfs interface
"/sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw".
Load the system with Aquarium 1000 Fish, average FPS should be
meeting target 60 with this change.
Change-Id: I8e083192e8018edc2cf8b88530df1e05ede10bde
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: eb9aa00a4271875b5471c33883aa7da022f1cb0e
Original-Change-Id: I0c61fe1a9f76a9cf9a306240fb66d4c081d2bb5e
Original-Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/314416
Original-Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Tested-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/12934
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
memmove.c came from the linux kernel, so also gets the standard
coreboot v2 license header, but gets the added attribution that it
was derived from the linux kernel. Unlike many coreboot files,
this file may not be re-licensed as GPL V3.
Change-Id: I1fdc26b543e059f7a42d4b886f7222f4c74b959d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12916
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
thermal.asl was written as part of the coreboot project, so gets
the standard coreboot license header.
ec_commands.h came from the chrome ec tree, so gets the BSD license
from that tree as mentioned in the header that has been replaced.
Change-Id: I514138fd4ed236105998b25d1d2d8eb8441cf91d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12918
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These were mostly written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: Ief13339647d3172e65bb18e6dcb54312a5c9472e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12917
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I51e1e504b3bc7be2a00c9356d8775b87f2a1db5a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12912
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The read and write routines take a number of bytes to write, which
should be 1,2, or 4. We now return an error if an invalid size
is specified.
Change-Id: I93344bc0837c3715fc7660503f405c8878eb711c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12936
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Values are taken from the vendor BIOS of my X200s. Notable effect:
Stops display from flashing during native graphics init / Linux mode
setting.
Change-Id: Ie5d9efc010a78dd46317b6bbdb7bfacc2c9d2cbf
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Register settings are the same as on newer chips (compare sandy-
bridge), just at different locations.
Change-Id: Iea0359165074298a376e0e2ca8f37f71b83ac335
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12885
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Skip everything but the final setting of PP_CONTROL, i.e. triggering
the power up. The settings with PANEL_UNLOCK_REGS are useless as no
lockable registers were touched in between. Also the loop waiting for
the panel power up to finish was a no-op as the registers with the
power timings were never filled (see follow-up commits).
Change-Id: Ife27dcafdf197b2246c4e69f2bf7a3a6765d1d82
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/12884
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The century byte is used by most RTC (default 0x32@nvram).
Even the century byte can disabled via ACPI it's more safe to reserve
it's space. Because some RTC will act with that byte anyhow.
Some OS overwrite it when syncronize the RTC.
Change-Id: I078c0c57215ccb925afa85b9d067f15268801ec9
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-on: https://review.coreboot.org/11853
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I4fccc8055755816be64e9e1a185f1e6fcb2b89ae
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12911
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These were all written as part of the coreboot project, so get
the standard coreboot license header.
Change-Id: I74438e8032c84f4190ef49f306969f7157234001
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12910
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This continues what was done in commit a73b93157f
(tree: drop last paragraph of GPL copyright header)
Change-Id: Ifb8d2d13f7787657445817bdde8dc15df375e173
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12914
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Because these platforms haven't been getting build testing, they've
missed out on some of the improvements that the other platforms have
gotten.
Enable MAINBOARD_HAS_LPC_TPM so that they will build.
Change-Id: I5e44135b6dfa800fa14e5b08c3e3e5921d50b082
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12865
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Don't redefine D0F0_PCIEXBAR_LO, use the #define in x4x.h
- Move TPMBASE and TPM32() definitions into iomap.h
- Use "" style include for x4x.h in nortbridge files.
- Move includes of .h files out of x4x.h and into the c files that need
them.
- Protect function definitions in bootblock.
Change-Id: I3fdb579235c5446733a0ffba05fffe1a73381251
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12849
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This method of reporting has been removed from the current Skylake
ME binaries so is no longer needed.
Change-Id: I774982146c19f37418f5aee29ae8883fcd3d0c8c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12854
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Migrate google/guado (Asus Chromebox CN62) from Chromium tree to upstream,
using google/auron and google/panther as refs.
TEST=built and booted guado with full functionality
Change-Id: If7a500fb408197a61c9619b9d5ea1458d1f4d702
Tested-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12800
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
There's nothing in these files that needs to be hidden if
GOP support is disabled. Removing this allows skylake to
build when GOP support is turned off.
Change-Id: I2a4f47cd435f48668311719f388b502ae77eca99
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12859
Tested-by: build bot (Jenkins)
Reviewed-by: York Yang <york.yang@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Since only X220 with i7 have the USB3 controller this was
probably overlooked.
Before this patch lspci on Linux would not show the NEC USB 3 controller
as well as the PCI bridge it is behind. After, both the bridge and the
NEC controller can be found in the output:
05:00.0 USB controller: NEC Corporation uPD720200 USB 3.0 Host Controller
(rev 04)
Change-Id: I5e7e3f0c7d023f6206a7bec42a39f8955a3d9331
Signed-off-by: Marian Tietz <mtcoreboot@gmail.com>
Reviewed-on: https://review.coreboot.org/12882
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
I think this has a fairly low likelyhood of happening, but if AGESA
can't determine the voltage of the memory, it assignes a value of 255
to the variable that it later uses to read from an 3-value array. There
is an assert, but that doesn't halt AGESA, so it would use some random
value. If the voltage can't be determined, fall back to 1.5v as the
default value.
Fixes coverity warning 1294803 - Out-of-bounds read
Change-Id: Ib9e568175edbdf55a7a4c35055da7169ea7f2ede
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12855
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This just tells the OS that it can use the 16GB of address space
at the 48GB mark for PCI. This is the upper 16GB of Bay Trail's 36 bit
physical address space.
This could be hardcoded into the UMEM definition, but doing it this way
makes it more plain what it's doing, and allows for modification
to put it just above the top of upper memory, similar to what is done
with the standard PCI region above the top of low memory.
Change-Id: Id6208c3712e5d94d62a83c4ac69e8ffd0e19f4ad
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12791
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: York Yang <york.yang@intel.com>
The Braswell IFD & ME blobs aren't published in the 3rdparty repo, so
disable them by default for now.
Change-Id: If68ff1f37fbf7afb2f9eb1e5d9942afcf40ab1e3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12828
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This has been broken out from http://review.coreboot.org/#/c/10581/
Change-Id: Ia6153115ff75e21657fa8c244c9eb993d0d63772
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/11025
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Since the GOP drivers aren't published in the 3rdparty blobs repo yet,
disable the GOP support for now so that abuild can build these
platforms.
Change-Id: Ic98671c163b433ebde89c8bf240ef4b2be393586
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12829
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
When microcode updates are enabled, this fixes an issue identical
to that described in GIT hash 7b22d84d:
* drivers/pc80: Add optional spinlock for nvram CBFS access
Change-Id: Ib7e8cb171f44833167053ca98a85cca23021dfba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12063
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The AMD Family 10h/15h processors use a TSC that increments at
the P0 core frequency. Allow coreboot to query the TSC frequency.
Change-Id: I73ead4fd4af18991452d59985b667a54689778cd
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12834
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This reverts commit 65e33c08a9.
This was the wrong logic to fix the master header.
Change-Id: I4688034831f09ac69abfd0660c76112deabd62ec
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12824
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The Braswell CPU seems to have two different Video BIOS roms, one for
the C0 revision, and one for other revisions. Build them both into
the coreboot image, and let coreboot sort out which one should be used
at runtime. This should allow one rom to be used for all revisions.
The initial reason for this patch was that the Kconfig symbol
C0_DISP_SUPPORT didn't exist, and was causing issues. This
seems like the best way to eliminate the need for that symbol.
Change-Id: I5b9f225c0daf4e02fda75daf9cd07bb160bf0e0f
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12826
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide a common routine to hash the contents of a cbfs
region. The cbfs region is hashed in the following order:
1. potential cbfs header at offset 0
2. potential cbfs header retlative offset at cbfs size - 4
3. For each file the metadata of the file.
4. For each non-empty file the data of the file.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized in chromeos cros_bundle_firmware as well as at
runtime during vboot verification on glados.
Change-Id: Ie1e5db5b8a80d9465e88d3f69f5367d887bdf73f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12786
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
We will soon need to handle empty files.
Change-Id: Ia72a4bff7d9bb36f6a6648c3dd89e86593d80761
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/12785
Tested-by: build bot (Jenkins)
Some of the files need to be adjusted so that they can be used
both in cbfstool as well as coreboot proper. For coreboot,
add a <sys/types.h> file such that proper types can be included
from both the tools and coreboot. The other chanes are to accomodate
stricter checking in cbfstool.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Built on glados including tools. Booted.
Change-Id: I771c6675c64b8837f775427721dd3300a8fa1bc0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12784
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
To continue sharing more code between the tools and
coreboot proper provide cbfs parsing logic in commonlib.
A cbfs_for_each_file() function was added to allow
one to act on each file found within a cbfs. cbfs_locate()
was updated to use that logic.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.
Change-Id: I1f23841583e78dc3686f106de9eafe1adbef8c9f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Provide a helper function which returns the relative offset
between 2 region_devices that have a parent-child child relationship.
BUG=chrome-os-partner:48412
BUG=chromium:445938
BRANCH=None
TEST=Utilized and booted on glados.
Change-Id: Ie0041b33e73a6601748f1289e98b6f1f8756eb11
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/12782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The code committed in GIT hash
* 1eaaa0 southbridge/amd/sr5650:Add MCFG ACPI table support
did not correctly locate the CPU MMCONFIG resource, leading to failures
with operating systems and firmware (e.g. SeaBIOS) when the PCI
extended configuration space option was activated.
Due to the southbridge routing not being set up, MMCONFIG accesses were
targetting DRAM and therefore the PCI devices were not being configured.
The failure normally manifests as a system hang immediately after PCI
configuration starts.
Search for the CPU MMCONFIG resource on all domains below the root
device.
Change-Id: I0df2f825fef2de46563db87af78d0609ab3d8c5a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12821
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This reverts commit d3deecdd9c.
Do not mix open-source AGESA and binary PI trees. Once you have
working S3 support for binaryPI platforms, add the adapted
oem_s3.c file as northbridge/amd/pi/oem_s3.c instead.
Change-Id: I7c981d0023a5c0225e046f9c0104acfa07436b79
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/12282
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Make the low-power and small form factor (SFF) options overridable
from romstage main. Also disable both options by default. That's ok
as there aren't yet any in-tree users of the GS45 chipset. As a nice
side-effect, this adds X200s support to the lenovo/x200 port.
Change-Id: I94373851262e6d424cf4885ceca7260c31bc9f61
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12814
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
All southbridge interrupt pin and routing registers (D*IP and D*IR)
are left at their default values (see ICH9 datasheet) and this file
just has to reflect them.
Change-Id: I687262556d918311757fda9afda9ebfdd7edf947
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12813
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Set up External Temperature to read via thermal diode/resistor
into TMPINx register by setting thermal_mode switch.
Original-Signed-off-by: Ted Kuo <tedkuo@ami.com.tw>
Change-Id: I0e8621b92faa5c6246e009d2f852c8d4db484034
Original-Reviewed-on: https://chromium-review.googlesource.com/260545
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Tested-by: Ted Kuo <tedkuo@ami.com.tw>
Original-(cherry picked from commit 973e2d393f2595b756f8aa20f6fbe3b6e045621a)
Original-Reviewed-on: https://chromium-review.googlesource.com/262340
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12798
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The RPU Clock register defaults to on for all clocks.
This is modified to OFF, and the MIPS clock control modified to ON,
by default. This is because the linux kernel will manage the
clocks at all times, but the RPU can only disable clocks if the WIFI
module has been loaded.
Change-Id: I155fb37afd585ca3436a77b97c99ca6e582cbb4f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
GRAM is 421056 bytes. The end of the SRAM region (GRAM plays the role
of SRAM) was placed at a 4K aligned address, resulting in a size of
408KB.
Change-Id: I9fa32ab818d600e7447bcac895e4b8c438f2f99d
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The base address for the I2C dividers (DIV1 and CLOCKOUT)
was erroneously set to the toplevel clock controller base
address and not to the correct peripherals clock controller
base address.
Change-Id: I66bbc1e741bcf6251babee7ddd6376d49d7cb3d1
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12771
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This region must be mapped uncached. This is necesary for an
U-boot payload which will obtain all register base addresses
as physical addresses from the device tree and will use them
as such.
Change-Id: Ib5041df7d90c6ef61b7448a18dd732afbd9489ca
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12770
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
When used with a U-boot payload it will need this region
identity mapped also, so we're defining it in preparation
for that functionality.
Change-Id: I27cee5b58cb899433b52bd06df07b5f2105212af
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12768
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Use SYS PLL in integer mode by default to reduce jitter.
DSMPD_MASK is defined and can be used to switch to fractional mode.
Tested on pistachio bring up board.
Change-Id: Ie6d2aca71c7af86b0993c804329e6d03e26ff754
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12767
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Board uses x4x native raminit
Board boots into Debian 8 with full graphics
IRQ9: nobody cared, gets disabled
(PIC needs IRQ settings?)
VGA:
- VGA native init works in grub with analog connector
- Fails to boot with both channels of ram populated
Change-Id: I7417813456817529b8cbaace45cefe47467d0a82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11306
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Passes memtest86+ with either one or two sticks of 2GB ram
but memory map needs a hole at 0xa0000000 to 0xc0000000
Change-Id: Ib34d862cb48b49c054a505fffcba1c17aeb39436
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11307
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This code looks like it was created from a disassembly of some
other driver. Attempt to fix it, without hardware or documentation.
CID 142909: Operands don't affect result (CONSTANT_EXPRESSION_RESULT)
Change-Id: I9b9cadf2acdba73913aad6bbe0d14ad64a652915
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12774
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
The FMD is board-specific, so it makes sense to have it in the
mainboard menu.
Change-Id: I52fba5ced869d51d10065f8c9ebd258d3a1d4156
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/12805
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Non-code flow assembly stubs do not have to be included in
bootblock.S, now that we have more freedom in bootblock linking.
Rather than bringing these stubs to the config system, just link them
in the bootblock.
Note that we cannot fully remove CHIPSET_BOOTBLOCK_INCLUDE at this
point, as some intel SOCs use this stub for code flow.
objdump -h build/cbfs/fallback/bootblock.debug on a few random boards
confirms that the appropriate sections are still included in the
final binary.
Change-Id: Id3f9ece14e399c1cc83090f407780c4a05a076f0
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: https://review.coreboot.org/11856
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Since the introduction of the new (interim?) master header, coreboot
searches the whole ROM for CBFS entries. Fix that by aligning it on top
of the ROM.
Change-Id: I080cd4b746169a36462a49baff5e114b1f6f224a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/12810
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
According to the PNP ISA v1.0a spec, config registers in the range of
0xf0 up to 0xfe are vendor defined and may be used for any purpose.
Config register 0xff is reserved and is defined as such.
Currently, only vendor specific registers 0xf0, 0xf1, 0xf4, and 0xfa
are able to be set using the PNP_MSCx bit flag masks.
This patch adds support for all 15 vendor specific config registers,
and updates the existing superio pnp_info to use them where appropriate.
Change-Id: Id43b85f74e3192b17dbd7e54c4c6136a2e59ad55
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/12808
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Boots to console on Gigabyte GA-G41M-ES2L
Ram initialization *not* included in this patch
VGA native init works on analog connector
Change-Id: I5262f73fd03d5e5c12e9f11d027bdfbbf0ddde82
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/11305
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
In order for a U-boot payload to work properly the soc_registers
region (device registers) needs to be mapped as uncached.
Therefore, add a coherency argument to the identity mapping funcion
which will establish the type of mapping.
Change-Id: I26fc546378acda4f4f8f4757fbc0adb03ac7db9f
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12769
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This requires changes the interface that sets up the system
PLL to support a given reference devider value and given
feedback value.
Also, this requires a change in the dividers used for UART,
USB, I2C setup.
Change-Id: I98cf7c655dbb3e95b8fcee3c7f468122021c70b5
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12765
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The EHCI debug device setup code was removed from broadwell in
commit 49ee5ef: http://review.coreboot.org/11874
However the generic device setup code is in the southbridge/common/intel
directory while broadwell is in the soc directory so this is not used.
Add it back to the broadwell soc to fix undefined reference compile
errors with 'pci_ehci_dbg_dev' and 'pci_ehci_dbg_enable'.
This was tested to compile and produce romstage and ramstage output on a
google/samus board.
Change-Id: Ia93825a1e21a770f6c82d0989cb97980a5c700d6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12794
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The port0 and port1 registers were swapped, which meant it did
not work to apply the DTLE settings to the correct SATA port.
This was tested on an unreleased mainboard but is verified with
the documentation to be the correct register addresses now.
Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12793
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Locking down the SPI controller with a specific opcode menu kills
the SPI console. Skip this when the SPI console config option is
enabled.
This was tested using an em100 and google/samus board to ensure
the console output does not stop at the finalize step.
Change-Id: Ie460f583214b47544e92d4afa8ef862563a11e36
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/12792
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Upcoming versions of IASL give a warning about unused methods. This
adds an operation after the read to use the local variable and avoid
the warning.
The warning can be completely disabled on the command line, but as it
can find real issues, my preference is to not do that.
Fixes warnings:
dsdt.aml 640: Store (CTMP, Local0)
Warning 3144 - Method Local is set but never used ^ (Local0)
Change-Id: If55bb8e03abb8861e1f2f08a8bcb1be8c9783afe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12704
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
- Remove it8772f c includes
- Add a new LED API, it8772f_gpio_led
- Stumpy: using it8772f_gpio_led
BUG=chrome-os-partner:28232
BRANCH=Guado
TEST=emerge-guado coreboot chromeos-bootimage
Change-Id: I08de52515d3c1e7e85d1761c09a0cebffda7dda3
Signed-off-by: David Wu <David_Wu@quantatw.com>
Reviewed-on: https://chromium-review.googlesource.com/241813
Tested-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: David Wu <david_wu@quantatw.com>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/12797
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Looking at the A10 datasheet, N should go in bits 2:0, but
was being cleared by shifting it left by three bits, then
anding it with 7.
Fixes coverity warning:
CID 1241888 (#1 of 1): Wrong operator used (CONSTANT_EXPRESSION_RESULT)
operator_confusion: (n << 3) & (7U /* 7 << 0 */) is always 0 regardless
of the values of its operands. This occurs as the bitwise second operand
of '|'.
Change-Id: I17e71a73adf37a62607e8e5865b1da749d7278aa
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12779
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Baytrail has I2c Busses 0 to 6, so is supposed to error out
if the I2c driver is called with 7 or greater. Due to an off-by-one
error it could be called with bus 7.
Fixes coverity warning:
CID 1287074 (#1 of 1): Out-of-bounds read (OVERRUN)
3. overrun-local: Overrunning array base_adr of 7 4-byte elements at
element index 7 (byte offset 28) using index bus (which evaluates to 7).
Change-Id: I7caec60298cf27bd669796e0e05e4a896f92befd
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12781
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
- Also update post code comment to keep under 80 characters.
Change-Id: Id0fd0ee5660f2628fe33188855bebb6e3eea8d2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12780
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Bit 8 of the MR register is automatically set by the PHY
during memory initilization but having it set in the
register leads to a more clear understanding.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: Ie6953e2a96ba2961521b372d280f362ee1c52b94
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12764
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Switching on DQS Gate Early and DQS Gate Extension with
500R DQS/DSQN Resistors. This setup was recommended by
Synopsys.
Tested on Pistachio bring up board; DDR2 and DDR3 are
initialized properly.
Change-Id: I6cd3888d506effe71f5d535367525af2e51f6ba3
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12763
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
root_port_init_config() pcie.c wasn't initializing a variable before
passing its pointer to pch_iobp_exec(). pch_iobp_exec() wrote the
uninitialized value into a register.
In theory, the register would only be used if data was being written,
and pch_iobp_exec() was being used to read the data, not write it, so
this change shouldn't have any practical effect.
Fixes coverity error:
CID 1293134 (#1 of 1): Uninitialized scalar variable (UNINIT)
Change-Id: I5d17863d904c6b1ceb30d72b94cd7a40c8fbb437
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/12778
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@google.com>
As the southbridge largely controls the PCI[e] configuration space
this patch moves the resource allocation from the northbridge
to the southbridge when the extended configuration space region
is enabled.
Change-Id: I0c4ba74ddcc727cd92b848d5d3240e6f9f392101
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12050
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
When enabling the IOMMU on certain systems dmesg is spammed with I/O page faults like the following:
AMD-Vi: Event logged [IO_PAGE_FAULT device=00:14.0 domain=0x000a address=0x000000fdf9103300 flags=0x0030]
Decoding the faulting address:
0x000000fdf9103300
fdf91x Hypertransport system management region
33 SysMgtCmd (System Management Command) = 0x33
3 Base Command Type = 0x3: STPCLK (Stop Clock request)
3 SMAF (System Management Action Field) = [3:1] = 0x1
1 Signal State Bit Map = [0] = 0x1
Therefore, the error appears to be triggered by an upstream C1E request.
This was eventually traced to concurrent access to the SP5100's SPI Flash controller by
multiple APs during startup. Calls to the nvram read functions get_option and read_option
call CBFS functions, which in turn make near-simultaneous requests to the SPI Flash
controller, thus placing the SP5100 in an invalid state. This limitation is not documented
in any public AMD errata, and was only discovered through considerable debugging effort.
Change-Id: I4e61b1ab767b1b7958ac7c1cf20eee41d2261bef
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/12061
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
The binary is taken from blobs, so the script should live over
there, too.
Change-Id: I3cc0aabc846c352ccf5cb348132b320a37f273a6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/12725
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
The usage of the pin has changed and therefore this pin needs
to be set up as output and drive low initially.
Change-Id: Ie3eb9cc703f7f73d59fad52ea9e514997d84606a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/12754
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
If we select CONFIG_GDB_STUB without CONFIG_SERIAL:
build/console/console.romstage.o: In function `__gdb_hw_init':
[...]src/include/console/uart.h:74: undefined reference to `uart_init'
build/console/console.romstage.o: In function `__gdb_tx_byte':
[...]/src/include/console/uart.h:75: undefined reference to `uart_tx_byte'
build/console/console.romstage.o: In function `__gdb_tx_flush':
[...]/src/include/console/uart.h:76: undefined reference to `uart_tx_flush'
build/console/console.romstage.o: In function `__gdb_rx_byte':
[...]/src/include/console/uart.h:77: undefined reference to `uart_rx_byte'
Note that CONFIG_GDB_STUB should also work trough usbdebug,
But due to the lack of testing, it has been disabled when added.
This commit gives more information on the issue:
f2f7f03 console: Add console for GDB
Change-Id: I9accf8189dfd2c4ae379c03649d2e5863183457b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12708
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This is to make towiki pick that information, to make
these boards end up in the laptop list at:
http://www.coreboot.org/Supported_Motherboards
Change-Id: Ibf8bf4bf6566080a34687e36675d4c4c8b89f334
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: https://review.coreboot.org/12716
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Implement system reset by calling the watchdog soft reset.
Following the soft reset, the SoC will reset to the same logic
state and therefore have the same effect as a hard (power-on)
reset except for:
- watchdog scratch registers will be unaffected (hard reset
will clear them)
- the real time clock will be unaffected
BUG=none
TEST=tested on Pistachio bring up board
Change-Id: I1332c2249c756f6d8574fc5c407de52f88e60f08
Signed-off-by: Ionela Voinescu <ionela.voinescu@imgtec.com>
Reviewed-on: https://review.coreboot.org/12755
Tested-by: build bot (Jenkins)
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Timothy Pearson