Commit graph

983 commits

Author SHA1 Message Date
Kyösti Mälkki
5e19fa4c51 AGESA fam12 fam14 fam15: Common handler for AGESA_DO_RESET
This is x86 "standard" 0xcf9 reset mechanism.

Change-Id: Ieb48290b21a7cb1425881fdd65c794e96da0248f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5680
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:28:09 +02:00
Kyösti Mälkki
c459f9658b AGESA: Add common callouts
Most of the callouts are not specific to board or even family.
Start new file with default callouts doing nothing and returning
either AGESA_SUCCESS or AGESA_UNSUPPORTED.

Also add callout for returning empty IdsIdData. This feature is
not used and could be easily overriden at board-level at later time.

Change-Id: I65dbcdd80dddc89d47669ebe62c22caa63792f5c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5678
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-26 09:27:31 +02:00
Edward O'Callaghan
68a56caf7e northbridge/amd/amdmct: Incorrect usage of logical over bitwise and
Small mix up of logical/bitwise logical and operation. Spotted by Clang.

Change-Id: I2c2256b9b2f2b6ca627914118c745f579555acc9
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5820
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23 01:49:48 +02:00
Edward O'Callaghan
ba363d3f18 northbridge/amd/amdmct: Superfluous parenthesis in if-statements
Remove superfluous parenthesis found in some if-statements, spotted by
Clang.

Change-Id: I98d2bf6b408caf320c5bcc8adb23d621b182976b
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5817
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-23 01:45:33 +02:00
Edward O'Callaghan
72ae4a3091 northbridge/amd/amdmct/mct: Initialize variables at the eol
Spotted by Clang

Change-Id: Idada98b7863ef986021943cf3ddb92d2f035e3e1
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5816
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-05-22 22:49:48 +02:00
Kyösti Mälkki
088fd67a38 AGESA: Implement EmptyHeap()
Heap allocation begins with BIOS_HEAP_MANAGER, no need to clear
the fields individually.

Change-Id: Ia1af84bd09d1edf8f72223752557d44a96dec6e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5659
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:50 +02:00
Kyösti Mälkki
8ef30253e3 AGESA fam14: Use common callouts
Backported from fam15tn and fam16kb.

This also implements GetHeapBase() to satisfy some requirements
of HAVE_ACPI_RESUME for the following boards:
  amd/inagua
  amd/south_station
  amd/union_station
  asrock/e350m1

Change-Id: I488d063d4eabf4bf45bcbabd1e8f13b88b2ef401
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5658
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:45 +02:00
Kyösti Mälkki
5601922130 AGESA fam14: Add fam14_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I868352b32ff56a8386c615ab1a9f59e7e875292e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5657
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:53:35 +02:00
Kyösti Mälkki
f15e53a730 AGESA fam15: Add GetHeapBase()
While fam15 boards do not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I222b418a0a79bbdf5f5cce6c876243ecb4912256
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5655
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:43 +02:00
Kyösti Mälkki
4f998a07b5 AGESA fam12: Add GetHeapBase()
While amd/torpedo does not select HAVE_ACPI_RESUME, backport this
from fam14.

Implementation of this function is common across different families.

Change-Id: I0e5099a0991a2655ec2b6990929196900e842fc1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5654
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:38 +02:00
Kyösti Mälkki
e3aef13933 AGESA fam15tn: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I562a132fa6d3ade2700d9a375d7aa21fcf8ea890
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:33 +02:00
Kyösti Mälkki
5caa9d9d81 AGESA fam16kb: Use common GetHeapBase()
Implementation of this function is common for all boards in family,
and also across different families.

Change-Id: I6aab710e76af9a361f0c0006922019a52feb3f6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:26 +02:00
Kyösti Mälkki
575cf9df66 AGESA fam15: Use common callouts
Backport from fam15tn and fam16kb.

Change-Id: I6d8f9a88f0dc43c36efb168c0111a6e2bcdda5fd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:19 +02:00
Kyösti Mälkki
05531a5f44 AGESA fam15: Add fam15_callouts header
Backported from fam15tn and fam16kb.

Change-Id: I13ca70d141a46220a5d8ea7bb3898bc7d7258424
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5650
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:10 +02:00
Kyösti Mälkki
5c96525b6a AGESA fam12: Move dimmSpd
Implemented under northbridge/ on other families.

Change-Id: I4d21af9d6c0f61eb1597e8e7095c08dd87ae2a84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5649
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:52:05 +02:00
Kyösti Mälkki
328ce9a8b4 AGESA fam12: Add fam12_callouts
Although amd/torpedo is only fam12 board at the moment,
backported this from fam15tn and fam16kb.

Change-Id: I72a856e2eb455a8428a886f0c4217ff80e60eb78
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5648
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-05 08:51:44 +02:00
Kyösti Mälkki
ae16d3dfbd AMD: Drop redundant test for CONFIG_RAMTOP
Same test is already done in x86/mtrr.h.

Change-Id: Ib0785d047567374294b9ee7afc4f4244f9ced926
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5620
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-05-03 09:51:21 +02:00
Furquan Shaikh
20f25dd5c8 Rename coreboot_ram stage to ramstage
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.

Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-04-26 13:27:09 +02:00
Kyösti Mälkki
f3e82f7969 AMD AGESA fam15tn/fam16kb: Remove unused source files
Change-Id: I45084ffe84fef4dd43acea843d7c93a81c255472
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5523
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-04-16 14:39:11 +02:00
Oskar Enoksson
42283e7994 Eliminate some ASL warnings
The ASL compiler warned about "Control Method should be made Serialized
(due to creation of named objects within)". This commit eliminates the
warnings by changing those NonSerialized into Serialized.

Change-Id: I639e769cf7a9428c34268e0c555a30c7dee1e04c
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/5189
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-02-13 01:04:02 +01:00
Aaron Durbin
029aaf627c x86: add common definitions for control registers
The access to control registers were scattered about.
Provide a single header file to provide the correct
access function and definitions.

BUG=chrome-os-partner:22991
BRANCH=None
TEST=Built and booted using this infrastructure. Also objdump'd the
     assembly to ensure consistency (objdump -d -r -S | grep xmm).

Change-Id: Iff7a043e4e5ba930a6a77f968f1fcc14784214e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172641
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4873
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-28 23:12:27 +01:00
Alexandru Gagniuc
af4bd599ca lib: Make log2() available in romstage on ARM, not just x86
On x86, log2() is defined as an inline function in arch/io.h. This is
a remnant of ROMCC, and forced us to not include clog2.c in romstage.
As a result, romstage on ARM has no log2().
Use the inline log2 only with ROMCC, but otherwise, use the one in
clog2.c.

Change-Id: Ifef2aa0a7b5a1db071a66f2eec0be421b8b2a56d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13 04:03:06 +01:00
Vladimir Serbinenko
0af61b6c82 lib/cbfs_core.c: Supply size of file as well in cbfs_get_file_content
Change-Id: I5b93e5321e470f19ad22ca2cfdb1ebf3b340b252
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4659
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
2014-01-12 17:41:02 +01:00
Vladimir Serbinenko
a37383db80 Replace all occurences of sprintf with snprintf
THis reduces risks of bufer overflows.

Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10 18:08:16 +01:00
Kyösti Mälkki
ea8d4607ce AMD K8 (rev F): Move rev F0/F1 workaround to header
Place this in header so it works also when raminit_f.c and
raminit_f_dqs.c are not #included in romstage.c build.

The workaround remains to be disabled for all boards.

Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4568
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:20:38 +01:00
Kyösti Mälkki
5c62375222 AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridge
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all
K8 rev F boards do the same things here.

Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30 07:19:10 +01:00
Kyösti Mälkki
7d3045b517 AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORT
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4558
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30 07:17:16 +01:00
Kyösti Mälkki
0946190e15 AMD K8 (rev-F): Always have RAMINIT_SYSINFO
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO,
so have the option enabled together with K8_REV_F_SUPPORT.
Also move the option under AMD K8.

Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4582
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29 19:45:50 +01:00
Kyösti Mälkki
2e77461051 AMD K8: Socket implies K8_REV_F_SUPPORT
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1).

Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4557
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-29 00:04:02 +01:00
Kyösti Mälkki
6c57f64e58 AMD fam10: Drop MEM_TRAIN_SEQ
This config was for AMD K8 only.

Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4555
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26 23:23:30 +01:00
Kyösti Mälkki
88a67f0cc9 AMD boards (non-AGESA): Cleanup earlymtrr.c includes
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4523
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26 23:19:11 +01:00
Idwer Vollering
d26da9c8f0 Coding style: punctuation cleanup [1/2].
Clean up superfluous line terminators.

Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4562
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2013-12-23 02:12:51 +01:00
Idwer Vollering
8c0cb8ae3b Correct file permissions.
Some files have incorrect/odd permissions,
correct them: remove unnecessary +x flags.

Change-Id: I784e6e599dfee88239f85bb58323aae9e40fb21c
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4490
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-07 00:39:09 +01:00
Alexandru Gagniuc
72dccce0c9 global: Fix usage of get_option() to make use of CB_CMOS_ codes
Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.

Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-12-02 22:11:20 +01:00
Christian Gmeiner
bd7e8d8d2b AMD Northbridge LX: simplify get_top_of_ram()
Get rid of not needed dependency to gliu0table. This change is
needed to move get_top_of_ram() to raminit.c - as needed for
EARLY_CBMEM_INIT.

Boot tested on a Bachmann OT200.

Change-Id: I0bfe40c366a3537775d5c1ff8e0b1f5ac94320b7
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3380
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-11-26 07:36:26 +01:00
Paul Menzel
7a00ca75d7 northbridge/amd/amdk8/raminit_f_dqs.c: Remove unused variable reg in setup_mtrr_dqs()
Change-Id: I7fc7819c329c058472031e82237be5c170b277f4
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3965
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
2013-10-13 19:10:10 +02:00
Stefan Reinauer
fd4f4136e8 Rename cpu/x86/car.h to arch/early_variables.h
and add an ARMv7 version.

Change-Id: I14fbff88d7c2b003dde57a19bf0ba9640d322156
Signed-off-by: Stefan Reinauer <reinauer@google.com>
[km: rebased fa004acf8 from chromium git]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3939
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2013-10-13 12:47:05 +02:00
Corey Osgood
5a7e127cd4 southbridge/cimx/sb900: Rename headers to match sb700 & sb800
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 & 
sb800, and points agesa/family12 and amd/torpedo to the new file 
names.

Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-09-24 01:20:02 +02:00
Kyösti Mälkki
dcb688e5ec CBMEM: Unify get_top_of_ram()
Change-Id: Ic40a51638873642f33c74d80ac41cf082b2fb177
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3904
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:16:00 +02:00
Kyösti Mälkki
42f4651434 CBMEM northbridges: Remove references to global high_tables_base
Use the new helper function set_top_of_ram() to remove remaining
uses of high_tables_base and _size under northbridge/.

Change-Id: I6b0d9615002ed2aff578c5811d7bd43dd2594453
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3561
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:09:47 +02:00
Kyösti Mälkki
2b790f6512 CBMEM AMD: Fix calls to set_top_of_ram_once()
We can postpone the call to set_top_of_ram_once() outside the
loops and make just one call instead.

As set_top_of_ram() is now only called once, it is no longer
necessary to check if high_tables_base was already set.

Change-Id: I302d9af52ac40c7fa8c7c7e65f82e00b031cd397
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3895
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-09-11 07:09:21 +02:00
Kyösti Mälkki
e7e847cd5c CBMEM AMD: Remove references to global high_tables_base
Prepare for removal of globals high_tables_base and _size
by replacing the references with a helper function.

Added set_top_of_ram_once() may be called several times,
but only the first call (with non-zero argument) takes effect.

Change-Id: I5b5f71630f03b6a01e9c8ff96cb78e9da03e5cc3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-09-11 07:06:15 +02:00
Bruce Griffith
42e11f5a03 AMD Richland: Add new graphics device IDs to Family 15, Models 10-1F
Change-Id: Ic7fdedc0a22e7664f14b105f2f7cecd8f55980be
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3857
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2013-08-15 18:41:44 +02:00
Mike Loptien
ac90d8013a AMD Kabini: Split DSDT into common sections
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.

Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
2013-08-15 18:40:11 +02:00
Kimarie Hoot
0cc33da553 ASUS F2A85-M: Split DSDT into common sections (as per Parmer)
Rearranged the F2A85-M DSDT file to match the functionality found
on Parmer.  As with the Parmer implementation, the F2A85-M dsdt.asl
file in the mainboard directory contains only #include references to
the appropriate files.

As with Parmer, some include files have no content but are left as a
template for other platforms and as placeholders for completing the
ACPI implementation for F2A85-M.

Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/3805
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
2013-08-08 05:58:29 +02:00
Bruce Griffith
76db07e8c2 AMD Kabini: Add map_oprom() function for Vendor/Device IDs
Change-Id: I14285f0677003fbf8b9b112207af202658807894
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3806
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 22:13:20 +02:00
Siyuan Wang
3e32cc00d1 AMD Kabini: Add northbridge AGESA wrapper (new AMD processor)
src/arch/x86/boot/tables.c and src/include/device/pci_ids.h are also
changed because these two files depend on F16kb northbridge macros

Change-Id: Iedc842f0b230826675703fc78ed8001a978319c5
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Bruce Griffith <bruce.griffith@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-08-05 18:23:34 +02:00
Steve Goodrich
bf0988b0a2 AMD Fam15tn: Split DSDT into common sections
Split the Parmer, Family 15tn, and Hudson DSDT into groups.  This splits
the DSDT table into includable ASL files which carry details specific
to the Family 15tn APU, the Parmer platform, and the Hudson FCH.  The
dsdt.asl file in the mainboard directory contains only #include
references to the appropriate files.

Initially, this split was done by moving each piece of functionality
into its own file (e.g. IRQ routing and mapping, processor tree, sleep
states and sleep methods, etc.) and those pieces were #included in
dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
with the extant version of the table.  Once the new tables were found
to exactly match the existing tables, the pieces were rearranged into
reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).

Some include files have no content but are left as a template for
other platforms and as placeholders for completing the ACPI
implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
sata.asl, etc.).

Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/3629
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-07-16 16:14:56 +02:00
Kyösti Mälkki
33e5df3f25 Set PCI bus operations at buildtime for ramstage
PCI bus operations are static through the ramstage, and should be
initialized from the very beginning. For all the replaced instances,
there is no MMCONF_SUPPORT nor MMCONF_SUPPORT_DEFAULT selected for
the northbridge, so these continue to use PCI IO config access.

Change-Id: I658abd4a02aa70ad4c9273568eb5560c6e572fb1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3607
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-07-11 01:29:35 +02:00
Kyösti Mälkki
872c922296 Fix MMCONF_SUPPORT_DEFAULT for ramstage
Define at one place whether to use IO 0xcf8/0xcfc or MMIO via
MMCONF_BASE_ADDRESS for PCI configuration access funtions in ramstage.

The implementation of pci_default_config() always returned with
pci_cf8_conf1. This means any PCI configuration access that did
not target bus 0 used PCI IO config operations, if PCI MMIO config
was not explicitly requested.

Change-Id: I3b04f570fe88d022cd60dde8bb98e76bd00fe612
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3606
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Aaron Durbin <adurbin@google.com>
2013-07-10 00:57:09 +02:00
Bruce Griffith
53abac1767 amd/cimx/rd890/amd.h: Eliminate redefinition of NULL
This change replaces a redefinition of NULL with the standard
definition from <stddef.h> to eliminate a compiler redefinition
warning.

Change-Id: I441fa569f545c0efb00284b5ee58aa27cb6617ba
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3540
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:36:29 +02:00
Bruce Griffith
58fff9d44f amd/agesa/family15/northbridge.c: Delete unused variable
This change eliminates an unused variable that causes a build warning.

Change-Id: I02487c7dd80d458f562d7afe1827eefcc0fb678b
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3526
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-06-28 01:35:59 +02:00
Kyösti Mälkki
6aeb4a269c AMD: Drop empty root_complex
There are no files to build left under AMD nortbridge/x/root_complex
directories. For some cases, even the Kconfig file was no longer sourced.
Remove all such references and empty files.

For devicetree.cb treat component paths with "/root_complex" in them valid
even when the directory does not exists. This is because AMD boards us this
dummy chip component as the root node in their devicetree.cb.

The generated devicetree file static.c remains unchanged.

Change-Id: I9278ebb50a83cebbf149b06afb5669899a8e4d0b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3434
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-24 17:22:44 +02:00
Rudolf Marek
5ce0506618 AMD Fam15tn: Add support for AGESA runtime allocation in CBMEM
The IOMMU AGESA needs a reserved scratch space and it wants
to allocate the stuff for runtime. So provide a simple
allocator for 4 KB CBMEM page.

Change-Id: I53bdfcd2cd69f84fbfbc6edea53a051f516c05cc
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/3315
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:53:52 +02:00
Rudolf Marek
88ebbeb7e2 AMD Fam15tn: Add IOMMU BAR allocation to northbridge
For IOMMU we need to allocate a 512 KB BAR in a non-standard
location. Use the standard allocator for that and limit the BAR
to 32-bits to be compatible with older systems.

Change-Id: I44414ce6b264b7f1c086a9b1c7ea275a0830205e
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3314
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-24 00:52:50 +02:00
Kyösti Mälkki
59d0d159f4 AMD: Kconfig cleanup
Change-Id: I21182eae1d389790c330f27e6a830d91c3ee4eb6
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3433
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-06-13 01:08:12 +02:00
Christian Gmeiner
7bc3575458 AMD Northbridge LX: get rid of #include "northbridge/amd/lx/raminit.c"
Change-Id: I249c63646267ebe8dd8e06980aa6367a16fe7297
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:48 +02:00
Christian Gmeiner
c4e07bb503 AMD Northbridge LX: convert spd_read_byte() to non-static version
Change-Id: Ie329606852dfd7109acb694e9a9ff851b023cc63
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3369
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:56:35 +02:00
Christian Gmeiner
e2dc80ceac AMD Northbridge LX: rename get_systop() to get_top_of_ram()
Change-Id: I6126d575b8289f76b38858304836e3037200bcdb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3367
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:45 +02:00
Christian Gmeiner
84ae76caf8 AMD Northbridge LX: include northbridge.h in raminit.c
Change-Id: Ic2f50ae184678637c611757d3391826c1d2719a1
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3365
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:55:15 +02:00
Christian Gmeiner
194ec4d4d5 AMD Northbridge LX: make GeodeLinkSpeed() function prototype non-static
Change-Id: Id914be1ae4dac96c51f2640f056af4ce58a248eb
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3364
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:56 +02:00
Christian Gmeiner
6f9f785d9b AMD Northbridge LX: add some missing includes
This commit fixes problems if we build raminit.c
for romstage.

Change-Id: Ic1380f3635ac28b939fa2a8ce614814012455c44
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3363
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:54:27 +02:00
Christian Gmeiner
eb6322f4b0 AMD Northbridge LX: make sdram_* function prototypes non-static
In order to get rid of the bad #include "northbridge/amd/lx/raminit.c"
line we need to do some prepartion steps. This commit is one of them.

Change-Id: I33173660bbda8894e7672e41e1b994d254d7ae8a
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3362
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:53:57 +02:00
Siyuan Wang
29840e234c AMD Fam 15tn: Use all memory on systems with more than 4 GB
Take a Parmer board with 4G memory as an example.

Use 'cat /proc/meminfo' to check memory, it reads 'MemTotal 3327540kB'.
Parmer uses 512M as video memory when it has 4G.
3327540+512*1024 = 3851828(kB), so some memory is lost.

When Parmer has 4G memory, TOM2 low is 0x1F000000, TOM2 high is
0x00000001. But in e820 table or coreboot table, the last item is

    6: 0000000100000000 - 0000000118000000 = 1 RAM

This is not correct, it should be

    6: 0000000100000000 - 000000011f000000 = 1 RAM

This patch changes the memory layout when TOM2 is set.

Change-Id: I4e2d163ae8fe1e65ddc384b520a5112ca067b1d1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3366
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-06-04 17:48:47 +02:00
Paul Menzel
42409e8732 northbridge/amd/amdmct: Use static const instead of const static
From ISO C99 standard: »The placement of a storage-class specifier
other than at the beginning of the declaration specifiers in a
declaration is an obsolescent feature.«

Found at <http://www.approxion.com/?p=41>.

The following command was used to make the change.

    $ git grep -l 'const static' src/ | xargs sed -i 's/const static/static const/'

As asked by Bruce Griffith, the changes in `src/vendorcode` were
reverted as that is what AMD prefers.

The same change was done already for AMD Persimmon in the following
commit.

    commit 824e192809
    Author: Jens Rottmann <JRottmann@LiPPERTembedded.de>
    Date:   Wed Feb 20 21:24:20 2013 +0100

        Persimmon: platform_cfg.h: Declare codec arrays as `static const`

        Reviewed-on: http://review.coreboot.org/2474

Change-Id: I233c83fdc95ea4f83f7296c818547beb52366a3d
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3197
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-06-03 08:20:54 +02:00
Stefan Reinauer
c5e036a043 Get rid of a number of __GNUC__ checks
In the process of streamlining coreboot code and getting
rid of unneeded ifdefs, drop a number of unneeded checks
for the GNU C compiler. This also cleans up x86emu/types.h
significantly by dropping all the duplicate types in there.

Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3226
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-10 17:31:31 +02:00
Stefan Reinauer
3949e37834 Drop CONFIG_AP_CODE_IN_CAR
This option has not been enabled on any board and was considered
obsolete last time it was touched. If we need the functionality,
let's fix this in a generic way instead of a K8 specific way.
This was mostly a speedup hack back in the day.

Change-Id: Ib1ca248c56a7f6e9d0c986c35d131d5f444de0d8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3211
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
2013-05-08 19:14:21 +02:00
Nico Huber
8ecec215be Revert "siemens/sitemp_g1p1: Make ACPI report the right mmconf region"
This reverts commit 1fde22c54c:

    commit 1fde22c54c
    Author: Patrick Georgi <patrick.georgi@secunet.com>
    Date:   Tue Apr 9 15:41:23 2013 +0200

        siemens/sitemp_g1p1: Make ACPI report the right mmconf region

        ACPI reported the entire space between top-of-memory and some
        (relatively) arbitrary limit as useful for MMIO. Unfortunately
        the HyperTransport configuration disagreed. Make them match up.

        Other boards are not affected since they don't report any region
        for that purpose at all (it seems).

        Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
        Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
        Reviewed-on: http://review.coreboot.org/3047
        Tested-by: build bot (Jenkins)
        Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

It sneaked in without it's dependencies and, therefore, broke the build for
all amdk8 targets. Paul Menzel already commented on the issue in [1]. It
also doesn't look like the dependencies would be pulled soon [2].

[1] http://review.coreboot.org/#/c/3047/
[2] http://review.coreboot.org/#/c/2662/

Change-Id: Ica89563aae4af3f0f35cacfe37fb608782329523
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3063
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-04-12 11:48:15 +02:00
Mike Loptien
573a1d6fa8 Persimmon/Fam14/SB800 DSDT: Split into common areas
Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory.  Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future.  I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time.  Removing
it until it is decided that it is actually necessary.

This change was verified in three different ways:
	1. Visual comparison of the compiled DSDT pulled from the
	Persimmon after booting into Linux using the ACPI tools
	acpidump, acpixtract, and iasl.  The comparison was done
	between the DSDT before and after doing the split work.

	This test is somewhat difficult considering the expanse
	of the changes.  Blocks of code have been moved, and
	others changed.

	2. Linux logs were dumped before and after the DSDT split.
	Logs dumped and compared include dmesg and lspci -tv.
	Neither log changed significantly between the two compare
	points.

	3. The test suite FWTS was run on the Coreboot build both
	before and after doing the DSDT split with the command
	'sudo fwts -b -P -u'.  The flag -b specifies all batch jobs,
	-P specifies all power tests, and -u specifies utilities.
	Interactive jobs were not run as most of them consist of
	laptop checks.  Again, there were no significant changes
	between the two endpoints.

These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.

This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)

Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-04-11 21:48:27 +02:00
Patrick Georgi
1fde22c54c siemens/sitemp_g1p1: Make ACPI report the right mmconf region
ACPI reported the entire space between top-of-memory and some
(relatively) arbitrary limit as useful for MMIO. Unfortunately
the HyperTransport configuration disagreed. Make them match up.

Other boards are not affected since they don't report any region
for that purpose at all (it seems).

Change-Id: I432a679481fd1c271f14ecd6fe74f0b7a15a698e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3047
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-04-10 17:40:49 +02:00
Paul Menzel
5b5cf3d610 AMD GX1: Remove useless copied header file northbridge.h
This was there since the beginning

    commit d24d6993b6
    Author: arch import user (historical) <svn@openbios.org>
    Date:   Wed Jul 6 17:06:46 2005 +0000

        Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-26
        Creator:  Hamish Guthrie <hamish@prodigi.ch>

        Added AMD GX1 northbridge and cs5530 Southbridge

but blindly copied from Intel 440 BX and is not used anywhere.

Thanks to Idwer Vollering for spotting this.

Change-Id: I38b3d3feb25966c3aa382994d323e59c3f3c9e6c
Reported-by: Idwer Vollering
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3020
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Tested-by: build bot (Jenkins)
2013-04-04 03:26:58 +02:00
Stefan Reinauer
24d1d4b472 x86: Unify arch/io.h and arch/romcc_io.h
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.

Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.

Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-03-22 00:00:09 +01:00
Kimarie Hoot
fa91819e89 AMD Fam15: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F15 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Dinar, and was changed to
use the devicetree.cb structures.  Significant cleanup and magic
number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBus initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I4e00ada288e1486cf30684403505e475f9093ec2
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/2777
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-19 17:08:10 +01:00
Martin Roth
3b2653b1fc AMD Fam14: Add SPD read functions to wrapper code
Change:
This is the initial step for moving the AMD F14 & HUDSON1,2,3
SPD-read callout out of the mainboard directories and into
the wrapper.  The next step is to update the platforms to use
this routine in BiosCallouts.c and to delete the code from the
mainboard directories.  The DIMM addresses should be moved into
devicetree.cb.
If there are significant differences or reasons that the mainboard
needs to override this code, it's perfectly reasonable to keep using
the version in the mainboard, but this allows us to remove duplicated
code and simplify the mainboard directories.

Notes:
This started by duplicating what was in Persimmon, and was changed to
use the devicetree.cb structures.  The ASF setup was also removed from
the persimmon copy (PMIO writes to 0x28 & 0x29) as that's not needed
for the SPD access and doesn't make sense to initialize here.
Significant cleanup and magic number reduction was done as well.

It is intended that this file will not be included in ramstage as
the DIMM init is all done in romstage.

This is similar to what was done for Parmer/Thatcher in commit
7fb692bd - http://review.coreboot.org/#/c/2190/
Fam15tn: Move SPD read from mainboards into wrapper

Yes, it would make sense to split this into two separate files
and move the SMBUS initialization and access into the southbridge
wrapper.  Maybe that can come next.

Change-Id: I1e106d3912c160b0015bf02158d9faba4f578ee3
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2497
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-03-07 18:29:23 +01:00
Paul Menzel
a46a712610 GPLv2 notice: Unify all files to just use one space in »MA 02110-1301«
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.

The following command was used to convert all files.

    $ git grep -l 'MA  02' | xargs sed -i 's/MA  02/MA 02/'

[1] http://www.gnu.org/licenses/gpl-2.0.txt

Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-03-01 10:16:08 +01:00
Stefan Reinauer
fd611f9c2c Drop CONFIG_WRITE_HIGH_TABLES
It's been on for all boards per default since several years now
and the old code path probably doesn't even work anymore. Let's
just have one consistent way of doing things.

Change-Id: I58da7fe9b89a648d9a7165d37e0e35c88c06ac7e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2547
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-28 00:00:30 +01:00
Paul Menzel
a8ae1c66f9 Whitespace: Replace tab character in license text with two spaces
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].

    $ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[        ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'

[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt

Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
2013-02-20 23:30:45 +01:00
Martin Roth
92f03c0a06 AMD Family12h: Fix warnings
Add needed prototypes to .h files.
Remove unused variables and fix types in printk statements.
Add #IFNDEFs around #DEFINEs to keep them from being defined twice.
Fix a whole bunch of casts.
Fix undefined pre-increment behaviour in a couple of macros.  These now
  match the macros in the F14 tree.
Change a value of 0xFF that was getting truncated when being assigned
  to a 4-bit bitfield to a value of 0x0f.

This was tested with the torpedo build.
This fixes roughly 132 of the 561 warnings in the coreboot build
  so I'm not going to list them all.
  Here is a sample of the warnings fixed:

In file included from src/cpu/amd/agesa/family12/model_12_init.c:35:0:
src/include/cpu/amd/amdfam12.h:52:5: warning: redundant redeclaration of 'get_initial_apicid' [-Wredundant-decls]
In file included from src/cpu/amd/agesa/family12/model_12_init.c:34:0:
src/include/cpu/amd/multicore.h:48:5: note: previous declaration of 'get_initial_apicid' was here

src/northbridge/amd/agesa/family12/northbridge.c:50:10: warning: no previous prototype for 'get_node_pci' [-Wmissing-prototypes]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'get_hw_mem_hole_info':
src/northbridge/amd/agesa/family12/northbridge.c:302:13: warning: unused variable 'i' [-Wunused-variable]
src/northbridge/amd/agesa/family12/northbridge.c: In function 'domain_set_resources':
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:587:5: warning: format '%lx' expects argument of type 'long unsigned int', but argument 3 has type 'device_t' [-Wformat]
src/northbridge/amd/agesa/family12/northbridge.c:716:1: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'long unsigned int' [-Wformat]

In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1282:0: warning: "TOP_MEM" redefined [enabled by default]
In file included from src/northbridge/amd/agesa/family12/northbridge.c:34:0:
src/include/cpu/amd/mtrr.h:31:0: note: this is the location of the previous definition
In file included from src/mainboard/amd/torpedo/agesawrapper.h:31:0,
                 from src/northbridge/amd/agesa/family12/northbridge.c:38:
src/vendorcode/amd/agesa/f12/AGESA.h:1283:0: warning: "TOP_MEM2" redefined [enabled by default]

src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetNumberOfComplexes':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:99:19: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfPcieEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:126:20: warning: operation on 'PciePortList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetLengthOfDdiEnginesList':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:153:19: warning: operation on 'DdiLinkList' may be undefined [-Wsequence-point]
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c: In function 'PcieInputParserGetComplexDescriptorOfSocket':
src/vendorcode/amd/agesa/f12/Proc/GNB/Modules/GnbPcieConfig/PcieInputParser.c:225:17: warning: operation on 'ComplexList' may be undefined [-Wsequence-point]

src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PciePhyServices.c:246:1: warning: no previous prototype for 'PcieFmForceDccRecalibrationCallback' [-Wmissing-prototypes]

In file included from src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/F12PcieComplexConfig.c:58:0:
src/vendorcode/amd/agesa/f12/Proc/GNB/PCIe/Family/LN/LlanoComplexData.h:120:5: warning: large integer implicitly truncated to unsigned type [-Woverflow]

And fixed a boatload of these types of warning:
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c: In function 'HeapGetBaseAddress':
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:687:17: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:694:19: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:701:23: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:702:23: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:705:23: warning: assignment makes integer from pointer without a cast [enabled by default]
src/vendorcode/amd/agesa/f12/Proc/CPU/heapManager.c:709:21: warning: assignment makes integer from pointer without a cast [enabled by default]

Change-Id: I97fa0b8edb453eb582e4402c66482ae9f0a8f764
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2348
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2013-02-18 05:01:53 +01:00
Stefan Reinauer
0aa37c488b sconfig: rename lapic_cluster -> cpu_cluster
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.

Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 07:07:20 +01:00
Stefan Reinauer
4aff4458f5 sconfig: rename pci_domain -> domain
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.

Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-02-14 02:00:10 +01:00
Steven Sherk
f04e68e9e2 Add MMCONF resource to AMD fam15 PCI_DOMAIN
This is a port of the following:
commit d5c998be99

	The coreboot resource allocator doesn't respect resources
	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
	PCI_DOMAIN to prevent overlap with PCI devices.

original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>
    URL - http://review.coreboot.org/#/c/2167/

Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 23:59:42 +01:00
Mike Loptien
7407f43c2b Family 12: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2250
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:19:19 +01:00
Mike Loptien
e133aab5b5 Family 15tn: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:18:10 +01:00
Mike Loptien
6eced514bf Family 10: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:17:34 +01:00
Mike Loptien
8401453486 Family 15: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: Ie71fec39df5e7703d35d6505dc7d5b55179e2c7e
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2234
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:16:43 +01:00
Steven Sherk
1cbabb00d9 Add MMCONF resource to AMD fam15tn PCI_DOMAIN
In the process of verifying change it was discovered the MMCONF
default base address 0xA0000000 was set below mem_top 0xE0000000
and bus number 256 wasn't a relistic number. The Kconfig defaults were
changed to mirror fam15 defaults base address 0xF8000000 and bus
number 64. Verified changes with boot to OS.

This is a port of the following:
commit d5c998be99

	The coreboot resource allocator doesn't respect resources
	claimed in the APIC_CLUSTER. Move the MMCONF resource to the
	PCI_DOMAIN to prevent overlap with PCI devices.

original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
    Signed-off-by: Marc Jones <marc.jones@se-eng.com
    URL - http://review.coreboot.org/#/c/2167/

Change-Id: I47660061538f8889f528b9b880a82645074886a7
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2260
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-02-04 18:14:35 +01:00
Martin Roth
7fb692bd86 Fam15tn: Move SPD read from mainboards into wrapper
Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.

Move the SPD address customization for the mainboard into the
devicetree.cb file.

Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects.  AGESA's structures all
use this, but coreboot's don't.  Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.

This fix has been tested.

Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2190
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
2013-02-01 04:00:02 +01:00
Hung-Te Lin
6fe0cab205 Extend CBFS to support arbitrary ROM source media.
Summary:
	Isolate CBFS underlying I/O to board/arch-specific implementations as
	"media stream", to allow loading and booting romstage on non-x86.

	CBFS functions now all take a new "media source" parameter; use
	CBFS_DEFAULT_MEDIA if you simply want to load from main firmware.
	API Changes:
		cbfs_find => cbfs_get_file.
		cbfs_find_file => cbfs_get_file_content.
		cbfs_get_file => cbfs_get_file_content with correct type.

CBFS used to work only on memory-mapped ROM (all x86). For platforms like ARM,
the ROM may come from USB, UART, or SPI -- any serial devices and not available
for memory mapping.

To support these devices (and allowing CBFS to read from multiple source
at the same time), CBFS operations are now virtual-ized into "cbfs_media".  To
simplify porting existing code, every media source must support both "reading
into pre-allocated memory (read)" and "read and return an allocated buffer
(map)". For devices without native memory-mapped ROM, "cbfs_simple_buffer*"
provides simple memory mapping simulation.

Every CBFS function now takes a cbfs_media* as parameter. CBFS_DEFAULT_MEDIA
is defined for CBFS functions to automatically initialize a per-board default
media (CBFS will internally calls init_default_cbfs_media).  Also revised CBFS
function names relying on memory mapped backend (ex, "cbfs_find" => actually
loads files). Now we only have two getters:
	struct cbfs_file *entry = cbfs_get_file(media, name);
	void *data = cbfs_get_file_content(CBFS_DEFAULT_MEDIA, name, type);

Test results:
 - Verified to work on x86/qemu.
 - Compiles on ARM, and follow up commit will provide working SPI driver.

Change-Id: Iac911ded25a6f2feffbf3101a81364625bb07746
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: http://review.coreboot.org/2182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2013-01-30 17:58:32 +01:00
Steven Sherk
5fc64dca45 Rename family15 pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Id7889bf02e2696220081251acdf695327267c796
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:39:50 +01:00
Steven Sherk
f434058b04 Rename family15tn pci northbridgeops functions.
This is a port of the following
commit 8a49ac7f80

    Rename fam14 pci northbridge ops functions.

    Clarify the northbridge ops function names.

original-Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
    Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Icda3ec58219baa177af3b1dce729c6ad1f744be8
Signed-off-by: Steven Sherk <steven.sherk@se-eng.com>
Reviewed-on: http://review.coreboot.org/2226
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-30 17:37:34 +01:00
Mike Loptien
58089e859d Family 14: Update for string portability.
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.

Change-Id: I6327c9769c2544bbc56155a2f89afd767487faf6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2227
Tested-by: build bot (Jenkins)
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-01-30 17:36:10 +01:00
Marc Jones
d5c998be99 Add MMCONF resource to AMD fam14 PCI_DOMAIN.
The coreboot resource allocator doesn't respect resources
claimed in the APIC_CLUSTER. Move the MMCONF resource to the
PCI_DOMAIN to prevent overlap with PCI devices.

Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2167
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Steve Goodrich <steve.goodrich@se-eng.com>
2013-01-22 19:17:35 +01:00
Marc Jones
8a49ac7f80 Rename fam14 pci northbridge ops functions.
Clarify the northbridge ops function names.

Change-Id: If7d89de761c1e22f9ae39d36f5cf334cc2910e1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2166
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
2013-01-22 12:18:10 +01:00
Martin Roth
73e86a88d2 F15tn: Fix all warnings, enable warnings as errors
Enable 'all warnings being treated as errors' in thatcher and parmer.

Fixed the following warnings on parmer / thatcher:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:
 In function 'GetPstateGatherDataAddressAtPost':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuPostInit.c:235:10:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:
 In function 'MemNInitNBDataTN':
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:353:32:
 warning: assignment from incompatible pointer type [enabled by default]
src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mntn.c:363:23:
 warning: assignment from incompatible pointer type [enabled by default]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:
 In function 'GetGlobalCpuFeatureListAddress':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/Feature/cpuFeatureLeveling.c:291:14:
 warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]

src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:
 In function 'SaveDeviceContext':
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:245:18:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.c:309:16:
 warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]

In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:37:0:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0:
 note: this is the location of the previous definition
In file included from src/northbridge/amd/agesa/family15tn/northbridge.c:41:0:
src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuRegisters.h:378:0:
 warning: "LOCAL_APIC_ADDR" redefined [enabled by default]
src/include/cpu/x86/lapic_def.h:9:0: note:
 this is the location of the previous definition

In file included from src/mainboard/amd/parmer/BiosCallOuts.h:24:0,
                 from src/mainboard/amd/parmer/mainboard.c:28:
src/vendorcode/amd/agesa/f15tn/AGESA.h:1547:0:
 warning: "TOP_MEM" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:31:0:
 note: this is the location of the previous definition
src/vendorcode/amd/agesa/f15tn/AGESA.h:1548:0:
 warning: "TOP_MEM2" redefined [enabled by default]
src/include/cpu/amd/mtrr.h:34:0: note:
 this is the location of the previous definition

Change-Id: Iecea28232f1761401cf09f7d2a77d3fbac2f5801
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2171
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-01-22 12:17:07 +01:00
Martin Roth
2892023fd4 AGESA F15tn: Move callouts into northbridge wrapper
There are currently too many things in the mainboard directories that
are really more suited to being in the northbridge / southbridge
wrappers.  This is a start at moving some of those functions down
into the wrappers.

Move the bios callback functions into the northbridge/amd/agesa/family15tn
directory from the mainboard directories.  These can still be overridden
by any mainboard just by updating the pointer in the callback table to
point to a customized version of the function.

Change-Id: Icefaa014f4a4abbe51870aee7aa2fa1164e324c1
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2169
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:54:51 +01:00
Martin Roth
2d8815197e F15tn: Modify devicetree to fix S3 resume
The way that devicetree.cb was configured for the family 15tn boards
was doing... interesting things to the video device initialization.
This was causing S3 resume to fail.

There is a disconnect between how the devicetree should be configured
if there are multiple HT links on the CPU and how it's configured if
there's only one HT link.  These platforms were set up as if they
had multiple HT links, which was causing duplicate instances of
devices in the device list.

The scan for the IO Hub was removed from the northbridge code which
isn't a problem for F15tn devices.

Change-Id: I3556b43027746e36b07de7cb1bece4d1b37a3c34
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2160
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2013-01-21 18:52:30 +01:00
Aladyshev Konstantin
9027845d65 rd890: clear IO-APIC before setup
Add function "clear_ioapic" before "setup_ioapic" for RD890 northbridge
like it is done for SB700 and SB800 chipsets ("amd/cimx/sb{7,8}00").

No functionality change is noticed.

Change-Id: I1fd87692d8bf35c166141c9b7a6a1e748c19a636
Signed-off-by: Aladyshev Konstantin <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/2045
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2013-01-04 06:38:24 +01:00
Dave Frodin
cbf3d407b8 Add function to map vendor/device to generic VBIOS IDs
Change-Id: I4d7c4ec2b91c97eacf96770c150c2b9a61309053
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1982
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-12-07 20:42:33 +01:00
Ronald G. Minnich
5079a0d32f Remove assembly coded log2 function
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.

Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
2012-11-28 07:57:17 +01:00
Patrick Georgi
bbc880eee7 amdk8/amdfam10: Use CAR_GLOBAL for sysinfo
This gets rid of the somewhat unstructured placement of AMD's
sysinfo structure in CAR.
We used to carve out some CAR space using a Kconfig variable,
and then put sysinfo there manually (by "virtue" of pointer magic).

Now it's a variable with the CAR_GLOBAL qualifier, and build
system magic.

For this, the following steps were done (but must happen together
since the intermediates won't build):
- Add new CAR_GLOBAL sysinfo_car
- point all sysinfo pointers to sysinfo_car instead of GLOBAL_VAR
- remove DCACHE_RAM_GLOBAL_VAR_SIZE
  - from CAR setup (no need to reserve the space)
  - commented out code (that was commented out for years)
  - only copy sizeof(sysinfo) into RAM after ram init, where
    before it copied the whole GLOBAL_VAR area.
  - from Kconfig

Change-Id: I3cbcccd883ca6751326c8e32afde2eb0c91229ed
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1887
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-28 07:45:05 +01:00
Patrick Georgi
23f38cd05c Get rid of drivers class
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.

These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.

With ramstage.a gone, we can drop this special class, too.

Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-11-27 22:00:49 +01:00
Kyösti Mälkki
e4d40b4d6e Drop no-op bootblock.c
Deletes unused file:
   src/northbridge/amd/agesa/family15tn/bootblock.c

Change-Id: Ic29553e008839407755d25bf125d599fa1f6131c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-11-17 02:12:02 +01:00
Siyuan Wang
becacec022 AMD G34 CPU: change lapic_id in northbridge.c to accommodate G34 CPU
Each G34 socket has two node. Previous lapic algorithm is written for
the CPU which has one node per socket. I test the code on h8qgi with
4 family 15 CPUs(8 cores per CPU). The topology is:
socket 0 --> Node 0, Node 1
socket 2 --> Node 2, Node 3
socket 1 --> Node 4, Node 5
socket 3 --> Node 6, Node 7
Each node has 4 cores.
I change the code according to this topology.

Change-Id: I45f242e0dfc61bd9b18afc952d7a0ad6a0fc3855
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1659
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 04:02:54 +01:00
Siyuan Wang
6f05c2eb59 AMD rd890 late.c: Don't enable PCIe ports after PCIe init.
PCIE devices are detected and initialized by the AMD PCIe init functions,
which is in cimx rd890. The parameters are read from devicetree.cb before PCIe init.
Now, all bridges and devices are trained on the device 0.0 enable.
After PCIe init, the PCIe ports with devices are on and the PCIe ports
without devices are off. so resources may be allocated correctly
during the rest of the PCI scan.

But if the devicetree was being used to enable/disable devices after initialization,
the problems would arise. Take a look at the serial log:

do_pci_scan_bridge for PCI: 00:02.0
PCI: pci_scan_bus for bus 01
PCI: pci_scan_bus returning with max=001
do_pci_scan_bridge returns max 1
do_pci_scan_bridge for PCI: 00:03.0
PCI: pci_scan_bus for bus 02
PCI: pci_scan_bus returning with max=002
do_pci_scan_bridge returns max 2
do_pci_scan_bridge for PCI: 00:04.0
PCI: pci_scan_bus for bus 03
PCI: pci_scan_bus returning with max=003
do_pci_scan_bridge returns max 3

PCI bridge 02.0, 03.0 and 04.0 are not inserted devices, but these bridges
are still scanned. This is not correct.

Change-Id: I87dac5f062c6926081970ed0c5f26a7e3f447395
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1640
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 02:03:36 +01:00
Siyuan Wang
fa678bb87f AMD agesa family15: PCI domain should scan bus from 0x18.0
There are four mainboards using agesa family15 code:
Supermicro h8scm and h8qgi, Tyan s8226 and AMD dinar.
All of these boards' PCI domain starts from 0x18.0. Take h8scm as
an example, PCI devices from 0.0 to 0x14.5 is under 0x18.0.
Now, the PCI domain's scan bus function stats from 0.0. This would
result to the PCI devices be scanned twice. Because when the function
run to device 18.0, it would scan from 0.0 again.
This issue would result to 2 problems:
1) PCI device may be assigned two different PCI address.
   If this happenned on VGA device, coreboot maybe not load
   vga bios correctly.
2) coreboot initializes rd890's IO APIC twice.
So this patch scans from 0x18.0 and could resolve the problems above.

Change-Id: I90fbdf695413fd24c7a5e3e9b426dc7ca6e128b1
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1639
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-11-07 02:03:05 +01:00
Kyösti Mälkki
02790369ff Remove chip.h files without config structure
Also deletes files not included in build:
    src/southbridge/amd/cimx/sb700/chip_name.c
    src/southbridge/amd/cimx/sb800/chip_name.c
    src/southbridge/amd/cimx/sb900/chip_name.c

Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-10-07 12:55:04 +02:00
Siyuan Wang
128c7d7315 agesa fam15 northbridge: change lapic_id to accommodate two CPUs
According to http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/vendorcode/amd/agesa/f15/Proc/CPU/cpuApicUtilities.c;hb=HEAD#l273 line 273,
adjust apic id to accommodate two CPUs.
The Tyan S8226 has two CPU sockets, and the current code just finds one CPU's cores.
we adjust apic_id in cpu_bus_scan so as to find all CPUs.

Change-Id: Ib3263fc6f5508f744b81e8e388fde9ccd9b51851
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1498
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-09-19 23:16:10 +02:00
Kyösti Mälkki
87213b655e Fix AMD UMA for RS780
In commit 6b5eb1cc2d setup of
UMA memory region was moved to happen at a later state and
this broke UMA with RS780 southbridge.

Share the TOP_MEM and UMA settings before any of the PCI or CPU
scanning takes place.

Change-Id: I9cae1fc2948cbccede58d099faf1dfe49e9df303
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1488
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-28 23:27:10 +02:00
Kyösti Mälkki
c33f1e9261 AMD northbridges: factor out CPU allocation
Factor CPU allocation out of AMD northbridge codes. As CPU topology
information is required for generation of certain ACPI tables, make
this code globally available.

For AMDK8 and AMDFAM10 northbridge, there is a possible case of
BSP CPU with lapicid!=0. We do not want to leave the lapic 0 from
devicetree unused, so always use that node for BSP CPU.

Change-Id: I8b1e73ed5b20b314f71dfd69a7b781ac05aea120
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1418
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27 15:36:47 +02:00
Kyösti Mälkki
cd9fc1aa5f AMD northbridges: rewrite CPU allocation
Use of alloc_find_dev() prevents creation of a device duplicates
for device_path and is SMP safe.

Reduce scope of variables to make the code more readable and in
preparation for refactoring the allocation out of northbridge.c.

Change-Id: I153dc1a5cab4f2eae4ab3a57af02841cb1a261c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1186
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-27 15:35:34 +02:00
Kyösti Mälkki
fee73df07a Auto-declare chip_operations
The name is derived directly from the device path.

Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-22 05:06:41 +02:00
Kyösti Mälkki
dbc4739a0d AMD northbridge: copy TOP_MEM and TOP_MEM2 for distribution
Take a copy of BSP CPU's TOP_MEM and TOP_MEM2 MSRs to be distributed
to AP CPUs and factor out the debugging info from setup_uma_memory().

Change-Id: I1acb4eaa3fe118aee223df1ebff997289f5d3a56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1387
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-09 19:15:32 +02:00
Kyösti Mälkki
7bdf85bfdb Move cpus_ready_for_init() to AMD K8
The function is a noop for all but amd/serengeti_cheetah.

Change-Id: I09e2e710aa964c2f31e35fcea4f14856cc1e1dca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1184
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2012-08-07 06:40:41 +02:00
zbao
ffb6bddea2 AMD f15: Change multiply ONE_MB to bit shifting (Propagation)
Apply the change
http://review.coreboot.org/1263
to family15 northbridge.

Change-Id: If1109f20ffd833a716e092c5e4f6f16ee6b968c7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
[km: rebased]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1405
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-08-05 16:18:47 +02:00
zbao
15dc3ccaab AMD f15 nb: Remove the misleading 0x100 from the limitk (Propagation)
Apply the change
http://review.coreboot.org/1265
to all the AMD northbridge.

Change-Id: Idf3994c1e9ec76cd19db9f740d825cf24059884f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1404
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 05:42:03 +02:00
zbao
49bb26a469 AMD NB: Limit the device field to 5 bits. (Propagation)
Apply the change
http://review.coreboot.org/1264
to all the AMD northbridge.

Change-Id: Ied74d6f579d2c0350288e2619d7810f8d44fa574
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1403
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-04 05:41:27 +02:00
zbao
d462736dfb Limit the device field to 5 bits.
The field device in PCI_ADDRESS only takes 5 bits. So if the device number is
more than 32, it will truncated to 5 bits. Before this patch, other pci devices
will be incorrectly probed as processor node.

Change-Id: I64dcd4f4fda7b7080a9905dce580feb829584b94
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 18:19:00 +02:00
Kyösti Mälkki
6b5eb1cc2d AMD and GFXUMA: move setup_uma_memory() to northbridge
UMA region can be determined at any time after the amount
of RAM is known and before the uma_resource() call.

Change-Id: I2a0bf2d3cad55ee70e889c88846f962b7faa0c7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1379
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:56:09 +02:00
Kyösti Mälkki
30f04645c1 AMD Agesa and GFXUMA: drop use of uma_memory_base
Without GFXUMA, variables were not referenced anywhere.
Fail builds on Family10 if GFXUMA is selected, because the northbridge
code does not set UMA base or size.

Change-Id: I15b91cf6241e9a890398eed03824b753828a0a51
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1247
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:55:28 +02:00
Kyösti Mälkki
f803ac4a45 AMD K8 and AMDFAM10, GFXUMA: drop use of uma_memory_base
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.

Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.

Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
2012-08-02 12:54:55 +02:00
zbao
9fd183efde AMD F15tn northbridge: Remove the misleading 0x100 from the limitk.
I dont known if missed something, but why an extra 0x100 was added to limit?
My board would get the wrong memory table entry 7f000000-7fffffff as RAM, which
is higher than TOM.
coreboot memory table:
0. 0000000000000000-0000000000000fff: CONFIGURATION TABLES
1. 0000000000001000-000000000009ffff: RAM
2. 00000000000c0000-000000005e13efff: RAM
3. 000000005e13f000-000000005effffff: CONFIGURATION TABLES
4. 000000005f000000-000000007effffff: RESERVED
5. 000000007f000000-000000007fffffff: RAM
6. 00000000a0000000-00000000afffffff: RESERVED

Ronald G. Minnich:
 I think someone who wrote the code was trying to round up the
next 0x100 boundary and did it incorrectly.
Here is code that would do it correctly:
limitk = ((resource_t)((d.mask + 0x00000ff) & 0x1fffff00)) << 9 ;

Zheng:
 Plus 0xFF is correct, but the d.mask take bit 0 as enable it.
This bit should be clear when we try to calculate the limitk.

Change-Id: I3848ed5f23001e5bd61a19833650fe13df26eef3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1265
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-08-01 17:24:04 +02:00
Patrick Georgi
efff733ad8 Refactor driver structs
Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.

Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
2012-07-26 22:25:10 +02:00
Patrick Georgi
7dc2864be7 amd/lx: Move configuration from source to Kconfig
LX has two values that are usually automatically derived but can
be overridden, that were so far defined in each board's romstage.

These values, along with the toggle to enable override are now
part of LX's Kconfig. For boards that gave values but requested
autogeneration, the values are removed.

Further improvements: Figure out the various fields in PLLMSRlo
and make them sensible Kconfig options (instead of the hex value
it is now)

Change-Id: I8a17c89e4a3cb1b52aaceef645955ab7817b482d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1227
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-26 21:33:31 +02:00
zbao
405cfe219a Change multiply ONE_MB to bit shifting.
2048 * ONE_MB will cause warning,
src/northbridge/amd/agesa/family15tn/northbridge.c:667:50: warning: integer overflow in expression [-Woverflow]
I guess it will change the data type to signed integer.
I think the bit shifting is better.

Change-Id: I823f7ead1f7d622bf653cb3bf2ae2343f5e76805
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1263
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-25 22:15:17 +02:00
zbao
d59d62484d sync the northbridge.c with other family.
Change-Id: Ice4d0202590fca0169dcda2770ca6add166b5c13
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1262
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-25 01:18:03 +02:00
zbao
6db7f348ea Trinity wrapper code improvement.
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.

Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-07-22 13:09:41 +02:00
Patrick Georgi
bcdbe90296 Drop VGA_BRIDGE_SETUP config option
It defaults to true, and isn't disabled anywhere in the tree.
I also couldn't think of a case where it's actually useful.

Change-Id: I126a47625d5294f3cfff225629f2a948a83c9b7e
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1250
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-07-20 23:36:22 +02:00
Kyösti Mälkki
1171986627 Drop invalid device ops on Agesa northbridge
One could not pass a device of type APIC to PCI resource functions.
The correct CPU model specific cpu->ops is set at later time in
cpu_initialize().

Change-Id: Ifa274185e4db3080433c1f07e3a48f2b55c0514f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1180
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 20:33:59 +02:00
Kyösti Mälkki
de3dde46fd AMD: Fix GFXUMA with 4GB or more RAM
Northbridge code incorrectly adjusted the last cacheable memory
resource to accomodate room for UMA framebuffer. If system had
4GB or more memory that last resource is not below 4GB and not
the one where UMA is located.

There are three consequences:

The last entry in coreboot memory table is reduced by uma_memory_size.

Due the incorrect code in northbridge code state.tomk,
end of last resource below 4GB, had not been adjusted.
Incrementing that by uma_memory_size diverts a region
possibly claimed for MMIO to RAM, as TOP_MEM is written.

Since the UMA framebuffer did not have IORESOURCE_CACHEABLE,
it was ignored from the MTRR setup and not set uncacheable.

The setting of TOP_MEM and TOP_MEM2, as well as all the MTRRs,
should be copied from BSP to all APs instead of deriving the data
separately for each Logical CPU.

Change-Id: I8e69fc8854b776fe9e4fe6ddfb101eba14888939
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1217
Tested-by: build bot (Jenkins)
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:57:43 +02:00
Kyösti Mälkki
ba589e3630 Move setup_uma_memory() to K8 northbridge
These boards had identical UMA code:
  amd/dbm690t
  amd/pistachio
  technexion/tim5690
  technexion/tim8690

The ones below had whitespace or debug level change
compared to the one above:
  kontron/kt690
  siemens/sitemp_g1p1

These boards use AMDFAM10 guidelines in code:
  asrock/939a785gmh
  amd/mahogany

Change-Id: Id7c3f48035727f5847f2d7c3a6e87a3d15582003
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1210
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:46:33 +02:00
Kyösti Mälkki
231f261402 Move setup_uma_memory() to AMDFAM10 northbridge
Following boards had identical code:
  advansus/a785e-i
  amd/bimini_fam10
  amd/mahogany_fam10
  asus/m5a88-v
  avalue/eax-785e
  gigabyte/ma78gm
  iei/kino-780am2-fam10
  jetway/pa78vm5

Following boards had identical code:
  amd/tilapia_fam10
  asus/m4a78-em
  asus/m4a785-m
  gigabyte/ma785gm
  gigabyte/ma785gmt

In between the two, only whitespace difference.

Change-Id: Iaa48cc7b0038ebcc81be49219b4fc87670aa9941
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1209
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:37 +02:00
Kyösti Mälkki
55fff930ce Move setup_uma_memory() to Agesa Family14 northbridge
Following boards had identical code:
  amd/inagua
  amd/persimmon

The following had only whitespace or debug level changes
compared to ones above.
  amd/union_station
  amd/south_station
  asrock/e350m1

Change-Id: I11ee46e06e1dd510cba551166189ebcaa144464b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1208
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:45:09 +02:00
Kyösti Mälkki
d4821fc702 Move setup_uma_memory() to Agesa Family12 northbridge
Change-Id: Ieaf284c207f0cd4b2f6b804c52f949c16435d823
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:44:29 +02:00
Kyösti Mälkki
03548aa6b8 Move setup_uma_memory() to Agesa Family15 northbridge
Change-Id: I5705623f5067823fae5986b3bcde58504a463508
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:43:35 +02:00
Kyösti Mälkki
cc55b9b919 Define global uma_memory variables
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.

It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.

Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:41:46 +02:00
Kyösti Mälkki
63f8c08830 Add global uma_resource()
Like ram_resource(), but reserved and not cacheable.

Switch all AMD northbridges to use this one.

Change-Id: I88515c6a0f59f80fd8607c390d0d4a2a35d805f2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1203
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-16 18:38:46 +02:00
zbao
2c08f6ade4 AGESA F15 wrapper for Trinity
The wrapper for Trinity. Support S3. Parme is a example board.

Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-07-03 09:38:55 +02:00
Vikram Narayanan
2f00ce3d96 cbtypes.h: Unify cbtypes.h used in AMD board's code
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.

Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-05-24 17:38:42 +02:00
Patrick Georgi
f8f00629e3 Some more #if cleanup
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)

Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +

Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-05-08 00:38:11 +02:00
Patrick Georgi
e166782f39 Clean up #ifs
Replace #if CONFIG_FOO==1 with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1[[:space:]]*\$,#if \1," {} +

Replace #if (CONFIG_FOO==1) with #if CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*1)[[:space:]]*\$,#if \1," {} +

Replace #if CONFIG_FOO==0 with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0[[:space:]]*\$,#if \!\1," {} +

Replace #if (CONFIG_FOO==0) with #if !CONFIG_FOO:
find src -name \*.[ch] -exec sed -i "s,#if[[:space:]]*(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]*0)[[:space:]]*\$,#if \!\1," {} +

(and some manual changes to fix false positives)

Change-Id: Iac6ca7605a5f99885258cf1a9a2473a92de27c42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1004
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
2012-05-08 00:34:34 +02:00
Martin Roth
a403c687b1 Add default map_oprom_vendev() for AMD Family 14h processors.
AMD supplies their video bios for the Family 14h processor line
with Vendor ID: 1002, Device ID: 9802.  This rom should work for
Device IDs 9802-9809.  This patch maps all those device IDs to
0x9802 so coreboot will be able to load the vbios.  If a vbios
rom using the ACTUAL Device ID is loaded, this function will not
be called.
This file should contain of all Family 14h Graphics PCI IDs so
that they don't need to be overridden on a per mainboard basis.

Change-Id: If3d4a744b3c400dea9444a61f05382af2b2d0237
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/955
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-30 17:20:32 +02:00
Patrick Georgi
26b00e6d39 Refactor some alignment handling
Made using coccinelle:
  @@
  expression E;
  @@
  -(E + 7) & -8
  +ALIGN(E, 8)

  @@
  expression E;
  @@
  -(E + 15) & -16
  +ALIGN(E, 16)

Change-Id: I071d2c98cd95580d7de21d256c31b6368a3dc70b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/910
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-04-20 21:18:02 +02:00
zbao
f72237346d S3 code in coreboot public folder.
1. Move the Stack to high memory.
2. Restore the MTRR before Coreboot jump to the wakeup vector.

Change-Id: I9872e02fcd7eed98e7f630aa29ece810ac32d55a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/623
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-04-16 18:22:47 +02:00
Bernhard Urban
cab72d9b7b amdfam10: add phenom II as known cpu
Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7
Signed-off-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-on: http://review.coreboot.org/864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-04-05 23:12:24 +02:00
Stefan Reinauer
dd3b227fb9 Fix AMD Fam15 CBMEM allocation
The Fam15 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: I8a00e05884bdb1d1a4a012433b0adfbb9eb22983
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/796
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:53 +01:00
Stefan Reinauer
30b46cefb5 Fix AMD Fam12 CBMEM allocation
The Fam12 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: I1eca18e21fa59ae32e802d8452e42e8b7a3575cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/795
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:45 +01:00
Stefan Reinauer
cc6c615d29 Fix AMD Fam10 CBMEM allocation
The Fam10 northbridge.c had hardcoded the CBMEM size. It should use
the one in cbmem.h instead.

Change-Id: Id6c4128d8f5f6a417f83daa3a39b2bfc8e810f8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/794
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-03-16 23:17:28 +01:00
Kyösti Mälkki
3ae1c65127 AMD Agesa: delete no-op bootblock files
Removes files:
  src/northbridge/amd/agesa/family10/bootblock.c
  src/northbridge/amd/agesa/family12/bootblock.c
  src/northbridge/amd/agesa/family14/bootblock.c
  src/northbridge/amd/agesa/family15/bootblock.c

Change-Id: Ic3617a673b38d065ca272c4de8ef765ecd3f98b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/793
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:40:48 +01:00
Kyösti Mälkki
d11ca1d08d Rename AMD_AGESA to CPU_AMD_AGESA
Also any CPU_AMD_AGESA_FAMILYxx selects CPU_AMD_AGESA, so remove
the explicit selects from the mainboards.

Change-Id: I4d71726bccd446b0f4db4e26448b5c91e406a641
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/792
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:40:35 +01:00
Kyösti Mälkki
f5bb4771de Fix AMD Agesa leaking Kconfig
Kconfig leaked XIP_ROM_SIZE to other platforms and also
defined obsolete option XIP_ROM_BASE.

Alias AMD_AGESA as NORTHBRIDGE_AMD_AGESA.
Break the circular dependency with family15 Kconfig.

Change-Id: Ic7891012220e1bef758a5a39002b66971d5206e3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/773
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 22:39:09 +01:00
Kyösti Mälkki
35e1c861f5 VIA southbridge K8T890: Apply un-written naming rules
Use separate Kconfig option to select a driver directory for
build and the specific type of southbridge to support.

Change-Id: I9482d4ea0f0234b9b7ff38144e45022ab95cf3f3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/685
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-03-16 19:45:47 +01:00
Marc Jones
5750ed253a Fix AMD Fam14 cbmen allocation
The Fam14 northbridge.c had hardcoded the cbmem size. It should use
in cbmem.h instead.

Change-Id: I910329fc98a4cf04dc81ef66f3aa05a1916f5b1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/790
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
2012-03-16 19:31:03 +01:00
Marc Jones
8d595698bf Clean up whitespace in fam14 northbridge.c
Change-Id: Id7947d7f3c67fdda67861065b1bc7a519b97208f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/789
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2012-03-15 21:27:20 +01:00
Patrick Georgi
c5fc7db355 Move C labels to start-of-line
Also mark the corresponding lint test stable.

Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-07 17:48:03 +01:00
Marc Jones
067d22340c Fix ECC disable option for AMD Fam10 DDR2 and DDR3.
The logic was backwards on the ECC enable/disable option. Also added better
debug output when the debug RAM init feature is enabled.

Change-Id: I60bffb6149d96cac65011247ef51cd06ed2210c6
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/670
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-03-02 23:35:26 +01:00
Patrick Georgi
472efa6041 Remove whitespace.
Fix issues reported by new lint test.

Change-Id: I077a829cb4a855cbb3b71b6eb5c66b2068be6def
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-02-17 19:04:31 +01:00
Kerry Sheh
6811f75457 AGESA F15: AGESA family15 model 00-0fh northbridge wrapper
Change-Id: I87c4d47f19161c604b0285102bb3809c8337375a
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/556
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 21:26:14 +01:00
Kerry Sheh
6b909f21af RD890: AMD RD890/SR56X0 CIMX wrapper
Support AMD RD890 CIMX support AMD RD890TV, RX780, RD780, SR56x0,
RD890 and 990FX chipsets.

Change-Id: I39dc5fc316fbb465808bac48a13a49b7d867f04f
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/559
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2012-02-16 19:35:09 +01:00
Nils Jacobs
976f8cc1e2 Make Geode GX2 VGA setup work.
Add MSR register write for VGA memory setup
Add missing license
Add bit explanation

Change-Id: I1cb36eeccd84f0056c829f50d9864047654ce906
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/580
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2012-01-26 22:15:56 +01:00
Nils Jacobs
d0ac789e21 Update geode GX2 tree to match LX.
Change-Id: I5b99c531e44ea09990b9da0b97213fb7945f34ee
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/512
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2012-01-07 11:46:50 +01:00
Marc Jones
84e0dfcbf2 Clean up AMD Fam14 SSDT
The old SSDT ACPI code would only include the AGESA or the coreboot SSDT. Now
include both. AGESA generates the Pstate SSDT and the second coreboot SSDT is
for TOM and TOM2. Now, generate the coreboot SSDT instead of patching it. This
fixes some ACPI errors in Linux and Windows bluescreens.

The Persimmon acpi_tables.c is where the main changes were made and then
replicated in the other Fam14 boards. Please test the other mainbords if you
have one.

Change-Id: I808c863597e024e3e8aeec0821e8618d96cc96a6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/516
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2012-01-05 17:29:11 +01:00
Nils Jacobs
a4f06f183b White space and coding style fixes.
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736
Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl>
Reviewed-on: http://review.coreboot.org/511
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-31 14:56:35 +01:00
Florian Zumbiehl
36b53bf244 k8: add CONFIG_K8_FORCE_2T_DRAM_TIMING and enable it for asus k8v-x
Change-Id: Ia457f92f6fb7e287defb838db07f12d0f1766757
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/481
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-12-14 08:50:45 +01:00
Kyösti Mälkki
2a830d0b98 Change AMD vendorcode build
Apply the normal method of recursively including subdirectories
for src/vendorcode. Remove redundant references under
mainboard and northbridge.

Change-Id: I914a6e262ed2abe83f407df36fe5c1af5eb4bcb0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/468
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-12-02 08:59:26 +01:00
Florian Zumbiehl
fa48b96908 k8 raminit: fix bug, improve clock selection, add clock limit for sock754
in amdk8 raminit:
- fix DDR SPD offset for (CLX - 1) (25 instead of 26)
- improve clock/CL selection algorithm
- implement load-dependent clock limiting for socket 754

Change-Id: I5eb8a3e02eaca18f3bef9a98de22f23b23650762
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/377
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-23 01:05:40 +01:00
Florian Zumbiehl
6f7b1589fa fix DDR_MASK in load-dependent clock limiting for socket 939 in k8 raminit
Change-Id: Ibdce9712f5019863b1cd61b68da11d7c46c6b6f8
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/376
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2011-11-16 22:40:21 +01:00
Florian Zumbiehl
7e9de01c47 Cycle time at CAS Latency (CLX - 2) is at 25 in DDR2 SPD, not at 26
Change-Id: Ic77854130ad43715daa7c0eb462291db48df9f84
Signed-off-by: Florian Zumbiehl <florz@florz.de>
Reviewed-on: http://review.coreboot.org/370
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-07 11:40:55 +01:00
Stefan Reinauer
5ff7c13e85 remove trailing whitespace
Change-Id: Ib91889a374515d36a2b12b53aeb12b6ea6e22732
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-11-01 19:07:45 +01:00
Stefan Reinauer
328a694a3f AMD CPU and chipset fixes for compilation with gcc 4.6
Change-Id: I05b08765b38d8d6cc9b7cbdaf87c127b33408c81
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/266
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-15 13:40:17 +02:00
Stefan Reinauer
86fc9848ae Fix compilation of AMD GX2 northbridge code with gcc 4.6
Change-Id: I71d96b7cd36dd99a3590ec311c11f67f13012e68
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/267
Tested-by: build bot (Jenkins)
Reviewed-by: Uwe Hermann <uwe@hermann-uwe.de>
2011-10-14 22:54:06 +02:00
Christoph Grenz
80311eab8c amdk8: ASL include for K8 temperature sensor support in ACPI
Add a ACPI Source Language snippet which if included as
shown in the comments in the file, exposes the 4 possible
temperature sensors in the CPU as ACPI thermal zones.

Change-Id: I94dd773108e348a0fdb9d2f8d6cfe415d5fa0339
Signed-off-by: Christoph Grenz <christophg+cb@grenz-bonn.de>
Reviewed-on: http://review.coreboot.org/222
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-12 07:54:25 +02:00
enok71
af90275a41 TINY_BOOTBLOCK problem-fix on amdk8+amd8111 platforms
The hp/dl145_g1 motherboard did not work since commit
1f7d3c5672 (svn 6124). That commit added
TINY_BOOTBLOCK for amd8111 southbridge. The result was that the boot process
stopped very early (no console output whatsoever). The same symptom was
reported on other AMDK8 based boards with amd8111 southbridge chips. This
commit seems to fix the bug. It adds a bootblock.c under
src/northbridge/amd/amdk8 that calls enumerate_ht_chains. Probably the
problem was that enum_ht_chains needs to be called before the southbridge
bootblock.c function, not after.

Change-Id: I74fb892aa39048e2d0e76c081b713f825d67f2d4
Signed-off-by: Oskar Enoksson <enok@lysator.liu.se>
Reviewed-on: http://review.coreboot.org/235
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-10-03 23:17:33 +02:00
QingPei Wang
8eb4273290 Add AMD Family 10h PH-E0 support
the patch file comes from
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/RevE
/F10MicrocodePatch010000bf.c

Change-Id: If701c8a908edf1c486665d3ce4df65da0f65c802
Signed-off-by: QingPei Wang <wangqingpei@gmail.com>
Reviewed-on: http://review.coreboot.org/202
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-09-24 15:58:12 +02:00
efdesign98
3f5ebd6533 AMD F14 Northbridge updates
This change is warning and whitespace fixes in the
northbridge code for AMD Family 14 rev C0 cpu update.
This does not address warnings in the mainboard,
Agesa, Cimx, or southbridge code.

Change-Id: I7ee7018a292ebb2343c9b7986dd21227185879dc
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/134
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-09-14 23:45:40 +02:00
Kerry She
feed329a0c AMD F14 southbridge update
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.

Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-09-07 01:08:57 +02:00
efdesign98
00c8c4a316 Update AMD SR5650 and SB700
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes.  The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements.  This particular change
affects all mainboards that use the SB700, and their changes are
include herein.  These mainboards are:
  Advansus a785e,
  AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
  Asrock 939a785gmh,
  Asus m4a78-em, m4a785-m,
  Gigabyte ma785gm,
  Iei Kino-780am2-fam10
  Jetway pa78vm5
  Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.

Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-07-22 00:20:59 +02:00
efdesign98
b58640c5ef Add AMD Family 10 cpu support to northbridge folder
This change adds the AMD Family 10 cpu support to the northbridge
folder.  The northbridge/amd/agesa Kconfig and Makefile.inc are
changed as well.

Change-Id: Id76e9fa388c79ac469a673aaedaa4f1bfd7619d9
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/98
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2011-07-18 21:55:59 +02:00
Scott Duplichan
7d6f0bf10e ASRock E350M1: ACPI-related BSOD fix
On installing/starting Windows (tested with Win7 Ultimate)
the system crashes with a Blue Screen of Death, reporting an ACPI BIOS error.

From Scott Duplichan:
To avoid the Windows BSOD, the uninitialized value TOM1 in the SSDT
must be corrected. The attached patch does this. It uses the older
patching method, and not the (possibly preferred) AML generation
method. To simplify the patching operation, I moved the AML item
'TOM1' to the start of the SSDT. The patch also includes code to
confirm the AML variable TOM1 is at the expected offset before patching.

Also tested & working with Linux.

Change-Id: I59cedc366e09d98f690b093d6a21fc0c864559c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/91
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-10 18:31:29 +02:00
Cristian Măgherușan-Stanciu
1fe6c64ba1 Fix memory size reporting on AMD family 14h systems for >= 4GB
Applying Scott Duplichan's fix for memory >=4GB

Adjusted it to the new directory structure (agesa_wrapper was renamed to
just agesa).

Boot-tested and confirmed to work, on my board Linux can now access the
whole RAM.

Change-Id: I31d66a488a7811d214d84653860b3e0116f67d19
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Signed-off-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Reviewed-on: http://review.coreboot.org/48
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
2011-07-09 01:51:42 +02:00
Rudolf Marek
23b215272d Improve VIA K8M890 HT settings. Use recommended settings for ROMSIP and
for the transmit clock driving control. Unfortunately this is not enough
to make the HT1000 work reliably, therefore blacklist this for now in CPU
HT code. If ever anyone figure out what is wrong, it could be removed. The
downgrading now makes the board work on HT800, which is certainly better than
not at all with a HT1000 CPU.

Change-Id: I949bfd9b0b48ee12bd0234c2fb1deaaa773bd235
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/68
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-30 19:16:37 +02:00
efdesign98
7c0c64e103 Addition of Family12/SB900 wrapper code
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.

Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2011-06-28 23:09:25 +02:00
efdesign98
621ca384a7 Move existing AMD Ffamily14 code to f14 folder
This change moves the AMD Family14 cpu Agesa code to
the vendorcode/amd/agesa/f14 folder to complete the
transition to the family oriented folder structure.

Change-Id: I211e80ee04574cc713f38b4cc1b767dbb2bfaa59
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/52
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:35:45 +02:00
efdesign98
05a89ab922 Rename {CPU|NB|SB}/amd/*_wrapper folders
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.

Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
2011-06-22 01:27:46 +02:00
Marc Jones
471f103e53 This patch sets max freq defaults for ddr2 and ddr3for fam10.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6619 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-06-03 19:59:52 +00:00
Peter Stuge
16c8e37a2d agesa_wrapper: Avoid repetitive Kconfig depends, trivial
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6595 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:40:40 +00:00
Scott Duplichan
8c46263721 Cosmetic cleanup.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6594 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:10:15 +00:00
Scott Duplichan
5d878ad312 1) Remove unused kconfig options.
2) Correct UMA graphics PCI device ID.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6593 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 22:09:09 +00:00
Scott Duplichan
9ab3c6c3a9 Build device paths for AP cores so that coreboot will report them to the OS.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:45:46 +00:00
Scott Duplichan
dc312cca53 Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15 21:26:04 +00:00
Patrick Georgi
8d6cf3a2d7 Work around unclean CMOS handling for now
Stefan switched away from #ifdef across the tree (and is absolutely right with that), but
unfortunately there are some special cases that trigger in even more special situations.

Revert one such change selectively. It's destined to go once CMOS is reworked.

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6566 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-11 07:44:27 +00:00
Patrick Georgi
b251753b4f Change read_option() to a macro that wraps some API uglyness
Simplify
read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault)
to
read_option(foo, somedefault)

Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10 21:53:13 +00:00
Stefan Reinauer
d4814bd41c more ifdef -> if fixes
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6536 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21 20:45:45 +00:00
Zheng Bao
b18f9b0ff4 The "temp" will be used later. So it has to be calculated correctly.
Comment by Peter,
The variable name "temp" unfortunately does not explain what the value
is. The commit message also does not have hints. Hopefully in the
future it's possible to also use a brief moment to improve the clarity
of the code, while it is already being fixed for some other
reason. Ie. fixing up variable names, writing particularly informative
commit messages, or of course both at the same time! :)

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6517 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 06:40:56 +00:00
Stefan Reinauer
432461ec7f cleanup wrong use of defined() after exporting all variables in Kconfig
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6514 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19 00:36:39 +00:00
Alexandru Gagniuc
5005bb06c1 Unify use of post_code
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>                                                                                                         
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11 20:17:22 +00:00
Zheng Bao
2ca2f17724 Add AMD C32 support.
It is based on other existing Fam10 code.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6464 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28 04:29:14 +00:00
Scott Duplichan
314dd0bee5 Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF.
The patch makes these changes:

1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15
   romstage.c files where it is used (AMD family 10h projects).
2) Add a prototype to amdfam10.h.
3) Modify the swap list and test in real hardware for mahogany_fam10 and
   kino family 10h and confirm HT3 operation for the SB link.

Abuild tested.

Signed-off-by: Scott Duplichan <sc...@notabs.org>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08 23:01:46 +00:00
Patrick Georgi
11ac1cfaa3 Mark non-returning function as noreturn to help some compiler versions
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6418 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01 07:30:14 +00:00
Xavi Drudis Ferran
6bdc83bf5e Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I don't understand what this was doing nor find docs for these regs
Maybe it was left over from some copy & paste ?

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:56:52 +00:00
Xavi Drudis Ferran
c3132105bd Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

In fact I changed coreDelay before deleting
the code in fidvid that called it. But there're
still a couple of calls from src/northbridge/amd/amdmct/wrappers/mcti_d.c
Since the comment encouraged fixing something, I
parametrized it with the delay time in microseconds
and paranoically tried to avoid an overflow at pathological
moments.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6408 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:49:28 +00:00
Xavi Drudis Ferran
6276b6f151 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

bits 13 - 15 of F3xd4 (StutterScrubEn, CacheFlushImmOnAllHalt and MTC1eEn
are reserved for revisions D0 and earlier, so whe should not set them
to 0 in fidvid.c config_clk_power_ctrl_reg0(...), called from prep_fid_change.
For revisions > D0 (when we support them) it is ok not ot clear them,
because they are documented as 0 on reset. bit 12 should be left alone
according to BKDG. Should I set 11:8 ClkRampHystSel to 0 in the mask
too, just to indicate we're touching them ? We'll OR them to 1111 anyway...

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6407 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:35:43 +00:00
Xavi Drudis Ferran
82b241a2b5 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Well, I understand it better like this, but maybe
it's only me, part of the changes are paranoic, and
the only effective change is for a factor depending on
mobile or not that I can't test.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6406 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:32:23 +00:00
Xavi Drudis Ferran
5bcedee0f8 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add an untested step in BKDG 2.4.2.8. I don't
have the hardware with Core Performance Boost and
I think it's only available in revision E that does
not even have a constant yet.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6405 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:25:07 +00:00
Xavi Drudis Ferran
ce62350d8f Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add to init_fidvid_stage2 some step
mentioned in BKDG 2.4.2.7 that was missing . Some lines
are dead code now, but may handy if one day we support
revison E CPUs.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6404 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:19:17 +00:00
Xavi Drudis Ferran
e80ce0a134 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Add to init_fidvid_stage2 some step for my CPU (rev C3)
mentioned in BKDG 2.4.2.6 (5) that was missing

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6403 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:12:00 +00:00
Xavi Drudis Ferran
26f97d2cf9 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Looking at BKDG the process for updating
Pstate Nb vid after warn reset seemed
more similar to the codethat was there fo
pvi than the one for svi, so I called the
pvi function passing a pvi/svi flag. I don't
find documentation on why should UpdateSinglePlaneNbVid()
be called in PVI, but since I can't test it,
I leave it as it was.

This patch showed some progress beyond fidvid in my
boar,d but only sometimes, most times it just didn't
work.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6402 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:08:06 +00:00
Xavi Drudis Ferran
19245c94c8 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Factor out some common expressions.
Add an error message when coreboots hangs waiting for a pstate
that never comes (it happened to me), and throw some
paranoia at it for good mesure.

If I understood BKDG fam10 CPUs never need a software initiated vid transition,
because the hardware knows what to do when you just request
a Pstate change if the cpu is properly configured. In fact
unifying a little what PVI and SVI do was better for my board (SVI).
So I drop transitionVid, which I didn't understand either (why
did it have a case for PVI if it is never called for PVI ?
Why did the PVI case distinguigh cpu or nb when PVI is
theoretically single voltage plane ? ).

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6401 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 03:02:40 +00:00
Xavi Drudis Ferran
e485aa496b Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Contemplate the possibility of nbCofVidUpdate not being
defined, trying to get closer to BKDG

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6399 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 02:33:59 +00:00
Xavi Drudis Ferran
1f93fea160 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

BKDG says nbSynPtrAdj may also be 6 sometimes.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6397 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:24:21 +00:00
Xavi Drudis Ferran
0e5d3e16b4 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

I didn't understand quite why it did that iwth F3xA0 (Power
Control Misc Register) so I moved Pll Lock time to rules in defaults.h
and reimplemented F3xA0 programming. A later patch will remove
a part I don't know what's mean to do.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6396 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:18:43 +00:00
Xavi Drudis Ferran
adb23a51f5 Improving BKDG implementation of P-states,
CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode.

Bring F3xD4 (Clock/Power Control Register 0) more in line
with BKDG i more cases. It requires looking at the CPU package type
so I add a function for that (in the wrong place?) and some
new constants

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6395 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28 00:10:37 +00:00
Xavi Drudis Ferran
70a3733155 Add 300 MHz and 500 MHz HT frequency limits
Needed to build successfully with Expert mode enabled.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6386 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-27 02:48:41 +00:00
Josef Kellermann
ed1d116e62 Add compile-time defaults to some K8 CMOS options in case they're absent in CMOS
This affects the CMOS options iommu, ECC_memory, max_mem_clock,
hw_scrubber, interleave_chip_selects.
If they're absent in cmos.layout, a Kconfig value is used if it exists,
or a hardcoded default otherwise.

[Patrick: I changed the ramstage CMOS handling a bit, and dropped the
reliance of hw_scrubber on ECC RAM, as it has nothing to do with it -
it's the cache that's being scrubbed here.]

Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6380 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24 14:35:42 +00:00
Josef Kellermann
f0ccf6ed18 Errata #169 works on HT, not MC
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6355 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 19:21:28 +00:00
Frank Vibrans
39fca80b00 This code provides cpu northbridge initialization for Family 14h cpus. It is dependent on the AMD Agesa code.
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6345 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14 18:35:15 +00:00
Alexandru Gagniuc
1df854248b Implemented workaround for erratum 169, obsoleting erratum 131.
Workaround for 131 removed.
Changed workaround for erratum 110 to only include pre-revision-F
processors.

For details, check AMD publications:
#25759 (Errata for Fam F pre-revision F processors)
#33610 (Errata for Fam F revision F and later processor)

Based on work and previous patches by:
Rudolf Marek <r.marek@assembler.cz> 
Josef Kellermann <seppk@arcor.de>

Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6340 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-10 07:51:51 +00:00
Zheng Bao
dd676ddc54 For Cx, each ChipSel need to be sent MR command.
After this patch, tilapia can run in higher memory frequency.
To test the high frequency, dont forget to change the freq limit in
mcti_d.c:
 static void mctGet_MaxLoadFreq(struct DCTStatStruc *pDCTstat)
 {
	 pDCTstat->PresetmaxFreq = 800;
 }

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6276 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20 02:09:24 +00:00
Nils Jacobs
c29675f332 Add a GX2 Kconfig option to choose the framebuffer size.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6275 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-19 07:25:26 +00:00
Zheng Bao
a7296e74f1 The code is tested on my board with register DIMMs. More tests need to be
done. Please send the testing report.

Note: The pDCTstat->PresetmaxFreq in mctGet_MaxLoadFreq() should be set
to a higher limit, otherwise the frequnce will be set as 400MHz.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Scott Duplichan <scott@notabs.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6258 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-17 02:20:33 +00:00
Zheng Bao
69436e1a8c Fix some settings fo AMD MCT. It is based on BIOS test suite.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6246 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06 02:18:12 +00:00
Nils Jacobs
8cf54c9f23 Use die() to assure the processor can't wake up from an interrupt.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6224 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-30 19:21:08 +00:00
Nils Jacobs
84be0f59b7 -Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
       databook. (Part1)
       This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code  to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .


Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29 21:12:10 +00:00
Nils Jacobs
19d69e3bab Move Geode GX2 UMA video memory size to Kconfig
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6211 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:24:50 +00:00
Nils Jacobs
642509c965 Remove dead and unused Geode GX2 code
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6210 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:21:18 +00:00
Nils Jacobs
3344743215 Replace Geode GX2 MSR addresses for GLCP on GLIU1 with names
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:16:47 +00:00
Nils Jacobs
1c6d4e6055 Clean up Geode GX2 comments, whitespace and coding style. Trivial.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6208 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26 05:12:49 +00:00
Rudolf Marek
cc1e645248 Attached patch implements the memory speed reductions (and 2T/1T clock logic) for DDR1 memory (939 sockets). The details can be found in BKDG chapter 4.1.3.3.
The patch looks at certain DDR configurations (dual rank/single rank) and lowers the clocks to 2T or frequency as guide suggest. It sets the DualDIMMen bit which I believe should be set for non-dual channel configs.

The patch does not implement support for three dimm configurations supported from revE.
On the other hand it should improve greatly memory stability across the 939 platform.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6176 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 20:43:33 +00:00
Rudolf Marek
59f410fa43 Following patch adds support to bring out the memory out of self refresh when doing resume.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>

The patch is based on my 2008 patch. 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6172 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:53:58 +00:00
Rudolf Marek
97be27ebba We hardcode highmemory size in every northbridge! This is bad, and especially if suspend to ram is involved. Let the default be taken from cbmem.h which also handles the suspend logic.
Abuild tested. Please check all changes if I did not make any wrong while converting this to bytes.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6171 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-13 19:50:25 +00:00
Stefan Reinauer
8677a23d5b After this has been brought up many times before, rename src/arch/i386 to
src/arch/x86. 

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6161 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-11 20:33:41 +00:00
stepan
8301d8348a second round name simplification. drop the <component>_ prefix.
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.

Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)

- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong

Signed-off-by: <stepan@coresystems.de>

Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6150 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-08 07:07:33 +00:00
Myles Watson
1bc5ccac51 Move MMCONF resource into the domain for fam10 for the resource allocator.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Scott Duplichan <scott@notabs.org>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6148 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-07 19:34:01 +00:00
Zheng Bao
ea62e9b47d More explicite and straight way to set seed.
The read-modify-write wasn't needed. This is easier to understand.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6136 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-02 01:50:38 +00:00
Rudolf Marek
bcaea142f3 1) wraps the s3 parts of chipset code/memory init code with if CONFIG_HAVE_ACPI_RESUME == 1 getting rid of ugly define in romstage.c
2) the patch implements get_cbmem_toc in chipset specific way if defined.
On Intel targets it should be unchanged. On K8T890 the the cbmem_toc is read from NVRAM. Why you ask? Because we cannot do it as on intel, because the framebuffer might be there making it hard to look for it in memory (and remember we need it so early that everying is uncached)

3) The patch removes hardcoded limits for suspend/resume save area (it was 1MB) on intel. Now it computes right numbers itself.

4) it impelements saving the memory during CAR to reserved range in sane way. First the sysinfo area (CAR data) is copied, then the rest after car is disabled (cached copy is used). I changed bit also the the copy of CAR area is now done uncached for target which I feel is more right.

I think I did not change the Intel suspend/resume behaviour but best would be if someone can test it. Please note this patch was unfinished on my drive since ages and it would be very nice to get it in to prevent bit rotten it again.
Now I feel it is done good way and should not break anything. I did a test with abuild and it seems fine.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz> 
Acked-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Stefan Reinauer <stepan@coreboot.org>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6117 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 22:00:52 +00:00
Stefan Reinauer
abc0c85516 Printing coreboot debug messages on VGA console is pretty much useless, since
initializing VGA happens pretty much as the last thing before starting the
payload. Hence, drop VGA console support, as we did in coreboot v3.

- Drop VGA and BTEXT console support. 
  Console is meant to be debugging only, and by the time graphics comes up
  99% of the risky stuff has already happened. Note: This patch does not remove
  hardware init but only the actual output functionality. 

  The ragexl driver needs some extra love, but that's for another day
- factor out die() and post()
- drop some leftover RAMBASE < 0x100000 checks.

Signed-off-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: QingPei Wang<wangqingpei@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6111 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-22 08:09:50 +00:00
Uwe Hermann
d773fd370a Some more DIMM0 related cleanups and deduplication.
- VIA VT8235: Do the shift in smbus_read_byte() as all other chipsets do.

 - spd.h: Move RC00-RC63 #defines here, they were duplicated in lots of
   romstage.c files and lots of spd_addr.h files. Don't even bother for
   those spd_addr.h which aren't even actually used, drop them right away.

 - Replace various 0x50 hardcoded numbers with DIMM0, 0x51 with DIMM1,
   and 0xa0 with (DIMM0 << 1) where appropriate.

 - Various debug.c files: Replace SMBUS_MEM_DEVICE_START with DIMM0,
   SMBUS_MEM_DEVICE_END with DIMM7, and drop useless SMBUS_MEM_DEVICE_INC.

 - VIA VX800: Drop unused SMBUS_ADDR_CH* #defines.

 - VIA VT8623: Do the shift in smbus_read_byte() as all other chipsets do.
   Then, replace 0xa0 (which now becomes 0x50) with DIMM0.

 - alix1c/romstage.c, alix2d/romstage.c: Adapt to recent bit shift changes.

 - Various files: Drop DIMM_SPD_BASE and/or replace it with DIMM0.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6100 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-20 20:23:08 +00:00
Uwe Hermann
607614d0a9 Fix/drop some obsolete comments,
- s/Options.lb/devicetree.cb/
 
 - s/Config.lb/devicetree.cb/

 - s/cache_as_ram_auto.c/romstage.c/
 
 - h8dmr_fam10/README: Drop obsolete comment, we have mc_patch_01000086.h in
   the tree now.
 
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6095 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-18 20:12:13 +00:00
Tobias Diedrich
e0c0a82954 This problem was introduced with
http://tracker.coreboot.org/trac/coreboot/changeset/3953

Note that all corresponding DSDTs only ever check TOM2 against 0.

Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Rudolf Marek <r.marek@assembler.cz>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-17 11:02:05 +00:00
Scott Duplichan
f3cce2f3c4 MTRR related improvements for AMD family 10h and family 0Fh systems
-- When building for UMA, reduce the limit for DRAM below 4GB
   from E0000000 to C0000000. This is needed to accomodate the
   UMA frame buffer.
-- Correct problem where msr C0010010 bits 21 and 22 (MtrrTom2En
   and Tom2ForceMemTypeWB) are not set consistently across cores.
-- Enable TOM2 only if DRAM is present above 4GB.
-- Use AMD Tom2ForceMemTypeWB feature to avoid the need for 
   variable MTRR ranges above 4GB.
-- Add above4gb flag argument to function x86_setup_var_mtrrs. Clearing
   this flag causes x86_setup_var_mtrrs() to omit MTRR ranges for
   DRAM above 4GB. AMD systems use this option to conserve MTRRs.
-- Northbridge.c change to deduct UMA memory from DRAM size reported
   by ram_resource. This corrects a problem where mtrr.c generates an
   unexpected variable MTRR range.
-- Correct problem causing build failure when CONFIG_GFXUMA=1 and
   CONFIG_VAR_MTRR_HOLE=0.
-- Reserve the UMA DRAM range for AMD K8 as is already done for AMD
   family 10h.
Tested with mahogany on ECS A780G-GM with 2GB and 4GB.
Tested with mahogany_fam10 on ECS A780G-GM with 2GB and 4GB.
 
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6067 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-13 19:07:59 +00:00
Peter Stuge
02d66fd1bf Make amdk8 printk_raminit() accept just a single string parameter
The function is called with no format specifiers in the first parameter
throughout the code, so it needs to work also with just one parameter.

Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6056 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-10 02:12:05 +00:00
Patrick Georgi
7bbd7f2318 Move K8_ALLOCATE_IO_RANGE to Kconfig.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6036 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-07 18:20:51 +00:00
Patrick Georgi
00e1460a83 Move QRANK_DIMM_SUPPORT to Kconfig, removing it from romstage.c
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6028 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 22:59:49 +00:00
Nils Jacobs
eca32808cb Add Kconfig CPU speed selection to Geode GX2 boards.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:23:11 +00:00
Nils Jacobs
a1e2c56079 Remove banner wrapper function and unify print(k) usage.
- Drop banner(), use printk()s instead.

 - Uncomment a few printk()s, if a users doesn't want to see them he/she
   can lower the debug level.

 - Replace print_emerg() with printk(BIOS_EMERG) etc.

Also change 'Assymetirc' into 'Asymmetric', thanks to Idwer for spotting.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6021 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-05 00:13:14 +00:00
Nils Jacobs
a215b0f0be Remove some unused code from gx2/raminit.c.
This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6016 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 13:24:29 +00:00
Nils Jacobs
5beac7f996 Clean up some comments and white space in gx2/northbridgeinit.c
and gx2/raminit.c.

This is Abuild and boot tested.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6014 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-03 13:19:50 +00:00
Nils Jacobs
76890dde14 Change Geode GX2 to use the auto DRAM detect code from Geode LX.
Also, change the GX2 boards to use it.

Add a processor speed setting function in human readable MHz and remove
the useless and broken PLLMSR settings (the processor speed was hardcoded
to 366MHz in pll_reset.c).

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6011 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 15:20:27 +00:00
Nils Jacobs
9644623934 Remove some unused code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6010 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:39:49 +00:00
Nils Jacobs
809e29ec8f GX2: Clean up some white space and comments.
Also, add a copyright header to pll_reset.c.

Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6009 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:36:54 +00:00
Nils Jacobs
fc9fcf7414 GX2: Change MSR register numbers into more descriptive names.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6008 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-11-01 14:18:11 +00:00
Uwe Hermann
b69cb5a310 Convert some comments to proper Doxygen syntax.
Also, make them all fit in 80chars/column, fix some whitespace issues
and also some typos I noticed.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5993 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-26 22:46:43 +00:00
Scott Duplichan
1ba2eee2b4 Revision 5966 changed the end of line style of the 3 modified files. This change restores the original end of line style.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Scott Duplichan <scott@notabs.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:58:49 +00:00
Scott Duplichan
af786b618d When debug logging is enabled, a message such as '* AP 02 timed out:02010501'
is sometimes logged. The reason is that the AP first sets a completion value
such as 0x13, which is what function wait_cpu_state() is waiting for. Then a
short time later, the AP calls function init_fidvid_ap(). This function sets
a completion value of 01. When logging is off, wait_cpu_state is fast enough
to see the initial completion value for each of the APs. But with logging
enabled, one or more APs may go on to complete function init_fidvid_ap, which
sets the completion value to 01. While mostly harmless, the timeout does
increase boot time. This patch eliminates the timeout by making function
wait_cpu_state recognize 01 as an additional valid AP completion value.

Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5966 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-19 04:26:17 +00:00
Zheng Bao
89122856e0 Trivial. Clean up code and add some comments.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5946 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-13 02:46:59 +00:00
Uwe Hermann
4b42a62966 Factor out a few commonly duplicated functions from northbridge.c.
The following functions are moved to devices/device_util.c:

 - ram_resource()

 - tolm_test()

 - find_pci_tolm()

There are only two tolm_test() / find_pci_tolm() which differ from the
defaults, one of them can easily be eliminated in a follow-up patch,
maybe even both, but for now keep it simple and only eliminate the majority.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5937 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-11 19:36:13 +00:00
Zheng Bao
53b52f356a Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5928 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 07:18:50 +00:00
Zheng Bao
1dcf66896d Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5927 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-09 02:31:10 +00:00
Zheng Bao
c3af12fb8a Trivial. Spell checking.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 05:08:47 +00:00
Zheng Bao
3d682fe888 Trivial. Fix the typo.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5922 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-08 03:35:12 +00:00
Jonathan Kollasch
e5b7507882 Remove duplicate line from pci_ids.h.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5920 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-07 23:02:06 +00:00
Jonathan Kollasch
b7a7b7903b Use %p instead of %x to print void *.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Jonathan Kollasch <jakllsch@kollasch.net>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5915 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-05 19:38:04 +00:00
Jonathan Kollasch
ebe6d5820a Fix spelling/typos in comments.
Signed-off-by: Jonathan Kollasch <jakllsch@kollasch.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5904 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-02 12:51:38 +00:00
Patrick Georgi
e82618d037 Move CACHE_AS_RAM_ADDRESS_DEBUG out of romstage.c into Kconfig,
rename it slightly, make it visible only on relevant northbridges,
drop it entirely from via boards (as they seem to have picked it
up from AMD code without using it themselves), and make it
default to false for all boards.

Some romstages used to set this to "true" (ie. "print debug output"),
but I didn't follow up on it in Kconfig - if you need it to debug CAR,
enable it yourself.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5898 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 14:50:12 +00:00
Zheng Bao
52000e1688 Trivial. Re-indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5889 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-10-01 06:27:35 +00:00
Patrick Georgi
8463dd9db0 Rename build system variables to be more intuitive, and
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs

The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y

Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.

Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-30 16:55:02 +00:00
Zheng Bao
7b1a3c334c Trivial. re-Indent the code.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5874 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-28 04:43:16 +00:00
Xavi Drudis Ferran
7cdf1eca92 Obviously missing brackets.
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5867 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-27 21:08:40 +00:00
Patrick Georgi
86224f634a Mark read-only data as read-only, so the global vars test doesn't fail on it.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5846 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25 17:24:10 +00:00
Stefan Reinauer
10ec0fed8e - Fix race condition in option_table.h generation by moving the include
statement to those files that actually need it. This significantly 
  reduces the number of dependencies, so it's no longer extremely ugly to
  specify them manually (see the src/pc80/Makefile.inc portion)
- Add double include guards around option_table.h defines
- Also, drop the AMD DBM690T work around for the issue

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5838 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-25 10:40:47 +00:00
Zheng Bao
0c51ddd98b Complete the code which was missing.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5822 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 02:51:31 +00:00
Zheng Bao
951a0feb2d Fix the typo. Field DisAutoRefresh is in DramTimngHi.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5821 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-21 01:24:55 +00:00
Myles Watson
6c029e6963 Add reserved areas for fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5808 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:50:20 +00:00
Myles Watson
687b3ba327 Port k8 UMA handling to fam10.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5807 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 14:49:02 +00:00
Myles Watson
cb817beb67 Fix a typo reported by Sylvain Hitier.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5804 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-13 13:23:20 +00:00
Myles Watson
6ea2115cea Move memory type information out of some AMD sockets.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5800 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-10 18:33:24 +00:00
Arne Georg Gleditsch
d6689ed781 Please find appended. This patch gets rid of the %gs magic altogether,
fixes a few alignment wrinkles and sets up and registers the MMCONF area
for AMD Fam10h CPUs (where selected by mainboard configuration).  It
removes a bit of code that proved troublesome in MMCONF setups from
mcp55_early_setup_car.c, as per earlier discussion.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numascale.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5796 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 14:54:07 +00:00
Arne Georg Gleditsch
e150e9a571 Also improve boot time on AMD for the DDR3 code path.
Fix a typo, too.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5792 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 10:35:52 +00:00
Arne Georg Gleditsch
6556534bab Apparently, it's not crucial to clear this at the exact moment we switch
to using ram, so something like the appended is perhaps more
appropriate.  Confirmed to work on hw.

Signed-off-by: Arne Georg Gleditsch <arne.gleditsch@numscale.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5791 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-09 09:56:19 +00:00
Zheng Bao
f7a999ae65 Trivial. Currently the max frequency is preset as 400Mhz. We need to set a
platform specific value. Before that, we can set it manually if the boards
need to run in a higher frequency, which has been tested on Tilapia.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5777 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-05 05:52:33 +00:00
Kerry She
08c92e03bf AMD DDR2 and DDR3 MCT function InitPhyCompensation() compliant with AGESA code.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5776 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-09-04 06:13:02 +00:00
Zheng Bao
9fae99fc4e Get Byte65/66 for register manufacture ID code. RegMan1Present will
be used in write levelization training.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5758 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-31 06:10:54 +00:00
Kerry She
819ee74888 Multi-DIMMS on AMD ddr2 MCT channel B fixed.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5749 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 09:40:41 +00:00
Kerry She
99cfa1e6bd Multi-DIMMS on AMD ddr3 MCT channel B works.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 07:31:31 +00:00
Kerry She
108d30ba86 Trivial syntax correction of AMD mct_ddr3 dir.
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Kerry She <Kerry.she@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5747 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-30 07:24:13 +00:00
Jens Rottmann
b3f8090f4e drop three unneeded config variables:
- HAVE_HIGH_TABLES
- HAVE_LOW_TABLES
- FALLBACK_SIZE

Jens Rottmann sent an almost identical patch at the same time, so
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5745 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-27 09:36:41 +00:00
Jens Rottmann
0d11f2db1f CONFIG_DEBUG_RAM_SETUP and CONFIG_DEBUG_SMBUS are only available if the board /
chipset support it.  But this involves a long list of 'depends', which you have
to remember updating manually.  Converted this into HAVE_... properties, which
will be inherited automatically if someone copies a chipset to create a new
one.

Signed-off-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5743 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-26 12:46:02 +00:00
Aurelien Guillaume
6f22ecc2c9 * Adds support for PC Engines Alix.2D(1)3 board to Coreboot.
* DRAM initialization done message is now printed in debug-mode only, rather than everytime.

Signed-off-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5739 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-24 12:58:17 +00:00
Xavi Drudis Ferran
4793ef1f82 documented workaround erratum 414, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

with patch.erratum414 it stops here (next patches don't make it get further,
but they're needed according to documentation, don't break anything for me and
I still don't have a solution for booting, so I'm keeping them there in case
they fix something.

testx = 5a5a5a5a                                                                
Copying data from cache to RAM -- switching to use RAM as stack... Done         
testx = 5a5a5a5a                                                                
Disabling cache as ram now                                                      
Clearing initial memory region: Done                                            
Loading stage image.                                                            
Check CBFS header at fffffd2e                                                   
magic is 4f524243                                                               
Found CBFS header at fffffd2e                                                   
Check fallback/romstage                                                         
CBFS: follow chain: fff00000 + 38 + 15b41 + align -> fff15b80                   
Check fallback/coreboot_ram                                                     
Stage: loading fallback/coreboot_ram @ 0x200000 (1114112 bytes), entry @
0x20000

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5733 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:54:26 +00:00
Xavi Drudis Ferran
213ab94ea4 documented workaround erratum 372, see
Revision Guide for AMD Family10h processors (#41322) rev 3.74 June 2010

with this one  it stops here or earlier (as soon as before the patch,
sometimes):
               
*** Yes, the copy/decompress is taking a while, FIXME!                          
v_esp=000cbf48                                                                  
testx = 5a5a5a5a                                                                
Copying data from cache to RAM -- switching to use RAM as stack... Done         
testx = 5a5a5a5a                                                                
Disabling cache as ram now                                                      
Clearing initial memory region: 

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>




git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5732 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:51:34 +00:00
Xavi Drudis Ferran
cc6244a922 Include RB_C3 in erratum 346
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5730 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:48:29 +00:00
Xavi Drudis Ferran
752f1b4ee7 Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.
While reviewing impact of this change it seems code for erratum 531 was not in
sync with current docs. I have checked uses of AMD_FAM10_ALL, but I
haven't looked up the docs for all of them, at first sight it seems ok
to include all FAM10 revisions in this mask.

Apply errata 531 only to revisions listed in  Revision Guide for AMD Family10h
processors (#41322) rev 3.74 June 2010. Before it was applied also to
DR-B0, DA-C3 or HY-D0 which are not affected according to current docs.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5729 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-22 19:45:57 +00:00
Xavi Drudis Ferran
e660f04161 Fix warnings (that become errors) in AMDHT for certain configurations (unused functions)
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5704 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-17 06:12:59 +00:00
Zheng Bao
23ffe8b690 The number of cores is got by reading the bit 15,13,12 of [0,24,3,e8].
The bit 15 seems to be a new feature when CPU started to have more than 4
cores.

Zheng

Yes, this was add for revD.

Marc Jones

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5684 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-08-05 06:12:16 +00:00
Nils Jacobs
e474070bdd This patch converts the Geode GX2 boards to CAR.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-26 23:46:25 +00:00
Cristi M
2f969a6ab0 Trivial -Werror fix.
Signed-off-by: Cristi M <cristi.magherusan@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5663 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-09 18:06:23 +00:00
Stefan Reinauer
6f57b514cb Fix all warnings in the tree
(does not fix the cmos.layout race yet)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-08 16:41:05 +00:00
Stefan Reinauer
817d7542f7 get rid of even more fam10 and k8 warnings.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5659 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-08 00:37:23 +00:00
Stefan Reinauer
5e33e82708 fix some more warnings
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-07 21:59:06 +00:00
Myles Watson
7bcaa920e8 Eliminate a couple of warnings from setup_resourcemap.c
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06 21:40:11 +00:00
Edwin Beasant
eb50c7d922 Re-integrate "USE_OPTION_TABLE" code.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5653 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-07-06 21:05:04 +00:00