1. Apply the DPTF parameters receive from the thermal team.
2. Change PL2 min value from 25W to 15W.
3. Change PL2 max value from 64W to 51W.
BUG=b:166696500
BRANCH=puff
TEST=build and verify by thermal team
Change-Id: I53a4e8809369883c3ba77744fdc05fb510408209
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44903
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch converts the current DPTF policies from static ASL files into
the new SSDT-based DPTF implementation. All settings are intended to be
copied exactly.
BUG=b:158986928
BRANCH=puff
TEST=duffy boots and dumped SSDT table for quick check.
Change-Id: I45987f44ec381917173f8d2a878edb50da454b4b
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The bus master bit is set at many places in coreboot's code, but the
reason for that is not quite clear. We examined not setting the
bus master bit whereever possible and tried booting without it,
which worked fine for internal PCI devices but not for PCIe. As a PCIe
device we used a Samsung M.2 NVMe SSD.
For security reasons, we would like to disable bus mastering where
possible. Depending on the device, bus mastering might get enabled
by the operating system (e.g. for iGPU) and it might be required for
some devices to work properly. However, the idea is to leave it disabled
and configure the IOMMU first before enabling it.
To have some sort of "backwards compatibility", add a method which
configures bus mastering based on an additional config option. Since
CB:42460 makes usage of this treewide, enable it by default to keep the
current behaviour for now.
Tested with Siemens/Chili, a Coffee Lake based platform.
Change-Id: I876c48ea3fb4f9cf7b6a5c2dcaeda07ea36cbed3
Signed-off-by: Felix Singer <felix.singer@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42459
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIO_144 is REPORT_EN pin for the touchscreen controller where 1 means
enable operation and 0 means stop operation. Override tree exposes
this pin as stop GPIO. Thus, it needs to be configured as active low
i.e. 0 = active (stop), 1 = inactive (enable report).
Change-Id: I349123655260349b78d2f75f846da0ce1dc966fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44911
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
v3.6+ of reference schematics have moved to using active low polarity
for touchscreen GPIO. This change sets the default polarity in
override tree accordingly to active low. To support boards from older
builds, variant_touchscreen_update() already updates the polarity to
active high.
BUG=b:161937506
Change-Id: I370bdb27ea5d0601612d13b515113a6048018964
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Clone entirely from Jasperlake
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
4. Clean up upd override in fsp_params.c, will be added later
5. Temporarily remove _weak attributes in fsp_param & romstage.c
6. Add required headers into include/soc/ from jasperlake directory
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If2bbe0b8a12bb78b3650f9d0a60f002f7eacb513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44801
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Clone entirely from Jasperlake
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/36550
List of changes on top off initial jasperlake clone
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Rename structure based on Jasperlake with Elkhartlake
6. Add required headers into include/soc/ from JSL directory
Elkhart Lake specific changes will follow in subsequent patches.
1. soc/intel/elkhartlake: Update Kconfig
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9f91c1efa81a358b1f59e032e209e07b62d54613
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The BT instruction stores its result in CF and not ZF so use the
correct jump instruction.
This fixes a hang in postcar on CPUs lacking support for this
instruction. This concerns older pre-SSE2 hardware.
Change-Id: I704e3c579150fb9b9a292ef0e83050e7bf7cb078
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Checked with the schematics that all PCIe clocks have a corresponding
clock enable pin.
BUG=b:149970243
BRANCH=zork
Change-Id: If96cdf95e213682217e46a98fc69c5c2ef4a148d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44892
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.
BUG=b:149970243
BRANCH=zork
Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The _SHIFT postfix is a bit clearer than the _SHL one and more in line
with the names used for this kind of defines in coreboot. The
documentation on that register is currently wrong and will hopefully be
fixed in the future; the defines should now match the hardware.
BUG=b:149970243
BRANCH=zork
Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The code using the macro was found not working after finally enabling
the HDA PCI device on the hermes board.
Fix a typo to generate the correct verbs.
Tested on prodrive/hermes.
Change-Id: I953c2e9fbebc1f02bdf71ce868a95f578300c3a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44900
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Replacing the existing defines with macros makes them easier to use in a
function that applies the setting for a certain GPP/GFX clock output.
Also add macros for statically enabling or disabling the clock outputs
and not only for configuring them as controlled by the #CLK_REQx pins.
BUG=b:149970243
BRANCH=zork
Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and
this was probably just copied over from stoneyridge.
BUG=b:149970243
BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Linux kernel drivers bind to "DMI quirks." In this case, the audio
fw_config is added as an OEM string, e.g., "AUDIO-MAX98357_ALC5682I_I2S"
so the audio topology can be correctly discovered.
But add all successfully probed fw_config items as well, because this
makes it easier to view what is selected from userspace.
BUG=b:161963281
TEST=With CBI FW_CONFIG field set to 0x201:
localhost ~ # dmidecode -t 11
# dmidecode 3.2
Getting SMBIOS data from sysfs.
SMBIOS 3.0 present.
Handle 0x0009, DMI type 11, 5 bytes
OEM Strings
String 1: DB_USB-USB4_GEN2
String 2: AUDIO-MAX98373_ALC5682I_I2S
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7b7586b0ebfe7b2fd888f448a50ae086364fa718
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44783
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a backing cache for all successfully probed fw_config fields that
originated as `probe` statements in the devicetree. This allows recall
of the `struct fw_config` which was probed.
BUG=b:161963281
TEST=tested with follower patch
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I0d014206a4ee6cc7592e12e704a7708652330eaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPP_F11 was in the early gpio table, but the definition was missing
from the main gpio_table. This change adds GPP_F11 to the gpio_table
array.
BUG=none
TEST="emerge-volteer coreboot" and verify it builds correctly.
Change-Id: I40f887300a9dfd4f8e790031b77bbee8a014f499
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Add Makefile.inc to include six generic DDR4 SPDs for the following
parts for Eldrid:
DRAM Part Name DRAM ID to assign
H5AN8G6NDJR-XNC 0 (0000)
MT40A512M16TB-062E:J 1 (0001)
H5ANAG6NCMR-XNC 2 (0010)
K4A8G165WC-BCWE 0 (0000)
K4AAG165WA-BCWE 3 (0011)
MT40A1G16KD-062E:E 3 (0011)
Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use
by gen_spd, the generic DD4 SPD generation tool.
Add dram_id_generated.txt to specify DRAM ID strap settings.
NOTE that Eldrid specified DRAM IDs for the first three parts to be 0
though 2 (i.e. no combined DRAM IDs for parts that use the same SPD).
BUG=b:161772961
TEST="FW_NAME=eldrid emerge-volteer coreboot" and verify it builds
without error.
Change-Id: Ica62e299ed40e60c2d5928b29ead5d2205b1af66
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This SuperIO chip is used on the Intel DQ45EK mainboard. Restore the
driver that was deleted in commit d3a1a4171e ("src/superio: Remove
unused superio chips"). Changes from the previous version include:
- Replacing the early serial implementation with Winbond common code,
- Replacing the license boilerplate with SPDX headers, and
- Removing unnecessary header file references.
Change-Id: I0ff1a63c47d5dff2599c83a1cebe1ac5ff2136b1
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable TBT2 setting in overridetree.cb based on schematic.
BUG=b:165175296, b:166060548
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I23ecf76a3c2f631211b0ae2898707c68862b374b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44747
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Set tcc offset to 5 degree celsius for kaisa and duffy
BUG=b:166696500
BRANCH=puff
TEST=Build, and verify test result by thermal team.
Change-Id: I2bb977b98c0764f0b9cac3543074da56057717cf
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44901
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MODEM_CLKREQ / CNVI_CLKREQ has no external pull-down resistor.
When there is no M.2 card populated, the pin is floating. Thus
enable an internal 20K PD.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I37e0a9d7e9e0a8c8a7ac198abfd3995b8b0f9e3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Add CNVi and PCIe wifi devices to the devicetree and enable the wifi
driver and SMBIOS tables in Kconfig.
Test: both CNVi and PCIe wifi devices work fine
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I16e04dbbf5fc3a163ce5a2bb8de646877d5cbc0f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43654
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework the comments:
- fix wrong gpio / net names
- convert all comments to <gpio> / <net name>
- add more information where appropriate
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I51b552fd3255d5627dcc012e677bad51be517cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43650
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
INTP_OUT can be used as Type-C VBUS sense input/interrupt but is
currently unused in coreboot. It isn't a requirement for PD to work.
Disable it for now.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I233fbb562969487dff095ba6589fb9da3301ae4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43647
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable internal pull-ups for SATAXPCIE pads since there are external
ones at the M.2 slot's PEDET pins.
Test: both, SATA and NVME devices work fine on both slots
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43645
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are pads being unused for various reasons:
a) missing board support (DeepSx: SUSWARN#)
b) unneeded feature ID pins
- currently no known device models without keyboard backlight
- currently no known device models without TPM
c) BOARD_ID (L140CU/L140ZU) is fixed and known at build time
d) DDR_TYPE_*: there is only one known ram model
e) strap-only pads
f) unconnected pads
Configure them as NC with appropriate pull-up if no external pull exists.
The latter was checked by schematics and looking at the board.
When any of the unused ID pins is needed in the future, they can be
reactivated easily (configure as GPI).
Further, convert from use of legacy macro PAD_CFG_NC to PAD_NC.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43644
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support CSE Lite firmware update, CSE RW partition is extracted from
CSE blob binary and added to FW_MAIN_A and FW_MAIN_B.
CSE RW size for TGL is close to 2.3MB; hence, the size of FW_MAIN_A and
FW_MAIN_B is increased to avoid an overflow.
BUG=b:140448618
TEST=build with me_rw binary blob for volteer and boot to kernel.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: Ie3c2b657f0426d206dfe3729829ec34ff57812c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43790
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
L140CU has a TPM2 connected via SPI. Add the TPM device to the
devicetree and enable it.
According to Intel doc#615170-001, PIRQ is required for SPI TPM to work.
Since the TPM is connected to GPP_A7, enable NF1 (PIRQA#) and set it as
TPM interrupt in Kconfig.
Note: The PCH maps either LPC TPM or SPI TPM to the same address and
handles either LPC or SPI communication transparently. Thus we can use
MAINBOARD_HAS_LPC_TPM here, which implements TPM via that address.
Tested, but only polling works currently, because there is some upstream
issue with the tpm_tis module in current Linux kernels. [1]
[1] https://bugzilla.redhat.com/show_bug.cgi?id=1770021
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43641
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows calling GETSEC[CAPABILITIES] during early init, when the MSR
isn't locked yet.
Change-Id: I2253b5f2c8401c9aed8e32671eef1727363d00cc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This is a security lock and is required for TXT, among other things.
Tested on Asrock B85M Pro4, still boots.
Change-Id: I7b2e8a60ce92cbf523c520be0b365f28413b9624
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44884
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix an issue the assembler didn't warn about to fix a crash on real
hardware. qemu didn't catch this issue either.
The linker uses the same address for variables in BSS if they aren't
initialized in the code. This results in %edx being set to the value
of %eax, which causes an exception restoring IA32_EFER on real
hardware.
Tested on qemu with KVM enabled.
Change-Id: Ie36a88a2a11a6d755f06eff9b119e5b9398c6dec
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We can now factor out the essentially duplicated ME functions.
We include a .c file to preserve reproducibility. This is needed because
there are two different `mei_base_address` global variables, and we have
to access the same variables in order for builds to be reproducible.
The duplicate global in `me.c` and `me_8.x.c` will be completely gone
once this new `me_common.c` file becomes a standalone compilation unit.
We are wrapping some things in static inline functions, as they won't be
directly accessible anymore after moving to a separate compilation unit.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 remains identical.
Change-Id: I057809aa039d70c4b5fa9c24fbd26c8f52aca736
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
This PCI ID is required in order for the CML devices to perform
SSDT generation for DPTF.
CML Processor, EDS, Vol 1,
Table 9-5, Section 9.2.
BUG=b:158986928
BRANCH=puff
TEST=builds
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Change-Id: I94aea6b9e0f60656827daada7b2cc2741604b8b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Andrew McRae <amcrae@google.com>
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa
signature against digest using PSP svc.
This function will be later used by vboot to accelerate rsa
verification.
BUG=b:163710320, b:161205813
TEST=build zork firmware with vboot modification, confirm it's booting
and boot time is reduced by ~230ms.
Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SATA is currently turned on in the Dalboz and Trembyle base board
variant devicetrees, even though no Google/Zork device uses SATA; for
mass storage they either use eMMC or NVME PCIe SSDs. This patch disables
both the SATA PCIe device and the bus where it was the only enabled
device on. The next patch in this patch train sets a new FSP-M UPD
setting
BUG=b:162302027
Change-Id: Ie7773d9dcb0518c3e01bdd0af23b62268ab64694
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44068
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.
BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.
Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on OCP Delta Lake, with FSP WW34 DCI can be connected if enabled.
Change-Id: I8e0dff921cef02dfc66467a2b8fa3e196fb36ac2
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Intel CPX-SP FSP ww34 release added some features:
a. change DDR frequency limit.
b. define MRC debug message verbosity level.
c. enable/disablee of PCH DCI.
In addition, there are some changes to HOB data structures.
Update UPD and HOB header files and adapt soc accordingly.
TESTED=booted on YV3 DVT to target OS command line. Also rebooted okay.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iadbf5dc850c445f988bc7f07a24165abed2298c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44685
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parts have not been used in any woomax devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=woomax
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611555
TEST=none
Change-Id: I651539c2df8e6d817582573d45b9e77156ece7d4
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44872
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These parts have not been used in any berknip devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=berknip
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611704
TEST=none
Change-Id: I9020fc9cbbb4a97664b0c969dd841c5696a4d60f
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44871
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These parts have not been used in any dirinboz devices. Removing
so IDs can be assigned more efficiently.
Command to generate files:
go build gen_part_id.go
local variant=dirinboz
./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/${variant}/spd/ ../../../src/mainboard/google/zork/variants/${variant}/spd/mem_parts_used.txt
BUG=b:165611271
TEST=none
Change-Id: I605550d44ba57d979df1bd5bef114f8ecc94fa3a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44846
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add mem_list_variant.txt, a list of memory parts used by elemi SKUs.
Add dram_id.generated.txt, a list of dram id's to use for each memory part.
Add Makefile.inc, to specify DDR4 and build the SPD file list.
BUG=b:165461530
TEST=none
Change-Id: I6dbcccf577161cc0c787775e2ac03e0c7039baef
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44650
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory parts needed by zork boards. Attributes are derived from data
sheets.
BUG=b:162939176
TEST=Compared generated SPDs with data sheets and checked in SPDs
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I67f205f9af24bbc5c12656be1f363a15fe975955
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44447
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a memory part is a x16 part that has two dies and only a single
rank, then the x16 describes the part width (since this solution will
need to be a stacked solution) and as such, we must translate the
DeviceBusWidth to the "die bus width" instead.
Change DeviceBusWidth variable name to PackageBusWidth to be more
descriptive
BUG=b:166645306, b:160157545
TEST=run gen_spd and verify that spds for parts matching description
above changed appropriately.
Change-Id: Ia6f3ca109d344b7a015da28125a94ce10d2bdfb8
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The TS_DONE_LOADING timestamp description had "(ignore for x86)", but
the implementation in vboot_logic.c will read every bytes, so the
timestamp is correct even for devices with memory mapped boot device
(e.g., x86).
To prevent confusion we should remove the 'ignore for x86' message.
BUG=None
TEST=make -j
BRANCH=None
Change-Id: I01d11dd3dd0e65f3a17adf9a472175752c2b62bc
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44800
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I noticed that re-running the lpddr4x SPD parts id tool that generates
the variants/VARIANT_NAME/memory/Makefile.inc changed the SPD that is
used for the H9HCNNNCPMMLXR-NEE part.
$ go run ./util/spd_tools/lp4x/gen_part_id.go \
src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/delbin/memory
src/mainboard/google/volteer/variants/delbin/memory/mem_list_variant.txt
Based on the currently checked in generic SPDs for LPDDR4x, this
operation changes the Makefile.inc to use lp4x-spd-3.hex for the
H9HCNNNCPMMLXR-NEE part instead of lp4x-spd-2.hex.
This change updates that discrepancy in Delbin's memory Makefile.inc.
BUG=none
TEST=none
Change-Id: I9a19ab7b1bcdc3814fdd9c462ca2f590c8ed2935
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a SPI-NOR flash controller which supports pio mode.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I1e38672a532dd8234b3ef24c84113888c8795810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Change lp4x spd names to include lp4x memory type (eg. lp4x-spd-1.hex).
BUG=b:160157545
TEST=run gen_part_id for volteer variants and verify that it changed
spd names to prepend the "lp4x-" to the filename..
Change-Id: I0c59da7eb78f34640aad2e852ca725d3e8571a8e
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44784
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that generic SPD files have the memory type prepended to the
filename, they can be stored in the same location. This CL moves
the generic SPDs to the new location.
Change the ddr4 gen_part_id.go and gen_spd.go tools to use
"ddr4_spd_manifest.generated" instead of "spd_manifest.generated".
Change the lpddr4x gen_part_id.go and gen_spd.go tools to use
"lp4x_spd_manifest.generated" instead of "spd_manifest.generated".
Move TGL DDR4 and LPDDR4x generic SPDs into a common location.
Move JSL DDR4 and LPDDR4x generic SPDs into a common location.
Change the volteer/spd/Makefile.inc to use the new path for the spds.
Change the dedede/spd/Makefile.inc to use the new path for the spds.
BUG=b:165854055
TEST="emerge-volteer coreboot" and verify all variants build correctly.
Change-Id: I83b088cb718d15ffd3012c84a12b5231ae84a3e4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44648
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that GCC's LTO doesn't like the way we implement
DECLARE_OPTIONAL_REGION(). This patch changes it so that rather than
having a normal DECLARE_REGION() in <symbols.h> and then an extra
DECLARE_OPTIONAL_REGION() in the C file using it, you just say
DECLARE_OPTIONAL_REGION() directly in <symbols.h> (in place and instead
of the usual DECLARE_REGION()). This basically looks the same way in the
resulting object file but somehow LTO seems to like it better.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I6096207b311d70c8e9956cd9406bec45be04a4a2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Enable IPU for Volteer and Volteer2 variants for MIPI camera.
BUG=165340186
BRANCH=None
TEST=IPU is enabled and shows in lspci.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I66d60474e16c7a9aa8006d42b22510c1495dbd84
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44628
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set psyspl2 to 97% of adapter rating, based on our experiment results.
BUG=b:160676773
TEST=Built and check firmware log.
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I4b621a8cc1749ee52a9f16a7ad2ae7a7aa0f7a5a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
DRIVERS_WIFI_GENERIC is a dependency for these SAR settings.
However, coreboot.org builders are not failing, but chromium
builders are only for serial configurations. It's not clear as
to why. Either way correct this.
BUG=b:159304570
Change-Id: I978b622a3a5a2490b0e3aaa14c24807d5afdff9a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44825
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The gpio_common.h needs EINT_BASE from addressmap.h.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I20834e38343410526da0a489fed907acbf479d02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Most of the code is generated using autoport.
Working:
* booting Arch Linux from SeaBIOS
* PCIe/SATA/USB ports (see overridetree and early_init for lists)
* LVDS, DisplayPort, VGA, 3.5 mm jacks, RJ-45
* keyboard, touchpad
* C-States, S3 suspend
Not working:
* rfkill hotkey
* color of the mute hotkey
* sleep f-key
Untested:
* internal speakers and microphone (defective on my machine)
* FireWire
* docking station
* TPM (SeaBIOS detects it, no further test done)
Signed-off-by: Pablo Stebler <pablo@stebler.xyz>
Change-Id: I916583fad375f16e5b02388cbcad2e8a993e042f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Rename the pch_init function to bootblock_pch_init and romstage_pch_init
according to the stage it is defined in.
TEST=successfully built and booted TGLRVP
Signed-off-by: Alexey Buyanov <alexey.buyanov@intel.com>
Change-Id: Ib7450fcdc3024dfb5e375a54f9bdcdca9bc373d8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44051
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Returning a const uint32_t doesn't do anything, and it conflicts with the
declaration of sku_id() in include/boardid.h.
Change-Id: I2719e5782c9977f8ca4ce8f1dd781f092aa73d64
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1428708
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44746
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow HW schematic to correct DDSP_HPD1/2/3 and USB_OC3 pin.
BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f941141d761b1b69bc8f9ef0b0c4516062fec4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Removing entry covering root region leads to situation where
num_entries counter is set to 0. This counter is further decremented
in function obtaining address to last entry (see root_last_entry()).
Such negative number may be further used as an index to the table.
Current implementation may lead to crash, when user removes last entry
with imd_entry_remove() and then calls for example imd_entry_add().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I6ff54cce55bf10c82a5093f47c7f788fd7c12d3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44668
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
One of the checks inside imdr_recover() was written with the
assumption that imdr limit is always aligned to LIMIT_ALIGN. This is
true only for large allocations, thus may fail for small regions.
It's not necessary to check if root_pointer is under the limit, since
this is implicitly verified by imdr_get_root_pointer().
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I25d6291301797d10c6a267b5f6e56ac38b995b7b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Previously it was allowed to create an imd_entry with size 0, however
algorithm sets the offset of such entry to the exact same address as
the last registered entry.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: Ifa2cdc887381fb0d268e2c199e868b038aafff5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Add a check that root_size provided by the caller accounts for one
imd_entry necessary for covering imd_root region. Without this, we
may end up with writing on unallocated memory.
Signed-off-by: Jan Dabros <jsd@semihalf.com>
Change-Id: I0a39d56f7a2a6fa026d259c5b5b78def4f115095
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Get rid of the second check whether r is NULL (this is already done by imdr_has_entry()).
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibee1664ee45b29d36e2eaaa7dff4c7cc1942010b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Remove the repetition from the comment.
Signed-off-by: Anna Karas <aka@semihalf.com>
Change-Id: Ibe6e38636b96b6d8af702b05a822995fd576b2fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44662
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Includes changes related to GPIO pad to configure I2C4 required for UFC
Change-Id: Ica3ac31f10214b8aff3bb64a2c3b42ccfa28bdcd
Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This unlocks 1866 MHz frequency for AMD boards of f15tn family.
Tested on ASUS A88XM-E with A10-6700 and Crucial BLT8G3D1869DT1TX0.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I547d7e9ca89524d66ee0ee307de41699d991f9fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40490
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 81066b7ce7.
Reason for revert: The hang observed when not exposing the reset GPIOs was root caused to zork sharing the same I2C bus between touchscreen and touchpad and interleaving of messages during probe which resulted in incorrect information returned back by touchscreen firmware. Exposing the reset GPIO changed the timing of probe and hence helped workaround the hang issue. The touchscreen driver is now fixed to perform I2C transactions in a single transfer and so the hang is no longer observed when reset GPIO isn't exposed.
BUG=b:162596241
BRANCH=zork
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ica11c33d542dd2324bb0b8905c5de06047cee301
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This will ensure that the cold reset is performed when CSE Lite jumps
from RO to RW.
BUG=b:162977697
TEST=Verify CSE reset is cold (sits in S5 for PCH Min Slp Duration time)
Change-Id: Ib1173e219ba46ee3275824220c8cf790b1d497fa
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Serial Presence Detect (SPD) data for memory modules is used by Memory
Reference Code (MRC) for training the memory. This SPD data is
typically obtained from part vendors but has to be massaged to format
it correctly as per JEDEC and MRC expectations. There have been
numerous times in the past where the SPD data used is not always
correct.
In order to reduce the manual effort of creating SPDs and generating
DRAM IDs, this change adds tools for generating SPD files for DDR4
memory used in memory down configurations on Intel Tiger Lake (TGL)
based platforms. These tools generate SPDs following JESD79-4C and
Jedec "4.1.2.L-5 R29 v103" specification.
Two tools are provided:
* gen_spd.go: Generates de-duplicated SPD files using a global memory
part list provided by the mainboard in JSON format. Additionally,
generates a SPD manifest file (in CSV format) with information about
what memory part from the global list uses which of the generated
SPD files.
* gen_part_id.go: Allocates DRAM strap IDs for different DDR4
memory parts used by the board. Takes as input list of memory parts
used by the board (with one memory part on each line) and the SPD
manifest file generated by gen_spd.go. Generates Makefile.inc for
integrating the generated SPD files in the coreboot build.
BUG=b:160157545
Change-Id: I263f936b332520753a6791c8d892fc148cb6f103
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If there's already been an error and PSP_verstage is booting to RO,
don't reset the system. It may be that the error is fatal, but if the
system is stuck, don't intentionally force it into a reboot loop.
BUG=None
TEST=Force an error, still boots to RO instead of going into a boot loop
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibb6794fefe9d482850ca31b1d3b0d145fcd8bb8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Jasper Lake does not have any use case for multiphase SI init so
Disable it.
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43816
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
We hit a similar issue on Cereme, so I checked the trembyle base board
which also uses AUX4/HDP4 for the last DDI port, so using AUX3/HDP3 is
wrong there.
Change-Id: I99f9426969488cc5c5a14bd432b38bfd69ae7ef0
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Instead of halting if the vboot workbuf is not passed to coreboot by the
PSP, reset and reboot into recovery mode.
This process is made more difficult because if the workbuf isn't
available, we can't reboot directly into recovery - the workbuf is
needed for that process to be done through the regular calls, and we
don't want to go around the vboot API and just write into VBNV directly.
To overcome this, we set a CMOS flag, and reset the system.
PSP_verstage checks for this flag so it will update VBNV and reset the
system after generating the workbuf.
BUG=b:152638343
TEST=Simulate the workbuf not being present and verify the reboot
process.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I049db956a5209904b274747be28ff226ce542316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We need to pull update_mrc_cache into mrc_cache_stash_data, so moving
to end of the file to make sure update_mrc_cache is defined before.
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I9e14fec96e9dabceafc2f6f5663fc6f1023f0395
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create two new functions to fetch mrc_cache data (replacing
mrc_cache_get_current):
- mrc_cache_load_current: fetches the mrc_cache data and drops it into
the given buffer. This is useful for ARM platforms where the mmap
operation is very expensive.
- mrc_cache_mmap_leak: fetch the mrc_cache data and puts it into a
given buffer. This is useful for platforms where the mmap operation
is a no-op (like x86 platforms). As the name mentions, we are not
freeing the memory that we allocated with the mmap, so it is the
caller's responsibility to do so.
Additionally, we are replacing mrc_cache_latest with
mrc_cache_get_latest_slot_info, which does not check the validity of
the data when retrieving the current mrc_cache slot. This allows the
caller some flexibility in deciding where they want the mrc_cache data
stored (either in an mmaped region or at a given address).
BUG=b:150502246
BRANCH=None
TEST=Testing on a nami (x86) device:
reboot from ec console. Make sure memory training happens.
reboot from ec console. Make sure that we don't do training again.
Signed-off-by: Shelley Chen <shchen@google.com>
Change-Id: I259dd4f550719d821bbafa2d445cbae6ea22e988
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44006
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
update telemetry value with the SDLE test result.
BUG=b:158964769
BRANCH=none
TEST=emerge-zork coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ic419ca5ca00e4e8602dbc12212a8a63ed3657e02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Move interrupt status and wake status clearing to after GPIO config so
that configuration does not incorrectly set interrupt or wake status.
i.e. when PULL_UP is configured on a pad, it incorrectly sets in the
interrupt status bit. Thus, the interrupt status bit must be cleared
after initial pad configuration is complete.
BUG=b:164892883, b:165342107
TEST=None
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: If4a5db4bfa6a2ee9827f38e9595f487a4dcfac2c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Each variant WiFi SAR CBFS will be added with the default name
"wifi_sar_defaults.hex".
so we just need to look up the default CBFS file as the WiFi SAR
source.
BUG=b:159304570
BRANCH=zork
TEST=1. cros-workon-zork start coreboot-private-files-zork
2. emerge-zork chromeos-config coreboot-private-files-zork \
coreboot chromeos-bootimage
Change-Id: Idf859c7bdeb1f41b5144663ba1762e560dcfc789
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Jasper Lake SoC had PCI root port mapping swap, thats why we were
using swapped mapping earlier for all the boards
Recently, patch was pushed to handle this swap in PCI enumeration code
for Jasper Lake and we need to correct this mapping. Now this mapping
aligns with actual port mapping in the schematics
BUG=None
BRANCH=None
TEST=NVMe and WLAN are getting detected after this changes
Change-Id: Ide5f8419a15f559cefeb6039f155fabf97c279f8
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
pmc_set_acpi_mode will set EC SMI mask to 1 in the end.
However google_chromeec_events_init will clear EC SMI mask.
If google_chromeec_events_init is ran after pmc_set_acpi_mode, the EC SMI mask
will be 0 in depthcharge and causes lidclose function not working.
So, pmc_set_acpi_mode() should run after google_chromeec_events_init.
This code is mainly from CB:42677
BUG=b:16338215
TEST=Close lid in depthcharge and the dut can be shutdown on waddledoo.
Signed-off-by: Kane Chen <kane.chen@intel.com>
Change-Id: I0f06e8b5da00eb05a34a6ce1de6d713005211c08
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Configure gpio settings for FPMCU on Halvor.
BUG=b:153680359
TEST=After flash FP MCU FW, during bootup we see spi id spi-PRP0001:01 in dmesg.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I5503cfe0fb9933e98ed01afeef8cad1345593ac6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44575
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Halvor uses TBT 0/1/2 for USB type C. We doesn't use PCIE/USB3 port
therefore disable PCIE/USB3 ports and enable TBT 2.
Follow volteer to set USB2 OC_SKIP.
BUG=b:165175296
BRANCH=none
TEST=Check all USB ports USB2 and USB3 both functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifb844ce475f3d58f0c95be0f172fc49edb4cd5fe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Create areas for console & timestamp data in psp_verstage and pass it to
the x86 to save for use later.
BUG=b:159220781
TEST=Build & Boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
- FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.
- Enable Vtd IPU and IGD settings only if respective IPs are enabled.
BUG=165340186
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.
Change-Id: Ieff57fb0ebc8522546d6b34da6ca2f2f845bf61d
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44627
Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com>
Reviewed-by: John Zhao <john.zhao@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_D16 is routed to the main power enable pin on several PCIe SD card
controllers on SD daughterboards. We should enable the power to these
chips as early as possible so they can participate in PCIe
enumeration.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
JSL FSP support FSP 2.2. FSP 2.2 introduces Multiphase SI init
support through the FSP-S arch UPD. The FSP-S arch UPD structure
is added in edk2 stable 2020 branch. Switching the support for
JSL to edk2-stable202005 to intercept the FSP2.2 related support.
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: Ieed1b58e491d5a89043c418f0f44f2ee9af111f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44576
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move a size of DDR3 SPD memory (always 256 bytes) to a common define.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I80c89ff6e44526e1d75b0e933b21801ed17c98c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Introduce FSPT_ARCH_UPD and FSPS_ARCH_UPD to support debug events
and multi-phase silicon initialization.
For backward compatibility the original structures are kept and
new ARCH_UPD structures will be included only when UPD header
revision equal or greater than 2.
ref:
- https://bugzilla.tianocore.org/show_bug.cgi?id=2781
BUG=b:162184827
BRANCH=None
TEST=Build and boot JSLRVP
Cq-Depend: chrome-internal:3221772
Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com>
Change-Id: I728aff1df3d361e21e4617647c4ec0e2d345a8c2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Add charger input current throttling for drawcia system
BUG=None
BRANCH=None
TEST=Built and tested on drawcia system
Change-Id: I34fdc23fcd84b5c27c2bada769f7a9049c2a56a5
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2.
BUG=b:154654737
TEST=dmidecode -t 17 matches expected speed
Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add downgrade support for CSE RW firmware.
When CSE FW is downgraded, CSE may get into data compatibility issues.
To avoid such issues, coreboot sends DATA CLEAR HECI command to CSE to
clear CSE run time data on proactive basis during a downgrade and
when CSE indicates a data mismatch error through GET_BOOT_PARTITION_INFO.
BUG=b:144894771
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I0a3a3036e448e5a743398f6b27e8e62965dbff3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40561
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix compilation under x86_64.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: I2a3ac3e44a77792eabb6843673fc6d2e14fda846
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The code can only be compiled as x86_32. Mark it as such to fix errors
in the x86_64 assembler. The caller has to make sure to call this code
in protected mode only.
Tested on HP Z220:
* Still boots on x86_32.
Change-Id: I4c0221fb3886b586c22fe05e36109fcdc20b7eed
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44674
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enter long mode on secondary APs.
Tested on Lenovo T410 with additional x86_64 patches.
Tested on HP Z220 with additional x86_64 patches.
Still boots on x86_32.
Change-Id: I916dd8482d56c7509af9ad0d3b9c28bdc48fd0b1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The zork devices use the ACP (audio co-processor) and the I2S interface
for audio and not the HDA (HD audio) device and interface.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=Equivalent change on Mandolin disabled the non-GPU HDA device with
the corresponding FSP change applied.
Change-Id: I6c7de881cff8398fe416151fab219142d4fc904a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
FSP has recently added support for a UPD switch to disable the non-GPU
HD Audio controller. This change adds the coreboot side of the feature.
To avoid having two HD Audio enable options, the value of the
hd_audio_enable UPD is determined by the enable state of the non-GPU HD
Audio controller in the platform devicetree.
BUG=b:158535201,b:162302028
BRANCH=zork
TEST=With the corresponding FSP change applied the non-GPU HD Audio
device is hidden when switched off in devicetree and remains present and
functional when switched on in devicetree.
Change-Id: Ib2965e0742f4148e42a44ddad8ee05f0c4c7237e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44680
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 65605276a4.
This patch shouldn't have been merged yet, since the issues on the FSP
side aren't sorted out yet, so the FSP-side changes haven't landed yet.
This byte will be used for an audio-related setting instead to have the
audio settings grouped together.
BRANCH=zork
Change-Id: If79900f3a92fd949d7653001e1ca2faac7061e3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44678
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Puff uses CSE Lite SKU that supports in-field CSME
updates an additional reset is triggered when jmp from RO
to RW during boot. However this reset is not detected by
the cr50 running older firmware because the strapping
configuration for EFS2 uses PLT_RST_L to assert to cr50
that a AP reset occured. The older cr50 firmware
version of 0.0.22 only monitors AP resets via SYS_RESET_L
and hence never detects the reset.
To mitigate the issue above a modified reset sequence is
required to be performed to signal the reset occured and
hence a board-specific cse_board_reset() strong symbol is
provided to modify the flow accordingly.
V.2: Select CHROMEOS_CSE_BOARD_RESET_OVERRIDE common
implementation instead of a local variant in mainboard.c
BUG=b:162290856
BRANCH=puff
TEST=none
Change-Id: I27ab9711aedf92b5af7a58f3b5472ce79f78c8fa
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44454
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will ensure that the cold reset is performed when CSE Lite jumps
from RO to RW.
BUG=b:162386991
TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is
triggered when cr50 is running firmware versions newer than 0.0.22. On
cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I46a390c71e380328cd7fe70214df09553b2db75c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When CSE Lite jumps from RO to RW, certain boards need to request
Embedded Controller (EC) to trigger cold reset of SoC. This change
introduces a helper to override the default global reset.
BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that global reset is
triggered when cr50 is running firmware versions newer than 0.0.22. On
cr50 versions 0.0.22 or older, EC triggers cold reset of AP.
Change-Id: I8078e2436d1d58a650bf7b0cf38b5bb89a474187
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Introduce a helper to get the cached cr50 firmware version. This
information is in turn used to identify the strap configuration
supported by Cr50.
BUG=None
TEST=Ensure that Drawcia board boots to OS. Ensure that the version
cached cr50 firmware version is returned.
Change-Id: Id84b152993f253878a6c133cc433a0da2c990cf2
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44653
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make GPIO_4 and GPIO_5 PAD_NC in ezkinil/gpio.c. None of the Ezkinil SKUs
use internal stylus and hence pen pads are configured as NC.
BUG=b:164892883, b:165342107
TEST=Verified taht pen detect GPIO does not cause spurious wakes.
BRANCH=None
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I7557575cf8b8e0f849e05bda1d69acf61e91a157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44629
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to the IT8728F datasheet it is possible to add an extra delay
between 3VSBSW# being set and PWRGD3 being set during resume from
Suspend-to-RAM. This is enabled in the special function selection
register, the default being 0.
This is also useful for the IT8720F although this chip does not have the
PWRGD3 output. On the corresponding pin it has PWROK2, which the setting
then seems to apply to.
The datasheet for the IT8720F marks the corresponding bit as reserved,
but the vendor BIOS of an Acer Aspire M3800 sets it anyway. Without
setting the bit, coreboot fails to resume from S3. Oscilloscope
measurements have shown that setting the bit increases the delay between
3VSBSW# being set and PWROK2 being set from around 1 us to 140 ms. The
actual use of PWROK2 on the board design is unclear - the only
destination it seems to reach is a pin header near the SuperIO marked as
"GPIO1".
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: I51cbf2470dc2b840a647a20090acb5a0cf4f4025
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44639
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The assumption was that the fmap cache would be initialized in
bootblock, otherwise an error is shown. This error is showing
up in psp_verstage when the fmap cache is initialized there, so
create a new ENV value for ENV_INITIAL_STAGE.
BUG=None
TEST=Boot, see that error message is gone from psp_verstage
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I142f2092ade7b4327780d423d121728bfbdab247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43488
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When booting from the RO region of a VBOOT enabled ROM, there shouldn't
be a reliance on anything outside of the RO section. This includes the
APOB_NV region (similar to the MRC cache region). By skipping the
region when setting up the BIOS Directory table, the PSP won't try to
use the region when booting.
The APOB_NV region is still used for the VBOOT RW sections.
BUG=b:158363448
TEST=Build RO with no APOB_NV region. Dump the BDT and verify that
it's not in RO, but is in RW_A & RW_B. Boot into recovery.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I13c35ba8a2331492744d2acf257db15e4a53102a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44046
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Utilize the SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF option to provide
full range backlight settings to the kernel.
BUG=b:163583825
Change-Id: I3c337fad38e668488800f4d6bc583a82a93659d3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Linux kenerl driver for AMD gpu currently has a floor
value of 12 for brightness settings (AMDGPU_DM_DEFAULT_MIN_BACKLIGHT).
AMD indicates they did this because they were concerned with certain
panels flickering at lower backlight values. However, for unaffected
panels it's desirable to be able to have the panel "turn off" at
the lowest backlight setting. The only way to do that is to provide
ATIF bindings that indicate backlight range.
Option SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF is added to provide a full
range for the backlight setting. If needed, this path can be built upon
for fuller support, but for the time being this is the only thing
necessary to make the backlight be full range.
BUG=b:163583825
Change-Id: If76801a8daf6a5e56ba7d118956f3ebce74e567a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The GDT loading did work fine on x86_64 a few months ago, but today it
only works in QEMU, but not on real hardware or KVM-enabled QEMU. This
might be related to toolchain changes.
Use 64bit GDT loading on x86_64 and force the assembler to generate a
64bit address load on the GDT. This will make sure no 32bit (signed)
displacement op is being generated, which points to the wrong address
in longmode.
Verified using readelf and made sure no R_X86_64_32S relocation symbol
is emitted. Disassembled the romstage ELF and made sure the GDT address
is 64bit in size.
Tested on QEMU and KVM-enabled QEMU: Doesn't crash any more on KVM.
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Change-Id: Ia824f90d9611e6e8db09bd62a05e6f990581f09a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Convert raw GPIOs to coreboot macros using newly-added support
for Cannon/Whiskey/Coffee/Cometlake SoCs to intelp2m
Test: build/boot Librem Mini, no smoke released.
Change-Id: I6ac747ad4e650c24d2b7e34228ff74140c51a0c1
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
IPU is required to be enabled for platform supporting MIPI camera.
IPU is by default disabled in devicetree for all variants. Enable
IPU for Waddledoo and Waddledee supporting MIPI camera.
BUG=None
BRANCH=None
TEST=IPU is enabled for platforms and enumerates in lspci.
Change-Id: Ia3cf06d78be4301c68bfa8b1118ddff231d24a66
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44271
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mitigate issues presented in "Digging Into The Core of Boot" found by
"Yuriy Bulygin" and "Oleksandr Bazhaniuk" at RECON-MTL-2017.
Validate user-provided pointers using the newly-added functions.
This protects SMM from ring0 attacks.
Change-Id: I8a347ccdd20816924bf1bceb3b24bf7b22309312
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, to
have Cr50 generate longer than default interrupt pulses.
This needs to be selected on all Tiger Lake systems, since Tiger Lake
(and likely future Intel SoCs) require at least 100us interrupt pulses.
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
BUG=b:154333137
Change-Id: I20100d72ce426203943c1788d538bb2cd9d82e11
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Compiler's instrumentation cannot insert asan memory checks in
case of memory functions like memset, memcpy and memmove as they
are written in assembly.
So, we need to manually check the memory state before performing
each of these operations to ensure that ASan is triggered in case
of bad access.
Change-Id: I2030437636c77aea7cccda8efe050df4b77c15c7
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage as it has been tested.
Change-Id: I3b5263f5342a78968d9a1ecf72996fff0946b204
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44282
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage for apollolake as it has been tested on
Siemens MC-APL3.
Change-Id: I2f2f965151a4ef4672f2f16979a6ad8492879aeb
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in romstage for haswell as it has been tested on
Lenovo ThinkPad T440P.
Change-Id: I6eae242c71f41c9159658ae68d61b4036ad42d42
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Enable ASan in ramstage if ASAN is selected in menuconfig for an
x86 platform.
Change-Id: Id5b3dc18368a5da6bdc70c84527b95d1688dc19f
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44259
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of enabling ASAN_IN_ROMSTAGE from Kconfig file in a
platform's dedicated directory, let's introduce a new config
option HAVE_ASAN_IN_ROMSTAGE to denote if a given platform
supports ASan in romstage.
Similary, use HAVE_ASAN_IN_RAMSTAGE to indicate
if a given platform supports ASan in ramstage. Consequently, we
no longer have to make ASan x86 specific.
Change-Id: I36b144305465052718f245cacf61d3ca44dfb4b4
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44258
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds ASan support to romstage on x86 architecture.
A Kconfig option is added to enable ASan in romstage. Compiler
flags are updated. A memory space representing the shadow region
is reserved in linker section. And a function call to asan_init()
is added to initialize shadow region when romstage loads.
Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch adds address sanitizer module to the library and reserves
a linker section representing the shadow region for ramstage. Also,
it adds an instruction to initialize shadow region on x86
architecture when ramstage is loaded.
Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
An additional compiler flag is added to make use of the shadow
offset callback feature we introduced in our GCC patch. Also,
a comment is added to tell user that this GCC patch needs to be
applied in order to use ASan.
Change-Id: Ia187e4991bf808f4ae137eff0ffdb9baea0085e9
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add a Kconfig option to enable address sanitizer on x86 architecture.
Create ASan dummy functions. And add relevant gcc flags to compile
ramstage with ASan.
Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891
Signed-off-by: Harshit Sharma <harshitsharmajs@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
On MT8192 the SPI flash is actually using a SPI-NOR controller with
its own bus. The number here should be a virtual value as
(SPI_BUS_NUMBER + 1).
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ibc269201a34968c8400d2235e8da2ecd88114975
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With CSE-lite enabled, we were going through the lengthy memory
training procedure twice on the first power-on boot or after full BIOS
SPI flash update. This moves the global reset performed to achieve the
CSE-lite RO to RW reboot to a later boot phase so that it happens
after the memory training data has been written to the MRC cache. Now,
the 2nd (and subsequent) reboot can utilize the memory training data
established during the 1st boot.
This reduces the first boot time by about 20s on a 16GB system.
Looking at the timing stats form cbmem, the normal boot penalty is
about 300ms - mostly attributed to running FspSiliconInit a 2nd
time. We will get this time back when the mrc_cache refactoring effort
lands (cb:44196, et. al).
BUG=b:162021048
TEST=Booted on volteer, confirmed 20s faster boot time.
Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add code for IVRS generation to coreboot. Publish coreboot generated
structure rather than IVRS generated by FSP binary.
Reference Doc: 48882_IOMMU_3.05_PUB.pdf
BUG=b:155307433
TEST=Boot trembyle to shell and extract and compare IVRS tables and make
sure they cover the same devices.
Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For Volteer (and future Tiger Lake boards) we can enable mode S0i3.4
only if we know that the Cr50 is generating 100us interrupt pulses.
We have to do so, because the SoC is not guaranteed to detect pulses
shorter than 100us in S0i3.4 substate.
A new Kconfig setting CR50_USE_LONG_INTERRUPT_PULSES controls new code
running in verstage, which will program a new Cr50 register, provided that
Cr50 firmware is new enough to support the register.
BUG=b:154333137
TEST=util/abuild/abuild -t GOOGLE_VOLTEER -c max -x
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Change-Id: If83188fd09fe69c2cda4ce1a8bf5b2efe1ca86da
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Kconfig 5.8 interprets $(...) itself using environment variables, which
generally means that they expand to the empty string. \$(...) works
with both our current and new Kconfig with the desired behavior
(to pass it through unmodified).
Change-Id: I726567eeb61d2035560152677d2b4548c1472be9
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44584
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows the Super I/O to know how hot the CPU is.
Change-Id: I9c91136c3bb5aae541bb7ac64bb62be36c3c0b5d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Not selecting `ME_MBP_CLEAR_LATE` results in a build failure. Since both
traditional and ULT platforms are known to be working, drop the option.
Change-Id: I09ce27f812966800e36f6c0624c93759089faf45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Together with the "AMD_XMP" changes, now this board with Crucial
BLT8G3D1869DT1TX0 sticks could run at 1600 MT/s CL8 (8-8-9-23) speeds.
Earlier only 1333 MT/s CL9 (9-9-10-27) has been possible with coreboot.
1866 MT/s CL9 is impossible on f16kb without northbridge overclocking.
tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of
Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7e9f5120421221043f9f9dfe143b51bfa61936be
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44462
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD f16kb boards are perfectly capable of working at 1600MT/s RAM speeds
even with two DDR3 UDIMM modules per channel. AM1I-A only supports a
single-channel operation, with at most two DIMMs per channel, so raising
these limit values is required to let it and similar boards run faster.
Successfully tested on AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs,
together with related AMD_XMP changes - also required to get a 1600MT/s
with this set of modules which have only 1333MT/s at JEDEC part of SPD.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44461
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will remove the warning:
"src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate"
Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Remove references to clk_pm_support which is currently ignored
by Picasso AGESA FSP.
BUG=b:161218965,b:162423378
TEST=Build test Trembyle and Dali, boot to ChromeOS 5 times each
Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44556
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Justin Frodsham <justin.frodsham@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update fsp_dxio_descriptor comments to be more comprehensive
of the currently available data fields. Most of these are not
currently utilized with Zork but may be in future projects.
BUG=b:161218965
TEST=Build test Trembyle
Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44554
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since Volteer also uses the CSE Lite SKU and the cr50, it is subject
to a problem where old cr50 FW will not be able to properly detect an
SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW
jump should instead get an assist from the EC, which can perform a
full cold reset.
BUG=b:162977697
TEST=Verify EC performs the cold reset
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
* Enable optional x86_64 romstage, postcar and ramstage
* Add Kconfig for x86_64 compilation
* Add documentation for x86 qemu mainboards
* Increase CAR stack as x86_64 uses more than 0x4000 bytes
Working:
* Boots to Linux
* Boots to SeaBIOS
* Drops to protected mode at end of ramstage
* Enumerates PCI devices
* Relocateable ramstage
* SMM
Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When compiled in RAMSTAGE use the segments for ramstage.
Allows to call this assembly code in ramstage to exit long mode.
The next commit makes use of this.
Tested on qemu:
Still boots on x86_64.
Change-Id: I8beb31866bd15afc206b480b1ba05df995adc402
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
* On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode.
* Add a helper function to jump to arbitrary code in protected mode,
similar to the real mode call handler.
* Doesn't affect existing x86_32 code.
* Add a macro to cast pointer to uint32_t that dies if it would overflow
on conversion
Tested on QEMU Q35 using SeaBIOS as payload.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The AM335X is a SoC, so should be in the soc tree.
This moves all the existing am335x code to soc/ and updates any
references. It also adds a soc.c file as required for the ramstage.
Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Implements fit_payload_arch for the arm (aarch32) architecture, so that
FIT images can be used. The implementation is very similar to the
existing implementations for arm64 and riscv, and has mostly been
lifted from these other ports.
TEST: Booted Beaglebone Black (in progress port, to be submitted soon!)
with a FIT image containing a 5.4 kernel, dtb and initramfs.
Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233
Signed-off-by: Sam Lewis <sam.vr.lewis@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Capture the GPIO subsystem wake state and add events to
the eventlog.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to log gpio events for wake purposes the state
of the gpio subsystem should be snapshotted. Add the ability
to capture state of gpio subystem as well as saving up to 16
gpios that indicate their wake status.
Likewise, provide the eventlog additions based on state.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44534
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch from locating the AMD firmware in the RW_A &
RW_B regions with their hardcoded locations to using CBFS to find
them. They still need to be at the hardcoded locations so that we
can set the location inside the binary, but instead of just setting
the pointer directly to them, we now search for them with cbfs.
BUG=b:154441227
TEST=Boot & verify that binaries are located in both RW-A & RW-B
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42831
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This #define wasn't removed when the tests were removed, so get rid
of it now.
BUG=None
TEST=Build
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ie0005b6ee97037bf3dfb80f0c2408d8bd9ee9633
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There are only headers for the SoC's UART 0 and 1 on the board.
BUG=b:165020060
TEST=Linux only detects UART 0 and 1.
Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order for Linux to find and use the SoC's integrated UARTs, they need
to be exposed in ACPI.
BUG=b:165020060
TEST=Linux detects the SoC's integrated UARTs.
Change-Id: Iaa66657b88f62b2067c865c3e1945b7bdbf9be23
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Using the SOC's UART 0 as console requires moving a few resistors on the
Mandolin board.
BUG=b:165020060
TEST=coreboot console works on SoC UART 0 when AMD_LPC_DEBUG_CARD isn't
selected.
Change-Id: Idaf73ae84f54028da2182ce42035f9ecd63f4776
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
In CB:44488 the cbmem addition was re-filling the object
when it should be memcpy()ing from static object. Correct
that oversight. The side effect from the previous implementation
would be if FSP-M modified the GPE state.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I158a89ae28431896fa9b5789292000fcbf0b066d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44533
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPP_A19(DP_HPD1) and GPP_A20(DP_HPD2) were configured native function
(NF1) without internal pull-down which wrongly presents HPD interrupts.
DP_HPD had been removed for EVT design as those events are through eSPI.
This change configures GPP_A19 and GPP_A20 to be no connection and
disables DdiPort1Hpd and DdiPort2Hpd.
BUG=b:162566436
TEST=Booted to kernel and verified no kernel HPD pins assertion message
on Volteer EVT board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ia3245741b776b75073d2b43d36c8ea40b476b3ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44501
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The wake source macro for GPE events was using 'GPIO'. However,
current usage is really all GPEs. Therefore, provide clarity
in the naming in order to allow for proper GPIO wake events
that are separate from the ACPI GPE block.
BUG=b:159947207
Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44527
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure TRACKPAD_INT_ODL pad reset config to DEEP and
map PMC_GPE_DW to PMC_GPP values.
TEST=System should wake from S3 via trackpad
Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43949
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
PMC_GPE_DW mapping was not configured correctly and hence
coreboot skipped programming Tier 1 GPIOs resulting in failure of
S3 wake from Trackpad.
TEST=System should wake from S3 via trackpad
Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Similar to commit b45ed65, the HOB structure is actually a 8 byte
address pointing to the HOB data.
Tested=Verified the values of the hob fields are the same printed by
soc_display_memmap_hob().
Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable long mode in SMM handler.
x86_32 isn't affected by this change.
* Enter long mode
* Add 64bit entry to GDT
* Use x86_64 SysV ABI calling conventions for C code entry
* Change smm_module_params' cpu to size_t as 'push' is native integer
* Drop to protected mode after c handler
NOTE: This commit does NOT introduce a new security model. It uses the
same page tables as the remaining firmware does.
This can be a security risk if someone is able to manipulate the
page tables stored in ROM at runtime. USE FOR TESTING ONLY!
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I26300492e4be62ddd5d80525022c758a019d63a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Eugene Myers <cedarhouse1@comcast.net>
Add new librem_whl baseboard and Librem Mini variant.
Tested with SeaBIOS, Tianocore, and Heads payloads.
All functions working normally except SATA, which is limited
via a FSP UPD to 3Gbps until the correct HSIO PHY settings
can be determined.
https://puri.sm/products/librem-mini/
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
FSP enables IPU (Imaging Processing Unit) by default even if its
disabled in devicetree. We need to fill FSP upd based on the device
enablement in devicetree.
BUG=None
BRANCH=None
TEST=IPU is disabled and doesn't show in lspci.
Change-Id: I0f9a40e85427fd88bb12a40770ecf7b939b1d8cd
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Enable the introduced LPSS ACPI uart driver.
Tested on Hermes using Linux 5.6:
The UART2 appears as /dev/ttyS2.
Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Emit ACPI code for LPSS UARTs operating in ACPI mode. In this mode the
device vendor ID reads as 0xffff, the PCI devices is still operate.
Add ACPI device IDs for APL, GLK, SPT, SPT_H and CNP_H.
The mainboard's devicetree needs to be adapted to include the chip
driver and the PCI ID when it wouldn't have been hidden.
Example:
chip soc/intel/common/block/uart
device pci 19.2 hidden
register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2"
end # UART #2
end
Tested on Linux 5.6 with Sunrise Point ACPI ID for UART2.
Tested on Windows for all other UARTs.
Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40405
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPE events were not be recorded in the eventlog. Add those
to the eventlog when the status register indicates those events.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously the chipset state was snapshotted very late in the boot
(ramstage). Instead start gathering the state early in romstage
prior to calling any FSP routines so there's a clean snapshot.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44488
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that no one is consuming this object, remove its definition.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Now that all users of the functions manipulating global state
and using soc-specific objects are removed remove those functions.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status(). However,
in subsequent patches picasso will be snapshotting state way sooner than
ramstage.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Transition the current call sequence to using the newly added common
ACPI helper functions. Semantically, the expectations are that this
sequence is the equivalent of previous acpi_clear_pm1_status().
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In order to reduce code duplication provide an acpi_fill_gnvs()
helper function. Intent is to move stoneyridge and picasso over
to using this common implementation instead of duplicating it.
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The existing code in common/block/acpi is mixing multiple operations:
saving things to cbmem in common code but then soc code uses that
information, reliant upon soc-specific struct soc_power_reg object,
and only saving/snapshotting ACPI registers very deep in ramstage.
To unwind the above provide some functions that are more targeted:
- Add struct acpi_pm_gpe_state object
- Add acpi_fill_pm_gpe_state()
- Add acpi_pm_gpe_add_events_print_events()
- Add acpi_clear_pm_gpe_status()
BUG=b:159947207
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This fix is required to avoid the division-by-zero error described at
https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html
while trying to run the DDR3 memory at 1866 MT/s (933 MHz).
With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MT/s.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40485
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Required for adding the XMP profiles support. SPD buffer is
already 256 bytes at AMD AGESA vendorcode, so this is fine.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40484
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Naming a device allows an ACPI _ROM method to be written for it. GPUs
may require this to make the configuration data contained within
available to an OS driver. This may be required for GPUs that do not
contain their vBIOS, or perhaps the drivers require it in this form/fashion.
Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully
obtains the vBIOS via ACPI (kernel 5.7.11).
Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
With new board designs being introduced it does not make sense for the default
devicetree setting to be retimer disabled on port 0 for Aux Orientation.
Change the default to be Aux Orintation retimer controlled on all ports and
move the SOC controlled overrides to the corresponding overridetree files.
BUG=NONE
BRANCH=NONE
TEST=Built image for delbin and verified that port 0 flip is working.
Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44358
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
This change sets the EFS config for SPI read mode to normal read mode
when using em100. With this, the boot is stable again without any
random hangs in PSP.
BUG=b:164429022
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt Papageorge <matthewpapa07@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
And also remove the deprecated by cl#43989
https://review.coreboot.org/c/coreboot/+/43989
BUG=None
TEST=Build the magolor board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I3348b7fbeff038b85e7d3c9137517e05a35bf3dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44408
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The board also supports Atom processors, which have four physical cores.
Signed-off-by: Reto Buerki <reet@codelabs.ch>
Change-Id: I98a3da660052eb7ad2f18b0c7fc0e67a609eac54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
current setting got 0.278us which is less than the min 0.3us.
increase i2c2 data hold time for TP.
BUG=b:163613330
BRANCH=master
TEST=1. emerge-zork coreboot chromeos-bootimage
2. data hold time measured by scope: 0.3805us
Change-Id: I2d564983383c17ed43cc5cc5aaff0fcd67ce6928
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This applies to the goodix touch screen on both the volteer and
volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen
"Report_Switch" signal. Goodix defines a 1ms (minimum) delay after
stop off. In addition, no longer drive this GPIO high by default as it
is now controlled by the kernel through ACPI.
BUG=b:153705232
TEST=touch screen still functional on volteer; confirmed timings with
scope (VDD, RESET, REPORT_SWITCH)
Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
More space is required in the COREBOOT CBFS to accommodate some features.
Currently no alternate firmware is stuffed into RW_LEGACY CBFS and has
~1 MB of unused space. Borrow some space from RW_LEGACY CBFS and extend
the RO_SECTION. Even within RO_SECTION, GBB requires only 12 KiB. So
adjust the GBB region accordingly and extend the COREBOOT CBFS.
BUG=b:162159386
TEST=Build the JSLRVP mainboard.
Change-Id: Ia8bb381c31ddf76f3211f9d4ac5c8c18c27834b7
Signed-off-by: Karthikeyan Ramasubramanain <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Value stored to 'size' is never read.
Also drop unused parameter.
Change-Id: If3e96ac90f06966ee408964e0748730bc237ec19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All the Sandy/Ivy Bridge EliteBook and ProBook laptops currently
supported by coreboot and on review all support TPM 1.2 according the
maintenance and service guide manuals of these laptops. So select the
Kconfig options of TPM and TPM 1.2 and add the entry of it to the
common device tree.
The device tree C source files of 8460p generated by sconfig before
and after this change are compared. All the device nodes still exist
with nodes under LPC having different device number.
Tested with 2560p, which still works without problems, and the TPM can
be detected and used in the system.
Change-Id: Ic6158d3346a55e3d09c0a4ced9fd141b9a6c4256
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Most of the code is generated by autoport. The laptop works well under
coreboot with SeaBIOS 1.13.0 payload, running Arch Linux with kernel
5.4.39 and 5.6.11.
Change-Id: I126916e201fb8e4b9067f2dececebfb5bae6df73
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41159
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The Allwinner code has been removed from the master branch for quite
some time now.
Change-Id: I9e5fd267140c180ae145d12b325cc489725f9ad0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This can be used in romstage in particular to know if dram is ready.
Change-Id: I0231ab9c0b78a69faa762e0a97378bf0b50eebaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38736
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
INVD is called below so if postcar is running in a cached environment
it needs to happen.
NOTE: postcar cannot execute in a cached environment if clflush is not
supported!
Change-Id: I37681ee1f1d2ae5f9dd824b5baf7b23b2883b1dc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Coverity detects that value assigned to variable "ret" is overwritten
before it is used. Fix the issue by returning right value.
Found-by: Coverity CID 1255942, 1241836
TEST=None
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44185
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CPU variant has a different CPUID signature.
Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This patch updates the SLP_Sx assertion widths and power cycle duration
for the Japerlake RVP.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on JSLRVP.
Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch updates the SLP_Sx assertion width and power cycle duration
for the dedede platforms.
Power cycle duration:
With default value,
S0->S5 -> [ ~4.2 seconds delay ] -> S5->S0
With value set to 1,
S0->S5 -> [ ~1.2 seconds delay ] -> S5->S0
BUG=b:159104150
TEST=Verified that the power cycle duration is ~1.2s with global
reset on waddledoo.
Change-Id: I7079cbd564288b5d5b69e07661434439365063d3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43792
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Initialize watch dog so the system won't reboot on timeout.
In addition, print the reason of reboot triggered by watch dog.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Initialize CPU mmu and config range.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Those flags already get unconditionally set in soc/amd/picasso/acpi.c.
Change-Id: I978c7d67480499d92c193d5bb87bc876211187db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Two of the items in the FADT ACPI table frequently are partially board-
specific, so let's make it easy to update them via devicetree settings.
- fadt_boot_arch 0="legacy free" which while reasonable, probably isn't
what will be wanted by most mainboards, so this should generally get
updated in the specific devicetree.
- In fadt_flags all chipset-specific flags get set while the mainboard
has to set all other flags that it needs to have set.
This patch changes the default for fadt_boot_arch.
Change-Id: I6e8d0c60cadfdd24b6926703b252abbc56d436de
Signed-off-by: Martin Roth <martinroth@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The DISPLAY_3D class is for graphics devices that are not connected to
displays. This includes GPUs implementing muxless Nvidia Optimus.
According to CB:31502, some AMD GPUs are identified as DISPLAY_OTHER.
Therefore, consider the entire DISPLAY class as GPUs.
Change-Id: I0f203a013c010337ae7a9fddbd13330f380050a4
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Xeon-SP Skylake Scalable Processor can have 36 CPU threads (18 cores).
Current coreboot SMM is unable to handle more than ~32 CPU threads.
This patch introduces a version 2 of the SMM module loader which
addresses this problem. Having two versions of the SMM module loader
prevents any issues to current projects. Future Xeon-SP products will
be using this version of the SMM loader. Subsequent patches will
enable board specific functionality for Xeon-SP.
The reason for moving to version 2 is the state save area begins to
encroach upon the SMI handling code when more than 32 CPU threads are
in the system. This can cause system hangs, reboots, etc. The second
change is related to staggered entry points with simple near jumps. In
the current loader, near jumps will not work because the CPU is jumping
within the same code segment. In version 2, "far" address jumps are
necessary therefore protected mode must be enabled first. The SMM
layout and how the CPUs are staggered are documented in the code.
By making the modifications above, this allows the smm module loader to
expand easily as more CPU threads are added.
TEST=build for Tiogapass platform under OCP mainboard. Enable the
following in Kconfig.
select CPU_INTEL_COMMON_SMM
select SOC_INTEL_COMMON_BLOCK_SMM
select SMM_TSEG
select HAVE_SMI_HANDLER
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
Debug console will show all 36 cores relocated. Further tested by
generating SMI's to port 0xb2 using XDP/ITP HW debugger and ensured all
cores entering and exiting SMM properly. In addition, booted to Linux
5.4 kernel and observed no issues during mp init.
Change-Id: I00a23a5f2a46110536c344254868390dbb71854c
Signed-off-by: Rocky Phagura <rphagura@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43684
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Simplify some if-blocks which are used for the configuration, enablement
and disablement of the PEG devices.
This changes the logic of the code, since it configures PegxEnable
before the if-blocks, where x is the number of the PEG device, and the
further configuration of the PEG devices depends on the enablement of
PegxEnable.
Change-Id: I6dd88ce752ce8f0255c424d0e5b2d8ef918885a1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner
Move InternalGfx config option out of the if-else-block and replace the
left over config option IgdDvmt50PreAlloc by a ternary expression. Also,
adjust related code comments to fit the new logic of this code.
This changes the logic of the code, since InternalGfx is configured
first and IgdDvmt50PreAlloc depends on its value. The negation in the
ternary expression is removed to improve the readability.
Change-Id: I89ff17f4574a7ade228c1791f17ea072fb731775
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44369
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
* Add support for loading GDT on x86_64.
* Add x86_64 assembly code to do the same as the x86_32 code.
* Separate x86_32 and x86_64 code.
Tested on qemu x86_32 and x86_64 using additional MTRRs.
Tested on Lenovo T410 with additional x86_64 patches.
Change-Id: I1c190627f5f0ed6f82738cb99423892382899d7b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30500
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TBT ports should be disabled if the DB is a USB3 DB. It is assumed if
the DB doesn't support USB4 the platform as a whole should only be USB3
capable and TBT functionality on both ports should not be enabled.
BUG=NONE
BRANCH=NONE
TEST=Built coreboot and verified that TBT was disabled on platform with
USB3 DB and enabled on platform with USB4/TBT DB
Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is
reset as part of global reset, TPM initialization fails. This is because
AP reset is not detected by TPM hosting an older firmware version. Request
Embedded Controller (EC) to perform AP reset so that TPM can detect that
event.
BUG=b:162290856, b:162386991
TEST=Ensure that the device boots to OS with the board-specific reset
sequence when CSE Lite jumps from RO to RW with an older and newer Cr50
firmware.
Cq-Depend: chromium:2337430
Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Add a helper function to initiate AP reset through Embedded Controller
(EC).
BUG=b:162290856
TEST=Ensure that the EC resets AP on boards where the command is
supported.
Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44188
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
When CSE Lite jumps from RO to RW, global reset is initiated. When AP is
reset as part of global reset, in some boards TPM initialization fails.
This is because AP reset is not detected by TPM hosting an older firmware
version. To signal TPMs running older firmware version about AP reset, a
modified reset sequence needs to be performed. Hence add support to
perform board-specific reset sequence.
BUG=b:162290856, b:162386991
TEST=Ensure that the device boots to OS with the board-specific reset
sequence when CSE Lite jumps from RO to RW with an older and newer Cr50
firmware.
Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44187
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested=On OCP Delta Lake, BMC SOL can see POST codes
Change-Id: I2c27055475e6dadcd4282cd1bf191a1b83150f02
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Set default value of ModPhyIfValue parameter in FSPS_UPD.
Without this setting, it will be set to '0' and system may not detect
USB 3.0 device.
BUG=b:163382089
BRANCH=firmware-octopus-11297.B
TEST=Built
Change-Id: Ide3d1637f99dba28251102f771b6ce370cc5d8e4
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Per the datasheet and the it87 kernel driver, the IT8728F supports
both 5 fans (vs 3) and use of a single 7-bit register for the
PWM slope (5 bits in closed-loop mode).
Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for tachometer closed loop mode, and programming
of initial RPM vs initial PWM value.
Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44418
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Currently sku_id is used to enable/disable eMMC as boot media on
Dalboz. This patch will check eMMC bit in firmware configuration
table to enable/disable eMMC.
On Dalboz Proto and EVT devices with eMMC, there was an issue found
after SMT. This patch checks for board_version instead of SKU_ID to
configure eMMC in HS200.
Configure HDMI based on daughterboard_id in FW_CONFIG.
BRANCH=none
BUG=b:152817444
TEST=Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: Ifa2a49a754d85fb6269f788c970bd9da58af1dad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44421
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently SKU_ID is used to enable/disable eMMC as boot media on
Ezkinil. This patch will check eMMC bit in firmware configuration
table to enable/disable eMMC.
BRANCH=none
BUG=b:162344105
TEST=Check eMMC is enabled or disabled based on the eMMC bit in
FW_CONFIG.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I62318cf71ec70790f2d9e787febd1e0b787741fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
After confirming that all zork variants and phases have valid
FW_CONFIG value in CBI, this patch is dropping FW_CONFIG validity checks
like VARIANT_HAS_FW_CONFIG and VARIANT_BOARD_VER_FW_CONFIG_VALID in Kconfig
and will also remove associated helper functions.
BRANCH=none
BUG=b:162344105,b:152817444
TEST=Check if FW_CONFIG bits can be read in coreboot and FW_CONIFG helper
function do not return 0 if board has a valid FW_CONFIG in CBI.
Signed-off-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Change-Id: I633dc7c500ef8759f3fffb0db6b76d96257c3c9a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch sets the GPP_H1 to PAD_CFG_GPO which is general
purpose output with no pullup/down. We need this GPIO for
the detection of soundcard in TGL RVP's.
BUG=none
BRANCH=none
TEST=Build and boot tglrvp successfully. From "aplay -l"
output check that soundcards are listed properly.
Change-Id: Ic0ef33079af7940360c986efacabd6d367aad516
Signed-off-by: Shaunak Saha <shaunak.saha@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
To be consistent with the rest of the tree, replace all left ternary
expressions, which are used for device enablement / disablement,
with `dev && dev->enabled`.
Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
The port is based on the F2A85-M, the main differences are:
- 2 DDR3 dimms
- 2 PS/2 ports
- 2*USB2.0 and 2*USB3.0 ports
- 3+2 phase VRM
- 6 channel audio
- 6 SATA ports
- ASP1206 VRM controller
- Bolton D4 chipset
- no optical SPDIF/IO
Successfully booted configurations:
-RAM: 2*8GB Kingston KVR 1333Mhz LP, 2*8GB Crucial BLT8G3D1869DT1TX0
-CPU: AMD A8-6500 (Richland), AMD A10-6700 (Richland)
-OS: Arch Linux 4.19 (SATA, USB), Linux Mint 19.3, Artix Linux 2019
-SeaBIOS: 1.12 and 1.13
Known problems:
- IRQ routing is done incorrect way - common problem of fam15h boards
- Windows 7 can't boot because of the incomplete ACPI implementation
Change-Id: I60fa0636ba41f5f1a6a3faa2764bf2f0a968cf90
Signed-off-by: Balazs Vinarz <vinibali1@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30987
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0
based, so it doesn't reuse coreboot's stack, but sets up its own stack.
In contrast to all other FSP 2.0 based platforms, this stack isn't in
the CAR region, since AMD Picasso doesn't support CAR and the DRAM is
already available when the x86 cores are released from reset. Selecting
FSP_USES_CB_STACK ended up doing the right thing, but is semantically
wrong. Instead of wrongly selecting FSP_USES_CB_STACK in soc/amd/picasso
we take the corresponding code path if ENV_CACHE_AS_RAM is false which
is only the case for non-CAR platforms.
BUG=b:155501050
TEST=Timeless build results in an identical binary for amd/mandolin,
asrock/h110m-dvs and intel/coffeelake_rvp11 which cover all 3 cases
here.
Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This reduces the differences between both ME source code files.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I08e07ca2691bb854682692476153a98967bf05da
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
This patch updates regions-for-file function in the
security/vboot/Makefile.inc to support adding a CBFS file into
required FMAP REGIONs in a flexible manner. The file that needs to be
added to specific REGIONs, those regions list should be specified in the
regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable.
For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT,
then below code needs to be added in a Makefile.inc.
regions-for-file-foo := FW_MAIN_B,COREBOOT
cbfs-file-y := foo
foo-file := foo.bin
foo-type := raw
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43766
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The placeholder functions and build rules for generating a minimal
firmware to run on MT8192 SOC based mainboard "Asurada".
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43963
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DRAM resource in ramstage to load payload.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The first Makefile to support building minimal stage files for MT8192 SOC.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43962
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO
to 8MiB") updated the flash layout which moved RW_SECTION_A and
RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION
and PICASSO_FW_B_POSITION configs need to be updated accordingly to
retain the same behavior as before i.e. amdfw_a/b are placed at the
start of FW_MAIN_A/B by placing them right after the CBFS header.
This change fixes the value of PICASSO_FW_A_POSITION and
PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS.
BUG=b:161949925
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44425
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Starting with v3.6 of reference schematics, headphone jack interrupt
is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no
longer need I2S wake to be enabled in the ACP for boards using v3.6+
version of schematics.
This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default
0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl()
if the board is still using older version of reference schematics.
BUG=b:159934887
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44403
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Latest EDK2 code inside
"UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c"
is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence
coreboot need to fill required information (package, core and thread
count).
TEST=Able to see package, core and thread information as part of FSP
debug log.
Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch sets FSP-M UPD Heci1BarAddress to avoid disconnect between
coreboot and FSP-M. Currently coreboot uses 0xfeda2000 as a PCI BAR address
for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR
address is overridden with 0xfed1a000. This causes HECI transactions to
fail between FSP-M call and postcar.
BRANCH=puff
TEST=Verified sending HECI commands before and after FSP-M call on hatch.
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44211
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add DTT (Dynamic Tuning Technology) support on Jasper Lake based drawcia
system. Add information on sensors, power limits and tcc_offset for DTT
based thermal control.
BRANCH=None
BUG=b:161993459
TEST=Built for dedede system
Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
espi_poll_status describes better what the function actually does, since
it polls the status register instead of just doing a single read to
check.
Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the ranges of bitfields as comments on the struct.
Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Also remove the meaningless `sata_traffic_monitor` devicetree option.
Function parameters will be removed in a reproducible follow-up.
Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
There's no mobile ICH10 variant. This was copied from i82801ix.
Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Taken directly from i82801jx code.
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These were probably copy-pasted from some ICHx southbridge, and then
some were corrected because native PCH init uses them. Delete the
definitions which are unused and are invalid for this southbridge.
Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
These were probably copy-pasted from some ICHx southbridge. However,
datasheet shows that some of these are located elsewhere, and some
others have disappeared completely. As they aren't in use, drop them.
Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Michael Niewöhner
Create the lindar variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.1.2).
BUG=b:161089195
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_LINDAR
Signed-off-by: Julia Tsai <julia.tsai@lcfc.corp-partner.google.com>
Change-Id: I08923cde932b7304bcb01cd747530c87949e4692
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Enable PCI_COMMAND_MASTER for SATA controller to ensure device can
behave as a bus master. Otherwise, the device can not generate PCI
accesses.
BUG=b:154900210
TEST=Able to build and boot CML and TGL platform.
Change-Id: Icc6653c26900354df4ee6e5882c60cbe23a5685c
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44299
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On CNP-H, only four I2C controllers are available, so PCI devices 19.0
and 19.1 are missing. However, PCI device 19.2 still exists as UART 2.
That function 0 is missing means UART 2 can only be used in ACPI mode.
Both devices need to be marked as hidden on the devicetree so that the
allocator takes UART 2 into account.
Change-Id: Ie77198cc0327414b9f88cf15ba4efaddb4f5cca4
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43481
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Values are taken from pci_irqs.asl.
The common code will make use of those defines to generate ACPI
SSDT code for LPSS uarts operating in "ACPI mode".
Change-Id: I5ef93493965834cda30d70918e65de3129e547b7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44260
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change reorganizes flash map layout for zork to allow WP_RO to
grow to 8MiB. This is to allow more space for the firmware UI screens
in RO. Following changes are made in the layout:
1. MRC_CACHE_HOLE is dropped since only one slot of 64K is used for
MRC cache. Next section can start on 64K boundary immediately after
MRC cache.
2. RW_SECTION_A and RW_SECTION_B are dropped down in size to 3MiB
each. Each region is currently at ~2MiB of usage.
3. RW_ELOG is restrictred to 4KiB as that is the maximum elog size
supported by coreboot.
4. SMMSTORE is restricted to 4K.
5. RW_LEGACY region is dropped down to ~1.9MiB.
BUG=b:161949925
TEST=Verified that write-protection for RO still works fine, device
boots in recovery and non-recovery mode. Also, verified that the dump
of fmap looks correct:
dump_fmap -h firmware/image-trembyle.serial.bin
name start end size
WP_RO 00800000 01000000 00800000
RO_SECTION 00804000 01000000 007fc000
COREBOOT 00875000 01000000 0078b000
GBB 00805000 00875000 00070000
RO_FRID 00804800 00804840 00000040
FMAP 00804000 00804800 00000800
RO_VPD 00800000 00804000 00004000
RW_LEGACY 0061d000 00800000 001e3000
SMMSTORE 0061c000 0061d000 00001000
RW_NVRAM 00617000 0061c000 00005000
RW_VPD 00615000 00617000 00002000
RW_SHARED 00611000 00615000 00004000
VBLOCK_DEV 00613000 00615000 00002000
SHARED_DATA 00611000 00613000 00002000
RW_ELOG 00610000 00611000 00001000
RW_SECTION_B 00310000 00610000 00300000
RW_FWID_B 0060ff00 00610000 00000100
FW_MAIN_B 00312000 0060ff00 002fdf00
VBLOCK_B 00310000 00312000 00002000
RW_SECTION_A 00010000 00310000 00300000
RW_FWID_A 0030ff00 00310000 00000100
FW_MAIN_A 00012000 0030ff00 002fdf00
VBLOCK_A 00010000 00012000 00002000
RW_MRC_CACHE 00000000 00010000 00010000
SI_BIOS 00000000 01000000 01000000
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I882f3d813c08ba5fb0ad071da4f79e723296f4b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44362
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
In order to help identifying right DRAM info (especially in user space),
we want to unify the mapping table and do the device-specific mapping by
a virtual offset based on build config.
BUG=b:161768221,b:159301679
BRANCH=kukui
TEST=emerge-jacuzzi coreboot
Change-Id: If89bf18c48d263deb79df3e7a60c33bec000d8a3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
With a CPUID of 10676, it is clearly model_1067x... Wait, it's already
there, but the comment is wrong. This ID isn't for Core Duo CPUs.
Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The base address of the memory mapped I/O registers should not
be cached across resource allocation. This CL will evict the cached
value upon exiting the BS_DEV_RESOURCES stage.
Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821
Signed-off-by: jbk@chromium.org
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44084
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change namespace from _PR to _SB.
Cq-Depend: chrome-internal:3208104
BUG=b:153242529
TEST=Boot a trembyle with change applied and dump SSDTs to ensure
processors are in _SB scope.
Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44325
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.
Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When address and data register for the SIO control register access is
passed as one I/O region with a size of 2, the corresponding special
decode enable register should be used instead of a generic one to save
the rather limited generic ones for other decode ranges.
Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We can just return at all places where the ret variable was written
before its value gets returned at the end of the function.
Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Since this is a bit mask applied to the raw value of a 32 bit register,
this should be a 32 bit unsigned type.
Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Th register number passed to the low level read/write functions should
never be negative.
Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some fields in GNVS seem to be copied over from Apollolake to
Stoneyridge. This patch removes the unused fields.
Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The USB OC pin mapping is similar enough to move it to the base board
and just have two overrides for trembyle, which is based on an older
version of the schematics, and one override for woomax, which doesn't
use one USB port.
BUG=b:163081097
Change-Id: I7e305d7e6f51d7ef7a4c699e3bacc6bcd699d2f2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add comments found when testing ECC scrubbing code.
This is a cosmetic change.
Change-Id: I7975f6070c2002930eec407a6b101a1295495b25
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40947
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The scrubbing method was never correct nor tested.
Fix that by observations made on mrc.bin.
Tested on HP Z220 with ECC memory and Xeon E3 CPU:
The whole memory is now scrubbed.
Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40721
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Add ECC test code when DEBUG_RAM_SETUP is enabled
* Move ECC scrubbing after set_scrambling_seed() to be able to observe
what has been cleared in the test routine. If clearing happens
before set_scrambling_seed the data is XORed with a different PRN.
Data read from memory will look random instead of all zeros.
* ECC scrubbing must happen after dram_dimm_set_mapping()
The ECC logic is set to "normal mode" in dram_dimm_set_mapping(). In
normal mode the ECC bits are calculated and stored on write
transactions.
* Move method out of try_init_dram_ddr3().
This satisfies point 2 and point 3 of the list above.
Change-Id: I76174ec962c9b0bb72852897586eb95d896d301e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The latest realtek RTS5261 SD daughterboard exposes the PRSNT# pin to
GPP_D16 but there is a RTS5261 requirement to pull up this pin and not
drive it at power on. We can meet this requirement without breaking
other boards by changing GPP_D16 to be a no-connect with an internal
pull up. Other boards use this signal as an enable input, so changing
this to pull up is OK.
BUG=b:162722965
TEST=Verified RTS5261 and GL9755 daughterboards enumerate on PCI and
can read SD cards.
Change-Id: I096d76ec12b7c3afaf02e621fd301b6704913d5d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The interface selection register of the environment controller (EC)
gives the choice between "Internal generated 32 MHz" and "24 MHz" for
the "SST/PECI Host Controller Clock Selection".
Previously the chip was always configured for the 32 MHz clock. Add an
option that can be set from devicetree.cb to allow using the 24 MHz
clock.
Without this setting the automatic fan control on an Acer Aspire M3800
was slow to respond to temperature changes.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44166
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This applies to the automatic fan control mode of the environment
controller (EC). Previously the affected bit was always cleared while
the default value is 1 according to datasheets. Add a variable that can
be set per mainboard in devicetree.cb.
In the IT8783E datasheet that bit is marked as reserved.
Signed-off-by: Michael Büchler <michael.buechler@posteo.net>
Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44165
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This isn't reproducible for some reason, but it is relatively simple.
Change-Id: I507229be71ac2c589c7ecd81495d38ce363d26a7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43275
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do it quick and dirty but in a reproducible manner. Variants will be set
up properly in subsequent commits.
Tested with BUILD_TIMELESS=1, both Lippert FrontRunner-AF and Toucan-AF
remain identical.
Change-Id: I71ff50099787e7806a9ab67429890a1c77061929
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43274
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use the same names as on other intel socs.
Will be used in intel common uart driver.
Change-Id: Ia418fefb3f925fe4d000683b5028682cf0b68a9b
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44200
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.1 and
0:19.2 can't be detected using standard PCI probing.
Remove I2C4, I2C5 and UART2 from generic ASL code on PCH-H platforms
that advertise its PCI conformance by the _ADR attribute.
Change-Id: I89f9ab7d4afb2e7d1b1e24d072adf99e0da6fecf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SA SMRAMC register PCI offset 0x88 is deprecated for ICL, JSL and TGL.
Removing the register programming for these platforms. The write to
this register does not take effect and remains configured to 0, even
when programmed.
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Change-Id: I3f581b90ea99012980f439a7914e8d901585b004
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Intel CPX-SP ww32 release has a number of bug fixes:
a. It fixed the issue related to some PCIe ports being hidden. This
affected DeltaLake config A, made the onboard PCIe NIC device not
working. ww32 release added two UPD parameters: PEXPHIDE, HidePEXPMenu.
b. It fixed the regression related to MRC cache.
c. It fixed the issue related to VT-d support, and added X2apic UPD
paramter. A separate PR will be submitted to enable VT-d in coreboot.
d. It fixed the issue related to enabling thermal device with PCI
or ACPI mode. [CB:44075] was submitted to enable it in coreboot.
e. It fixed the issue of FSP log level change UPD parameter DebugPrintLevel
not working.
There is a change in IIO UDS Hob.
TESTED=booted YV3 config A, and rebooted it. Access the target OS
remotely.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iaffcb9d635f185f9dd6d6fbe4457549984a993a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
David Wu