We ship it in the 3rdparty repository.
Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2060
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Add prefix coreboot_ to let make clean find it and delete it.
Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2029
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The file generated when the IMC or XHCI binaries are included in the rom
was named $(obj)/hudson_romsig.bin. The problem with this is that it
doesn't get deleted when the user does a make clean.
changing the name to coreboot_hudson_romsig.bin makes this happen.
Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1978
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
There was already a special case for the SPI base address in
lpc_set_resources for southbridge/amd/cimx/sb800 and
southbridge/amd/agesa/hudson, but it needed to be modified
to keep from killing the IMC rom during initialization. As
soon as the BAR is disabled by setting the new base address,
the IMC dies. The fix is to make sure it's still enabled
when setting the new base address instead of setting the new
address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1975
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The SB800 and Hudson now support adding the IMC ROM which runs from the same
chip as coreboot. When the IMC is running, write or erase commands sent to
the spi bus will fail, and the IMC will die. To fix this, we send a request
to the IMC to stop fetching from the SPI rom while we write to it. This
process (in one form or another) is required for writes to the SPI bus while
the IMC is running.
Because the IMC can take up to 500ms to respond every time we claim the
bus, this patch tries to keep the number of times we need to do that to a
minimum. We only need to claim the bus on writes, and using a counter for
the semaphore allows us to call in once to claim the bus at the beginning
of a number of transactions and it will stay claimed until we release it
at the end of the transactions.
Claim() - takes up to 500ms hit
claim() - no delay
erase()
release()
claim() - no delay
write()
release()
Release()
Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove the old, unflexible code for storing S3 data in SPI flash.
Refer to flashrom. Tested on Parmer.
Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Every line of text after a 'help' label in a Kconfig
file must have the same whitespace preceding it, otherwise
it's no longer considered help text.
Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1687
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Some 32 bit machines print integer higher than 0x80000000
as negative number.
Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1547
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Try
sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \
$1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \
od -Ax -t x
On Linux with gawk, we get
000000 005500aa
000004
On FreeBSD with nongnu-awk, we get
000000 000055aa
000002
In awk, all the numbers are floating point number. So division doesn't
round the result from 0.75 (3/4) to 0.
And, There is a fact that, for the FreeBSD awk,
sh> awk 'BEGIN {printf("%c", 0.75)}';
produces nothing, instead of 0.
Here we need to convert the floating point number to
integer by int(X), which is an awk built-in function, instead of GNU
extension.
Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h,
so we do some changes to remove such warnings.
Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1499
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Command expr in some systems only take 32bit as integer, which
value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to
calculate.
And some system doesnt take hex value in Makefile, even in awk instruction.
Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1527
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Forgot to change the code back after debugging.
Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1491
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Prior to this change the setting would be zeroes and
would cause a BSOD in 64 bit versions of Windows.
Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1475
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Maybe sooner or later python is not a default tools to build coreboot.
Most of the work is done by awk now. GNU extension of gawk is not used, isn't?
echo, expr, printf, cat, awk, test, mv are the external tools.
If XHCI, IMC or GEC firmware is not available and not defined, this script can skip
integrating them.
Change-Id: I9944b22b0b755672a46d472c355d138abafd6393
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1417
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The name is derived directly from the device path.
Change-Id: If2053d14f0e38a5ee0159b47a66d45ff3dff649a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1471
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The includes removed here were previously required for
struct lb_memory and lb_add_memory_range().
Change-Id: Ie6c0d4ef55c2225aa709cf3fbad30ff1080e3610
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1391
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Use IORESOURCE_RESERVE to exclude the region from system RAM table.
Change-Id: I61b51022165e1304a41554f67af75b3089d892af
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1393
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Apply the change
http://review.coreboot.org/1390
to all the AMD southbridge.
Change-Id: I8e94014f8883a0408b68355d9aa33aea4373881f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1406
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Parmer and thather hang at windows 7 booting process. Setting the
valid date in CMOS can fix that.
Change-Id: I5e427cfb42430ebebdb4c1e48bd25860c0fec45f
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1390
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The code in rs690 or rs780 is always used with K8 or AMDFAM10
northbridge. Without GFXUMA, both of these set the same static value
indirectly using the variable uma_memory_base.
Make the register setting with immediate value, to remove the obscure
use of variable uma_memory_base.
Change-Id: I5354684457a76e73013b4e34a4538a6d122eee8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1246
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Our driver infrastructure became more flexible recently.
Make use of it.
These are the low hanging fruits (files with 5 device
variants or more), but there are still lots of files
with less potential for deduplication.
Change-Id: If6b7be5046581f81485a511b150f99b029b95c3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1358
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
With this patch it is possible to use the smbus in ramstage. The
biggest part of the patch is a simple code split into a general
part (smbus.h) and the concrete users (early_smbus.c and cs5536.c).
After the switch from romstage to ramstage the smb base address
has changed, but that is no problem as the new base address is
stored in bar0 of the ISA bridge. It could also be read via msr,
but via PCI it is simpler. I used the following patch as
reference on how to readout the new base address:
http://lists.laptop.org/pipermail/commits-kernel/2006-November/000178.html
Change-Id: I9f86a1e474368c62f9ed3a95edfb3e63117aa156
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/1243
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Set the default location of hudson firmware to 3rdparty.
Move UMA code from mainboard to northbridge.
Change-Id: I11afea0c7fd04aa84a629dc762704c42baf002df
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1241
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Use of the uma_memory_base and _size variables is very scattered.
Implementation of setup_uma_memory() will appear in each northbridge.
It should be possible to do this setup entirely in northbridge
code and get rid of the globals in a follow-up.
Change-Id: I07ccd98c55a6bcaa8294ad9704b88d7afb341456
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1204
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Hudson code has been integrated from CIMx to AGESA. This patch is about the wrapper.
Change-Id: I63d951982140b82a3a77a97eb3d55fc75fc0caa3
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1157
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
awk on Cygwin created the UTF-8 value for the 0xff code point,
which makes it two bytes wide. This broke the build.
Change-Id: I4937ae7ce1136ba7a76d05b42f9dd2771203175d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1164
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Peter Stuge <peter@stuge.se>
The wrapper for Trinity. Support S3. Parme is a example board.
Change-Id: Ib4f653b7562694177683e1e1ffdb27ea176aeaab
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1156
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- Add #define to allow the FADT PM Profile to be overridden.
- Change the location of the PMA_CNT_BLOCK_ADDRESS to match
current documentation.
- cst_cnt should be 0 if smi_cmd == 0
- add a couple of default access sizes.
- Add a couple of #define values for unsupported C2 & C3 entries.
- Add PM Profile override value into amd/persimmon platform.
This does not use the #defines in acpi.h so that the files that
include this don't all need to start including acpi.h.
Change-Id: Ib11ef8f9346d42fcf653fae6e2752d62a40a3094
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1055
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Remove all the repeated sections of code in cbtypes.h and place it
in a common location. Add include dir in vendor code's Makefile.
Change-Id: Ida92c2a7a88e9520b84b0dcbbf37cd5c9f63f798
Signed-off-by: Vikram Narayanan <vikram186@gmail.com>
Reviewed-on: http://review.coreboot.org/912
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The fadt legacy free logic was backwards.
Change-Id: Ieb21ef335f7514ced70248d0bf8668ddb73cf59f
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1030
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)
The FADT iapc_boot_arch indicates the available information
for accessing legacy devices. By default, the setting supports
legacy. LEGACY_FREE and/or the iapc_boot_arch field may be
customized.
Change-Id: I5679741e1f8db923d3c00b57f6a5d813550f3a5e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1024
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
The South Station recieved updates that fix a number of fadt problems.
South Station now uses the southbridge fadt.
Change-Id: Ib990a69a359a4b7eae3431bb4323acd537acda1d
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1021
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Peter Stuge <peter@stuge.se>
Change source file modes from 755 to 644
The following files have been grepped for changes:
*.c
*.h
*Kconfig*
*Makefile*
Change-Id: I275f42ac7c4df894380d0492bca65c16a057376c
Signed-off-by: Alec Ari <neotheuser@ymail.com>
Reviewed-on: http://review.coreboot.org/1023
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The fadt.c is the same across all the platforms using the sb800
cimx southbridge wrapper.
Change-Id: Ifbbfc238732aa46aef96297eaa188b77d27151f3
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1019
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
These are the PMIO & PMIO2 read & write routines from
src/southbridge/amd/sb800/sb800.c & sb800.h for use in the cimx
tree. Currently most platforms using CIMX are calling WritePMIO()
directly from the src/vendorcode/amd/cimx/sbX00 directories
instead of using a wrapper function.
These functions only do byte reads & writes.
Change-Id: I881a6e2d4ddbba3dbdf4dd33e06313fe88b3682a
Signed-off-by: Martin L Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/981
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Replace #elif (CONFIG_FOO==1) with #elif CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]1),\1\2,g" {} +
(manual tweak since it hit a false positive)
Replace #elif (CONFIG_FOO==0) with #elif !CONFIG_FOO
find src -type f -exec sed -i "s,\(#.*\)(\(CONFIG_[A-Z0-9_]*\)[[:space:]]*==[[:space:]]0),\1\!\2,g" {} +
Change-Id: I8f4ebf609740dfc53e79d5f1e60f9446364bb07d
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1006
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Martin Roth <martin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
S3.rom is useless for all the other boards which don't use flash to
save sleep/wakeup settings. AGESA-based boards other than persimmon
haven't been validated the S3 resume. They don't need S3.rom yet.
Change-Id: I12693e9556ca6f8e0d80b2ab2dca5c85bdb97685
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/902
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Some places still hardcoded the address instead of using IO_APIC_ADDR.
Change-Id: I3941c1ff62972ce56a5bc466eab7134f901773d3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/677
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It is for S3, storing the recovring data in the nonvolatile storage,
i.e., flash.
Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/620
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Also mark the corresponding lint test stable.
Change-Id: Ib7c9ed88c5254bf56e68c01cdbd5ab91cd7bfc2f
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Southbridge SP5100 support was compiled with SB700 code, but static
device info structure would use sp5100/chip.h. To solve this drop
support for separate chip sp5100 and adjust the relevant Kconfig
options.
Removes chip directory:
src/southbridge/amd/sp5100/
Rename Kconfig option
from: SOUTHBRIDGE_AMD_SP5100
to: SOUTHBRIDGE_AMD_SUBTYPE_SP5100
Change-Id: I873c6ad3624ee69165da6ab7287dfb7e006ee8e8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/679
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I16b27e40ca1a201b2f968f8ce303eaafe43804c0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/660
Tested-by: build bot (Jenkins)
If PCI config cycles use MMIO instead of I/O in the SB600 bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O and
configures the southbridge decode range to what is defined by the
mainboards Kconfig.
Change-Id: I85297237f32f37b3fc1ff5b488cca0a43bcf20fd
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/632
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If PCI config cycles use MMIO instead of I/O in the SB700
bootblock code the cycles will go nowhere since the MMIO feature
hasn't been configured yet. This change forces the cycles to use
I/O and configures the southbridge decode range to what is specified
by the mainboards Kconfig.
Change-Id: I15a89a27645edf594d14ef20f129f75a315e9672
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/631
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
If PCI config cycles use MMIO instead of I/O in the bootblock
code the cycles will go nowhere since the MMIO feature hasn't been
configured yet. This change forces the cycles to use I/O.
Change-Id: I93dec45f7cd6764cef7736c774a4d4e61bf7d7e0
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/630
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Extend the Family10 revisions checked byt the printk message.
Change-Id: Ia94daeefb1aabfb128c577b1e0aa52cf63d5cf44
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/633
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge.
Change-Id: I7a7a1919b7a555156b8da21e8db7dd8f682d68e1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/661
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree board using that chipset has it not selected, so move
selection from boards to southbridge. (cimx/sb800 is a "different"
chipset)
Change-Id: If7cf2a141a1f2df60f687c51fbd760aa405c8480
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/666
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
No in-tree amd8111-using board has it not selected, so move
selection from boards to southbridge.
Change-Id: Iabbaa4cd2fd367ed6decec7ef5cdcbae3b264d52
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/654
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Change-Id: Ie3872c57990f9784aafda14f8c7fc842b3a65260
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Verb data is required for the HDA audio codec in the sb800 southbridge. Verb
data is not required for mainboards that use G-Series HDMI. It is also a setting
the may be boards specific. This fixes issues with Windows audio on Persimmon.
Change-Id: I067506871e92078d122cf79872363d8937d47e50
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/490
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Untested, changes ramstage build for boards:
supermicro/h8qme_fam10
amd/serengeti_cheetah
amd/serengeti_cheetah_fam10
AMD 8132 was not built for any mainboard due to a typo.
AMD Serengeti Cheetah:
Chip 8151 is referenced in devicetree.cb but was not built.
AMD Serengeti Cheetah Family10:
There are indications the board has 8151, but it is not listed
in the devicetree.cb. The 8151 chip is not added in the build.
Change-Id: I03acdfcc3f3440bd32e81a9a696159903bbbcb50
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/471
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
- move enable_usbdebug() declaration to usbdebug.h
- reinitialize debug driver in ramstage, as copying the data
structure from romstage doesn't work right now. This way of copying
data from romstage to ramstage is really board/cpu specific, and is
likely to break often. So don't do it.
Change-Id: I394678ded6679c1803e29eb691b926182bdcab68
Signed-off-by: Sven Schnelle <svens@stackframe.org>
Reviewed-on: http://review.coreboot.org/355
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I3ccb3860207e1b3ccac4313f7b537c434af5166f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/360
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
This change removes CONFIG_TINY_BOOTBLOCK, CONFIG_BIG_BOOTBLOCK, and
all their uses, assuming TINY_BOOTBLOCK=y, BIG_BOOTBLOCK=n.
This might break a couple of boards on runtime, but so far, fixes were
quite simple.
There's a flag day: Code that relies on CONFIG_TINY_BOOTBLOCK must be
adapted.
Change-Id: I1e17a4a1b9c9adb8b43ca4db8aed5a6d44d645f5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/320
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Linux implements it itself, but older Linuxes and other systems
might not. Without this, the host controller might not respond
to drivers.
Change-Id: I4ff0e3683c02e7aa00d188428847c64c4c5d589d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/345
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add configure option SB_GPP_UNHIDE_PORTS for mainboard
to hide/unhide the unused sb800 gpp ports.
Certain gpp port should be hidden, if no device was detected and
hotplug feature is disabled for such port.
Hidden unused ports makes lspci -vvv get more accurate information under Linux.
Test on avalue/eax-785e mainboard.
Change-Id: I1d7df0f2ab6ad69b1b99b8bf046411ae7cdb09c0
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/207
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Otherwise with a coreboot log on COM2 (which doesn't work) the boot
process takes eons.
Change-Id: I886f98b715c1f384c8693f2977671ff15897b5a5
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/241
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
SB800 RAID ROM require to put the misc ROM to specific position,
this patch enable user to put the RAID misc ROM to the right place
in the coreboot image.
Change-Id: I4fc64df8e091fb0cccd063826ab31a4f198942d1
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/249
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
In order to make sure AHCI/RAID ROM works correctly
For SB800_SATA_AHCI or SB800_SATA_RAID mode, SATA should
enable bus master and the ahci also should be enabled.
Change-Id: I9d9c557816d364d8373fe343860ad5fe45988200
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/248
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Add this option to enable/disable SATA IDE Combined Mode feature
Change-Id: I1ab8acd27947a71baf954f44d0741f81f48e5541
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/231
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
sb800 cimx entry sb_Before_Pci_Init was called in the device 16.2
enable_dev() function. If the devicetree don't have this device,
then sb_Before_Pci_Init will not get called.
Change-Id: I76ebad842e90b0f740abbec031165d7c39a80abf
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/230
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
If sb800 sata was configured as ahci or raid mode,
give the option to add ROM files.
Change-Id: I87a7814930ce3a7c38cde1e235d151223eea2107
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/225
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This change removes printk's that occur before
console init is called. In the best case, these
would cause an extremely slow boot, and in the
worst case would cause a complete post failure.
Change-Id: I50388e71225e95db602aa45835c39126c1c920a3
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/216
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Hide the unused gfx ports and gpp ports if they are not configured as hotplug.
lspci -vvv will get more accurate information under Linux,
tested on avalue/eax-785e.
Change-Id: Iaabfd362a0a01f21d0f49aa2bd2d26f9259013fb
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/206
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This patch enables access to the registers of the hardware monitor
logical device in the superio via isa ports 0x295/0x296.
Previously this was not enabled in the SB8xx LPC device.
This is required for initialisation in init_hwm() in
src/superio/winbond/w83627hf/superio.c and also by OS-level
sensor monitoring such as lm-sensors to access temperature,
fan monitoring and control and voltage registers.
asrock/e350m1 and advansus/a785e-i mainboard changes are included herein.
Change-Id: I2176885549277b335c0c41b48457d09b9b76b703
Signed-off-by: Per Hansen <perh52@runbox.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/159
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the southbridge related code to support
the update of the AMD Family14 cpus to the rec C0 level.
Some of the changes reside in mainboard folders but they
reference changed files in the southbridge folder so they
are included herein.
Change-Id: Ib7786f9f697eaf0bf8abd9140c4dd0c42927ec7e
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Signed-off-by: Kerry She <kerry.she@amd.com>
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/135
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The inline comment of sata_init function seems not placed correctly.
Rearrange it.
Change-Id: I63480da60e51cdc68e64c302ad2d8a6197e288f6
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/186
Tested-by: build bot (Jenkins)
This updates the code for the AMD SR5650 and SB700 southbridges.
Among other things, it changes the romstage.c files by replacing a
.C file include with a pair of .H file includes. The .C file is
now added to the romstage in the SB700 or SR5650 Makefile.inc.
file to the romstage and ramstage elements. This particular change
affects all mainboards that use the SB700, and their changes are
include herein. These mainboards are:
Advansus a785e,
AMD Mahogany, Mahogany-fam10, Tilapia-fam10,
Asrock 939a785gmh,
Asus m4a78-em, m4a785-m,
Gigabyte ma785gm,
Iei Kino-780am2-fam10
Jetway pa78vm5
Supermicro h8scm_fam10
The nuvoton/wpcm450 earlysetup interface is changed because the file
is no longer included in the mainboard romstage.c files.
Change-Id: I502c0b95a7b9e7bb5dd81d03902bbc2143257e33
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/107
Tested-by: build bot (Jenkins)
Reviewed-by: Kerry She <shekairui@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Move the AMD SB800 early clock setup code that is needed for early
serial port operation from mainboard/romstage.c to sb800/bootblock.c.
This prevents code duplication and simplifies porting.
Change-Id: I615cfec96c9f202d9c154dc6674ec7cbcf4090c3
Signed-off-by: Scott Duplichan <scott@notabs.org>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/96
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
sb800 pci bridge SHOULD enabled by default according to the chipset document,
but actually not enabled on some mainboard.
enable sb800 pci bridge when told to enable in devicetree.cb.
tested on ibase persimmon mainboard.
Change-Id: I42075907b4a003b2e58e5b19635a2e1b3fe094c3
Signed-off-by: Kerry She <shekairui@gmail.com>
Reviewed-on: http://review.coreboot.org/63
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change adds the wrapper code for the AMD Family12
cpus and the AMD Hudson-2 (SB900) southbridge to the cpu,
northbridge and southbridge folders respectively.
Change-Id: I22b6efe0017d0af03eaa36a1db1615e5f38da06c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/53
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This change renames the cpu/amd/agesa_wrapper, northbridge/
amd/agesa_wrapper, and southbridge/amd/cimx_wrapper folders
to {cpu|NB}/amd/agesa and {SB}/amd/agesa to shorten and
simplify the folder names.
There is also a fix to vendorcode/amd/agesa/lib/amdlib.c to
append "ull" to a trio of 64-bit hexadecimal constants to
allow abuild to run successfully.
Change-Id: I2455e0afb0361ad2e11da2b869ffacbd552cb715
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/51
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
So we don't waste time on the first cbfs scan.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
[adapt persimmon with the same change, and work around romcc bug
in bootblock code: it doesn't like MEMACCESS[idx] |= value;]
Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997
Reviewed-on: http://review.coreboot.org/9
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Scott Duplichan's patch from the mailing list:
sb800 cimx wrapper: Run the complete sb800 cimx sbBeforePciInit() function
once, after determining device 0x15 function enables.
1) Update the asrock e350m1 devicetree.cb to match the hardware.
2) Change the way the sb800 cimx wrapper code works. The original
cimx code calls sb800 cimx function sbBeforePciInit() once. When
ported to coreboot, the gpp component of this function was called
once for each gpp port, as the gpp port's enable/disable state
became known. A 05/15/2011 change makes the early gpp code run
only once, triggered by processing the 4th gpp port. This method
is not general enough because the 4th gpp port is not enabled on
all boards. With the current change, the early gpp code runs when
the first gpp port is processed. If any gpp ports are enabled, the
first must be enabled. Tested with Win7 and linux on asrock e350m1.
This change will also affect amd inagua, and has not been tested
on that board.
Change-Id: I93d44c216bfcab3c3a8fbb79d23dab43a65850e6
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marshall Buschman <mbuschman@lucidmachines.com>
Reviewed-on: http://review.coreboot.org/44
Tested-by: build bot (Jenkins)
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
Seabios doesn't have this support included yet,
which causes the generic Persimmon and other CIMx
sb800 platforms to not boot.
Change-Id: If07328b7c62d7fc314647adce8fab983ed327854
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: http://review.coreboot.org/14
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
src/southbridge/amd/cimx_wrapper/sb800/late
call clear_ioapic but not include the prototype declare header file.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6613 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6592 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6580 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Note: enable AHCI in seabios and apply seabios patch:
http://www.mail-archive.com/seabios@seabios.org/msg00437.html
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6579 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6576 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and remove RS780 get_cpu_rev().
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6560 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
some platform only use sb800 cimx code, not use AGESA v5 code.
for such platform, one can compile the sb800 cimx and AGESA v5 lib code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6559 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to unify calls to *_enable_usbdebug()
* rename *_enable_usbdebug() to enable_usbdebug()
* move enable_usbdebug() to generic romstage console init code
and drop it from the individual romstage.c files.
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Kerry she <kerry.she@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6488 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html
It's about time we follow this advice.
Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and
drop unused CPP define
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6465 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Since the SB700 has changed to sb7xx_51xx, change legacy name in
other mainboard.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Bit 0 of pm reg#74 have to be set turn on system after power resumes.
See '42661_sb600_rrg_nda_3.02.pdf' (or '46155_sb600_rrg_pub_3.03.pdf')
for details, look for 'PwrFailShadow'.
[Patrick: I didn't include the get_options reorganization as get_option
doesn't overwrite "on" if power_on_after_fail isn't found in CMOS.
Style changes were also left out.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6451 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also it enables the FID/VID changes in SB. Jakllsch had some troubles with that too but on am2 CPU. Those bits are only documented in SB600. They arent in RRG RPR and BDG.
Signed-off-by: Rudolf Marek <r.marek@asssembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot used to set the chipset to IDE mode unconditionally.
Now, the user has a couple of ways to choose the configuration:
- If a CMOS variable sata_mode exist, it is used to decide if IDE or
AHCI is to be used as interface.
- If not, a Kconfig option is used.
- If unchanged, the Kconfig option is set to IDE.
So unless the cmos.layout is extended or Kconfig is modified, this won't
change behaviour.
[Patrick: Compared to Josef's version, I changed the Kconfig option to
be boolean, instead of a magic string. Also, the "IDE" default is
handled in Kconfig, instead of an additional line of code.]
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6379 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Setting bit#21 in k8_f0#68 is part of the errata#169
which is handled in amdk8/coherent.c
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6354 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6346 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Everything else needs to be done by lpc.c Problem was that early settings survived, because the lpc.c is doing ORs only...
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6343 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
If enabled, set up 0xe0000000..0xf0000000 as MMCONF
area. Must still be configured in per-board ACPI for
the OS to pick it up, so it's disabled by default.
Signed-off-by: Josef Kellermann<seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6341 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some RS690 devices require subvendor/subdevice IDs to
be programmed at locations other than default 0x2c.
Signed-off-by: Josef Kellermann <seppk@arcor.de>
Acked-by: Patrick Georgi <patrick.georgi@secunet.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6330 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Hence we decode quite a lot and even strange ranges like IO port 0x4600 etc...
Also, if some port which does not fit to predefined set is requested, like 0x290 for Hardware monitor, the wide port is done, but in our case it has range 512 bytes which means we decode in fact 0x290 - 0x490. And if we hit GPU in the 0x3bx range I receive MCE exception if I do isadump -f 0x300 which is bad.
Therefore If I detect that the requested range is small (16 bytes) I additionally set the small wide io region so only 16 bytes is decoded.
While at it, I fix spelling typos and I init the regs so we don't write random garbage to regs even if we don't enable them later.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6316 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As Rudolf called.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The AcpiPmaCntBlk have to be set.
Further research is needed to find out why.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6293 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Note:
1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the
smp_write_config_table will run. Then intr_data will be written
into 0xC00/0xC01.
2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of
pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0).
The pci_locate_device will cause the system crash.
3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why?
4. early_setup.c: pmio 0x65 has change its meaning.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
by using 'Int32FromChar' macro, instead of the ASCII code.
Signed-off-by: Kerry She <kerry.she@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6248 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We did the same with other chipsets in r6150.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Kerry She <Kerry.she@amd.com>
Acked-by: Stefan Reinauer <stepan@coreboot.org>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6230 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to FG (FooGlue). As the GX2 has no VIP port.
-Change the Memmory setup MSR register names so they correspond better to the
databook. (Part1)
This is less confusing for beginners.
-Add a MSR printing function to northbridge.c like in the Geode LX code.
-Remove the AES register names.(GX2 has no AES registers)
-Delete some unused code.
-Clean up GX2 northbridge code to match Geode LX code.
-Add missing copyright header to northbridge.c.
-Move hardcoded IRQ defining from northbridge.c to irq_tables.c .
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
-Remove some white spaces.
-Remove some leading zeros.
-Fix a typo in LX code.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The writes to NVRAM are not used in asrock board (k8 pre rev f) but they should work when used with am2 boards. In fact maybe the suspend will work on mahogany or others ;) - with some simple patch which follows for asrock.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6173 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6166 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6165 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Factor out the ROM decode enable functionality into bootblock.c and
handle it via the usual TINY_BOOTBLOCK mechanism.
Use "select TINY_BOOTBLOCK" in the southbridge, not individual boards.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6159 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All southbridges using TINY_BOOTBLOCK have a bootblock.c files which
simply includes an enable_rom.c files. As discussed on the mailing
list, drop the enable_rom.c file by merging it into bootblock.c.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6158 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the prefix was introduced in the early v2 tree many years ago
because our old build system "newconfig" could not handle two files with
the same name in different paths like /path/to/usb.c and
/another/path/to/usb.c correctly. Only one of the files would end up
being compiled into the final image.
Since Kconfig (actually since shortly before we switched to Kconfig) we
don't suffer from that problem anymore. So we could drop the sb700_
prefix from all those filenames (or, the <componentname>_ prefix in general)
- makes it easier to fork off a new chipset
- makes it easier to diff against other chipsets
- storing redundant information in filenames seems wrong
Signed-off-by: <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6149 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
De-asserts STRAP_BIF_all_valid for
PCIE-GFX core.
After lane reversal,
Asserts STRAP_BIF_all_valid for
PCIE-GFX core.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: QingPei Wang <wangqingpei@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, add missing license header to amd8111_enable_rom.c, add some more code
comments and use PCI IDs from pci_ids.h instead of hardcoding.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick@georgi-clan.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6124 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
AMD RS780 uma graphics. Tested with frame buffer sizes 64m through 1GB
by running dxdiag and Windows media player at 1600x1200 true color.
Additional changes needed to boot Win7 on Mahogany_fam10 will follow.
-- Enable and program the debug bar as required by the ATI graphics driver.
First, make the debug bar writable and allow resource allocation code
to program it. Once programmed, enable its operation.
-- Disable the family 10h processor mmconf while the RS780 mmconf is in use.
-- Make strap programming more closely follow the reference BIOS.
-- Disable PCIe bar 3 after using it.
-- UMA size is no longer hardcoded.
-- Disable write combining for all steppings to eliminate stability problem.
-- Correct task file data.
-- Improve the accuracy of the Atom table that passes information to the driver.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6120 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
addressing scheme to match the rest of the tree
(0x50 instead of 0xa0).
abuild tested.
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It affects only systems booting from SPI flash, not those booting from
LPC flash. By default, the SB700 reads dwords from the SPI flash chip.
Setting PrefetchEnSPIFromHost causes the SB700 to read entire cache
lines from the flash chip.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5965 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to zero, so for boards with RS780 not on CPU's HT chain 0, the function will
mis-configure the MMIO dst-link routing, and the following enable_pcie_bar3()
function will hang when it visits the MMIO.
The following patch fixes the problem, and is tested on a K8 board with RS780
on HT chain 1.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5959 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Fix that to read the register from the chain where the SB chip is on.
Signed-off-by: Liu Tao <liutao1980@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5958 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some mainboards need to disable the power button to avoid turning off
right after being turned on, while other boards ship with a jumper over
the power button and should allow the user to configure the behavior.
This adds infrastructure in the form of four mutually exclusive options
which can be selected in a mainboard Kconfig (power button forced on/off,
and user-controllable with default on/off) and one result bool which
source code can test. (Enable the button or not.)
The options have been implemented in CS5536 code and for all mainboards
which select SOUTHBRIDGE_AMD_CS5536, but should be used also by other
chipsets where applicable. Note that if chipset code uses the result
bool ENABLE_POWER_BUTTON, then every board using that chipset must
select one out of the four control options in order to build.
All touched boards should have unchanged behavior, except
pcengines/alix1c, traverse/geos and lippert/hurricane-lx where the
power button can now be configured by the user.
Build tested for alix1c, alix2d, hurricane-lx and wyse-s50. Confirmed
to work as advertised on alix1c both with button enabled and disabled.
Includes additional traverse/geos changes from Nathan and
lippert/hurricane-lx changes from Jens to correctly use the new
feature on those boards.
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Aurelien Guillaume <aurelien@iwi.me>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5948 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
As both ioapic.h and acpi.h define a macro named "NMI", rename one
of them (NMI -> NMIType in acpi.h).
Abuild-tested.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5943 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Following patch enables UDMA on ALL IDE devices. The current code enables it only for primary master, which causes my DVD drive to fail under windows install
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5933 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
primary / secondary IDE channel with SATA (in IDE mode).
The bug was that setup was done in wrong device.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5932 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and even after hard reset in linux (DMA seems lockup).
The fix should not have any influence for Linux because the IDE driver will
correctly reprogram this bit.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5931 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
bit in the AMD processor 'MMIO Limit Address Register'.
I suspect it is because of a typo where 0x80 was entered
as 0x8. If 0x80 is used, then the strap configuration
register accesses become non-posted, which is how the
Shiner reference BIOS does it.
Signed-off-by: Scott Duplichan <scott@notabs.org>
Acked-by: Rudolf Marek <r.marek@assembler.cz>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5919 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- move EHCI_BAR and EHCI_DEBUG_OFFSET to Kconfig to be set by USB debug port enabled southbridges
- drop USB debug code includes from romstage.cs and use romstage-srcs in the build system instead
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5911 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The AMD SB700 allows changing the physical USB port to be used as
USB Debug Port, implement support for this.
Also, fix incorrect PCI device of the SB700 EHCI device. Actually, the
SB700 has _two_ EHCI devices (D18:F2 and D19:F2), but for now we only use
D18:F2. Our generic USBDEBUG code cannot handle multiple EHCI PCI devices
currently, AFAICS.
Hook up all SB700 boards to the CONFIG_USBDEBUG_DEFAULT_PORT facility.
Untested, but should work.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5907 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
at the same time let the user specify sources instead
of object files:
- objs becomes ramstage-srcs
- initobjs becomes romstage-srcs
- driver becomes driver-srcs
- smmobj becomes smm-srcs
The user servicable parts are named accordingly:
ramstage-y, romstage-y, driver-y, smm-y
Also, the object file names are properly renamed now, using
.ramstage.o, .romstage.o, .driver.o, .smm.o suffixes consistently.
Remove stubbed out via/epia-m700 dsdt/ssdt files - they didn't
easily fit in the build system and aren't useful anyway.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coreystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5886 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is selected that uses a chipset which actually has that functionality _and_
we have code to initialize the Debug Port in coreboot (for that chipset).
Also, remove the duplicate list of PCI IDs and just link to the wiki page at:
http://www.coreboot.org/EHCI_Debug_Port
The list is now less useful in the kconfig help as this option will only
appear for those boards where it's actually supported.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5848 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Use PCI_COMMAND and PCI_COMMAND_MEMORY from pci_def.h instead of
hardcoding their values.
- SB600/SB700: Drop useless/unused SB600_DEVN_BASE and SB700_DEVN_BASE.
- ICH7: Drop unused EHCI_CONFIG_FLAG and EHCI_PORTSC.
- s/uint32_t/u32/.
- Cosmetics, whitespace, coding style fixes and added code comments.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5847 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also fixes random whitespace issues, typos, etc.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5837 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Without a (currently) dummy set_debug_port() function the build fails,
this may or may not be fixed differently in the future.
Manually build-tested on all SB600/SB700 boards, and tested on hardware on
one SB600 board I own, works fine.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5833 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
consits of weak function which always exists (with defaults) and a possibility to
override this with normal function in main.c. This is the other way of
doing that and not using the devictree.cb.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5825 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
and SB600.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5781 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
detected by the existence of dev3. Some other RS780 mainboard has
the same function. The patch added the function to make these boards work
smoothly.
Signed-off-by: Wang Qing Pei <wangqingpei@gmail.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5714 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5705 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5703 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Revert until someone with the boards refactors it.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5681 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also clean up gx2def.h and geode_post_code.h a little.
abuild tested and boot tested on a Wyse S50.
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5671 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl>
Acked-by: Joseph Smith <joe@settoplinux.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5669 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
there is no free list.
Converting resource arrays to lists reduced the size of each device
struct from 1092 to 228 bytes.
Converting link arrays to lists reduced the size of each device struct
from 228 to 68 bytes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5626 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
However on these platforms we were causing a resource conflict by
letting the resource allocator start allocations at 0x400.
Change the constraints to start at 0x1000 so we avoid allocating over
LPT ports (0x778-0x77f), PCI (0xcf8-0xcff) and some other fixed
resources that might live down there (smbus base, acpi base,...)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
range as detailed on p104 of the cs5536 Device Data Book.
Extended to 0x1000. Same change for cs5535.
Signed-off by: Edwin Beasant edwin_beasant@virtensys.com
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/model_fxx/model_fxx_update_microcode.c
src/northbridge/amd/amdk8/amdk8_acpi.c
src/southbridge/amd/amd8132/amd8132_bridge.c
Signed-off-by: Frank Vibrans <frank.vibrans@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
http://www.coreboot.org/pipermail/coreboot/2010-June/058668.html
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5607 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To apply this patch you need to
cp src/northbridge/amd/gx2/chipsetinit.c src/southbridge/amd/cs5535/
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Nils Jacobs <njacobs8@hetnet.nl>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
coreboot is direct. This patch does it.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5586 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cs5536.c:chipsetinit() is called during northbridge pci_domain_enable()
which happens before scan_bus() so the device tree does not have PCI
vendor/device ids yet. Let's use dev_find_slot() for now. This works
only as long as the CS5536 has PCI device id 0xf in all mainboards,
and a better solution is needed in case that ever changes!
Signed-off-by: Peter Stuge <peter@stuge.se>
Acked-by: Nathan Williams <nathan@traverse.com.au>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5581 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* integrate vsm init into normal x86.c code (so it can run above 1M)
* call void main(unsigned long bist) except void cache_as_ram_main(void)
on Geode LX (as we do on almost all other platforms now)
* Unify Geode LX MSR setup (will bring most non-working LX targets back
to life)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
only. Keeping them as #warnings will not likely that they're fixed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5459 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5356 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Only some assembler files still have \r\n ... Can we move that part to C
completely?
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5342 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Interesting enough, console_printk was only used in a single place and
duplicated a large part of console.h which is included in the same place.
Thus, just drop console_printk.c and we're one down with console complexity
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5274 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Some other random warnings.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5268 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
CONFIG_CAR_FAM10 was renamed some time ago to
CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as
l3_cache().
Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
otherwise it will keeps reboot. The comment was also added in
detail to make less confusing when we debug SB600/SB700.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5240 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5223 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Makefile and Kconfig.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5222 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* PCIe initialization.
* Internal Graphics initialization.
* HT Link initialization. It works in HT1 or HT3 mode.
Note:
1. I tried to add the description of every step to the code. For example,
if it is made based on rpr, section 2.4.5, I will pasted the words
from 2.4.5 to the c code. But the document I worked with might be
different with the most updated one. A new section has been added and
the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I
correct every comment if I met one. But I have to confess that I am so
reluctant to find out everyone. I believe it will be correct in the long
run.
2. The interanl graphics part is done by Libo Feng <libo.feng@amd.com>.
3. There is a conflict between RPR and our CIM code. Please see the comment in
switching_gppsb_configurations in rs780_pcie.c.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5219 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
* SATA initialization.
* USB initialization.
* HDA initialization.
* LPC initialization.
* IDE initialization.
* SMBUS initialization.
Note:
1. I tried to add the description of every step to the code. For example,
if it is made based on rpr, section 2.4.5, I will pasted the words
from 2.4.5 to the c code. But the document I worked with might be
different with the most updated one. A new section has been added and
the 2.4.5 might be changed to 2.5.5. That migh lead to confusing. I
correct every comment if I met one. But I have to confess that I am so
reluctant to find out everyone. I believe it will be correct in the long
run.
2. I only test the SATA port 0-3. The ports 4, 5 are "PATA emulations".
I am confused about it.
3. This patch is not only about SB700. Actually it should be
SB7x0. But I dont think it is nice to change everything to
SB7x0. It is ugly, isn't it. As far as I know, they all use the
same code with revision checking. If you guys think it is
appropriate, please modify it to sb7x0.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5218 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Previously the sb600 setup was equivalent to clear_ioapic(), so that is what we will do for now.
Signed-off-by: Marc Jones <marcj303@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Permit early setup of COM2
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5097 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5089 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault).
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Edwin Beasant <edwin_beasant@virtensys.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5074 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5060 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Add appropriate Kconfig defines to provide 8mb of VGA ram allocation
Add the Kconfig defines to cover TSC calibration from TIMER2 and UDELAY setup
Two small warning removals about excessive prototyping.
Signed-off-by: Edwin Beasant <edwin_beasant@virtensys.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5059 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
from mainboards.
Some adaptations were necessary after the IOAPIC cleanup,
so this should fix the build.
Fix intel/d945gclf build, which was missing some ACPI component.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5039 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
of components. This patch is a rewrite of the generic IOAPIC setup code.
Additionally it drops the other 12 instances of IOAPIC setup code and
makes the components use the generic code.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5023 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
read32(unsigned long addr) vs readl(void *addr)
and
write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr)
read32 was only available in __PRE_RAM__ stage, while readl was used in stage2.
Some unclean implementations then made readl available to __PRE_RAM__ too which
results in really messy includes and code.
This patch fixes all code to use the read32/write32 variant, so that we can
remove readl/writel in another patch.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Set __PRE_RAM__ define per default
- Properly handle ignored (#ifdef'd out) #include lines
amd/serengeti_cheetah_fam10:
- write ACPI files to $(obj) instead of the top dir (alias $(CURDIR))
tinybootblock:
- provide a way to define code that should be added to the bootblock,
to map the entire ROM for use by CBFS
amd/model_fxx, amd/model_10xxx:
- add CONFIG_SSE
walkcbfs.S:
- eliminate the use of two registers, to make space for romcc to wiggle
amd/serengeti_cheetah_fam10:
- use the enable_rom framework. not entirely functional yet
Boot-tested on emulation/qemu-x86
Build-tested on amd/serengeti_cheetah_fam10
amd/serengeti_cheetah_fam10 fails in amdht/ somewhere, but builds
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4994 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
__ROMCC__ now means "Don't use prototypes, since romcc doesn't support them."
__PRE_RAM__ means "Use simpler versions of functions, and no device tree."
There are probably some places where both are tested, but only one is needed.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4921 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
VGA ROM can not run. After make, run
> ./cbfs/cbfstool ./coreboot.rom add ../vga_bios.rom pci1002,791f.rom optionrom
to make the final image with vga bios.
The macro vga_rom_address is out-of-date when CBFS starts play its role. it also should
be eliminated from rs690/chip.h as below. But it will cause building error on other board, which I
cant make test on.
## Index: src/southbridge/amd/rs690/chip.h
## ===================================================================
## --- src/southbridge/amd/rs690/chip.h (revision 4782)
## +++ src/southbridge/amd/rs690/chip.h (working copy)
## @@ -23,7 +23,6 @@
## /* Member variables are defined in Config.lb. */
## struct southbridge_amd_rs690_config
## {
## - u32 vga_rom_address; /* The location that the VGA rom has been appened. */
## u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
## u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
## u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
##
Don't apply above patch about rs690/chip.h before every board has been fixed.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4783 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to build, but by default all the tables that are available are built.
Make PIRQ table build for qemu.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4778 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4748 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4731 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4719 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- northbridges are done
- southbridges are done
- Intel CPUs are done, with a design that the board only has to specify
the socket it has, and the CPUs are pulled in automatically. There is
some more cleanup possible in that area, but I'll do that later
- a couple more mainboards compile:
- intel/eagleheights
- intel/jarrell
- intel/mtarvon
- intel/truxton
- intel/xe7501devkit
- sunw/ultra40
- supermicro/h8dme
- tyan/s2850
- tyan/s2875
- via/epia
- via/epia-cn
- via/epia-m
- via/epia-m700
- via/epia-n
- via/pc2500e
(PPC not considered, probably overlooked something)
All of them only _build_, but some options are probably completely
wrong. To be fixed later
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4673 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/cpu/amd/socket_F/Kconfig: Remove second occurrence of CPU_SOCKET_TYPE.
src/mainboard/amd/serengeti_cheetah/Kconfig: Add HT_CHAIN_UNITID_BASE here, since it is board specific.
src/mainboard/tyan/s289X/Kconfig: Fix typo and change APIC_ID_OFFSET to match old config.
src/devices/Kconfig: Change default value of *_PLUGIN_SUPPORT to match old config.
src/southbridge/amd/amd8131/Makefile.inc: Remove check since it was a typo, and the correct variable is checked in the parent directory.
src/Makefile:Use devicetree.cb instead of Config.lb to generate static.c.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4657 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
tested. I also addressed questions raised by Uwe:
TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
UDELAY_TSC
Are now defined as booleans in src/cpu/x86/Kconfig and can be selected in
the mainboard Kconfig. The remaining question of Uwe's is a deeper
problem:
---
We'll have to check if this works. From a quick glance
the Rumba does not have the mmx related lines (which _are_ in
Makefile.romccboard.inc, though):
crt0-y += ../../../../src/cpu/x86/fpu/enable_fpu.inc
crt0-y += ../../../../src/cpu/x86/mmx/enable_mmx.inc
crt0-y += auto.inc
crt0-y += ../../../../src/cpu/x86/mmx/disable_mmx.inc
---
We're going to need a whole variant of this standard mainboard OR
we're going to have to make (some) of the unconditional includes above
conditional.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4618 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It also brings in the vsm from v3, which was a much cleaner cut.
Over time, I hope to bring all the code back from v3. I have
some rumbas at home and want to use them.
I have a patch which comes in next that makes the rumba build.
Note that I am holding the src/*/amd/Kconfig patch until these get merged.
These have no impact on the current system.
Note that this is not complete but I want to fill in the blanks bit
by bit.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4611 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The SB600 SATA code printed that two BARs had the same address because
it didn't mask the correct number of bits in the BAR.
Functionality was not affected, but the debug output was incorrect.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4591 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
monitors.
Signed-off-by: Libra Li <libra.li@technexion.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4585 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- Whitespace fixes, remove trailing whitespace, use TABs for identation
(except in Kconfig "help" lines, which start with one TAB and two spaces
as per Linux kernel style)
- Kconfig: Standardize on 'bool' (not 'boolean').
- s/lar/cbfs/ in one Kconfig help string.
- Reword various Kconfig menu entries for a more usable and consistent menu.
- Fix incorrect comment of NO_RUN in devices/Kconfig.
- superio/serverengines/Kconfig: Incorrect config name.
- superio/Makefile.inc: s/serverengine/serverengines/.
- superio/intel/Kconfig: s/SUPERIO_FINTEK_I3100/SUPERIO_INTEL_I3100/.
- mainboard/via/vt8454c/Kconfig: Fix copy-paste error in help string.
- mainboard/via/epia-n/Kconfig: Fix "bool" menu text.
- console/Kconfig: Don't mention defaults in the menu string, kconfig
already displays them anyway.
- Kill "Drivers" menu for now, it only confuses users as long as it's emtpy.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4537 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Works on Kontron, qemu, and serengeti.
Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
tested on abuild only.
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4534 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
single core.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4415 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Major changes:
1. Separate resource allocation into:
A. Read Resources
B. Avoid fixed resources (constrain limits)
C. Allocate resources
D. Set resources
Usage notes:
Resources which have IORESOURCE_FIXED set in the flags constrain the placement
of other resources. All fixed resources will end up outside (above or below)
the allocated resources.
Domains usually start with base = 0 and limit = 2^address_bits - 1.
I've added an IOAPIC to all platforms so that the old limit of 0xfec00000 is
still there for resources. Some platforms may want to change that, but I didn't
want to break anyone's board.
Resources are allocated in a single block for memory and another for I/O.
Currently the resource allocator doesn't support holes.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4394 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
It's basically done with the following script and some manual fixup:
VARS=`grep ^define src/config/Options.lb | cut -f2 -d\ | grep -v ^CONFIG | grep -v ^COREBOOT |grep -v ^CC`
for VAR in $VARS; do
find . -name .svn -prune -o -type f -exec perl -pi -e "s/(^|[^0-9a-zA-Z_]+)$VAR($|[^0-9a-zA-Z_]+)/\1CONFIG_$VAR\2/g" {} \;
done
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4381 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
starts to play its role. Then the system hangs at HDA init. I dont know what the
VC1 is. The RPR says "Optional Features (only needed if CMOS option is enabled)"
in 5.10.2. Before I know what it is, I think it is better to skip it.
Tested on dbm690t.
Add comment from Rudolf,
"
VC is virtual channel. Its used for isochronous transfer of data to sound card.
The virtual channel guarantee "on time" delivery. In other words it sets up a
channel for data to sound card, which means that that arrivs in time and there will
be no interuptions in audio stream.
http://www.microsoft.com/whdc/connect/pci/wlp_interrupt.mspx
"
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4339 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
1. In rs690_cmn.c, mask the lower 4 bits of the BAR3. No doubt, right?
2. In rs690_pcie.c,
(1) Obviously, the mask should be 0xF, and bit 19 should be set to 1 (in comment).
In rpr 5.10.2, step 2, step 2.1 & step 2.6
(2) The dynamic buffer allocation is enabled by setting bit 11 of PCIEIND: 0x20,
instead of PCIEIND_P: 0x20.
In rpr 5.10.2, step 5. Dynamic Slave CPL Buffer Allocation
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4336 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This reverts commit eb7bb49eb5b48c39baf7a256b7c74e23e3da5660.
Stepan pointed out that "s" means string, which makes the following statement
in this commit message invalid: "Since we either have reserved space (which
we shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go."
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Luc Verhaegen <libv@skynet.be>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4335 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.
get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.
The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.
build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.
Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
a long time ago. This will make it easier to port v2 boards forward to v3 at
some point (and other things)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
- make uma_memory_base and uma_memory_size uint64_t as they may be 64bit BARs
on some platforms.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3949 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Reorder HDA (HD Audio) init:
The reordering was based on what order things happen in the BIOS
Developers guide, RPR, and SATA driver. I fixed the order of the devices
that didn't matter to clean up the change log.
1. Enable the Chip
2. Setup the SMBus registers
3. Setup the Device Registers
4. Look for Codec
5. Init Codec
The codec init was changed to match the description in the RRG pg 235.
Mem Reg: Base + 08h Bit 0. There were unneeded things happening.
Added 1ms delay to match the BKDG while waiting for BAR+0xe to set its
bits.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Tested on AMD DBM690T and AMD Pistachio by Maggie Li. Works.
Tested on Asus M2A-VM by Carl-Daniel Hailfinger. Improves the situation,
but some warnings remain.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3930 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Maggie Li <maggie.li@amd.com>
Reviewed-by: Zheng Bao <Zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
SATA port status kept returning 0x1: BAR5+po+28h
1h = Device presence detected but Phy communication not established
This patch adds logic to force 1.5g if the drive fails to communicate at 3.0g.
Signed-off-by: Dan Lykowski <lykowdk@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3864 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
is no longer 0xA0 or 0xB0. It simply assumes that will never happen.
My 500 GB Seagate Barracuda ST3500820AS triggers that corner case on the
first init after poweron.
The current code hangs forever with my drive. Fix this by rerunning the
init sequence after SATA_BAR0+6 is no longer 0xA0 or 0xB0.
Add support for SATA port 2-4 (Primary Slave, Secondary Master,
Secondary Slave).
If only the 2nd SATA port is connected and the hardware acts strangely
(contrary to documentation), it will print the error message below and
continue anyway. The official AMD asm code behaves the same way.
SATA port 0 status = 0
No Primary Master SATA drive on Slot0
SATA port 1 status = 23
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
[8 repetitions]
0x6=7f, 0x7=7f
drive no longer selected after 0 ms, retrying init
Primary Slave device is not ready after 10 tries
Activate and improve debug messages for SPEW log level.
Fix some comments.
New log messages look like this:
PCI: 00:12.0 init
sata_bar0=3020
sata_bar1=3060
sata_bar2=3030
sata_bar3=3070
sata_bar4=3000
sata_bar5=fc309000
SATA port 0 status = 23
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
0x6=a0, 0x7=80
drive detection not yet completed, waiting...
[... 281 repetitions ...]
0x6=0, 0x7=50
drive no longer selected after 2820 ms, retrying init
drive detection done after 0 ms
Primary Master device is ready after 2 tries
SATA port 1 status = 23
drive detection done after 0 ms
Primary Slave device is ready after 1 tries
SATA port 2 status = 0
No Secondary Master SATA drive on Slot2
SATA port 3 status = 0
No Secondary Slave SATA drive on Slot3
With this patch, my Asus M2A-VM boots into Linux without problems.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Zheng Bao <zheng.bao@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3845 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.
Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3839 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
The device ID of 690G is 0x791E, while the ID of 690M and 690T is 0x791F
This fixes booting on 690G.
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3816 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mainboard specific code. (And add a hook to allow other mainboards do
a similar thing if required)
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3812 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
document verification against the data sheets.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Maggie Li <maggie.li@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3811 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joe Bao <zheng.bao@amd.com>
Reviewed-by: Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3786 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Joe Bao <zheng.bao@amd.com>
Reviewed-by: Maggie Li <maggie.li@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3785 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.
Build-tested with the AMD dbm690t target.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Build-tested with the AMD dbm690t board.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3655 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marcj.jones@amd.com>
Acked-by: Marc Jones <marcj.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3643 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
We shouldn't assume the presence of a working HDA codec, so put in
a reasonable timeout of 50usecs (timeout value borrowed from the kernel).
This makes SimNow work, since apparently though the codec is
present in Simnow, it is non functional.
Signed-off-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3640 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3636 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
certainly won't build -- that comes later. I am hoping to get some
eyeballs on it for simple errors.
rs690 is next.
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3630 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code to use it. That makes the code more readable and also less
error-prone.
Abuild tested.
Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3624 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Most of the functions in SB600 are enabled except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3589 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
All the PCIe slots are enabled in this patch except power management.
Signed-off-by: Michael Xie <Michael.Xie@amd.com>
Reviewed-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3588 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
pci_write_config8.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3282 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
You can see this by executing commands like this:
grep -r pci_assign_irqs coreboot/src/*
This basically AMD/LX based boards: pcengines/alix1c,
digitallogic/msm800sev, artecgroup/dbe61, amd/norwich, amd/db800.
Also for AMD/GX1 based boards need a patch
[http://www.pengutronix.de/software/ptxdist/temporary-src/references/geode-5530.patch]
for the right IRQ setup.
AMD/GX1 based boards is: advantech/pcm-5820, asi/mb_5blmp, axus/tc320,
bcom/winnet100, eaglelion/5bcm, iei/nova4899r, iei/juki-511p.
I have two ideas.
1. Delete duplicate code from AMD/LX based boards.
2. Add IRQ routing for AMD/GX1 boards in coreboot.
The pirq.patch for IRQ routing logically consist from of two parts:
First part of pirq.patch independent from type chipsets and assign IRQ for
ever PCI device. It part based on AMD/LX write_pirq_routing_table() function.
Second part of pirq.patch depends of type chipset and set PIRQx lines
in interrupt router. This part supports only CS5530/5536 interrupt routers.
IRQ routing functionality is included through PIRQ_ROUTE in Config.lb.
Tested on iei/juki-511p(cs5530a), iei/pcisa-lx(cs5536) and also on
TeleVideo TC7020, see
http://www.coreboot.org/pipermail/coreboot/2007-December/027973.html.
Signed-off-by: Nikolay Petukhov <nikolay.petukhov@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3196 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Due to the automatic nature of this update, I am self-acking. It worked in
abuild.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
code is changed.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3052 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Check that the SMBus controller is found and stop on an error.
Clean up and add additional path through the 8111 reset functions.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Reviewed-by: Jordan Crouse <jordan.crouse@amd.com>
Acked-by: Myles Watson <myles@pel.cs.byu.edu>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3015 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
rodata.pci_driver" warnings are coming from? We were packing those
structures into a read-only segment, but forgot to mark them const.
Despite its size, this is a fairly trivial patch created by a simple
search/replace
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2891 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Painting the splash graphic is now ifdef'ed.
Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Peter Stuge <peter@stuge.se>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2836 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
to set up one of five screen resolutions (sorry no autodetection at runtime,
resolution is selected at buildtime) and displays a graphic in the right
bottom corner (splash screen).
Signed-off-by: Juergen Beisert <juergen127@kreuzholzen.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2827 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
mostly undocumented, had a broken coding style, contained lots of dead
code and had several other problems, e.g. it enabled write access to the
ROM (why?), it unconditionally enabled primary/secondary IDE (which should
have a config option) and that even _twice_ (which is um... wrong).
The new code
- has 'ide0_enable' and 'ide1_enable' config options (which actually
work) to enable/disable the primary/secondary IDE interface in
Config.lb.
- Does _not_ enable write access to the ROM (or is there some good
reason to do that? If so, it should at least have a config option).
- Contains a bit more documentation.
- Uses readable (and documented) #defines instead of hardcoded magic values.
- aaand... it actually compiles ;-) Yep, that's right. The previous code
wouldn't even build, as it hadn't been fully ported from v1 (still used
v1 functions which are simply not available in v2).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2775 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2726 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
return that skipped the disable code. This patch removes the return and
fixes the UART disable code.
The problem was that the disable code was ORing bits into the Legacy_IO
MSR causing issues with the LPC SIOs init code that would manifest as a
hang because the IO would not be decoded correctly. ANDing to clear the
bits fixes the issue.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2706 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
the new src/southbridge/amd/cs5536 code completely replaces it.
The Artecgroup dbe61 board currently uses it, but that is broken anyway
at the moment. A fix to use the new CS5536 code for it is being worked on.
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2697 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2687 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
setup as the host on USB port4. In client mode the headers remain
available. Also fixes an outb to 0x80 to use the post_code() function.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2660 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2658 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2656 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
-This line, and those below, will be ignored--
M cs5536.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2637 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
AMD GX and LX processors. This aguments the previous code, which was
very specific to the OLPC platform with general purpose support and
better integration with the VSA and CPUs.
Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2631 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
same format for all CHIP_NAME() entries in LinuxBIOS (Closes#20).
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Stefan Reinauer <stepan@linuxbios.org>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2490 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
cs5536, but I don't want to mess up the OLPC, and we really need the lx
support NOW.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
signed-off-by: Jordan Crouse
Signed-off-by: Ronald G. Minnich
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2410 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This one actualy works. You cannot just go mucking about with stuff that the VSA
has under its thumb. Bad Things happen. This does it the VSA way.
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2392 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
