The Picasso APUs advertise 23 MCA banks in the lower byte of the
IA32_MCG_CAP MSR, which is more than the 7 core MCA banks.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3e1c8ed437820b350c78b0517e6521582002ee1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The bank names were copied over from Stoneyridge, but they don't match
for Picasso.
TEST=Checked the Picasso PPR.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia86cf3874f8b16b007bad46535af6dafb776fbdd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51476
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This UPD will be used to pass VBIOS buffer pointer to FSP PEI GOP
driver.
BUG=b:171234996
BRANCH=Zork
Change-Id: I0c5d4a9d96e5c3d47e262072b689ed62e59129b3
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49866
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
PSP_SHAREDMEM_BASE made the assumption that _psp_sharedmem_dram would
only match once. With CB:49332 there are now two symbols, and it was
grabbing the wrong one.
This change makes it so we match the exact symbol. It also switches to
using awk to simplify the code.
The bootblock.elf target that is added to the list of prerequisites also
creates the bootblock.map file that gets used to extract the base
address of the _psp_sharedmem_dram symbol.
BUG=b:181354692
TEST=Boot zork past bootblock
Fixes: 82d16b150c ("memlayout: Store region sizes as separate symbols")
Suggested-by: Julius Werner <jwerner@chromium.org>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I79675bd73f964282b54bca858830e26de64037c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the UPD updating hook in early stage for customization.
BUG=b:117719313
BRANCH=zork
TEST=build,check the hook function been executed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I4954a438a51b29b086015624127e651fd06f971b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51181
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also replaces the southbridge_ prefix of the handler functions with
a handle_ prefix.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib6ea1f4e2700c508a8bf72c488043e276ba4a062
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51354
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file is common for all the AMD platforms.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I10ee600b4bcd7aaff39bfab075eb4dbc9096b435
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51299
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Printing this in both bootblock and romstage is redundant, since the CPU
family and model aren't expected to change between bootblock and
romstage entry.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Paul Menzel <pmenzel@molgen.mpg.de>
Change-Id: Id7c6aea0d8a6dac39114593584e534661faea89d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The device function is missing in the PCI device table in the PPR, but
is present in the hardware. Verified on a Mandolin board with PCO APU.
The corresponding ticket for the PPR is DESPCSOC-6667.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie91438bc905691d443ca4e7841549d1e3bca39ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso currently declares the BAR region between TOM and IO_APIC_ADDR.
This region includes MMCONF. We don't want to map any PCI BARs in this
region. This also matches what intel does.
See soc/intel/braswell/acpi/southcluster.asl for an example.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9474fd6ac75a7245b3c35151c38186e913219bb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50894
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This will also be used for cezanne. Stoney also has a similar function,
but it hard codes the scope path. I didn't have a device setup to test
if switching to this function was a no-op. So I left it.
TOM2 isn't used by any ASL, so we could remove it later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7c8f476a7735fea61a3244b97988e3ead3b42e79
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50892
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This adds the SMM finalization to Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1a2b433d92df2a76979e2e6a3d1dde996303ba78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50801
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 64d0ad347b. In the
current revision 3.001 of the PPR #56569 the register exists and the bit
definitions match.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie7a97843c3dac897f79f229b660b7e30b34eef93
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that all ACPI names are moved to the corresponding PCI devices, the
functionality in the chip code isn't needed any more.
TEST=No warnings or errors on coreboot console or in the Linux ACPI
parser.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I2d39b6d4bd53cd0ca189fb6f55ca26dab68793fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50822
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This function isn't used outside of the same compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I332046341bc7a5a499355f2147296e8c09d7e0ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50817
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Without the cast the left shift is done on a 32 bit variable that gets
extended to 64 bits afterwards which results in missing MSBs. To avoid
this, do the cast to 64 bits before the left shift.
Found-by: Coverity CID 1443793, 1443794
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7cfa5b9b6ad71f36445ae2fa35140a8713288267
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This was replaced by APM_CNT defined in src/include/cpu/x86/smm.h, so
remove the now unused definitions.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ibd25dcdb57de14fe42352f01067cedca53712d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50777
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I also removed the unnecessary #include in soc.asl.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifbd79871fd49b18f45d97f64ccd68fa96eaaebce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50572
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
With chipset_power_state filled in romstage CBMEM hooks and
GNVS allocated early in ramstage, GNVS wake source is now
also filled for normal boot path.
Change-Id: I2d44770392d14d2d6e22cc98df9d1751c8717ff3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When USE_PSPSECUREOS isn't selected, we get stuck in FSP-S.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60d0e5ab0bd9f4d76cc48d08ca05d27c60e898c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50603
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The number of data fabric MMIO registers is SoC-specific, so we need to
keep that in the SoC code. This also removes a redundant pair of
brackets and moves a loop counter declaration into the head of the loop.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8499f1c1f7bf6849b5955a463de2e06962d5de68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50638
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The exact same mechanism is used on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I3179d8ec35efa29f9bc66854c3690b389d980bba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50619
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We also want to support uCode loading on cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I6f10564c93ce72aea7ff52a8565d65d8b56452f3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Stoneyridge used CONFIG_MAX_CPUS and CONFIG_MAX_CPUS + 1 directly as
IOAPIC IDs and Picasso had Kconfig options to configure that, but still
used the common SMBus controller code that used CONFIG_MAX_CPUS as ID
for the FCH IOAPIC. If a board overrides the PICASSO_FCH_IOAPIC_ID
Kconfig option to a value that isn't CONFIG_MAX_CPUS, we'll get a
mismatch between the ID that gets written into the FCH IOAPIC register
and the ID in the corresponding ACPI table. In order to avoid that add
defines to each SOC's southbridge.c and use them in all soc/amd code.
Change-Id: I94f54d3e6d284391ae6ecad00a76de18dcdd4669
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50575
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is another common ACPI setting.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Iefecabae1d83996a9a4aaadd2a53c2432441e1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50558
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is ACPI specific config that applies to all the AMD SoCs. Stoney
doesn't currently use this, but we can add that functionality later.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0be7d917d7c5ba71347aa646822a883e2cf55743
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50557
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between stoney, picasso, and cezanne.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I5fb40e8c6817773212c5fbd66c5c06bd2bae1eda
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50556
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is common between all the chipsets.
It's also required by common/block/lpc/lpc.c.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I361dfabfe0c04667a2c112955133831a985d5cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The same functionality will eventually be needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ib49124c2c774ad3352ea2f7d8d827388029be041
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50401
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since SMM is in TSEG on the platforms which is the default, drop the
SMM_TSEG condition for the default of SMM_TSEG_SIZE.
Change-Id: I7bd965c0794efa12ea4886a55522cc5193a1d3ac
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50498
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The corresponding bit is marked as reserved in the PPR. Also there's no
BKDG for Picasso any more; the BKDG was mostly replaced by the PPR. Also
fix the style of the comment.
Change-Id: Iffdbb9e951cb140e4352ab0f198f72a71ba798dc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50495
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variable PICM was not inside GNVS region and can use a static
initialisation value.
For most AMD platforms PICM default changes from 1 to 0.
Fix comments about PICM==0 used to indicate use of i8259 PIC for
interrupt delivery.
Change-Id: I525ef8353514ec32941c4d0c37cab38aa320cb20
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49905
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize variable to 1 to indicate AC power supply.
If platform has EC it will set this correctly based on
whether plugged on the charger or not.
Change-Id: I3f834cf7563b9e512fcab34cdb7a27a9f0fd31c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49352
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
signed int should only be used when we need negative values and in those
cases the value shouldn't became negative.
Change-Id: Iefac021260ff363c76bf5cd3fe3619ea1dbabdba
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50486
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The common code gets moved to soc/amd/common/block/cpu/smm, since it is
related to the CPU cores and soc/amd/common/block/smi is about the SMI/
SCI functionality in the FCH part. Also relocation_handler gets renamed
to smm_relocation_handler to keep it clear what it does, since it got
moved to another compilation unit.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I45224131dfd52247018c5ca19cb37c44062b03eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50462
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The old name was misleading, since it doesn't disable the generation of
SMIs, but clears the status registers.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iddadbec013091c2e5993a6303e291451c3d1e7ce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50459
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The picasso SPI registers are different than the ones defined in
amdblocks/lpc.h. The BASE_ALIGNMENT has changed and the
PSP_SPI_MMIO_SEL bit has been added.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0b5a0c88c6dbb95cdbc62b949a7d30bfad1fa725
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
southbridge.c was renamed and split into early_fch.c and fch.c.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie439e746fb3dfe9ec865481a76a09eab378242bb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50458
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Triggering SMI is not part of the semantics of global_smi_enable(), so
move it to the post_mp_init handler. Even without the !acpi_is_wakeup_s3
check we don't get PSP warnings/errors during resume, so we can drop the
workaround introduced in commit 5dbe45e0f5
in this patch.
Change-Id: Id0e7723c2bb9811f80fe36c38199a01445dc1d7d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42987
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 75f6ab35ff.
Reason for revert: The 5.4 Linux kernel is not configured for AMDI0030. This causes an issue where the WP pin is not recognized.
BUG=b:179320024
TEST=WP pin shows up properly in crossystem after reverting this change.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I0850fd085b5ee70522752633900f69d4d3732321
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50052
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The same functionality is needed on Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I40f9d2fe7d144e94369a417225bcca0a299d1f45
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
No PCI or PNP functions are used in here.
TEST=Timeless build results in identical image.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I577e2ecdc59dbd09e739ae800cbe021168a34812
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50399
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPI S3 is a global state and it is no longer needed to
pass it as a parameter.
Change-Id: Id0639a47ea65c210b9a79e6ca89cee819e7769b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50360
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need the same functionality for cezanne.
TEST=Boot ezknil
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I0800c662bb473eb571c74e76a8247298f534b53f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
add UPD for RV2 USB3 phy setting adjust.
Note: it only for RV2 silicon and not available for RV/PCO.
Usb 3.1 PHY Parameters:
1. RX_EQ_DELTA_IQ_OVRD_VAL
-Override value for rx_eq_delta_iq. Range 0-0xF
2. RX_EQ_DELTA_IQ_OVRD_EN
-Enable override value for rx_eq_delta_iq. Range 0-0x1
3. Override value for rx_vref_ctrl. Range 0 - 0x1F
4. Enable override value for rx_vref_ctrl. Range 0 - 0x1
5. Override value for tx_vboost_lvl: 0 - 0x7.
6. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
7. Override value for rx_vref_ctrl. Range 0 - 0x1F
8. Enable override value for rx_vref_ctrl. Range 0 - 0x1
9. Override value for tx_vboost_lvl: 0 - 0x7.
10. Enable override value for tx_vboost_lvl. Range: 0 - 0x1
BUG=b:175192931
TEST=Build/verify the valule will been apply on dirinboz
Change-Id: I1d5f69e840952cc5171af1ce8597628d1bede5cb
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50240
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was the only I/O base address in Kconfig, no board changed it and
if a board changed it, it needs to make sure that it won't overlap with
other I/O resources, so just use the same value as constant in the
define instead of the value from Kconfig. Also remove the PICASSO_
prefix from ACPI_IO_BASE.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I7ea62f1101ddefa8785da92de5ba2aaf7945694a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Add new Kconfig symbols to mark FSP binary as x86_32.
Fix the FSP headers and replace void pointers by fixed sized integers
depending on the used mode to compile the FSP.
This issue has been reported here:
https://github.com/intel/FSP/issues/59
This is necessary to run on x86_64, as pointers have different size.
Add preprocessor error to warn that x86_64 FSP isn't supported by the
current code.
Tested on Intel Skylake. FSP-M no longer returns the error "Invalid
Parameter".
Change-Id: I6015005c4ee3fc2f361985cf8cff896bcefd04fb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The `_MASK` macros should be using the corresponding `_SHIFT` macros.
Change-Id: I78370e17d2396f77ab820771f93cf15957bcf674
Found-by: Coverity CID 1445928
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso has 32 configurable GPEs, not only 28.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia156e64e7a69764776f3af7597b680b8ddd4e650
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
There's no dedicated south bridge any more and now we have integrated
FCHs in the SoCs.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I19126da09f034f51b134f8d6ae2006f57fac1b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50209
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
commit 3f2467032e changed this in the APCI
code itself, but the change in the ACPI byte code generation in
pcie_gpp.c was missed and this patch fixes that.
TEST=Fixes the regression on Mandolin.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I60de29581296101947336f70343d6206af97e307
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This define was copied over from Stoneyridge, but isn't present on
Picasso and newer.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ideb144c4bff441cf043a647b3f44a65691038eba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
It's a static value that is neither referenced from SMI handler
nor needs to be updated on S3 resume path.
Change-Id: Iab2741242b0e2df8a0429ffaad270ce21882588c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The function to get the PSP mailbox address is the same on Picasso and
Cezanne, so move it to the common PSP generation 2 code. The function is
only used in the same compilation unit, but it can't be marked as static
due to the function prototype in amdblocks/psp.h that is still needed
for Stoneyridge.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ieea91ef76523d303f948d29ef48e3b2e56293f26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50151
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
If MSR_PSP_ADDR is uninitialized, it's all zeros and not all ones.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iecd3039f63f9d0cb75fe3cb37aee92ba65bbbb50
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
TEST=Checked that the MSR is the same for Stoneyridge, Picasso and
Cezanne.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id15715ed1c17f4fc475985dcb1c31a83713ee65c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50149
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
acpi_is_wakeup_s3() is defined in acpi/acpi.h
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I53916cd15bb28484eb06be4d43f26152de159391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50125
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also move the fch_* functions in the header file in the order they get
called.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I9b6c6ad744b26f8488015c38a84d7e21c7d7687a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50093
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Only specify the type of MMCONF_BASE_ADDRESS and MMCONF_BUS_NUMBER once.
Change-Id: Iacd2ed0dae5f1fb6b309124da53b3fa0eef32693
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50032
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow to override the RFMUX setting if the board does not use PD chip.
BUG=b:177389383
BRANCH=none
TEST=Build; Check the USB_PD port been override.
Change-Id: Idd559b67668846805005a6e00f5a84655310f348
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49932
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For builds with MAINBOARD_HAS_CHROMEOS=y but CHROMEOS=n, there
is reduced dsdt.aml size and reduced GNVS allocation from cbmem.
More importantly, it's less error-prone when the OperationRegion
size is not hard-coded inside the .asl files.
Change-Id: I54b0d63a41561f9a5d9ebde77967e6d21ee014cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49477
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a common place where acpigen generates these,
so the declarations for the OperationRegions should be
centralized too.
Change-Id: I772492ca9e651b60244c565d1e926dc2ad33cfd8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49795
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI0 MMIO window was defined between TOM and 4 GiB. This was
overlapping with the FCH MMIO devices. The first MMIO device after TOM
is the FCH IOAPIC.
This wasn't causing a problem for linux other than the fact that
/proc/iomem showed all the MMIO devices under the PCI root bridge.
On Windows this was causing all the MMIO devices to have conflicting
resource errors.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux and verify peripherals all work. Boot windows and
verify the i2c controllers show up. The GPIO controller still has a
problem related to power.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idc409f1318e6da5a693ccbb3da74aafd13f1e058
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49853
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Zork platform was not booting with MCACHE enabled since psp_verstage
had following issues with MCACHE.
Fix all the issues and re-enable MCACHE for Zork.
* psp_verstage should call vboot_run_logic, not verstage_main.
vboot_run_logic calls after_verstage which handles RW MCACHE build.
* It should avoid low-level apis for cbfs access.
cbfs_map will build RO MCACHE if it's the first stage, while other
low-level apis won't.
* It should call update_boot_region before save_buffers
MCACHE should be transferred to x86 so we should build it before
calling save_buffers
BUG=b:177323348
BRANCH=none
TEST=boot Ezkinil
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I08c5f8474600a06e3a08358733a38f70787e944a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49468
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is not the correct way to specify the FixedDMA devices. I'm
removing for now since it adds confusion.
BUG=none
BRANCH=zork
TEST=Boot zork to linux and make sure UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I17b9c8dbe4f9c4b64ee1bd69cb9b30998e727632
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The default case is only needed to make the compiler happy.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Idf54e7128f9e9d96f15ac7ab121f22621e033fac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49941
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The empty string causes an undetectable build error.
Filter out the board which doesn't define this variable.
A great odds that the reason is the board doesn't set a
valid ROM size.
Change-Id: Iade1961460285acdec245c553c7b84014c30c267
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Use the same variable name as soc/intel to implement a common
_PIC method at top-level ASL.
Change-Id: I48f9e224d6d0101c2101be99cd18ff382738f0dd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Cezanne doesn't have eSPIx00034 register define in PPR. Currently only
Picasso need this option.
Change-Id: Icb8e8a1a59393849395125108bfaa884839ce10f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Do not pass ACPI S3 state as a parameter, by locally
calling acpi_is_wakeup_s3() compiler has better chance
for optimizing HAVE_ACPI_RESUME=n case.
Test for acpi_s3_allowed() is already included in the
implementation of acpi_is_wakeup_s3() and is removed
as redunandant.
For ramstage, acpi_is_wakeup_s3() evaluates to
romstage_handoff_if_resume().
Change-Id: I6c1e00ec3d5be9a47b9d911c73965bc0c2b17624
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49838
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This matches the _HID used in the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify peripherals still work
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ieb441696cbe67a772632990347c12d1d15cfaf13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
This does change the fixed clock used by linux from 133 MHz to 150 MHz.
BUG=none
BRANCH=zork
TEST=boot linux and verify touch screen and touchpad still function
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I37fcb4a4f0148f4843d026902d694c03aeed3c3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This is the new _HID that was used for Raven. It matches the _HID used
by the picasso UEFI bios.
BUG=none
BRANCH=zork
TEST=boot linux and verify UART still works
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I138cb445c84997f4a4006cbb4f6617dac25a61b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Change the hardcoded location of microcode patches to using
FIRMWARE_LOCATION.
Change-Id: Iae3d159aa5413a416c54935ab7a809d0f4ff776f
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49734
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add UPDs for eDP power sequence adjust
all pwr sequence numbers below are in uint of 4ms.
BUG=b:171269338
TEST=Build; Verify the UPD was pass to system integrated table; measure
the power on sequence on dalboz
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I6eceebd1c3f522e6a8dfaadc487a590107ae3131
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48864
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If a _HID/_CID are not unique, we need to add a _UID field to
differentiate the objects.
BUG=b:175146875
BRANCH=zork
TEST=Boot linux, dump ACPI table and verify UIDs are unique
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Icd2ccede2b6c2e332157e2eeca89fba14a46b360
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Create uniform logging for the (unlikely) case of a CBMEM
entry disappearing.
Change-Id: I7c5414a03d869423c8ae5192a990fde5f9582f2d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
To implement some common helpers for CBMEM_ID_POWER_STATE
allocation use the same struct name as soc/intel.
Change-Id: I5d2c06a2a7b4602374562197c99b0ad7bcf50afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
There is no reason to duplicate the table.
BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ief714266cdb1b4f89afd0d9e50238200b87687ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
I think it makes the code a bit cleaner.
BUG=b:170595019
BRANCH=zork
TEST=boot zork with pci=nomsi and verify /proc/interrupts didn't change
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ib5e8e5b690d9612e8ae257f5d15c25122e1c91e6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Each bridge can only have one device.
BUG=b:170595019
BRANCH=zork
TEST=none
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7e476221dfcabc841cc1ed4bc4b1175c0652dcfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The dummy AOAC parent device was nice because it grouped all the AOAC
devices. Unfortunately windows doesn't like this dummy device and causes
"Not Found" errors. This change moves the AOAC devices to the actual
devices that use them.
BUG=b:175146875
TEST=Boot linux and make sure power resources are enabled/disabled.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Idd4a94baa4358ee4f15c461a5bb54ca925023a13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug, so there is no need to specify a MMIO address for the early EHCI
BAR configuration.
Change-Id: I5e904c160c68805a8606a8b2d1ab4fb6172066e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Picasso doesn't have any EHCI controllers, so it can't support EHCI
debug.
Change-Id: I2dae22c0db294f5334d9796d90f432d6c8d304df
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The SoC code has in implicit dependency on this option, so select it in
the SoC code instead of the mainboard code.
Change-Id: Iea908c142f4a94a107cf74a31d9f5e29668d4b5b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The layout of GNVS has expectation for a fixed size
array for chromeos_acpi_t. This allows us to reduce
the exposure of <chromeos/gnvs.h>.
If chromeos_acpi_t was the last entry in struct global_nvs
padding at the end is also removed.
If device_nvs_t exists, place a properly sized reserve for
chromeos_acpi_t in the middle.
Allocation from cbmem is adjusted such that it matches exactly
the OperationRegion size defined inside the ASL.
Change-Id: If234075e11335ce958ce136dd3fe162f7e5afdf7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add code to collect all required information and generate ACPI CRAT
table entries. Publish tables generated from cb, rather than use the
tables created by FSP binary.
BUG=b:155307433
TEST=Boot trembyle and compare coreboot generated tables with tables
that FSP published previously.
BRANCH=Zork
Change-Id: If64fd624597b2ced014ba7f0332a6a48143c0e8c
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This struct isn't used anywhere else, so there's no need to name it.
Change-Id: I22eda07f14096d2b7400e6ab715641ffd68fbc08
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49444
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are no longer really useful. We can also enable Power Resource
ACPI debug in the kernel if we want these messages.
BUG=none
BRANCH=zork
TEST=emerge-zork and verify debug messages are no longer posted
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I936e816266825f1c59377c2e079ffe1a5188838c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This will result in less code duplication when the common AMD SoC UART
support gets used for more AMD SoCs.
Change-Id: Id1786f32324de3e3947d792c599e2019705c5a85
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49373
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This partially reverts commit 6f8f9c969b
by moving CONSOLE_UART_BASE_ADDRESS back to the SoC-specific code, since
the number and base addresses of UARTs turned out to be rather SoC-
specific. The help text for the AMD_SOC_CONSOLE_UART option also
contained those base addresses, so remove that as well.
Change-Id: I01211ec62421c56f22ed611313d6245a05bdea67
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49372
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The UARTs in the Picasso SoC are memory mapped, but there is also some
hardware support that isn't used by any board to make the UARTs behave
like the ones found on legacy x86 machines from the 90s.
In the MMIO mode the MMIO address of the UART controller is passed to
the OS via ACPI. The OS expects the base clock of the UART controller to
be 48MHz (see the cz_uart_desc struct in drivers/acpi/acpi_apd.c and
drivers/tty/serial/8250/8250_dw.c in the Linux kernel) in this case. It
is also possible to enable additional decodes from four 8 byte legacy
I/O locations used for serial ports to the different UART controllers,
which doesn't disable the MMIO access though. The legacy I/O-mapped
serial ports are usually expected to have a base clock of 16*115200Hz
which the hardware can also provide to the UART's baud rate generator.
So there are two possible valid configurations to use the UARTs; either
MMIO access in combination with a 48MHz base clock or the legacy I/O
decode with a ~1.8MHz base clock.
The existing code unconditionally generates ACPI objects for all enabled
UARTs, so those shouldn't be put into legacy mode and switching the base
clock to ~1.8MHz was only done in the case that the UART was used as
coreboot console UART which still used the MMIO access, but the lower
base clock. Since no board even selects this option and it's rather
invasive to properly implement this feature, just drop the corresponding
broken code.
TEST=SoC UART console still works on Mandolin.
Change-Id: I26fa8fdfc781b583ba56ac4dbcbbfb6100e84852
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49371
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is causing boot errors on zork:
coreboot-v1.9308_26_0.0.22-18590-g4598a7bed945 Wed Dec 16 17:32:25 UTC 2020 bootblock starting (log level: 8)...
Family_Model: 00820f01
PSP boot mode: Development
Silicon level: Pre-Production
PMxC0 STATUS: 0x800 BIT11
I2C bus 3 version 0x3132322a
DW I2C bus 3 at 0xfedc5000 (400 KHz)
FMAP: area FW_MAIN_B found @ 312000 (3137280 bytes)
ASSERTION ERROR: file 'src/commonlib/bsd/cbfs_mcache.c', line 106
BUG=b:177323348
TEST=Boot ezkinil to OS
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I1f2bbdd9c87c4efdfb0042e90a20b489fa0efced
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.
Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.
BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly
generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.
BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The set_resources field in the root_complex_operations struct shouldn't
be NULL, but a pointer to noop_set_resources instead. This fixes the
error "PCI: 00:00.0 missing set_resources".
Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Move CPUID definitions out of msr.h into new cpuid.h header.
BUG=b:155307433
BRANCH=Zork
Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
GEVENT_MASK should cover all GEVENT pins, but was missing
SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8.
Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.
The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.
Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We took the assumption the APCB(0x60) and APCB_BK(0x68) are the
same file. For picasso, they are. For later programe, they are not.
Change-Id: Idea7847691c2b511b489c306f04a8cb8945fd057
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add new helper function to support reading a register from the data
fabric.
BUG=b:155307433
TEST=Boot trembyle with If64fd624597b2ced014ba7f0332a6a48143c0e8c and
confirm read values match expected values.
BRANCH=Zork
Change-Id: If0dc72063fbb99efaeea3fccef16cc1b5b8526f1
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47726
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The FSP integration code needs this function to be present. It's not
supposed to be called, but if it is, it'll print an error and call the
SoC's cold reset function.
Change-Id: I15f2622d9d9d0f22e3cf8e6283b578f5933b1a9f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The actual UART initialization code will be factored out in follow-up
commits.
Change-Id: Ie4ddf1951b230323c5480c4389376c62dd74b0e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
all-y will also add a compilation unit to the verstage on PSP build that
runs on an ARM code instead of a x86 one. At the moment Cezanne doesn't
have verstage on PSP support yet, but since it'll eventually land it
doesn't hurt to already add the comment now.
Change-Id: I15fb66e796cab48737ba5ac463c4c973794a005a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since aoac gets also linked into verstage on PSP, all-y can be used
here.
Change-Id: I74607123ebc8115aa7efbb9a364d9632372b52cb
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48506
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FCH_AOAC_UART_FOR_CONSOLE will only be used in the code if
PICASSO_CONSOLE_UART is selected, so only check if it's a valid value in
this case.
Change-Id: I103dd8d469a084c7dc7dcf55175b1f77f900adc5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48485
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The register name and the name of one bit are slightly different, but
have the same functionality.
Change-Id: I025f1c7b2c7643afe245f2275ae6ef45e64b951a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48487
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Stoneyridge some PCI registers were accessed in this compilation
unit, but on Picasso this is no longer the case.
Change-Id: Ifbf65f9724a14d4847af98930759c865453775b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48486
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The two Socs don't use this functionality and biosram.c in the common
code is the only place where those defines are used, but it doesn't
include soc/iomap.h and has its own definitions instead.
Change-Id: I973df4ab39a94e89ea2ed6ffb639c5a85b8df456
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The number at the end actually means the max MiB/s. So 52 MHz clock @ 8x
data width, sampled on each clock edge = 104 MiB/s.
According to JEDEC Standard No. 84-B51A (JESD84-B51A), maximum bandwidth
& clock frequency for various MMC bus speed modes are (at x8 bus width):
MMC_Legacy: 26 MB/s at 26 MHz Single Data Rate (SDR)
MMC_HS: 52 MB/s at 52 MHz SDR
MMC_DDR52: 104 MB/s at 52 MHz Dual Data Rate (DDR)
MMC_HS200: 200 MB/s at 200 MHz SDR
MMC_HS400: 400 MB/s at 200 MHz DDR
BUG=b:159823235
BRANCH=zork
TEST=build zork
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I7818d8cb5ed5974c60a900477a0aa2ecc904db0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48309
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due the location of X86_RESET_VECTOR, the anchor point
for linking the bootblock is at the end, which equals
ROMSTAGE_ADDR.
Change-Id: I2d25911582393c9a10fd3afa1a484eda2604d95a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The architectural requirement is for the address to be
located at the end of bootblock -0x10 bytes, so the
definition was redundant with other Kconfig variables.
Change-Id: Ia014470cfadf0b401a12a2de6dce3b1fc1862137
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The ramstage parts gets renamed to fch.c and the bootblock one to
early_fch.c. No functionality from the old southbridge file is used in
romstage, so don't link it there.
Change-Id: I7ca3b5238c3b841191dd0459996b691edd76fbf8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Replace sb prefix with fch prefix, since those are all FCHs and no south
bridges any more. Verstage on PSP uses the I/O access mechanism instead
of the MMIO one, so keep a separate function for that, but also move it
to the common mmio_util file to have them all in one place.
Change-Id: I47dac9ee3d9e27f7b7a5fddab17cf4fc10de6c3e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48435
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
ACPIMMIO_DECODE_REGISTER_04 is the definition in the common ACPIMMIO
code block that actually gets used. Also fix the indentation of the
ACPIMMIO register decode defines in the common code.
Change-Id: Ib2c460541be768fe05d8cc3d19a14dbd9c114a45
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now pci_domain_ops in chip.c can also be marked as static.
Change-Id: Ia92b778a5882d991b391dc29aeee0a5615677913
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48315
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since config.c also gets linked into verstage on PSP and not only into
the stages running on the x86 cores, use all-y instead of adding
config.c to all classes separately.
Change-Id: Icacb13e73e80e6f3d8c2141784702fb895daf7db
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding MSRs of all AMD family 17h and 19h CPUs/APUs match the
code.
Change-Id: I29cfef5d8920c29e36c55fc46a90eb579a042b64
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The CPU core clock divisor ID needs to be in the range from 8 to 0x30
including both numbers.
TEST=Compared with Picasso's PPR #55570
Change-Id: Ie5ee342d22294044a68d2f4b2484c50f9e345196
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIO controller on Picasso has 4 banks of GPIOs with a size of 256
bytes each, so increase the reserved size to match the hardware.
Also replace the base GPIO address with the corresponding define.
Change-Id: I453f1c531d612a0e82ee0d91762fec6cdb2b8556
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The functionality in smi_util applies for all 3 AMD SoCs in tree. This
patch additionally drops the HAVE_SMI_HANDLER guards in the common
block's Makefile.inc, since all 3 SoCs unconditionally select
HAVE_SMI_HANDLER in their Kconfig and smi_util doesn't use any
functionality that is only present when that option is selected.
Change-Id: I2f930287840bf7aa958f19786c7f1146c683c93e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
IASL version 20180927 and greater, detects Unnecessary/redundant uses of
the Offset() operator within a Field Unit list.
It then sends a remark "^ Unnecessary/redundant use of Offset"
example:
OperationRegion (OPR1, SystemMemory, 0x100, 0x100)
Field (OPR1)
{
Offset (0), // Never needed
FLD1, 32,
Offset (4), // Redundant, offset is already 4 (bytes)
FLD2, 8,
Offset (64), // OK use of Offset.
FLD3, 16,
}
We will have those remarks:
dsdt.asl 14: Offset (0),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
dsdt.asl 16: Offset (4),
Remark 2158 - ^ Unnecessary/redundant use of Offset operator
Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file()
to cbfs_map() and cbfs_load() respectively. This is supposed to be the
start of a new, better organized CBFS API where the most common
operations have the most simple and straight-forward names. Less
commonly used variants of these operations (e.g. cbfs_ro_load() or
cbfs_region_load()) can be introduced later. It seems unnecessary to
keep carrying around "boot" in the names of most CBFS APIs if the vast
majority of accesses go to the boot CBFS (instead, more unusual
operations should have longer names that describe how they diverge from
the common ones).
cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly
reap mappings when desired. A few new cbfs_unmap() calls are added to
generic code where it makes sense, but it seems unnecessary to introduce
this everywhere in platform or architecture specific code where the boot
medium is known to be memory-mapped anyway. In fact, even for
non-memory-mapped platforms, sometimes leaking a mapping to the CBFS
cache is a much cleaner solution than jumping through hoops to provide
some other storage for some long-lived file object, and it shouldn't be
outright forbidden when it makes sense.
Additionally, remove the type arguments from these function signatures.
The goal is to eventually remove type arguments for lookup from the
whole CBFS API. Filenames already uniquely identify CBFS files. The type
field is just informational, and there should be APIs to allow callers
to check it when desired, but it's not clear what we gain from forcing
this as a parameter into every single CBFS access when the vast majority
of the time it provides no additional value and is just clutter.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At least a part or the remaining definitions in the soc-specific smi.h
files are also common, but those have to be verified more closely.
Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The patch also rewrites the bit definition using shifts to make them
easier to read.
The older non-SoC chips can probably also use the new header file, but
for this patch the scope is limited to soc/amd, since the older non-SoC
chips don't use the SMBUS controller code in soc/amd/common.
TEST=Timeless build for amd/mandolin and amd/gardenia doesn't change.
Change-Id: Ifd5e7e64a41f1cb20cdc4d6ad1e675d7f2de352b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The code on Stoneyridge didn't set the FCH_AOAC_TARGET_DEVICE_STATE bits
to FCH_AOAC_D0_INITIALIZED like the code for Picasso does, but that is
the default value after reset for those bits on both platforms.
Change-Id: I7cae23257ae54da73b713fe88aca5edfa4656754
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The register locations and bit definitions are the same for Stoneyridge
and Picasso. Since not all devices are present on all SoCs, keep those
numbers in the SoC-specific code.
Change-Id: Ib882927e399031c376738e5a35793b3d7654b9cf
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Now that the initial version of the Picasso FSP binaries have finally
landed, we can set the default paths to point to them now.
Change-Id: Ib2241cc90c7113e0c3de4409e08b9ae1f4c2f51e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42472
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The numbers in the array are unsigned, so use an unsigned type there.
Change-Id: I9a85594de0e4c53db965ab84239f19eb46432348
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The power_off_aoac_device function clears the FCH_AOAC_PWR_ON_DEV bit,
so the comment should be that it powers off the devices.
Change-Id: Ia5e5d80b1977c3f53fcd9cf6d48bdb59045dfc3c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in
the corresponding SoC code, so remove it from the SoC's Kconfig and
reanme it in the mainboard's Kconfig to MANDOLIN_LPC.
Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The corresponding functionality in the SoC's Makefile.inc was removed in
commit ef3395d990
Change-Id: Iba84d9deb155ce314b3a3588781752b83a21486b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There's no need to have the bootblock in its own sub-directory, so move
it to each SoC's main directory to avoid clutter. This makes soc/amd
more consistent with the coreboot code base in src/northbridge,
src/southbridge and src/soc with the exception of src/soc/intel.
Change-Id: I78a9ce1cd0d790250a66c82bb1d8aa6c3b4f7162
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47982
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There will be more files added to the common non-CAR Makefile.inc, so
use an ifeq statement there.
Change-Id: I1f71954d27fbf10725387a0e95bc57f5040024cc
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47880
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
AMD family 17h and newer don't use cache as RAM, since the RAM is
already initialized by the PSP when the x86 cores are released from
reset. Therefore they use a different linker script as the rest of the
x86 chips in coreboot do. Since there will be support for newer
generations than Picasso will be added, move those linker scripts from
soc/amd/picasso to soc/amd/common/block/cpu/noncar.
TEST=Timeless build of amd/mandolin and amd/gardenia result in identical
binaries.
Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Different models within family 17h have different PCI IDs for their PCIe
GPP port and internal bus devices.
Change-Id: I386df908ce5451b4484be2a2e4a9018c3d47d030
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47677
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Different models within family 17h have different PCI IDs for their data
fabric PCI devices.
Change-Id: I44f8d32c950710e962dc519495b08c92f357ed20
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
SOC_AMD_COMMON needs to be selected to be able to select
SOC_AMD_COMMON_BLOCK which only includes the Kconfig files from the
function block sub-folder. Removing SOC_AMD_COMMON_BLOCK and the
corresponding Kconfig file and make SOC_AMD_COMMON include all Kconfig
files from the sub-folders simplifies this a bit.
Change-Id: I9068d57a80bdc144e73d2b8c00e7b2cae730d4b6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change drops the inclusion of entry16.ld and reset16.ld and
instead adds the content of those files directly in memlayout_x86.ld
in amd/picasso. This is done to allow the work for top-aligning
bootblock to happen independent of Picasso layout. Once that is
complete, Picasso layout can be re-evaluated to see if it can make use
of the common bootblock linker file includes.
TEST=Verified that coreboot.rom generated using --timeless is the same
with and without this change for trembyle.
Change-Id: Ib1218b24a06d0f69b856fb21458a6183fd21fcbc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
In the file uintptr_t that is defined in stdint.h and struct device that
is defined in device/device.h are used, so include them directly to
avoid having to rely on them being included in the file that includes
this header file.
Change-Id: I9893619924d45e5690a5cfc65252ace4cb7f1486
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This also reduces the difference to the equivalent file from
stoneyridge.
Change-Id: I3fc44f057047995cc4054a85a1bb69427aa28531
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47581
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SMU mailbox access code from Picasso can be reused in the next
generation, so factor out the code to soc/amd/common/block/smu. Since
the mailbox register offsets in the indirect address space, the number
of arguments and the message IDs don't always match between different
devices, keep those in the soc-specific directories.
Change-Id: Ibaf5b91ab35428e4c771e7163c6e0c4fc50371e7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This prototype will be used outside of soc/amd.
Change-Id: Icc69cf8a910764b27edf64f0f527b8f6a9013121
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45813
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The RV1 CPUID is already in the cpu.h file, but was still missing from
the CPU table in cpu.c.
Change-Id: Iad78cbe933b40e946d421e4c93e523f9e31f1089
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
On picasso's psp_verstage, the vboot hash is being calculated by
hardware using relatively expensive system calls. By increasing the
block size, we can save roughly 150ms of boot and S3 resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I6642073357327811b415dcbcad6930ac6d2598f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46903
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increasing the vboot hash buffer size greatly speeds up the SHA
calculations. Going from a standard 4k buffer to a 36k buffer
takes ~150ms of the boot and resume time.
TEST=Build & boot see that boot time has decreased.
BRANCH=Zork
BUG=b:169217270 - Zork: SHA calculation in vboot takes too long
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibca868ad7be639c2a0ca1c4ba6d71123d8b83c92
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46902
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The amdfwtool is not available at the beginning of the
building. So it may have error if it is missing.
Change-Id: Id4db70986755cef8e98877c4e92841b25ced5452
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Since the mainboard Kconfig is sourced before the SoC one, it would
still be possible to override this setting at mainboard level, even
though that shouldn't be needed. The maximum CPU count for Picasso is 8,
since the chips have only up to 4 cores with up to two threads each.
Change-Id: I53449b8fa73c5d13e6ea77bee6eed8896b7d3ec3
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47205
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize timestamp table with data from psp_verstage on bootblock.
PSP keeps its own timestamp and pass it in transfer_buffer. However PSP
timestamp and TSC may be out of sync so we can't just merge two tables
without modification.
info->timestamp contains PSP's clock value (in us) when x86 processor
released and base_timestamp contains TSC value when bootblock is
started. The time between x86 release and bootblock entry should be very
short so we can think those two happened at the same time and use them
for sync.
In some cases there will be underflow in timestamp entries but cbmem
utility can handle wrap-over in entries. Few timestamp values including
1st timestamp can be very large but we can still get the time spent on
boot without any problem.
BUG=b:159220781, b:167148121, b:171422583
BRANCH=zork
TEST=boot to kernel, run 'cbmem -t' and check verstage timestamps are
included in the result.
Change-Id: I5e89bb54f478153fb40ba51b5ab61fa20af3b99a
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Zork(picasso) platform we run verstage on the PSP. It has its own
timer, but the frequency is not matched with TSC.
To ease the work to merge timestamps from the PSP and TSC, add a layer
around tsc to have microsecond granularity for timestamp table. PSP
already records timestamp in microseconds.
BUG=b:159220781
BRANCH=zork
TEST=build, flash and boot, check timestamps are correct
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifced4a84071be8da547e252167ec21cd42f20ccc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46058
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of having the same linker layout for the transfer buffer between
the x86 & PSP linker layout scripts, put the common layout into a file
shared between the other linker scripts.
BUG=None
TEST=Boot zork board, verify the buffers are aligned.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ib9d9d8b046bc9e9e7a4ee939324960bfc44c3508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Replace the initial bl_errorcodes_public.h (a temporary, minimal
version) with the full version released by AMD.
BUG=None
TEST=Build
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I82585c74d74139a96419b9bffe1df3b8c344eb5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Align coreboot's PSP MboxBiosCmdSmmInfo setup to how AGESA's PSP
library was implemented. The trigger address must be an SMI trigger
register. Assign one of the reserved triggers to the PSP.
The #define of SMITYPE_PSP 33 is still correct and is intentionally
unmodified.
This patch should be innocuous as the system doesn't currently support
SMI-based features of the PSP. The call only exists so the PSP will
honor a mailbox command during S3 suspend.
BUG=b:171815390
TEST=Run SST on Morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I74029271a522a4f23e54fd76f99a8e3eb0dd4d55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46854
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To verify the consistency, see if timeless builds with and without
this patch result in identical coreboot.rom files.
BUG=b:154032833
TEST=Build & boot on mandolin
Change-Id: Icae73d0730106aab687486e555ba947796e5e757
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42859
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Include platform.asl to link acpi methods for _INI, _WAK, and _PTS to
correctly enable backlight in OS for zork.
BUG=b:158087989
BRANCH=Zork
TEST=check backlight during reboot and suspend
Signed-off-by: Josie Nordrum <JosieNordrum@google.com>
Change-Id: I702f807a5907d85d083295cf339ba9d31b246627
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove all typedefs and cleanup references to all structs and enums.
BUG=b:159061802
TEST=Boot morphius to shell.
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I403075e18886b566f576d9ca0d198c2f5e9c3d96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The Picasso build describes the DRAM region where the PSP places
our bootblock. Rather than relying on Kconfig values, make the build
more robust by using the actual size and target base address
from the boot block's ELF file.
Sample output of "readelf -l bootblock.elf" is:
------------------
Elf file type is EXEC (Executable file)
Entry point 0x203fff0
There is 1 program header, starting at offset 52
Program Headers:
Type Offset VirtAddr PhysAddr FileSiz MemSiz Flg Align
LOAD 0x001000 0x02030000 0x02030000 0x10000 0x10000 RWE 0x1000
Section to Segment mapping:
Segment Sections...
00 .text .data .bss .reset
------------------
We can extract the information from here.
BUG=b:154957411
TEST=Build & boot on mandolin
Change-Id: I5a26047726f897c57325387cb304fddbc73f6504
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46092
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP does not accept the SmmInfo command during a resume so
remove the call.
BUG=b:163017485
TEST=Run SST on trembyle, verify error message goes away
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ib75a20c9594bc331aa7abf77be95196085a3dbc6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44398
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the base address. This should have no noticeable effect,
as SMC_MSG_S3ENTRY accepts no arguments and doesn't return. The
argument writes were not getting to any target.
BUG=b:171037051
TEST=Run SST on morphius
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Ie3402f743cf7d4f4f42b8afa3e8b253be4761949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Replace vb2ex_hwcrypto_rsa_verify_digest with vb2ex_hwcrypto_modexp.
Instead of using hardware acceleration for whole RSA process,
acclerating only calculation part(modexp) increases transparency
without affecting boot time.
BUG=b:169157796
BRANCH=zork
TEST=build and flash, check time spent on RSA is not changed
Change-Id: I085f043bf2014615d2c9db6df0b7947ee84b9546
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45987
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To remove the xhci0_force_gen1 and use usb3_port_force_gen1 instead.
The xhci0_force_gen1 is used for force all port on xhci0 to USB3 GEN1.
Now variant can use the usb3_port_force_gen1 to customize which port
it needs to limit.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: If5f0c1f22d8c98c4461f09d074bf082c340b14d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add UPD usb3_port_force_gen1 for support USB3 port force to gen1.
BUG=b:167651308
BRANCH=zork
TEST=Build, verify the USB3 speed in gen1
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I896c185988c3ea5dbdd72957b363ebdaa2747cff
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45333
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The PSP will now pass us data on the PSP boot mode and the production
silicon level. Print these values out to save in the log.
These definitions are in a vendorcode include directory that was
previously only included in verstage. Add the include directory
to all stages.
BUG=b:170237834
TEST=Build & Boot - See values printed.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iee87413d1473786cf0e148a8088d27f8d24a47a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46113
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
The transfer buffer check had gotten large enough to deserve a function
of its own, so break it out.
BUG=None
TEST=Build
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idf46f8edb6b70c63f623522e2bcd2f22d6d4790b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46112
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:169199392
TEST=Corrupt vboot signature to force an error, see that the system
halts instead of rebooting forever.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I949f94e78d25720f6cd7e81de8d030084e267f29
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45964
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
psp_verstage uses separate printk implementation, which does not include
code to add console output to cbmem.
Add cbmemc_init and cbmemc_tx_byte to add console output to cbmem.
BUG=b:159220781
TEST=build
BRANCH=zork
Change-Id: I63ba5814903565c372dbeb50004565a371dad730
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46059
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The PSP bootloader version 0.08.0B.7B added support for the Mod Exp
svc call.
BUG=b:169157796
BRANCH=zork
TEST=build verstage for zork
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Ifdbf20544b21b7fa90a49c5497ff4a5da61bebb1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45985
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Added new config BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES to accomodate
older x86 platforms that don't allow writing to SPI flash when early
stages are running XIP from flash. If
BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES is not selected,
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY will get auto-selected if
BOOT_DEVICE_SPI_FLASH_RW_NOMMAP=y. This allows for current platforms
that write to flash in the earlier stages, assuming that they have
that capability.
BUG=b:150502246
BRANCH=None
TEST=diff the coreboot.rom files resulting from running
./util/abuild/abuild -p none -t GOOGLE_NAMI -x -a --timeless
with and without this change to make sure that there was no
difference. Also did this for GOOGLE_CANDY board, which is
baytrail based (and has BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES
enabled).
Change-Id: I3aef8be702f55873233610b8e20d0662aa951ca7
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45740
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The PSP will be adding information into these fields after verstage
runs. This allows data to be passed directly to coreboot very early
in the boot process.
BUG=b:168895748
TEST=None
Branch=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idbd1dfece59e99f6f15dfd8d002529ea6417cdbe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This allows passing in the presets to FSP.
I will set the UPD values after all the zork boards have had their
presets correctly set. This way we don't override the UPD defaults with
0s.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I44951cacb1e9d788016a70283cf9688bf88a09f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Add code to generate p-state and c-state SSDT objects to coreboot.
Publish objects generated in native coreboot, rather than the ones
created by FSP binary.
BUG=b:155307433
TEST=Boot morphius to shell and extract and compare objects created in
coreboot with tables generated by FSP. Confirm they are equivalent.
BRANCH=Zork
Change-Id: I5f4db3c0c2048ea1d6c6ce55f5e252cb15598514
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Parse the generated fmap_config.h file instead of the .fmd file supplied
by the board to determine the size and location of the APOB region.
Parsing the generated file allows to write .fmd files without having to
take into account that the shell script part in Picasso's Makefile.inc
can only parse a subset of the .fmd syntax.
BUG=b:157068645
TEST=Timeless build for amd/mandolin resulted in identical binary.
BRANCH=zork
Change-Id: I6ed1903a8157374d78d2865621baa15774d2a7d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45595
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Verstage in PSP used stub for timestamps since we didn't know about
clock. Now we figured out clock source so we can enable timestamp
functions.
BRANCH=zork
BUG=b:154142138, b:159220781
TEST=build without CONFIG_PSP_VERSTAGE_FILE, flash and boot
Change-Id: I431a243878e265b68783f54ee9424bb1d4fe03c1
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Clean up configuration of the legacy UART and add Kconfig options for
the mapping between UART and legacy I/O decode.
BUG=b:143283592
BUG=b:153675918
TEST=Linux detects an additional legacy serial port for each active MMIO
one if PICASSO_UART_LEGACY is selected.
BRANCH=zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
add dptc support for different power parameter on tablet/clamshell mode
The BIOS may choose to adjust power and/or thermal parameters at its own
discretion. The DPTC interface(DPTCi) ALIB Function adds flexibility by
allowing the BIOS to request power state changes independently of specific
events.
BUG=b:157943445
BRANCH=none
TEST=Build.Generated ASL code from SSDT by acipgen_dptci().check the setting changed.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Icae94103f254f8fdb84e6ee0f5404fb09fa97b2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The register number is always non-negative, so it should be an unsigned
type.
Change-Id: I6b6df5a41fe58efc53eaa87c01b88426ea8daa6e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
data_fabric.c uses types from stdint.h, but doesn't include stdint.h
directly, so replace the inclusion of stdbool.h with types.h which
includes both stdbool.h and stdint.h.
Change-Id: I4c1ea444e50218cf19fc8fff499929336265bd03
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Memory speed is given as an integer in MHz. In some cases it has
an implicit fractional speed, so simply multiplying by 2 is not
sufficient.
Use method from dram/ddr4.c instead.
BUG=b:167155849
TEST=Boot ezkinil, check output of 'mosys memory spd print all'
and dmidecode -t17
BRANCH=Zork
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Icc77c21932c68ee9f0ff0b8e35ae7b1a3732b322
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This I/O region is already covered by the range declared right above the
deleted one.
TEST=Linux stops complaining about overlapping I/O regions.
BRANCH=zork
Change-Id: I149fb0dc85bfe721a6b0d81e4e9c197194718876
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45368
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I plan on adding another eMMC parameter. This refactor keeps the config
contained in a single struct.
BUG=b:159823235
TEST=Build test
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I4b57d651ab44d6c1cad661d620bffd4207dfebd4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We added transfer_info_struct to contain various information about
memory region we pass from PSP to x86 in commit 0c12abe462.
This should be at the start of transfer region but we only manipulated
it as local variable and didn't put data into the region, resulting
garbage data for transfer_info when x86 tries to read it.
Copy the content of local variable to beginning of _transfer_buffer
before requesting transfer to PSP so coreboot on x86 can access it.
BUG=b:159220781
BRANCH=zork
TEST=check transfer_info_struct is correctly populated on romstage
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I14bc34e6af501240a6f633db3999a7759e88d60b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44751
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
That devicetree setting is about the Audio Co-Processor and not ACPI.
BRANCH=zork
Change-Id: I7f376371ee094392d4434340c77f0fc8d0d8e4e1
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45300
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The AOAC device number is never negative, so make it unsigned.
BRANCH=zork
Change-Id: I3e0d15a646f02da5767504471961d5d9f8f28bea
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45308
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change is separate from CB:45308 to only have the directly UART-
related changes in this patch train.
BRANCH=zork
Change-Id: Ie587fdbd1e6229c1374fce3568c6a361577dc6c4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The UART index is never negative, so make it unsigned and drop the
checks for the index to be non-negative.
Change-Id: I64bd60bd2a3b82552cb3ac6524792b9ac6c09a94
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The UART index is never negative, so make it unsigned and drop the check
for the index to be non-negative.
BRANCH=zork
Change-Id: I38b5dad87f8af4fbe8ee1d919230efe48f68686c
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fix TSC frequency calculation per Picasso PPR. This code was copied
from Stoney and was incorrect for Picasso.
BUG=b:163423984
TEST=verify Dalboz TSC to be 1GHz
BRANCH=zork
Change-Id: Ibe3f49c7d295e7336ee042da2b94823171b6eb55
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Move APCB generation out of the picasso makefile and into the mainboard
makefile. APCB generation tends to be mainboard specific and does not
belong in the soc makefile.
BUG=b:168099242
TEST=Build mandolin and check for APCB in coreboot binary
Build and boot ezkinil
Change-Id: Ib85ad94e515f2ffad58aafe06c1f1d4043e9303c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45222
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the missing entry using new Kconfig symbol for IOAPIC ID. coreboot
will always enable the GNB IOAPIC.
Cq-Depend: chrome-internal:3247431, chrome-internal:3253044
BUG=b:167421913, b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Dump MADT and IVRS tables. Cross check ioapic entries
in MADT against IVRS.
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: Ic4a2e9b71dba948e8a4907e5f97131426d8a4a3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45056
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Kconfig symbols for the FCH and GNB IOAPIC IDs, then pass
the info to FSP to keep it in sync with coreboot. Do the same
for the northbridge's IOAPIC base address.
Use the new values where needed, and reserve the resources
consumed by the GNB IOAPIC.
BUG=b:167421913, b:166519072
TEST=Boot Morphius and verify settings
BRANCH=Zork
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I57d3d6b2ebd8b5d511dbcb4324ea065cc3111a2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45115
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previous CL (1916f8969b) misinterpreted
spec as requiring size alignment on all IVHD device entries. The correct
requirement specifies only for 4-byte entries. The unneeded realignments
result in gaps in the table. The kernel hangs in early boot due to the
malformed table.
Remove 8-byte entry alignment.
BUG=b:166519072
TEST=Boot fully to morphius board with and without amd_iommu kernel
parameter. Confirm IVRS contains no alignment gaps/corruption.
Change-Id: Iddcff98279be1d910936b13391dd2448a3bb2d74
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The PSP bootloader and verstage are only used out of the RO region,
so don't build them into the RW sections.
BUG=None
TEST=Build & Boot
BRANCH=zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ic7bcb9a6a78926325e80755c010bb047e4a9485c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
This allows a platform to specify the location of the signing token
for the PSP verstage, and build it into the firmware image.
BUG=b:166108929
TEST=Build file into PSP firmware, verify that it's present and has
the correct ID.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I182ad9b48a2776ccd29ead0f54cfe14c5bf45560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
To use a signed PSP verstage, we're going to need to build it first,
then sign and store the binary. This patch allows the stored (signed)
verstage binary to be used.
BUG=b:166108929
TEST=Build with existing verstage binary instead of re-building it.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I5cbceca3b75f05c5460190b1c829d1ffaab2c736
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Eric Peers <epeers@google.com>
Move PSP_SHAREDMEM_DRAM_END after _etransfer_buffer to ensure that the
transfer buffer actually lives within the 32KiB that is supported to be
transferred. Resulting symbol address change in bootblock.debug file
summarized below.
BEFORE:
02011000 T _psp_sharedmem_dram
02011000 T _transfer_buffer
02011000 T _transfer_info
02011040 T _etransfer_info
02011040 T _vboot2_work
02014040 T _evboot2_work
02019000 T _epsp_sharedmem_dram
02019000 T _preram_cbmem_console
0201a600 T _epreram_cbmem_console
0201a600 T _timestamp
0201a800 T _etimestamp
0201a800 T _fmap_cache
0201ac52 T _efmap_cache
0201ac52 T _etransfer_buffer
AFTER:
02011000 T _psp_sharedmem_dram
02011000 T _transfer_buffer
02011000 T _transfer_info
02011040 T _etransfer_info
02011040 T _vboot2_work
02014040 T _evboot2_work
02014040 T _preram_cbmem_console
02015640 T _epreram_cbmem_console
02015640 T _timestamp
02015840 T _etimestamp
02015840 T _fmap_cache
02015c92 T _efmap_cache
02015c92 T _etransfer_buffer
02019000 T _epsp_sharedmem_dram
BUG=b:167243965
BRANCH=None
TEST=checked 'cbmem -1' for FMAP error after ec reboot
Signed-off-by: Josie Nordrum <josienordrum@google.com>
Change-Id: I9b482aced5deb40bd87d19d9c42585d8a6db5fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45045
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make the general purpose PCIe clock outputs configurable to be either
permanently enabled, permanently disabled or dynamically enabled via
their corresponding external #CLK_REQx pins in the board's devicetree.
BUG=b:149970243
BRANCH=zork
Change-Id: I3f5760c0b869e8a9416ba9b57d182a88a2eb5e44
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The _SHIFT postfix is a bit clearer than the _SHL one and more in line
with the names used for this kind of defines in coreboot. The
documentation on that register is currently wrong and will hopefully be
fixed in the future; the defines should now match the hardware.
BUG=b:149970243
BRANCH=zork
Change-Id: I977f107d466521484ca13fa1f4dd86a50c8150d7
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Replacing the existing defines with macros makes them easier to use in a
function that applies the setting for a certain GPP/GFX clock output.
Also add macros for statically enabling or disabling the clock outputs
and not only for configuring them as controlled by the #CLK_REQx pins.
BUG=b:149970243
BRANCH=zork
Change-Id: I14198f224639721fe6ca71ca3dcd9cb413a587d5
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
On Picasso MISC_CLK_CNTL1 doesn't contain OSCOUT[12]_CLK_OUTPUT_ENB and
this was probably just copied over from stoneyridge.
BUG=b:149970243
BRANCH=zork
Change-Id: I32f459026c4e8632672123681b20736245f198b2
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44886
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add vb2ex_hwcrypto_rsa_verify_digest function for verifying rsa
signature against digest using PSP svc.
This function will be later used by vboot to accelerate rsa
verification.
BUG=b:163710320, b:161205813
TEST=build zork firmware with vboot modification, confirm it's booting
and boot time is reduced by ~230ms.
Change-Id: Ic5c1d13092db5a84191642444f3df9c26925e475
Signed-off-by: Kangheui Won <khwon@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44456
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
FSP has recently added support for a UPD switch to power gate SATA. This
change adds the coreboot side of the feature. To avoid having two SATA
enable options, the value of the sata_enable UPD is determined by the
enable state of the AHCI controller in the platform devicetree.
BUG=b:162302027
BRANCH=zork
TEST=Verify AHCI controller can be hidden/disabled.
Change-Id: I48bf94a7e6249db6079a6e3de7456a536d54a242
Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com>
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44067
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch all zork boards to use generated generic SPDs from spd_tools.
HMAA1GS6CMR6N-VK is unused by Ezkinil, and all other boards, so it was
removed.
picasso/Makefile.inc was updated to populate the 2nd APCB channel based
on APCB_POPULATE_2ND_CHANNEL. This removes the need to suffix spd
entires with _x1/_x2.
Command to generate files:
$ find src/mainboard/google/zork/variants/ -maxdepth 1 -type d | grep -v '/$' | while read b; do
n=$(basename ${b});
if [ "${n}" = "baseboard" ]; then
continue
fi
go run util/spd_tools/ddr4/gen_part_id.go src/mainboard/google/zork/spd \
src/mainboard/google/zork/variants/${n}/spd \
src/mainboard/google/zork/variants/${n}/spd/mem_parts_used.txt
done
BUG=b:162939176
TEST=Boot ezkinil and dalboz check dmidecod -t17
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I0553858f83d3d1e90cf35bece108768f004a29a5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44480
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If there's already been an error and PSP_verstage is booting to RO,
don't reset the system. It may be that the error is fatal, but if the
system is stuck, don't intentionally force it into a reboot loop.
BUG=None
TEST=Force an error, still boots to RO instead of going into a boot loop
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Ibb6794fefe9d482850ca31b1d3b0d145fcd8bb8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44652
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of halting if the vboot workbuf is not passed to coreboot by the
PSP, reset and reboot into recovery mode.
This process is made more difficult because if the workbuf isn't
available, we can't reboot directly into recovery - the workbuf is
needed for that process to be done through the regular calls, and we
don't want to go around the vboot API and just write into VBNV directly.
To overcome this, we set a CMOS flag, and reset the system.
PSP_verstage checks for this flag so it will update VBNV and reset the
system after generating the workbuf.
BUG=b:152638343
TEST=Simulate the workbuf not being present and verify the reboot
process.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I049db956a5209904b274747be28ff226ce542316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Create areas for console & timestamp data in psp_verstage and pass it to
the x86 to save for use later.
BUG=b:159220781
TEST=Build & Boot trembyle
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: I41c8d7a1565e761187e941d7d6021805a9744d06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This field eventually gets interpreted as MT/s by SMBIOS instead of MHz. Translate from Mhz to MT/s by multiplying by 2.
BUG=b:154654737
TEST=dmidecode -t 17 matches expected speed
Change-Id: I51b58cb0380f2a2bf000347395ac918ac0717060
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
