Followup deals further with Fam15 case. For unknown reasons calls
were commented out for amd/dinar and they remain that way.
Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6237
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Leave it to the implementation of flash->write() to split the writes
to match SPI controller and SPI flash part restrictions. This allows
for some optimisation for auto-address-increment (AAI) commands.
Kconfig AMD_SB_SPI_TX_LEN can be kept as local.
Change-Id: I4a8bc55ab7eb0eeda8f25003a8f5ff2a643ab7a7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6164
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
SPI controllers in Intel and AMD bridges have a slightly different
restriction on how long transactions they can handle.
Change-Id: I3d149d4b7e7e9633482a153d5e380a86c553d871
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6163
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This change makes it possible for vboot to avoid an
exploit that could cause involuntary switch to dev mode.
It gives depthcharge/vboot some information on the
type of input device that generated a key.
BUG=chrome-os-partner:21729
TEST=manually tested for panther
BRANCH=none
CQ-DEPEND=CL:182420,CL:182241,CL:182946
Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://chromium-review.googlesource.com/182357
Reviewed-by: Luigi Semenzato <semenzato@chromium.org>
Tested-by: Luigi Semenzato <semenzato@chromium.org>
Commit-Queue: Luigi Semenzato <semenzato@chromium.org>
Reviewed-on: http://review.coreboot.org/6003
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This will make USB keyboards connected to USB3 ports work
in libpayload on Beltino.
BUG=chrome-os-partner:23396
BRANCH=none
TEST=Use USB keyboard on Beltino in dev mode screen
Change-Id: I70b03d733bd9e4c8be5673b48bd2196effa8a5e7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/173640
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Tested-by: Stefan Reinauer <reinauer@chromium.org>
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6018
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
When USB3 devices are attached while in suspend, or two USB3 devices
that are both plugged in are switched to the other port while in
suspend the kernel does not seem to notice this -- despite the cold
attach status bit. This results in the devices showing up in the USB
list at the old enumerated device numbers and higher layers continuing
to think they are present but not reseponding.
With the kernel workaround to deal with devices that are logically
disconnected it is possible for firmware to send a warm port reset to
devices that are in this state and then the kernel will see them disappear
and handle it properly.
This same issue exists in the EFI firmware on the Whitetip Mountain 2
reference board so it is not specifically a coreboot bug. If this
behavior is fixed in the kernel then this workaround could be removed
since it is in RW firmware.
BUG=chrome-os-partner:22818
BRANCH=falco,peppy,wolf,leon
TEST=manual:
1) attach two USB3 devices
2) suspend system
3) switch the ports that the USB3 devices are attatched to
4) resume system
5) confirm that the devices are re-enumerated and come up properly
Original-Change-Id: Ifba3ffc94a06dc0b2436d7d7d464d824657362af
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170335
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit 203d200268f4af6445224962190cbc66ad2a83e4)
Change-Id: I54fd2847ee25a60f25c2cefebdc1a3c18455464a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170579
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6017
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
I have been attempting to work around USB3 issues that appear in the
kernel with hacks in the firmware, but this is resulting in more
headaches in the kernel.
Instead remove all the work that was being done at resume time and undo
the change that was issuing a warm reset to all ports at suspend time.
The bad device behavior will be dealt with at the kernel level to
handle devices that get stuck in polling state after enable/disable
sequence.
BUG=chrome-os-partner:22754
BRANCH=falco,peppy,wolf,leon
TEST=manual:
suspend/resume with several misbehaving devices:
Kingston USB3 Media Reader
Transcend USB3 Media Reader
Various ADATA USB3 drives
Various Kingston USB3 sticks
Original-Change-Id: I0894454af42d2ced456fe0da921d74c9e74902d0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170107
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
(cherry picked from commit c2abb4d0dad6ed00e1e230d604c4c0a76eb4eef7)
Change-Id: Ib215d9c230f90a1c9f34bf29254bb9feec28c67e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170578
[pm: rebase to master branch of coreboot upstream]
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove some ASCII art past 80 columns.
Change-Id: I00ad79f2e1ddd78935efcfab19d9e166f0349ae3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6155
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
If one commented out HAVE_ACPI_RESUME in Kconfig file for a board
using agesa/hudson the build failed.
Change-Id: Ifbad8f6e23ce4b5431e596bf67e6ab108fedb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6253
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Whenever spi_xfer is called and whenver it's implemented, the natural unit for
the amount of data being transfered is bytes. The API expected things to be
expressed in bits, however, which led to a lot of multiplying and dividing by
eight, and checkes to make sure things were multiples of eight. All of that
can now be removed.
BUG=None
TEST=Built and booted on link, falco, peach_pit and nyan and looked for SPI
errors in the firmware log. Built for rambi.
BRANCH=None
Change-Id: I02365bdb6960a35def7be7a0cd1aa0a2cc09392f
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192049
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6175
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The spi_flash_probe and and spi_setup_slave functions each took a max_hz
parameter and a spi_mode parameter which were never used.
BUG=None
TEST=Built for link, falco, rambi, nyan.
BRANCH=None
Change-Id: I3a2e0a9ab530bcc0f722f81f00e8c7bd1f6d2a22
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: https://chromium-review.googlesource.com/192046
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: Gabe Black <gabeblack@chromium.org>
[km: cherry-pick from chromium]
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6174
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This is needed to successfully build fox_wtm2 from external repo.
BUG=chrome-os-partner:18638
BRANCH=none
TEST=manual: successfully compile coreboot for fox_wtm2 and
create an image with chromeos-bootimage/cros_bundle_firmware
Change-Id: Iaa4e9983faa1d86c2b29d8fd4f577be035497e38
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48676
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4132
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Some USB3 devices are not showing up after suspend/resume cycles.
In particular if a device uses a lower power state like U2 it may
take longer to come up and the firmware needs to wait after sending
a warm port reset.
In addition skipping port reset to connected ports in the way into
suspend was causing problems so instead send all ports a reset
before suspend.
BUG=chrome-os-partner:22402
BRANCH=falco,peppy,leon,wolf
TEST=manual:
Suspend/resume with ADATA HE720 HDD (and other devices) both
connected at suspend and connecting while in suspend and ensure
that the devices always show up in the kernel.
Change-Id: Ib7b15dc65792742b4ceb7dcfc4b2c83192eafcc2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/169548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6015
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
In order to enable a Super I/O in non Chrome EC systems we
need to make pch_enable_lpc() available to the mainboard
romstage.c
BUG=none
BRANCH=none
TEST=boot ChromeOS on Beltino
Change-Id: I34e7d23012e1852c69e82ba7cdc81a05751846de
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/172180
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: http://review.coreboot.org/6019
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add the chip option to disable SATA DEVSLP. This disables
the SDS bit in the SATA CAP2 register.
BUG=chrome-os-partner:23186
BRANCH=leon
TEST=Manual: System runs without SATA failure for more than 10 hours
Original-Change-Id: I8baa40935421769aeee341a78441fb19ecaa3206
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/174648
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
(cherry picked from commit 49d25812b04a983d687a53a39530559ba99fd9b4)
Change-Id: Iac0b32f80958f5ffb571733484dc931bee216f55
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: https://chromium-review.googlesource.com/176352
Reviewed-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/6013
Tested-by: build bot (Jenkins)
This will allow the legacy mode boot path to leave USB
ports routed to EHCI so they can be used by SeaBIOS.
BUG=chrome-os-partner:22085
BRANCH=falco,peppy
TEST=manual: Build and boot from USB and SeaBIOS on falco
Change-Id: I46870eccd1b846dc8a7f8d7948969c8e623e18cd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/66547
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/6011
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Current build configuration always wants to include an Intel Management Engine
(ME) firmware (`me.bin`) on Intel Lynx Point systems. However, we can have a
working coreboot without it, as long as the factory delivered ME firmware is
kept untouched in the flash ROM. So let the user decide if a ME firmware will
be included in the build by introducing the Kconfig option `HAVE_ME_BIN`.
The same was done in commit 99fd30e4 (sandybridge: Make inclusion of me.bin
optional) [1] for Intel Sandy Bridge (BD82x6x).
[1] http://review.coreboot.org/3522
Change-Id: I7c6048fd0f56288769ad90acbfb67b908ac8d824
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6047
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
On newer Intel systems, like Intel Lynx Point, the flash ROM is shared
between the host processor (BIOS), its Management Engine (ME) and an
integrated Ethernet controller (GbE). The layout of the flash ROM (and
other information) is kept in the so called Intel Firmware Descriptor
(IFD). If we only want to build coreboot to update the BIOS section,
all we need is the flash layout.
So add the option to specify the flash layout in the mainboard’s
Kconfig, and thus, to build without the real IFD. However, with such a
build, one has to make sure that the IFD section on the flash ROM will
not be written over (nor any other section that has not been included
by coreboot). A patch to write selected sections of a flash ROM with
IFD has been sent to the flashrom mailing list [2].
The same was done in commit a15cd66b [1] (sandybridge: Make build
possible without descriptor.bin) for Intel Sandy Bridge (BD82x6x).
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
[PATCH] Add option to read ROM layout from IFD
[2] http://review.coreboot.org/3524
Change-Id: I26a604446cdf37a6bbcee2b14a107b7ccf417d5c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/6046
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
To be precise, wakeup from S3 does not involve SPI writing, while
preparing for it on cold power-ons currently does.
For S3DataTypeMtrr storage is changed such that the first 4 bytes
is the length of data stored like with the other two S3DataType.
Change-Id: Id920650474530d4191075da4ef70daa66c904c5b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6085
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Port the changes that were made in amd/cimx to amd/agesa
as were done in:
commit c93a75a5ab
Author: Mike Loptien <mike.loptien@se-eng.com>
Date: Fri Jun 6 15:16:29 2014 -0600
AMD/CIMx: Add functions for AMD PCI IRQ routing
This change also moves the PCI INT functions to
southbridge/amd so that they can be used by CIMX and
AGESA. The amd/persimmon board is updated for this
change.
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Change-Id: I525be90f9cf8e825e162d53a7ecd1e69c6e27637
Reviewed-on: http://review.coreboot.org/6065
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Move some __SMM__ functions under the #if preprocessor condition to
avoid warnings about unused functions.
Change-Id: I7f6fbc6a577032bc4e4635d91e8e94aecb517bd3
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/6127
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
These parameters are not specific to the southbridge device, but
the implementation of S3 storage defined by CPU code.
Change-Id: Ic341cc2b7669cf8e3e920c48473826ec03fc7d8d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6081
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This existed for ChromeOS but was no longer used with DYNAMIC_CBMEM.
Change-Id: I558a7ae333e5874670206e20a147dd6598a3a5e7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/6032
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Try to 'standardize' the otherwise peculiar method naming to be somewhat
more in-line with other ACPI implementations. This makes it easier to
compare with vendor DSDT dumps for example.
Change-Id: I5ba54f7361796669ac0cab7ff91e7de43b22e846
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5888
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The IMC functions were being called and timing out when the
CONFIG_SB800_IMC_FWM/CONFIG_HUDSON_IMC_FWM were defined as 0.
Changing to a IS_ENABLED will keep the IMC handshake from
occuring if the IMC firmware isn't running.
Tested on a Persimmon platform which makes three calls to
spi_claim_bus() with each call timing out after 500ms.
Change-Id: I5d4bbcecf003b93704553b495a16bcd15f66763b
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5974
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The CIMX sb700/sb800/sb900 and agesa/hudson code was treating
the LPC SPI BAR as a normal PCI BAR. This will set the
resources for a fixed size at a fixed address. This was tested
on hp/abm, amd/persimmon, and gizmosphere/gizmo boards.
Change-Id: I1367efe0bbb53b7727258585963f61f4bd02ea1d
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5947
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The PCI_INTR table is an Index/Data pair of I/O ports
0xC00 and 0xC01. This table is responsible for physically
routing IRQs to the PIC and IOAPIC. The settings given
in this table are chipset and mainboard dependent, so the
table values will reside in the mainboard.c file. This
allows for a system to uniquely set its IRQ routing.
The function to write the PCI_INTR table resides in
cimx_util.c because the indices into the table have
the same definitions for all SBx00 FCH chipsets.
The next piece is a function that will read the PCI_INTR
table and program the INT_LINE and INT_PIN registers in
PCI config space appropriately. This function will read
a devices' INT_PIN register, which is always hardcoded to
a value if it uses hardware interrupts. It then uses this
value, along with the device and function numbers to
determine an index into the PCI_INTR table. It will read
the table and program the corresponding value into the PCI
config space register 0x3C, INT_LINE. Finally, it will set
this IRQ number to LEVEL_TRIGGERED on the PIC because it is
a PCI device interrupt and the must be level triggered.
For example, the SB800 USB EHCI device 0:18.2 has an INT_PIN
value hardcoded to 2. This corresponds to PIN B. On the
Persimmon mainboard, I want the USB device to use IRQ 11. I
will program the PCI_INTR table at index 0x31 (this USB device
index) to 11. This function will then read the INT_PIN register,
read the PCI_INTR table, and then program the INT_LINE register
with the value it read. It will then set the IRQ on the PIC to
LEVEL_TRIGGERED by writing a 1 to I/O port 0x4D1 at bit position 4.
Also, the SB700 has slightly different register definitions than
the newer SB800 and SB900 so it needs its own set of #defines for
the pci_intr registers.
Only the Persimmon mainboard is adapted to this change as an
example for other mainboards.
Change-Id: I6de858289a17fa1e1abacf6328ea5099be74b1d6
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/5877
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Without this change the IOAPIC memory window would collide
with PCI config space. This was tested on the hp/abm board.
Change-Id: I5dd53463961f75bab80a41dc7beff8d0434b24ae
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/5946
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Spotted by Clang.
Change-Id: Ie4bed914ab694f4e96155140b8b54b6eb96d70d7
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5819
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Spotted by Clang
Change-Id: I0f04c380b5ada28fb900710facc293edd65ac177
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5815
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There are a couple of places where CPPFLAGS are
pasted into CFLAGS, eliminate them.
Change-Id: Ic7f568cf87a7d9c5c52e2942032a867161036bd7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5765
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Rename INCLUDES to CPPFLAGS since the latter is more
commonly used for preprocessor options.
Change-Id: I522bb01c44856d0eccf221fa43d2d644bdf01d69
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/5764
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This is a empty struct that has propagated through the superio's & ec's
but really does nothing. Time to get rid of it before it adds yet more
cruft. However, since this touches many superio's at once we do this in
stages by first changing the function type to be a pure procedure.
Change-Id: Ibc732e676a9d4f0269114acabc92b15771d27ef2
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5617
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
We should configure i8254/i8259 down in to the southbridge rather than
romstage of every AGESA/CIMx board much like Intel boards do.
Change-Id: Id7c4f0baa0819d52aef9b0ee03c20d0fa16b9352
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5669
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
CPU - fsp_model_206ax:
- Remove Kconfig options and mark this as using the FSP.
- Use shared FSP cache_as_ram.inc file
Mainboard - intel/cougar_canyon2:
- Update to use the shared FSP header file.
- Modify to call copy_and_run() directly instead of returning to
cache_as_ram.inc.
Northbridge - fsp_sandybridge:
- remove mrccache, fsp_util.[ch]
- add fsp/chipset_fsp_util.[ch] with chipset specific FSP bits.
- Update to use the shared FSP header file.
These changes were validated with FSP:
CHIEFRIVER_FSP_GOLD_001_09-OCTOBER-2013.fd
SHA256: e1bbd614058675636ee45f8dc1a6dbf0e818bcdb32318b7f8d8b6ac0ce730801
MD5: 24965382fbb832f7b184d3f24157abda
Change-Id: Ibc52a78312c2fcbd1e632bc2484e4379a4f057d4
Signed-off-by: Martin Roth <gaumless@gmail.com>
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/5636
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Rename coreboot_ram stage to ramstage. This is done in order to provide
consistency with other stage names (bootblock, romstage) and to allow any
Makefile rule generalization, required for patches to be submitted later.
Change-Id: Ib66e43b7e17b9c48b2d099670ba7e7d857673386
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: http://review.coreboot.org/5567
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The ACPI IO ports, and the respective SMI (for HAVE_SMI_HANDLER), were
initialized when the FADT table was written. This works well on a cold
boot, but the ACPI ports are not initialized on S3 resume, as ACPI
tables are not written. This will not work on S3 resume if the default
ports are not what we set them, or if AGESA sets them to some other
value.
To solve this, move the port configuration to southbridge chip init.
Change-Id: Ib4043f0fa5e20f08d320acd12ce84d4d789cd035
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5559
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
The power button was declared by hudson's ASL as \_SB.PCI0.PWRB, and
always had the wake source declared as GPE3. This is not the correct
wake source for all boards. On some laptops declaring a wake source is
not needed, as the wake mechanism is handled by the EC.
Move the declaration of the power button to mainboard ASL files, and
scope it as \_SB.PWRB . This also makes the naming consistent with the
examples in the ACPI spec. The wake source for the PWRB of HP Pavilion
M6 1035dx is removed, as it is incorrect.
Change-Id: I9c76566025e7f200c0376673f6c6ea299afa4a5d
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
The ACPI IO ports were defined twice, and used inconsistently. Only
keep one of the definitions for consistency.
Change-Id: If5744f9375fdaa97ceb9ba03dca8aa825eecf159
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SPI controller driver used numerical offsets to access SPI
registers, making it unreadable without the datasheet. Use less magic
and more #defines to improve readability.
Change-Id: I8a1f11645cfce027e5df7a41a98c70249695889e
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5557
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Following boards use cimx/sb700:
amd/dinar
supermicro/h8qgi
supermicro/h8scm
tyan/s8226
Only amd/dinar had APIC_ID_OFFSET defined, thus all had 0x0.
There was a nonsense preprocessor directive (MAX_CPUS * MAX_PHYSICAL_CPUS >= 1).
Except for tyan, (MAX_CPUS * MAX_PHYSICAL_CPUS) % 256 == 0.
Together with documented 4-bit restriction for APIC ID field, this APIC ID
programming matches with MP tables and ACPI tables.
I believe this would also fix cases of cimx/sb700 with MAX_CPUS<16, which
we do not have in the tree.
Change-Id: If8d65e95788ba02fc8d331a7af03a4d0d8cf5c69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5539
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Match the definition of NODE_PCI() with get_node_pci(), so romstage
and ramstage agree of the PCI BDFs for nodes.
Note that all board have CONFIG_CDB = 0x18 and the maximum for
nodes = 8, so we always have (CONFIG_CDB + x) < 32.
Change-Id: I676ee53a65ef5b1243df2c5889577dd987c8fc9c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5536
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Refactor hudson_enable_gevent_smi() to allow configuring the interrupt
mode and trigger level. Move the utilities which are useful in SMM to
a separate file that is included in both ramstage and SMM. This is
useful for SMI handlers which need to enable or disable GEVENT SMIs
on-the-fly. A follow-up patch makes use of this infrastructure.
Change-Id: Ifa4c300c00c178b18d7280690cfc4b8367c669b8
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/170
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This function isn't used on hudson, and seems to be copy-paste from
older southbridges. It is used in sb700 to enable or disable certain
PCI devices. On hudson, these configuration bits are moved to the PM
space.
Change-Id: I9b967a2d0a5dddc8341204dadeed90460251915c
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5513
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This enables the ACPI SMI command port in the FADT table, and sets up
the hardware accordingly. If we have SMI enabled, then we don't set
the SCI_EN bit at boot, causing the OS to send the ACPI_ENABLE
command, as required by the ACPI spec. This gives us a chance to hook
into the mainboard_smi_apmc() handler.
Change-Id: Ib4c63d55b3132578dcae48bfe2092d4ea35821dd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5511
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
This sets up the infrastructure to handle SMIs generated by the Hudson
southbridge. An API for interfacing to mainboard handlers is not
defined at this point. A few functions are defined to allow mainboard
code to enable SMIs from GEVENT pins. These are the only functions which
I expect to be needed anytime in the foreseeable future.
SMIs are always acknowledged and cleared, as not clearing an SMI will
cause us to re-enter the SMI, effectively bricking the machine if a
southbridge-generated SMI without a handler occurs.
Change-Id: Ibceb21ac5423eb134d3eb7d24800280b183f7619
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5494
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Tested-by: build bot (Jenkins)
The MMIO region is set up by AGESA very early on, so we can use it to
access the PM register space in ramstage. 16-bit accessors are also
provided to simplify some setup tasks. 16-bit accesses are not
possible via PIO.
The pm2_iowrite/read accessors are removed, as they are not used.
Change-Id: Ie7967b5086eb004525c39721338c6495aedc8165
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5503
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@gmail.com>
Just like in commit
* 1d87dac hp/pavilion_m6_1035dx: Sanitize #includes
Include AGESA headers specifying the path relative to AGESA_ROOT. The
path is specified relative to AGESA_ROOT as opposed to src/ since this
code may include headers from different AGESA families, depending on
the board.
Change-Id: Ide38cc34e207a8b617d1d319fd9c17a785f55833
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5423
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Not all boards which use the AMD Hudson southbridge have IDE. However,
the southbridge's asl included an 'ide.asl' file which had to be
present in $(mainboard_dir)/acpi.
Address this issue by removing the inclusion of 'ide.asl' from the
southbridge 'fch.asl' and remove 'ide.asl' from Hudson boards, none
of which have IDE.
If future hudosn board will come with IDE, the device can be declared
in the PCIO scope of dsdt.asl, right below the inclusion of 'fch.asl'.
Change-Id: Ie2efb7ebf8f5b527e26d7aaaeafbd3053a9a6b28
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/5459
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Follow along hudson, cut out "SLP_TYP type was 0" excessively filling
the buffer. We could make this conditional on non-zero?
Change-Id: Iffd4c146b2ac4f57dbc3a011a683c92b6e132e39
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5495
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Not all boards which use the AMD cimx/sb800 southbridge have IDE.
However, the southbridge's asl included an 'ide.asl' file which had to
be present in $(mainboard_dir)/acpi.
Address this issue by including ide.asl only in boards which have IDE,
and remove it from all other cimx/sb800 boards.
Change-Id: I57fcb4db9f85234b05ae1705ef81a576c478cee6
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-on: http://review.coreboot.org/5460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
GP0e does not fit into the naming scheme of the field units surrounding
this field unit definition. Also the keys for e and 3 are close to each
other supporting the theory that this is indeed a typo.
Change-Id: I43cf288fe1e0240b33971073c1aa8a1db5762e31
Reported-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5483
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The SerialIO DwordIo() definition is fixed up before returning
it in the serialio device _CRS method, so the values that are set
in the raw ASL are not actually used.
However modern versions of IASL do not like that the RangeLength is
set to zero and will fail to compile. Set this value to 1 to make
IASL stop complaining, but the real value is still fixed up in _CRS
so this has no real effect on the end result.
Change-Id: Iceb888e54dd4d627c12d078915108a11f45b1a2d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Removing `-Wno-unused-but-set-variable` from `CFLAGS` results in the error
below, when building for example the HP DL145 GL1.
CC southbridge/amd/amd8111/acpi.ramstage.o
src/southbridge/amd/amd8111/acpi.c: In function 'acpi_init':
src/southbridge/amd/amd8111/acpi.c💯11: error: variable 'dword' set but not used [-Werror=unused-but-set-variable]
Removing the variable `dword` fixes this error.
The read is left in the code, as I do not know if it has an effect or
not.
Change-Id: I9957cef3a996c5974c275423c9de63ccf230974e
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/5315
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The previous SBxxx generations were setting up LPC bridge based
on the PNP resources. Implement it also for AGESA Hudson.
The AGESA itself opens one big region DFLT_SIO_PME_BASE_ADDRESS
(512 bytes). Make the code smart enough to detect already used
region and if any resource fits into AGESA defined region, do nothing.
Change-Id: I718d034bc4c778697a7bd0506d4550c8f5a43159
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/4497
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
SPI registers didnt change since ICH8. No need to have separate
files for them. Unify.
Change-Id: I4e2ac3221b419c007e135c9ee615fc3b84424cbc
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5254
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Without this memory decoding isn't activated which, in turn,
makes SeaBIOS crash.
Change-Id: I3dcc721b500ab7468e1082157eeeed38044462d0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5326
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
With generic load using 32-bit accesses this is no longer has a
huge impact it previously did. It's also unnecessarily
component-speficific.
Change-Id: I7e8a74ea1ceaa225e1024f9eb43e7280773e2b5a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5131
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Properly determine temperature target and set it in early
init rather than hardcoding it in late init.
Change-Id: Ie763f205890674a9dd1d9c5974caaccdd67cea14
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5264
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Chrome OS environment sends an SMI to finalize the chipset/board
at the end of the "depthcharge" payload, but there is no facility to
send this command if not using the full ChromeOS firmware stack.
This commit adds a callback before booting the payload that will
issue this SMI which will lock down the chipset and route USB devices
to the XHCI controller.
Change-Id: I2db9c44d61ebf8fa28a8a2b260a63d4aa4d75842
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5181
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is responsibility of end-user application. When coreboot does
it, it is only for the purpose of debug console.
Change-Id: Idbbf9528c60b9b819b7bea9dfe84078a3f055bc9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5251
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Andrew Wu <arw@dmp.com.tw>
This sequence was derived from BD82X6X and on ibexpeak it inadvertently
disables interrupts. In older kernels it wasn't a problem but in new kernel
it makes codec probe fail.
Change-Id: I40184ae8c4cfe758869af1a1565b88f0a238150e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5074
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Remove the bit of code that was putting the SerialIO devices into
D3Hot state when they are switched from PCI to ACPI mode. Instead,
add the appropriate ACPI Methods to allow the kernel to control the
power state of the device.
The problem seems to be that if the device is put in D3Hot state
before it is switched from PCI to ACPI mode then it does not properly
export its PCI configuration space and cannot be woken back up.
Adding the ACPI Methods for _PS0/_PS3 allows the kernel to transition
the device into D0 state only when it is necessary to communicate with
the device, then put it back into D3Hot state.
Change-Id: I2384ba10bf47750d1c1a35216169ddeee26881df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/5193
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
It is inappropriate for chipset code to be redefining
types -- especially NULL to a non-pointer type. There's
only one non-straight forward change. A condition
being checked was '!ptr_type == NULL' (0 as int). That
check is actually 'ptr_type != NULL'.
Change-Id: Iab5733e5a573baba6fec94e0c955ba4fad72c836
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5088
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This claim is useless when done before EHCI controller reset. Code in
usbdebug_init_() already sets this properly after reset, see use of
DBGP_OWNER.
Change-Id: Ic17493fe4edbbbed6ebcbef35a264fbf188f1fba
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4709
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Also relocate and split header files, there is some interest
for EHCI debug support without PCI.
Change-Id: Ibe91730eb72dfe0634fb38bdd184043495e2fb08
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5129
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Broken with/since commit d1cb0eec.
Original intention was to set the frequency for 'Fast Read' command
in bits 15..14, and enable 'Fast Read' command.
Modified register contains SPI frequency for 'Normal Read' command
in bits 13..12. Default for this is 11b for 16.5 MHz. Existing code
unintentionally clears these bits, increasing SPI frequency to 66MHz
for 'Normal Read' command.
This is above specifications for many common SPI flash components
and also makes flashrom older than 0.9.7-r1750 to operate unreliably
on read/write/erase for these platforms.
Change-Id: I30109e2a0410c0bb0bdc968ea71787396b32e761
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5089
Tested-by: build bot (Jenkins)
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
imc_reg_init: init fan control related registers.
enable_imc_thermal_zone: AGESA does not enable thermal zone. We enable
it here.
Change-Id: I93c729982d78b6d2c7c20bcb1a3e27a7dd0eba91
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/4300
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
When 2 chips are present to get to the second one you have to use hardware
sequencing. Also use it as the fallback if chip is unknown.
Based on code in flashrom by Stefan Tauner and Carl-Daniel Hailfinger
distributed under compatible license.
Tested on Lenovo X230 which has EN25QH64 (8M) + N25Q032..3E (4M)
Change-Id: I56f3cf0406b5f09fa327ed052c8e8b1df1d8a11f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4613
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Change-Id: Iefd6852f2300f703ebed8b52aee627107a024f85
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/4570
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Without it ME doesn't always start correctly and no temperature is reported,
no fan management and so on.
Change-Id: Iff71f3afbc35a1453a20d182890ae2d196c556bd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4636
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
probably a problem in MRC:
- EHCI output failure after sysagent
- no S3
- no MRC cache
- MRC needs watchdog
- less MTRR could be used by some memory map optimisations
Not tested:
- dock (probably doesn't work)
- msata (probably works)
- wwan (probably works)
- mini displayport (probably works)
Blobs:
MRC
VGA Oprom
Change-Id: I5bdb9372971f48e048848d57b6c924b79782dbde
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4679
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Show POST codes on a PCI device: implement hudson_pci_port80().
Remove the comments that use pci_locate_device():
using the code found in the comment seems to break booting.
This shares much code with sb600/sb700/sb800,
however the deduplication work needs to be discusses somewhere else
than in this review board.
Tested on an Asus F2A85-M.
The contribution is (C) by Rudolf Marek.
Change-Id: I54fb1dcb0614452c775ed70d867ab44ff263a61a
Author: Rudolf Marek <r.marek@assembler.cz>
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: http://review.coreboot.org/4559
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Ability to choose compatibility mode is interesting for testing payloads and
OS for compatibility with older systems.
As per comments
"ide_legacy_combined # TODO: Does nothing since
generations, remove from sb code?"
The "combined" mode was removed. It wasn't used by any mobo and the code for
it is almost identical to IDE one other than few bits relating to interrupt
handling and ISA mode.
Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4658
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Number one reason to use cbfs_get_file was to get file length.
With previous patch no more need for this.
Change-Id: I330dda914d800c991757c5967b11963276ba9e00
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4674
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
THis reduces risks of bufer overflows.
Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4279
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
DRAM reset gate GPIO is different on different mobos move it to hidden config
with 60 (current value) as default.
Set it to 10 for Lenovo X201.
Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4622
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Options for selecting the USB port and controller for usbdebug
were unintentionally hidden with commit 8232bc2c on AGESA platforms
using cimx/sb700 or cimx/sb800.
Change-Id: Ibacc81a580519fe7fa86f08374046625327340b4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4607
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this
is not a true option but copy-paste remainder from AMD K8.
Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4581
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The comment was copied around so fix all occurrences using the following
command.
$ git grep -l accessm | xargs sed -i 's/accessm/access/g'
Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/4577
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The main purpose of option rom is to supply int* handlers.
But supplying those is outside of coreboot scope and if someone needs those
they should run SeaBIOS anyway which runs the option roms wonderfully.
Running VGA oprom is kept because they're needed to init graphics.
This patch still keeps the options to include the option roms to make them
available to SeaBIOS.
Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4545
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
Originally, Vortex86EX PCI S/B internal resource reservation functions can
only support one big legacy I/O device space (0-0xfff).
Change function signature to support other non-legacy I/O device space in
the future.
Change-Id: I22f5c877ed441d59f29801d925ee40b24fb796ce
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3976
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The end of the _PS0 method that is supposed to transition the
XHCI device to D0 state is instead putting it in D3 state.
This triggers a PME_B0 GPE which causes a Notify to the XHCI
ACPI Device in the kernel and that increments the wakeup counter
and causes aborted suspends.
Instead if we just leave the device in D0 where it should be
after executing this function then the PME_B0 is not generated
and the kernel does not see a wakeup on XHCI.
Similarly I changed the _PS3 method to always put the device in
D3 at the end of the method, rather than depending on the state
to be D3 at the start.
Before this change the kernel would see the following sequence
when trying to suspend when the XHCI controller is in D3cold:
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [XHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802bc30
kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [EHCI] (Device) Value 0x02 (Device Wake) Node ffff88017802b8e8
kernel: evmisc-0169 [07] ev_queue_notify_reques: Dispatching Notify on [HDEF] (Device) Value 0x02 (Device Wake) Node ffff88017802b1b8
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
kernel: xhci_hcd 0000:00:14.0: PME# disabled
kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
kernel: PM: Wakeup pending, aborting suspend
kernel: last active wakeup source: 0000:00:14.0
Now it does not get a notification (due to PME_B0) when going to D0
on the way into suspend. XHCI goes from D3cold to D0 (in order to
be able to read mmio) and then back to D3hot before suspend.
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff88017802bf28)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
kernel: xhci_hcd 0000:00:14.0: PME# disabled
kernel: xhci_hcd 0000:00:14.0: enabling bus mastering
kernel: xhci_hcd 0000:00:14.0: setting latency timer to 64
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._S3D] (Node ffff88017802c000)
kernel: xhci_hcd 0000:00:14.0: PME# enabled
kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff88017802bf50)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D3hot
Change-Id: Id5cd28eede2b27d97640047feb17349ae4ab79b7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65236
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4448
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The coreboot and ACPI code that clears USB3 PORTSC change status
bits was not properly preserving the state of the PED (port enabled
or disabled) status bit, and it could write 0 back to this field
which would disable the port.
Additionally add back the code that resets disconnected USB3 ports
on the way into suspend (as stated in the BWG) but take care to
clear the PME status bit so we don't immediately wake.
suspend/resume with USB3 devices
1) suspend with no devices, plug in while suspended, then resume
and verify that the devices are detected
2) suspend with USB3 devices inserted, then suspend and resume
and verify that the devices are detected
3) suspend with USB3 devices inserted, then remove the devices
while suspended, resume and ensure they can be detected again
when inserted after resume
Change-Id: Ic7e8d375dfe645cf0dc1f041c3a3d09d0ead1a51
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65733
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4473
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The recommended value in docs is D2, but lynxpoint XHCI does not even
support D2 state which causes the kernel to think this device cannot
be used as a wake source:
kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Device does not support D2
kernel: xhci_hcd 0000:00:14.0: System wakeup disabled by ACPI
Additionally this means the kernel will never put the device into D3
state by itself. There is SMI code that will put the device into D3
before suspend so advertising D3 here should be correct.
With this change the kernel will put the controller into D3 on suspend
and back to D0 on resume, including executing the ACPI methods
for _PS0/_PS3 that contain chipset specific workarounds.
In addition add a _PSC method to directly return the D state from the
device registers. With ALL USB devices removed the XHCI controller
goes into D3 state and the kernel can have a hard time determining
the state of the device at boot.
A kernel compiled with CONFIG_ACPI_DEBUG=y and module parameters
acpi.debug_layer=0x7f acpi.debug_level=0x2f can be used to see
what ACPI methods are executed:
kernel: xhci_hcd 0000:00:14.0: System wakeup enabled by ACPI
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS3] (Node ffff8801000a7f50)
kernel: ACPI: Preparing to enter system sleep state S3
...
kernel: ACPI: Waking up from system sleep state S3
kernel: ACPI: Execute Method [\_SB_.PCI0.XHCI._PS0] (Node ffff8801000a7f28)
kernel: xhci_hcd 0000:00:14.0: power state changed by ACPI to D0
Change-Id: Ic64040eb4dd1947a1e2f0ee253a64be683e0ec70
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
meld with s3d
Change-Id: Ic6789720c4efe661dcb03a4afce8d88115854472
Reviewed-on: https://gerrit.chromium.org/gerrit/63916
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4409
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
- Put the device into D0 and not D3 so memory bar is available
and the subsequent commands actually do something useful
- Remove set of 818Ch[7:0]=FFh (gone in ref code)
- Fix reg 0x40/0x44 mixup
Verify that expected bits are set:
localhost ~ # pci_read32 0 0x14 0 0x10
0xe0500004
localhost ~ # mmio_read32 0xe0508144
0x000003ff
localhost ~ # mmio_read32 0xe050816c
0x000f0038
Change-Id: I388398e8c7d11e538ca18dab55d8bbd9b88f17df
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63801
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4408
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit adds a new Kconfig option for the LynxPoint
southbridge that will have coreboot route all of the USB
ports to the XHCI controller in the finalize step (i.e.
after the bootloader) and disable the EHCI controller(s).
Additionally when doing this the XHCI USB3 ports need
to be put into an expected state on resume in order to make
the kernel state machine happy.
Part of this could also be done in depthcharge but there
are also some resume-time steps required so it makes sense
to keep it all together in coreboot.
This can theoretically save ~100mW at runtime.
Verify that the EHCI controller is not found in Linux and
that booting from USB still works.
Change-Id: I3ddfecc0ab12a4302e6034ea8d13ccd8ea2a655d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63802
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4407
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Move this to the existing USB source files so they can share some
helper functions and keep the main smihandler code cleaner.
The XHCI sleep prepare code now implements the actual sleep
preparation steps from the ref code instead of the docs.
Change-Id: Ic90adbdaba947a6b53824e548c785b4fb3990ab5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4406
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Allow DTLE DATA / EDGE registers to be configured in board-specific
devicetree.
Change-Id: I82307d08c9cf73461db3ac7fb875a4fe70d6f9ea
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65716
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4475
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The PCIe root port has ASPM settings/workarounds that are only applied
based on the value of an undocumented bit in PCI config register 0x32C.
If that bit is not set for some reason then the settings are not applied.
This devicetree config option will force the ASPM settings for each port
based on the bit map.
Change-Id: I40b08ca9a0ef52742609bac72fb821454a373799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65314
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4453
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The default ME output is quite verbose and not all that useful
unless you are actively debugging the ME and then you can enable
the CONFIG_DEBUG_INTEL_ME option.
This commit silences the firmware capabilities and the MBP output.
Change-Id: I2b8abcb34ae0d00d9a38d029979e84ee0d0ca287
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65252
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4452
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This message allows unused clocks to be disabled based on a
devicetree setting in each mainboard.
Change-Id: Ib1988cab3748490cf24028752562c64ccbce2054
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65250
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4450
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The original ME code was assuming that the only type of messages
it would send were MKHI type and so it had some embedded checks
for that header and that type of message.
In order to support ICC messages this needs to change to handle
different header types, so now the header will be sent first
and then the data will follow, rather than the two both being
sent in the same low-level function.
This change has no real affect on the system, subsequent commit
will add new ICC messages.
Change-Id: I52848581e49b88c0a79e8bb6bda2a179419808a3
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/65249
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4449
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The management engine is occasionally hanging the system on resume
when it is accessed. Since we actually don't need to do anything
with it on resume it can be disabled early in the resume path and
avoid assigning resources just to remove them later.
suspend/resume on falco and check /sys/firmware/log
to ensure that device 00:16.0 is disabled early and that no
resources are probed or assigned and that the device init path
does not execute.
Change-Id: I35573681e3a1d43d816d24954842cbe9c61f3484
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62897
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4376
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The management engine is slow, requiring at least 500ms between
when the Dram Init Done message is sent (right after memory training)
to when the MBP will report that it is successfully cleared and
that the ME can finally be sent the EOP message.
Currently this is adding 100-150ms to the boot time. If we defer
waiting for the MBP Clear indicator until the finalize step we
can gain back that lost time.
boot on falco with SMI debugging enabled to
ensure that the ME is locked down in the finalize step:
Finalizing Coreboot
SMI# #0
SMI_STS: PM1 APM
ME: MBP cleared
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62633
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
There are specific programming requirements for the usb3 ports
on all LynxPoint chipsets when transitioning to D0 or D3.
LynxPoint-LP has additional workaround steps needed involving
resetting the disconnected ports when transitioning to D0.
The workarounds are implemented in ACPI code so the controller
can transition properly into D3 at runtime.
Change-Id: I3b428562f48c9cb250b97779a3b2753ed4f81509
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/62632
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4374
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965.
Deferring this step until the finalize stage will allow us
to defer waiting for the MBP clear indicator and speeding
up the boot.
Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559
Reviewed-on: https://gerrit.chromium.org/gerrit/62631
Tested-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4373
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This is needed for SMBUS drivers to write to devices.
It was copied from existing intel southbridge driver.
Change-Id: Id0ce2393b2946a9c741413bca563a1a4dc0a4f5e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/61893
Reviewed-on: http://review.coreboot.org/4364
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The LynxPoint-LP chipset only has one EHCI controller so we should
not attempt to write into the second one that only exists on LynxPoint-H.
Change-Id: I1eae060c7f0a5873c9684e5abfeea5cb5895ab62
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/63799
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4405
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The SystemAgent contains a mini-hd audio controller at PCI 0:3.0
which uses the same verb table init sequence as the southbridge.
In order to avoid two copies of the verb table loading code I
separated out the HDA verb table functions into a file that can
be re-used and then added a minihd driver to the haswell northbridge.
The minihd verb table is the same across devices so it can live
within the minihd driver rather than needing to be specified in
each separate mainboard.
I also fixed up the driver for lynxpoint HDA by following the
reference code.
Without HDMI cable plugged in driver does not find any codec,
and it does not seem to re-probe when HDMI is connected. We may
be missing kernel patches for this.
hda-intel 0000:00:03.0: no codecs found!
With a basic kernel patch to add 0x0a0c device ID to HDA driver
and with HDMI cable connected it is much happier:
snd_hda_intel 0000:00:03.0: irq 60 for MSI/MSI-X
input: HDA Intel MID HDMI/DP,pcm=3 as /devices/pci0000:00/0000:00:03.0/sound/card0/input9
snd_hda_intel 0000:00:1b.0: irq 61 for MSI/MSI-X
input: HDA Intel PCH Mic as /devices/pci0000:00/0000:00:1b.0/sound/card1/input10
input: HDA Intel PCH Headphone as /devices/pci0000:00/0000:00:1b.0/sound/card1/input11
Change-Id: Ifa587984be4fc2801704a0368b9cdf8379c2450e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59336
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4318
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
No need to show the choice of USB port or controller in case of older
hardware where location for usbdebug was hardwired.
Change-Id: Ia186bf2c6ed60be2834cf6fd0a1965c8bf81ed4d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/4290
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
- updates from 1.6.0 ref code
- remove the step comments as they are no longer even close
- add constants for LPT revisions
build and boot on Falco
Check that RCBA+2300[1] is set:
> mmio_read32 0xfed1e300
0x00000002
Change-Id: I8b3c5fda3f3170455699a7834239cb991603e7a8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59821
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4326
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There's a need to determine if a specific gpio pin is
is set up to be a native function or not. Implement this.
Change-Id: I91d57a549e0f4fddc0b1849e5f74320fc839642c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59589
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4324
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The BIOS spec for LynxPoint calls out additional
programming steps for the PCIe Root Ports. Implement those
steps from the BIOS spec. These steps are completed before
deeper PCIe probing. The "late" programming was removed as
that was applicable to Cougar/Panther point where this
code was originally copied, though there was some overlap.
Change-Id: I64f25e4451e035d98ca6b66b0335bd280b70b074
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59558
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4323
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
PCIe Root Ports should be disabled based on pin ownership
and the strapping configuration. Implement this logic
for LynxPoint. The chip_ops->enable_dev() path is no
longer used. Instead the PCIe driver handles the enabling
and disabling of devices. This allows for having an empty
or incomplete device tree since those "allocated" devices
do not travel through the chip_ops->enable_dev() path.
The coalescing was tested to be working properly, however
not all configurations were tested.
Change-Id: I1e8bfe5e447b72ff8a4b04b650982d8c1ae0823c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59424
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4322
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
mainboard_smi_gpi has recently been updated to take a u32 argument from a
u16, but the patch introducing the fsp_bd82x6x support has been verified
on a master before this change, thus resulting in a 'cast from incompatible
type' error. Update the pointer to the correct size argument.
Change-Id: I9d62ee43f7c8ed774898f54d29a87cf463b76e91
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4479
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Add support for the bd82x6x using the Intel FSP.
The FSP is different enough to warrant its own source files
for now. The mrc/system agent chromebook solution does much more
southbridge initialization and configuration than the FSP version.
It may be combined in the future.
Change-Id: Ie493945f3d321d854728d231979a0c172d2b36de
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/4017
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Ibexpeak shares few files with bd82x6x. In order for it to work correctly
their config structures from chip.h must match, so include bd82x6x/chip.h
in ibexpeak/chip.h
Change-Id: Ib56b311b8af04f4e4803d1834724680f604901cd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4277
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
LynxPoint-LP has a lot of GPEs and the "default" set has been
moved to register 4 starting at bit offset 96. This means
that PME_B0 bit in GPE0_EN/GPE0_STS is now bit 109 in LPT-LP
but still bit 13 in LPT-H.
suspend on falco and wake from usb
4 | 2013-06-19 10:49:17 | ACPI Enter | S3
5 | 2013-06-19 10:49:22 | ACPI Wake | S3
6 | 2013-06-19 10:49:22 | Wake Source | Internal PME | 0
Change-Id: I443cd4d17796888debed70c0bda27ae09accd09b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59265
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4253
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Do not directly check the return value of get_option, but instead compare
the returned value against a CB_CMOS_ error code, or against CB_SUCCESS.
Change-Id: I2fa7761d13ebb5e9b4606076991a43f18ae370ad
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/4266
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some of the pcie logic was located in pch.c as well
as pcie.c. Move all pcie logic to the same pcie.c
file. This is a straight cut-and-paste (no logic changes)
except for a rename from pch_pcie_enable() ->
pch_pcie_enable_dev().
Change-Id: I338c53039b95f255ab9ced313c51193a9d34b404
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59277
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4251
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The function to disable devices was formerly named
pch_hide_devfn(). This routine was doing more than hiding
devices. It was disabling them, i.e. turning them off.
Therefore, rename it to pch_disable_devfn(). Also, allow
external callers to this function.
Change-Id: Id5bb319d4e67892c02a39dff49e45b2811a2f016
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59276
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4250
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The iobp functions are useful to may of the southbridge
devices as certain values need to be updated to properly
initialize the devices. Therefore expose read, write, and
updated iobp functions.
Change-Id: Id7fdd8d0d9f022f92d6285ecd8f85a52024ec2bb
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/59275
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4249
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
There are useful values in NVS that are set at boot
and runtime and they should not be cleared on resume.
suspend/resume twice on slippy and ensure
that the USB ports are still powered on the second suspend.
Change-Id: I4bce60b02b6637f6683120ae9c4a5c64563aacf7
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56941
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4210
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
If Vortex86EX PS/2 keyboard controller system flag bit times out,
reload controller firmware code and try again.
Abort and die after 11 tries as this means the CPU is defect. Also
inform the user by printing a message.
Change-Id: I24aec4b20d85c721c01e72686f3eb1259f9334b8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3988
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Previously, I've set this config in mobo config, yet according to
Kyösti Mälkki this parameter is southbridge-specific and not
mobo-specific.
Change-Id: I92428aed5a69d88a371f5d7267bc54ba7530766c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4276
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
The wake device input pins are active low and the
GPIOs need to be set as inverted when they are marked
as an input so they are not spuriously logged.
suspend/resume on slippy with trackpad wake:
8 | 2013-05-29 07:43:14 | ACPI Enter | S3
9 | 2013-05-29 07:43:18 | ACPI Wake | S3
10 | 2013-05-29 07:43:18 | Wake Source | GPIO | 12
and with power button wake:
11 | 2013-05-29 07:43:35 | ACPI Enter | S3
12 | 2013-05-29 07:43:40 | EC Event | Power Button
13 | 2013-05-29 07:43:40 | ACPI Wake | S3
14 | 2013-05-29 07:43:40 | Wake Source | Power Button | 0
Change-Id: I15d38dcc9b2fb4b2b0eb27da358fa3c343e22323
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56940
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4209
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Both EHCI and XHCI controllers have additional setup steps
that are not part of the PEI reference code so they need to
be done later.
Both controllers also have specific clock gating setup
requirements that are now implemented.
Additionally they both have specific requirements when entering
sleep states. XHCI needs something in S3/S4/S5 and EHCI only
has steps for S4/S5 entry.
Change-Id: Ic62cbc8b6255455e56b72dd5d52e27a311999330
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57033
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4217
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is an LPT-LP specific method that will enable a specific
GPIO as an ACPI SCI wake source.
It can be used by a device _DSW method to enable a pin that is
otherwise not configured to generate SCI at runtime.
It will set:
- GPIO owner to ACPI
- GPIO route to SCI
- GPIO config to GPIO, Input, Inverted
Also clean up and remove ACPI field definitions that are unused
and/or incorrect.
Change-Id: I14acc2de50e6200f61c2898a7bd1252400e0f0be
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56621
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4189
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
LynxPoint-LP has an additional 16 entries in the IOAPIC that
can be assigned to specific GPIOs when they are configured
as PIRQ.
The maximum redirection entries field in the IOAPIC needs to
be set to 0x27 when this is enabled.
Additionally specific GPIOs need to be routed to PIRQ so they
interrupt via the IOAPIC instead of the GPIO IRQ 14/15.
Change-Id: Ie587e1d203422ff6fb7fc5056d20a5ae66720991
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56620
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4203
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ssdt2 generation code was calling acpigen_patch_len().
However, none of the entries had AML object lengths that
needed patching. That resulted in the following message:
ASSERTION FAILED: file 'src/arch/x86/boot/acpigen.c', line 52
Additionally, this caused an errant write to a memory address
whose value was in the variable ltop. This was the 0 address.
Change-Id: I44abf5a4e4225220575aee6b5c9bb6b0be093a28
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56299
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/4182
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ACPI code was defining two EHCI controllers and ignoring
the XHCI controller. This changes the second EHCI controller
to be XHCI instead and changes the wake resource to indicate
S3 and not S4.
cat /proc/acpi/wakeup
Device S-state Status Sysfs node
HDEF S4 *disabled pci:0000:00:1b.0
EHCI S3 *enabled pci:0000:00:1d.0
XHCI S3 *enabled pci:0000:00:14.0
Change-Id: If28775e6ef8608c22c85ca91d91d1f598ec7755d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56263
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4181
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Enable GPIO SMI for GPIO34 and set it as inverted so it
is only generated when it is raised by the EC.
1) ec console command: lidopen
2) wait until booted to developer screen
3) ec console command: lidclose
4) ensure system turns off
Change-Id: I7d50f171f3f4539c7c264103d1ffc7c5d0f1c7ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56052
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4177
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
The vendor ids were never updated to reflect LynxPoint's device
ids. Therefore, none of the initialization was being ran. Fix
this.
Change-Id: Ic6ec00c9fb1cbcb6087fd89b0acff3d83294ac6a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/55821
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4173
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to report whether coreboot enabled a SerialIO device
in ACPI mode we had been relying on reading NVS in the _STA
method for the SerialIO device.
The ACPI _STA method has restrictions on what it can access
and is unable to access OperationRegions outside its scope
which means it should not be trying to read NVS.
This change adds a new SSDT to the ACPI tables and fills it
with constants that indicate whether or not a device is enabled
in ACPI mode.
The ACPI code is changed to read these variables from the
SSDT and use that instead of trying to query a variable in NVS.
Attempt to use lpt-clk driver to probe the
device clocks for SerialIO devices and see that the kernel
does not complain about accessing the GNVS region.
Change-Id: I8538bee4390daed4ecca679496ab0cb313f174ce
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51369
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4170
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Disable EC software sync for now
- Report correct EC active firmware mode
- Force enable developer mode by default
- Set up PCH generic decode regions in romstage
- Pass the oprom_is_loaded flag into vboot handoff data
Change-Id: Ib7ab35e6897c19455cbeecba88160ae830ea7984
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/51155
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4169
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to probe the gpio-lynxpoint kernel driver the
LP GPIO controller needs to be exposed as a specific
ACPI device.
This also allows the resources to be exposed to the OS via
this device instead of the catch-all LPC device.
Ensure the driver loads at boot:
gpiochip_find_base: found new base at 162
gpiochip_add: registered GPIOs 162 to 255 on device: INT33C7:00
Also ensure the driver is visible in sysfs:
$ cat /sys/devices/platform/INT33C7:00/gpio/gpiochip162/label
INT33C7:00
Change-Id: I9f79c008f88da9b67ed1cdfdb9d3a581ce8f05ff
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/50215
Reviewed-on: http://review.coreboot.org/4158
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that we have RW ramstage we don't need to have the
management engine lock down step done in a final SMM.
ME: mkhi_end_of_post
ME: END OF POST message successful (0)
PCI: 00:16.0: Disabling device
Change-Id: I9db4e72e38be58cc875c1622a966d8fcacc83280
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49757
Reviewed-on: http://review.coreboot.org/4153
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There were two undefined MBP types that are now defined.
These include NFC status and some interesting timing data.
ME: Wake Event to ME Reset: 6 ms
ME: ME Reset to Platform Reset: 7 ms
ME: Platform Reset to CPU Reset: 51 ms
Change-Id: I67bf1f303f3c32497041e64c40eb9ccb6a63d88a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49756
Reviewed-on: http://review.coreboot.org/4152
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead of having an OS re-parse cbmem book-keeping records
for the cbmem allocator just to get the console buffer export
the pointer to the memory console directly in a field named 'CBMC'.
This field lives in the GNVS table.
Change-Id: Ief0c4da7b18df66feb9c816c9f4abdf5a72bd3a4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49764
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/4149
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Slight tweaks found when looking at latest ref code when
investigating package C-state issues.
A few bits in the clock gating register don't match the
documentation and are also cleaned up.
Change-Id: I36ced7280c160b114c70b2eeafc8b24813ff2f6a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49330
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4142
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Part of X201 port.
Change-Id: If17d707004aba9f08459dbd8f3a146fa3c076aa9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/4052
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
This reads PCH power levels via PCODE mailbox and writes the
values into the PMSYNC registers as indicated in the BWG.
Change-Id: Iddcdef9b7deb6365f874f629599d1f7376c9a190
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49329
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4143
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This will be used in a later commit to do some specific
power sequencing.
Change-Id: Id7f033bb80aed915c2498ea910cb3ac7290da37f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48947
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4137
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This adds some macros for the common GPIO defines and drops
the gpio number definition from each entry. The end result
is much easier to read. The wtm2 mainboard gpio list is modified
to use this.
Also fix a bug in the LP version of get_gpio() that was always
returning zero due to a miscompare.
Change-Id: I143e5aee412af1eda84e35f8026f31cf13df508e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48946
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4138
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
With the LynxPoint chipset there are more than 16
possible GPIOs that can trigger an SMI so we need
a mainboard handler that can support this.
There are only a handful of users of this function
so just change them all to use the new prototype.
Change-Id: I3d96da0397d6584f713fcf6003054b25c1c92939
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/49530
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4145
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Move into src/cpu/dmp/dmp_post_code.h
Change-Id: If9f4d842f352eb41618e71f49a226d3cc4ad0b46
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3989
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Besides the AGESA static settings, the settings in mainboard/buildOpt.c also
change the final configuration. We need to make sure the settings in FchParam
in resume stage are the same as they were in cold boot stage, otherwise the
board can not wake up more than once.
Tested on AMD/Olive Hill, AMD/Parmer and ASRock/imb-a180.
(USB keyboard doesn't work when board wakes up. It is not introduced by this
patch. It needs more debugging.)
Change-Id: I5a5e5502080e358ffc3577dc6a40bb762844d998
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/3932
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Removing `-Wno-unused-but-set-variable` from `CFLAGS` the build for
QEMU Q35 and Roda RK9, both using the Intel 82801Ix southbridge, fail
with the following error.
src/southbridge/intel/i82801ix/lpc.c: In function 'i82801ix_enable_apic':
src/southbridge/intel/i82801ix/lpc.c:45:5: error: variable 'dummy' set but not used [-Werror=unused-but-set-variable]
cc1: all warnings being treated as errors
Removing `dummy` should be safe as GCC probably optimizes it away before
anyway. That no dummy variable is used for an RCBA [1] access in Intel
Lynx Point supports that this can be dropped safely.
[1] root complex base address
[2] src/southbridge/intel/lynxpoint/early_pch.c
Change-Id: I1c138a3498228dbd025f68d5e6af0acc29ed3460
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3982
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Don't check keyboard controller system flag until before calling
pc_keyboard_init(). This makes waiting time shorter.
Change-Id: I2cdb533a5b25575e1717434533a60decf748f6d8
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3958
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The main usbdebug file lib/usbdebug.c was removed from romstage
build with commit f8bf5a10 but the chipset-specific parts were not,
leading to unresolved symbol errors for AMD platforms.
Add a silent Kconfig variable USBDEBUG_IN_ROMSTAGE for convenient
use of this feature.
Change-Id: I0cd3fccf2612cf08497aa5c3750c89bf43ff69be
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3983
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This is needed to apply a rule that get_top_of_ram() in romstage is
required to select HAVE_ACPI_RESUME, otherwise chipset/board has no
means to backup low memory to CBMEM on s3 resume.
Only board affected is asus/p2b.
Change-Id: Ia5cbf4e5e40af25f52a19de584d8bc5370487154
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3971
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Linux unhelpfully "fixes" the value in PCI_BASE_ADDRESS_1 when it is
0xfec00000 (that is, outside the range of bus 0 address space). This
causes IOAPIC interrupts to fail to work under Linux. This issue was
originally unnoticed by me when testing as sanity checking such as
this is not done by NetBSD.
Hiding the IOAPIC BAR is done by the OEM BIOS on the ck804 boards I've
checked.
Change-Id: I736db163750f709d68c988fac075597a50b29ab7
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3963
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Ibdd438455a545aa9266b0fd893d5ff27124ab22c
Signed-off-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-on: http://review.coreboot.org/3961
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Call pc_keyboard_init function in southbridge. It makes PS/2
keyboard work in coreinfo payload.
Change-Id: Idb79f87b09eeeade94e966fb8769dec7578e2cf5
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3957
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Qemu has the fw_cfg interface at 0x510, which conflicts with
power management base address in coreboot. Move the pmbase to a
non-conflicting address. No need to worry about speedstep, it
is not supported by qemu and isn't enabled in the qemu config.
Change-Id: I3e87d8301988028ca0ea7d96c08b4e26ac15a7c2
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-on: http://review.coreboot.org/3938
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Chipsets sb700 and sb800/hudson have more than one USB EHCI controller,
implement the selection logic using already existing Kconfig option.
Change-Id: I9e0df1669d73863c95c36a3a7fee40d58f6f097e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3928
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Northbridge code includes these headers, so they all need to
have the same name to allow different combinations of northbridge
and southbridge. This changes the sb900 names to match sb700 &
sb800, and points agesa/family12 and amd/torpedo to the new file
names.
Change-Id: I7a654ce9ae591a636a56177f64fb8cb953b4b04f
Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Reviewed-on: http://review.coreboot.org/3825
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This retrieves back the value stored with store_initial_timestamp()
in the bootblock for southbridge.
Change-Id: I377c823706c33ed65af023d20d2e4323edd31199
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Clean whitespace errors that have gotten past lint-stable-003-whitespace
and gerrit review.
Change-Id: Id76fc68e9d32d1b2b672d519b75cdc80cc4f1ad9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3920
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
AMD northbridges have a complex way to resolve top_of_ram.
Once it is resolved, it is stored in NVRAM to be used on resume.
TODO: Redesign these get_top_of_ram() functions from scratch.
Change-Id: I3cceb7e9b8b07620dacf138e99f98dc818c65341
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3557
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I46e69154cf576ddb642c34b6dd2bc0d27cc19b7e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3811
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: Ie6776b04ca0ddb89a0843c947f358db267ac4a70
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3809
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add option to choose one of the EHCI controllers in recent
intel chipsets for usbdebug use.
Since EHCI controller function changes from 0:1d.7 to 0:1d.0 in
rcba_config() for some mainboards, check the PCI class code
for match.
Change-Id: I18a78bf875427c163c857c6f0888935c1d2a58d4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3440
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Nowadays, chipsets or boards do not only have one USB port with the
capabilities of a debug port but several ones. Some of these ports are
easier accessible than others, so making them configurable is also necessary.
This change adds infrastructure to switch between EHCI controllers,
but does not implement it for any chipset.
Change-Id: I079643870104fbc64091a54e1bfd56ad24422c9f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3438
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
On AMD platforms, setting of USBDEBUG_DEFAULT_PORT=0 tries to scan
all physical ports one after other in incrementing order. To avoid
possible problems with other USB devices, one can select the port
number here and bypass the scan.
Intel platforms can communicate with usbdebug dongle on one
physical port only, and this option makes no difference there.
Change-Id: I45be6cc3aa91b74650eda2d444c9fcad39d58897
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3872
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
src/southbridge/amd/agesa/hudson/Kconfig config default value,
mainboard Kconfig config value for specific mainboard.
bit 1,0 - pin 0
bit 3,2 - pin 1
bit 5,4 - pin 2
bit 7,6 - pin 3
Change-Id: I54a87cf734685515a3e1850838ca7d94387172ce
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3879
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Declare the functions that may be used in both romstage and ramstage
with simple device model. This will later allow to define PCI access
functions for ramstage using the inlined functions from romstage.
Change-Id: I32ff622883ceee4628e6b1b01023b970e379113f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3508
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Letting SMI handler touch EHCI controller is an excellent source
of USB problems. Remove usbdebug entirely from SMM.
It may be possible to make usbdebug console work from SMM
after hard work and coordination with payloads and even
OS drivers. But we are not there.
Change-Id: Id50586758ee06e8d76e682dc6f64f756ab5b79f5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3858
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
The _OSC method is used to tell the OS what capabilities it can
take control over from the firmware. This method is described
in chapter 6.2.9 of the ACPI spec v3.0. The method takes 4
inputs (UUID, Rev ID, Input Count, and Capabilities Buffer) and
returns a Capabilites Buffer the same size as the input Buffer.
This Buffer is generally 3 Dwords long consisting of an Errors
Dword, a Supported Capabilities Dword, and a Control Dword.
The OS will request control of certain capabilities and the
firmware must grant or deny control of those features. We do not
want to have control over anything so let the OS control as much
as it can.
The _OSC method is required for PCIe devices. During Linux boot,
an error is logged to dmesg if _OSC is not found.
Change-Id: Icf6e7a82284d03d23fd30ee7b7db17754e988c9a
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3823
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Adding the 'WordBusNumber' macro to the PCI0
CRES ResourceTemplate in the AMD FCH ACPI code.
This sets up the bus number for the PCI0 device
and the secondary bus number in the CRS method.
This change came in response to a 'dmesg' error
which states:
'[FIRMWARE BUG]: ACPI: no secondary bus range in _CRS'
By adding the 'WordBusNumber' macro, ACPI can set
up a valid range for the PCIe downstream busses,
thereby relieving the Linux kernel from "guessing"
the valid range based off _BBN or assuming [0-0xFF].
The Linux kernel code that checks this bus range is
in `drivers/acpi/pci_root.c`. PCI busses can have
up to 256 secondary busses connected to them via
a PCI-PCI bridge. However, these busses do not
have to be sequentially numbered, so leaving out a
section of the range (eg. allowing [0-0x7F]) will
unnecessarily restrict the downstream busses.
Change-Id: Ib2d36f69a26b715798ef1ea17deb0905fa0cad87
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3822
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Split the Family16 (Kabini) DSDT file into logical regions.
Olive Hill is the only mainboard and Kabini is the only NB/CPU
currently using Family16 AGESA code.
Change-Id: I9ef9a7245d14c59f664fc768d0ffa92ef5db7484
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3821
Tested-by: build bot (Jenkins)
Hook this up into the DMP Vortex86EX. Before under Windows XP
the microphone did not work. With the new logic it does. Now
line-in,line-out and microphone all work.
The verb data table is generated by Realtek.
Change-Id: I1bcef898a15547c86c12c4b52ce0069d13e23c84
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3855
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
These Kconfig entries were forgotten from the commit
that re-enabled usbdebug for these southbridges.
Change-Id: Ia17f1dd3340408da7c033c2c949404d2636bed44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I58c4b021ac87a035ac2ec2b6b110b75e6d263ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3810
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Rearranged the F2A85-M DSDT file to match the functionality found
on Parmer. As with the Parmer implementation, the F2A85-M dsdt.asl
file in the mainboard directory contains only #include references to
the appropriate files.
As with Parmer, some include files have no content but are left as a
template for other platforms and as placeholders for completing the
ACPI implementation for F2A85-M.
Change-Id: Ic72cb6004538ca9d9f79826b9b3c8d6aeb25017c
Signed-off-by: Kimarie Hoot <kimarie.hoot@se-eng.com>
Reviewed-on: http://review.coreboot.org/3805
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin@se-eng.com>
Support code for sb700 and sb800 existed already, but Kconfig and
compile-time issues prevented from enabling USBDEBUG for boards
with the affected AMD southbridges.
Change-Id: I49e955fcc6e54927320b9dc7f62ea00c55c3cedf
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3439
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
With USBDEBUG selected, the file is built for both romstage and
ramstage. For the ramstage build, we need to explicitly use the
simple PCI config operations without devicetree.
Change-Id: I2de8d9c77bb458ba797c3aac9e2cd0d653e06684
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
This patch sets a bit in the Yangtze southbridge to enable
the extra protocol necessary to handle port multiplier chips.
This has been turned on during most of Kabini development
without any notable impact. Olive Hill has an optional daughter
board that incorporates Silicon Image Steel Vines chips. This
change has been tested with and without the daughter board. This
change can be regression tested using any Hudson-based motherboard,
although it has no impact on boards with discreet Hudson/Bolton
southbridges.
This was tested for impact on SATA performance in the absence of
a port multiplier using the IOZone benchmarks within the Phoronix
Test Suite. A SATA 3 hard drive (6.0 Gbps) and an SSD were
connected to the ports on Olive Hill without using the port
multiplier card. The test results contained more run-to-run
variation within the same configuration than was seen in the
aggregate results comparing the interface with and without the
port multiplier protocol additions. In other words, the test
had less accuracy than the impact caused by turning on port
multiplier support.
Change-Id: Ie87873b093f3e2a6a5c83b96ccb6c898d3e25f72
Signed-off-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3808
Tested-by: build bot (Jenkins)
Yangtze uses Hudson AGESA wrapper code but has some changes.
The changes are necessary and have no effects on Hudson.
Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I71923790aa03e51db01ae3a4745e1c44556d281f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3812
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The tests for __PRE_RAM__ or __SMM__ were repeatedly used
for detection if dev->ops in the devicetree are not available
and simple device model functions need be used.
If a source file build for ramstage had __PRE_RAM__ inserted
at the beginning, the struct device would no longer match the
allocation the object had taken. This problem is fixed by
replacing such cases with explicit __SIMPLE_DEVICE__.
Change-Id: Ib74c9b2d8753e6e37e1a23fcfaa2f3657790d4c0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3555
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Directory intel/common must be conditionally added in the list
of source directories, as the parent directory southbridge/intel
is unconditionally added even for boards without such device.
Change-Id: I7088bc6db9f56909ffa996aa7eff76cd72e177eb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3827
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Split the Parmer, Family 15tn, and Hudson DSDT into groups. This splits
the DSDT table into includable ASL files which carry details specific
to the Family 15tn APU, the Parmer platform, and the Hudson FCH. The
dsdt.asl file in the mainboard directory contains only #include
references to the appropriate files.
Initially, this split was done by moving each piece of functionality
into its own file (e.g. IRQ routing and mapping, processor tree, sleep
states and sleep methods, etc.) and those pieces were #included in
dsdt.asl to ensure an exact match (via acpidump/acpixtract/iasl -d)
with the extant version of the table. Once the new tables were found
to exactly match the existing tables, the pieces were rearranged into
reasonable groups (e.g. fch.asl, northbridge.asl, pci_int.asl, etc.).
Some include files have no content but are left as a template for
other platforms and as placeholders for completing the ACPI
implementation for Parmer (e.g. thermal.asl, superio.asl, ide.asl,
sata.asl, etc.).
Change-Id: I098b0c5ca27629da9bc1cff1e6ba9fa6703e2710
Signed-off-by: Steve Goodrich <steve.goodrich@se-eng.com>
Reviewed-on: http://review.coreboot.org/3629
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Routes IRQs for USB device, SPI1, MOTOR, HD audio, CAN bus.
Change-Id: I995a5c6d3ed6a7dca4f0d21545c928132ccbbc21
Signed-off-by: Andrew Wu <arw@dmp.com.tw>
Reviewed-on: http://review.coreboot.org/3725
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These are not specific to Intel. Further work needs to be done to
combine these with MMCONF_SUPPORT in arch/io.h.
Change-Id: Id429db2df8d47433117c21133d80fc985b3e11e4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3502
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Without that fix, and with CONFIG_SMM_TSEG, we have:
src/southbridge/intel/i82801gx/smihandler.c: In function 'southbridge_smi_sleep':
src/southbridge/intel/i82801gx/smihandler.c:340:3: error: implicit declaration of function 'smi_release_lock' [-Werror=implicit-function-declaration]
cc1: all warnings being treated as errors
make: *** [build/southbridge/intel/i82801gx/smihandler.smm.o] Error 1
The fix is modelled after src/cpu/x86/smm/smihandler.c which
ifdefs smi_release_lock().
Change-Id: Icdc6d039b34a1d95d0e607419bba2484d21abc5e
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3281
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This mistake was spoted by comparison with the
src/southbridge/intel/bd82x6x/smihandler.c file.
Change-Id: I1516f0131d524bd7d001e6780e9a45402d1814d1
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Reviewed-on: http://review.coreboot.org/3303
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add an option to mark all SPI regions write protected on each S3 resume.
We were used to lock the SPI interface in the payload which isn't run on
the resume path. So we have to do it here.
For the write protection to be effective, all write opcodes in the
opmenu have to be marked correctly (as write operations) and the whole
SPI interface has to be locked. Both is already done.
Change-Id: I5c268ae8850642f5e82f18c28c71cf1ae248dbff
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3594
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
All the additional work that needs to be done in EHCI BAR relocation
is independent of the hardware platform and was functionally identical
in all the copies removed.
When USBDEBUG is not selected, PCI EHCI controllers use standard
pci_dev_read_resources() call.
With USBDEBUG selected, PCI EHCI controller's device_operations
.read_resources is replaced with pci_ehci_read_resources() call,
which in turn will replace the device_operations .set_resources call.
The replacement for .set_resources reconfigures usbdebug driver side,
and calls the original .set_resources to configure hardware side.
Change-Id: I8e136a5da4efedf60b6dd7068c0488153efaaf8e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3412
Reviewed-by: Aaron Durbin <adurbin@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch is based on 'AMD S3: Program the flash in a bigger data packet'[1]
Some AMD south bridge can write bigger data when saving S3 info.
In this patch, I use config 'AMD_SB_SPI_TX_LEN' to contral data size.
AMD_SB_SPI_TX_LEN is defined in 'src/southbridge/amd/Kconfig'
and then can be overridden in the Kconfig for specific
southbridges that support larger size.
I have tested on AMD Parmer and Thatcher. We will release a new board
whose south bridge can transfer more than 4 bytes each time.
[1] http://review.coreboot.org/#/c/2306/
Change-Id: Id984955d46eae487e39d45979f1a90054aa9f54b
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/3413
Tested-by: build bot (Jenkins)
Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This change inserts a type cast to eliminate a compiler warning.
Change-Id: If223f61f1565caeadb1b7e0762975b1b2412eda5
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3541
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The xHCI controller's MMIO space has a length of 64KiB not 4KiB.
Therefore, setting the xHCI BAR to 0xe8001000 worked the same like
setting it to 0xe8000000, as bit12 is reserved and ignored. This again
interfered with the MMIO space of the first EHCI controller and broke
S3 resume on Ivy Bridge.
AFAIK, the MRC ignores the setting of the xHCI BAR, anyway. So just drop
these lines.
Change-Id: I8af9c2ba34133f15636a9056fc8880b3b6ab95e0
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3521
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Current build configuration always wants to include an Intel Management
Engine firmware (me.bin) on Sandy Bridge systems. However, we can have
a working coreboot without it, as long as the factory delivered ME
firmware is kept untouched in the flash ROM. So let the user decide if
a ME firmware will be included in the build.
Change-Id: I9a1cc29d4940ba22355eb9e653606e436f07e04c
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3522
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
On newer Intel systems, the flash ROM is shared between the host
processor (BIOS), it's Management Engine (ME) and an integrated ethernet
controller (GbE). The layout of the flash ROM (and other information) is
kept in the so called Intel Firmware Descriptor (IFD). If we only want
to build coreboot to update the BIOS section, all we need is the flash
layout.
This patch adds the option to specify the flash layout in the
mainboard's Kconfig, and thus, to build without the real IFD. However,
with such a build, one has to make sure that the IFD section on the
flash ROM won't be written over (nor any other section that hasn't been
included by coreboot). A patch to write selected sections of a flash ROM
with IFD has been sent to the flashrom mailing list [1].
[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
Change-Id: Ia23e439a00a197fb54852263f8e206f16c3e8851
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/3524
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
LynxPoint LP has only EHCI controller #1.
Change EHCI #2 to different BAR from EHCI #1.
Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.
Change-Id: I95c59fb9d5f09afd152872e9bc0418dc67e4aeb2
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3472
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@google.com>
Change EHCI #2 to different BAR from EHCI #1.
Even if the ECHI controllers are not to be addressed, it is bad idea
to set two different devices to claim the same PCI memory cycles.
Change-Id: Ib6f7cfac5acf3f8170508547d1584af90273e8c1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3471
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.huber@secunet.com>
Upgrade the ICH7 bootblock to store an initial timestamp like we do it
since Sandy Brigde. I've checked the datasheets for the used scratchpad
registers and grepped for their usage. I'm pretty sure that they aren't
used on any ICH7 based board (for anything before the usual S3-resume
indication).
Change-Id: I28a9b90d3e6f6401a8114ecd240554a5dddc0eb5
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: http://review.coreboot.org/3498
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
All 3 boards with AGESA_HUDSON had HAVE_HARD_RESET with the reset.c
file already placed under southbridge/.
All 15 boards with CIMX_SBx00 had HAVE_HARD_RESET with functionally
identical reset.c file under mainboard/. Move those files under
respective southbridge/.
Change-Id: Icfda51527ee62e578067a7fc9dcf60bc9860b269
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3486
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
To have USB 3.0 support the XHCI controller needs to be enabled
and the xhci.bin firmware needs to be added to CBFS.
Change-Id: I0b641b30b67163b7dc73ee7ae67efe678e11c000
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3464
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
They were hard-coded to be copied from 3rdparty/ which isn't always
the right choice.
Since the defaults stay the same, this should be compatible.
Change-Id: If2173bef86ad1fcf2335e13472ea8ca41eb41f3d
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3453
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The original lines had contradicting comment and code.
This change follows the code and sets MASTER bit too.
Change-Id: Id2886bfc107612530f0e9747e5d49a9740fb8532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3466
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
This patch provides the correct SD controller timings for
the Family16 device. It also will remove the SD controller
from PCI space when device 0:14.7 is set to off in devicetree.
This was tested on a AMD Parmer board and a AMD G-series SOC
reference board. The settings were found in the AMD
Hudson2 RRG and family16 BKGD.
Change-Id: I6d7e7997ddc39802ab75dc8a211ed29f028c0471
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3348
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In case with EARLY_CONSOLE, this printk is called before any other
console is configured to transmit data. This outputs garbage on
CONSOLE_SERIAL as baudrate is not yet programmed.
For case without EARLY_CONSOLE, the order in which different console
drivers initialize is obscure. Might sometimes work properly.
Change-Id: I3792161e0a6dc17e17262048cc9136044dd69dc5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3384
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Setting IRQ delivery to FSB got lost in the rebase process
for commit e6143531.
I captured following error on dmesg and this patch fixes it for
i82801dx.
..TIMER: vector=0x30 apic1=0 pin1=2 apic2=-1 pin2=-1
..MP-BIOS bug: 8254 timer not connected to IO-APIC
...trying to set up timer (IRQ0) through the 8259A ...
..... (found apic 0 pin 2) ...
....... failed.
...trying to set up timer as Virtual Wire IRQ...
..... works.
Change-Id: I0768976cc6b0deab213ad9bd4771e0f278de634c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3371
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Mapping is as follows: bit 15 corresponds to GPIO15 ... bit 0 corresponds to
GPIO0.
Change-Id: I661ce56d9373887270ba3c0518892fbbe6d9de7c
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/3436
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently in Intel BD82x6x southbridge’s `Makefile.inc` the
file `usb_debug.c` is added twice to the build.
This was introduced in
commit 4063ede3fb
Author: Ronald G. Minnich <rminnich@google.com>
Date: Mon Feb 4 20:31:51 2013 -0800
bd82x6x: Fix compiling with USB debug port support
Reviewed-on: http://review.coreboot.org/2784
but was unneeded because it had been already added in
the following commit.
commit 4141993536
Author: Sven Schnelle <svens@stackframe.org>
Date: Sat Jul 28 08:52:44 2012 +0200
bd82x6x: Fix CONFIG_USBDEBUG
Reviewed-on: http://review.coreboot.org/1376
Therefore basically revert that hunk.
There is no policy on how to order these additions, so leave
it to a possible separate commit, unifying this.
Kyösti Mälkki suspects that these additions were meant for
the Intel Lynx Point [1].
[1] http://review.coreboot.org/#/c/3424/
Change-Id: Iaa8de6fcc0d6f3a0a92a28fcb603d7777aa8b24c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3425
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix obvious mistake in cycle that displays GPI status
I hope i found all duplicates of it.
Change-Id: Ic21ff3ecab85953463e5c23daf808dd5edc82ff8
Signed-off-by: Konstantin Aladyshev <aladyshev@nicevt.ru>
Reviewed-on: http://review.coreboot.org/3435
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a common implementation of SMBus functionality for early chipsets. Note
however, that existing via chipsets are not ported to this code. Porting
will require hardware testing to make sure everything is fine.
This code is used in the VIA VX900 branch.
Change-Id: If5ad8cd0942ac02d358a0139967e7d85d395660f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/144
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Change-Id: Ica3afbf8277cb025251da7af181f8de0d0036b45
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/3389
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
There is no need to use everywhere BIOS_ERR.
Change-Id: If33d72919109244a7c3bd96674a4e386c8d1a19e
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-on: http://review.coreboot.org/3307
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Denis Carikli <GNUtoo@no-log.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Remove local copies of reading and writing I/O APIC registers by
using already available functions.
This change is similar to
commit db4f875a41
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Jan 31 17:24:12 2012 +0200
IOAPIC: Divide setup_ioapic() in two parts.
Reviewed-on: http://review.coreboot.org/300
and
commit e614353194
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting 82801a/b/c/d IOAPIC ID
Reviewed-on: http://review.coreboot.org/2532
and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.
As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].
[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
Change-Id: I6f2559f1d134590f781bd2cb325a9560512285dc
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3182
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Remove local copies of reading and writing I/O APIC registers by
using already available functions.
This change is similar to
commit db4f875a41
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Jan 31 17:24:12 2012 +0200
IOAPIC: Divide setup_ioapic() in two parts.
Reviewed-on: http://review.coreboot.org/300
and
commit e614353194
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting 82801a/b/c/d IOAPIC ID
Reviewed-on: http://review.coreboot.org/2532
and uses `io_apic_read()` and `io_apic_write()` too. Define
`ACPI_EN` in the header file `pch.h`.
As commented by Aaron Durbin, a separate `pch_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].
[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
Change-Id: I4478b1902d09061ca1db8eab6b71fef388c7a74c
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3183
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Apparently the files `smbus.{h,c}`, where never used and therefore
build beforehand. Needing one function in them for the ASUS F2A85-M
the build fails as some headers are missing. Including the headers
`stdint.h` and `io.h` fixes the following errors.
[…]
CC southbridge/amd/agesa/hudson/smbus.romstage.o
In file included from src/southbridge/amd/agesa/hudson/smbus.c:23:0:
src/southbridge/amd/agesa/hudson/smbus.h:67:24: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:67:43: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:67:55: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:68:25: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:68:44: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:68:56: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:68:69: error: unknown type name 'u8'
src/southbridge/amd/agesa/hudson/smbus.h:69:24: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:69:43: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:70:24: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:70:43: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:70:55: error: unknown type name 'u8'
src/southbridge/amd/agesa/hudson/smbus.h:71:20: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:71:35: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:71:49: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:71:59: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:71:69: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:72:20: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:72:35: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:72:49: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:72:59: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:73:20: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:73:32: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:73:44: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.h:73:54: error: unknown type name 'u32'
src/southbridge/amd/agesa/hudson/smbus.c: In function 'smbus_delay':
src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'outb' [-Werror=implicit-function-declaration]
src/southbridge/amd/agesa/hudson/smbus.c:27:2: error: implicit declaration of function 'inb' [-Werror=implicit-function-declaration]
[…]
Probably all the (AMD(?)) `smbus.{h,c}` suffer from this and
should be fixed. Even better, as these function do not differ
between most boards, the file should be moved out from the
specific southbridge directories.
[1] http://qa.coreboot.org/job/coreboot-gerrit/6168/testReport/junit/(root)/board/i386_asus_f2a85_m/
Change-Id: I285101fa06a365da44fa27b688c536e614d57f50
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3202
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Currently the code in the if statement
if (!byte)
do_smbus_write_byte(0xb20, 0x15, 0x3, byte);
only gets executed if `byte == 0x0`, that means only in the
default case where RAM voltage is 1.5 Volts. But the RAM voltage
should be changed when configured for the non-default case.
So negate the predicate to alter the RAM voltage for the
non-default cases.
To prevent the build error
OBJCOPY cbfs/fallback/coreboot_ram.elf
coreboot-builds/asus_f2a85-m/generated/crt0.romstage.o: In function `cache_as_ram_main':
/srv/jenkins/.jenkins/jobs/coreboot-gerrit/workspace/src/mainboard/asus/f2a85-m/romstage.c:106: undefined reference to `do_smbus_write_byte'
collect2: error: ld returned 1 exit status
make: *** [coreboot-builds/asus_f2a85-m/cbfs/fallback/romstage_null.debug] Error 1
add `southbridge/amd/agesa/hudson/smbus.c` providing the function
`do_smbus_write_byte` to ROM stage in `Makefile.inc`. That can
actually be used after the needed header files are included in a
previous commit.
Change-Id: I89542479c4cf6d412614bcf4586ea98e097328d6
Reported-by: David Hubbard <david.c.hubbard+coreboot@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3200
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
In the process of streamlining coreboot code and getting
rid of unneeded ifdefs, drop a number of unneeded checks
for the GNU C compiler. This also cleans up x86emu/types.h
significantly by dropping all the duplicate types in there.
Change-Id: I0bf289e149ed02e5170751c101adc335b849a410
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3226
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Commit "romcc: Don't fail on function prototypes" (11a7db3b) [1]
made romcc not choke on function prototypes anymore. This
allows us to get rid of a lot of ifdefs guarding __ROMCC__ .
[1] http://review.coreboot.org/2424
Change-Id: Ib1be3b294e5b49f5101f2e02ee1473809109c8ac
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3216
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Remove local copies of reading and writing I/O APIC registers by
using already available functions.
This change is similar to
commit db4f875a41
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Jan 31 17:24:12 2012 +0200
IOAPIC: Divide setup_ioapic() in two parts.
Reviewed-on: http://review.coreboot.org/300
and
commit e614353194
Author: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Tue Feb 26 17:24:41 2013 +0200
Unify setting 82801a/b/c/d IOAPIC ID
Reviewed-on: http://review.coreboot.org/2532
and uses `io_apic_read()` and `io_apic_write()` too.
As commented by Aaron Durbin, a separate `i82801gx_enable_acpi()` is
not needed: “The existing code path *in this file* is about enabling
the io apic.” [1].
[1] http://review.coreboot.org/#/c/3182/4/src/southbridge/intel/lynxpoint/lpc.c
Change-Id: I104a2d9c2898da14d26f8f2992d5a065ad640356
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3181
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit »haswell: Add initial support for Haswell platforms« (76c3700f)
[1] used `1 << 25` to set the I/O APIC ID of 2. Instead using
`2 << 24`, which is the same value, makes it clear, that the
I/O APIC ID is 2.
Commit »Intel Panther Point PCH: Use 2 << 24 to clarify that APIC ID
is 2« (8c937c7e) [2] is used as a template.
[1] http://review.coreboot.org/2616
[2] http://review.coreboot.org/3100
Change-Id: I28f9e90856157b4fdd9a1e781472cc4f51d25ece
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3123
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
The "gigabit ethernet controller" (GEC) block was added to AMD
Hudson A55E to integrate ethernet capabilities into an AMD
southbridge.
The GEC is designed to work with B50610 and B50610M gigabit PHY
chips from Broadcom. These parts may not be generally available
in small quantities for embedded development.
The GEC block requires an opaque firmware blob to function. The
GEC blob is controlled by AMD and Broadcom and is not available
from coreboot.org.
This change removes GEC support from AMD Parmer and AMD Thatcher
mainboards since these boards do not have the Broadcom PHY.
AMD has requested that the GEC be hidden for Hudson FCH since
the PHY parts are not generally available. This Kconfig option
can make it appear that this is a viable and supported way to
add Ethernet to an embedded board. It is possible to use the
Hudson GEC block with other PHYs, but this requires development
of a custom GEC blob and a custom Ethernet driver. A custom GEC
blob has been developed for a Micrel PHY, but there is no
accompanying driver.
Change-Id: I7a7bf4d41e453390ecf987c9c45ef2434fc1f1a3
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3127
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Commit 23023a5 correctly enabled the SB800 GPP PCIe ports but didn't
distribute the 4 GPP PCIe lanes amongst the enabled PCIe ports.
This fix was verified by openvoid on a AsRock E350M1 motherboard.
Change-Id: I0116c5f518e0d000be609013446e53da4112f586
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/3104
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Commit »Add support for Intel Panther Point PCH« (8e073829) [1] used
`1 << 25` to set the APIC ID of 2. Using `2 << 24`, which is the same
value, instead makes it clear, that the APIC ID is 2.
[1] http://review.coreboot.org/853
Change-Id: I5044dc470120cde2d2cdfc6e9ead17ddb47b6453
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3100
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Fixing warnings introduced by the following patches:
http://review.coreboot.org/#/c/2684/http://review.coreboot.org/#/c/2739/http://review.coreboot.org/#/c/2714/
These patches were meant to fix the dmesg warning about
the OSC method not granting control appropriately. These
patches then introduced warnings during the coreboot build
process which were missed during the patch submission
process. These warnings are below:
Intel ACPI Component Architecture
ASL Optimizing Compiler version 20100528 [Oct 15 2010]
Copyright (c) 2000 - 2010 Intel Corporation
Supports ACPI Specification Revision 4.0a
dsdt.ramstage.asl 1143: Method(_OSC,4)
Warning 1088 - ^ Not all control paths return a value (_OSC)
dsdt.ramstage.asl 1143: Method(_OSC,4)
Warning 1081 - ^ Reserved method must return a value (Buffer required for _OSC)
ASL Input: dsdt.ramstage.asl - 1724 lines, 34917 bytes, 889 keywords
AML Output: dsdt.ramstage.aml - 10470 bytes, 409 named objects, 480 executable opcodes
Compilation complete. 0 Errors, 2 Warnings, 0 Remarks, 494 Optimizations
This patch gives the following compilation status:
Intel ACPI Component Architecture
ASL Optimizing Compiler version 20100528 [Oct 1 2012]
Copyright (c) 2000 - 2010 Intel Corporation
Supports ACPI Specification Revision 4.0a
ASL Input: dsdt.ramstage.asl - 1732 lines, 33295 bytes, 941 keywords
AML Output: dsdt.ramstage.aml - 10152 bytes, 406 named objects, 535 executable opcodes
Compilation complete. 0 Errors, 0 Warnings, 0 Remarks, 432 Optimizations
The fix is simply adding an Else statement to the If which checks
for the proper UUID. This way, all outcomes will return a full
control package. This patch has no effect on the dmesg output.
Change-Id: I8fa246400310b26679ffa3aa278069d2e9507160
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3052
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reading the paste of code in a message to the mailing list [1],
a typo was spotted and found in one more place.
$ git grep egnoring
src/southbridge/amd/rs780/cmn.c: * egnoring the reversal case
src/southbridge/amd/sr5650/sr5650.c: * egnoring the reversal case
These typos are there since when the code was committed and are
now corrected.
[1] http://www.coreboot.org/pipermail/coreboot/2013-April/075644.html
Change-Id: I55c65f71e4834f209b60d678f0d44bc2f4217099
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/3062
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Split the Persimmon DSDT into common code areas.
For example, split the Southbridge specific code into
the Southbridge directory and CPU specific code into
the CPU directory. Also adding the superio.asl file
to the Persimmon DSDT tree. This file is empty for
the moment but will be necessary in the future. I have
also emptied the thermal.asl file in the mainboard
directory because it does not seem to perform as
intended (fan control does not change when it is
brought back into the code base) and it has been
inside a '#if 0' statement for a long time. Removing
it until it is decided that it is actually necessary.
This change was verified in three different ways:
1. Visual comparison of the compiled DSDT pulled from the
Persimmon after booting into Linux using the ACPI tools
acpidump, acpixtract, and iasl. The comparison was done
between the DSDT before and after doing the split work.
This test is somewhat difficult considering the expanse
of the changes. Blocks of code have been moved, and
others changed.
2. Linux logs were dumped before and after the DSDT split.
Logs dumped and compared include dmesg and lspci -tv.
Neither log changed significantly between the two compare
points.
3. The test suite FWTS was run on the Coreboot build both
before and after doing the DSDT split with the command
'sudo fwts -b -P -u'. The flag -b specifies all batch jobs,
-P specifies all power tests, and -u specifies utilities.
Interactive jobs were not run as most of them consist of
laptop checks. Again, there were no significant changes
between the two endpoints.
These tests lead me to believe that there was no change in
the functionality of the ACPI tables apart from what is
known and expected.
This patch is the first of a series of patches to split the DSDT.
The ASRock patch was merged before this one and breaks the ASROCK
E350M1 build (patch 8d80a3fb: http://review.coreboot.org/#/c/3050/).
Please be aware of this dependency when pulling these patches.
Other patches that depend on this patch are
'AMD Fam14: Split out the AMD Fam14 DSDT'
(http://review.coreboot.org/#/c/3051/)
and 'Fam14 DSDT: Also return for unrecognized UUID in _OSC'
(http://review.coreboot.org/#/c/3052/)
Change-Id: I53ff59909cceb30a08e8eab3d59b30b97c802726
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/3048
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
src/southbridge/intel/lynxpoint/pmutil.c was committed with two
things that needed fixing.
Change-Id: Ib83343a75840aa29847b607b0275971eb8140f12
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/3003
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
The ACPI NVS region was setup in place and there was a CBMEM
table that pointed to it. In order to be able to use NVS
earlier the CBMEM region is allocated for NVS itself during
the LPC device init and the ACPI tables point to it in CBMEM.
The current cbmem region is renamed to ACPI_GNVS_PTR to
indicate that it is really a pointer to the GNVS and does
not actually contain the GNVS.
Change-Id: I31ace432411c7f825d86ca75c63dd79cd658e891
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2970
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This adds configuration of SerialIO devices in the Lynxpoint-LP
chipset. This includes DMA, I2C, SPI, UART, and SDIO controllers.
There is assorted magic setup necessary for the devices and
while it is similar for each device there are subtle differences
in some register settings.
These devices must be put into "ACPI Mode" in order to take
advantage of S0ix. When in ACPI mode the allocated PCI BARs
must be passed to ACPI so it can be relayed to the OS. When
the devices are in ACPI mode BAR0+BAR1 is saved into ACPI NVS
and then updated and returned when the OS calls _CRS.
Note that is is not entirely complete yet. We need to update
the IASL compiler in our build environment to support ACPI 5.0
in order to be able to pass the FixedDMA entries to the kernel.
There are also no ACPI methods defined yet to do D0->D3->D0
transitions for actually entering/exiting S0ix states.
This is hard to test right now because our kernel does not support
any of these devices in ACPI mode. I was able to build and test
the upstream bleeding-edge branch of the linux-pm git tree. With
that tree I was able to enumerate and load the driver for the
DesignWare I2C driver and attempt to probe the I2C bus -- although
there are no devices attatched.
I am also able to see the resources from ACPI in /proc/iomem get
reserved properly in the kernel.
Change-Id: Ie311addd6a25f3b7edf3388fe68c1cd691a0a500
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2971
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This bit offset is incorrect and should only be set based
on another bit in a different register.
Change-Id: I6037534236e3a4a5d15e15011ed9b5040b435eaf
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2973
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The new enable_pm1() function was doing 2 things wrong:
1. It was doing a RMW of the pm1 register. This means we were
keeping around the enables from the OS during S3 resume. This
is bad in the face of the RTC alarm waking us up because it would
cause an infinite stream of SMIs.
2. The register size of PM1_EN is 16-bits. However, the previous
implementation was accessing it as a 32-bit register.
The PM1 enables should only be set to what we expect to handle in the
firmware before the OS changes to ACPI mode.
Change-Id: Ib1d3caf6c84a1670d9456ed159420c6cb64f555e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2978
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Previously southbridge_smm_init() was provided that did both
the clearing of the SMM state and enabling SMIs. This is
troublesome in how haswell machines bring up the APs. The BSP
enters SMM once to determine if parallel SMM relocation is possible.
If it is possible the BSP releases the APs to do SMM relocation.
Normally, after the APs complete the SMM relocation, the BSP would then
re-enter the relocation handler to relocate its own SMM space.
However, because SMIs were previously enabled it is possible for an SMI
event to occur before the APs are complete or have entered the
relocation handler. This is bad because the BSP will turn off parallel
SMM save state. Additionally, this is a problem because the relocation
handler is not written to handle regular SMIs which can cause an
SMI storm which effectively looks like a hung machine. Correct these
issues by turning on SMIs after all the SMM relocation has occurred.
Change-Id: Id4f07553b110b9664d51d2e670a14e6617591500
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2977
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
When calculating the offsets of the various binary blobs within the
coreboot.rom file, we noticed that using mawk as the awk tool instead
of using gawk led to build issues. This was finally traced to the
maximum value of the unsigned long variables within mawk - 0x7fff_ffff.
Because we were doing calculations on values up in the 0xffxxxxxx
range, these numbers would either be turned into floating point values
and printed using scientific notation, or truncated at 0x7fff_ffff.
To fix this, we print the values out as floating point, with no decimal
digits. This works in gawk, mawk, and original-awk and as the testing
below show, seems to be the best way to do this.
printf %u 0xFFFFFFFF | awk '{printf("%.0f %u %d", $1 , $1 , $1 )}'
mawk: 4294967295 2147483647 2147483647
original-awk: 4294967295 2147483648 4294967295
gawk: 4294967295 4294967295 4294967295
The issue of %d not matching gawk and original-awk has been reported
to ubuntu.
In the future, I'd recommend that whenever awk is used, a format is
specified. It doesn't seem that we can count on the representation
being the same between the different versions.
Change-Id: I7b6b821c8ab13ad11f72e674ac726a98e8678710
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2628
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This reclaims space in ACPI NVS by removing unused fields and
adds new fields for SerialIO BARs which will be used to communicate
the allocated resources to ACPI.
Change-Id: I002bf396cf7b495bc5b7e54b741527e507aff716
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2969
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the following commit
commit ee5c111755
Author: Paul Menzel <paulepanter@users.sourceforge.net>
Date: Tue Mar 12 12:41:40 2013 +0100
AMD CIMx SB800: Enable AHCI mode for SATA controller by default
Reviewed-on: http://review.coreboot.org/2661
I forgot to update the help texts to the new SATA mode default. Do
so now.
Additionally note that help texts for `choice` do not seem to be
shown.
Change-Id: I17f401633a2136efca2b21a621482e0724ff9f04
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2936
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Make it more similar to i82801d LPC init.
Change-Id: I7b32747ee8012c220c8628994d749999c144b716
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/2545
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The haswell patches that verified correctly were not yet submitted,
but verified correctly. However they still used romcc_io.h which was
dropped in another patch earlier today.
With a lot of development happening in parallel, this is
unfortunately nothing that the gerrit 2.6 Rebase If Necessary submit
type could have fixed.
Change-Id: Ifef9ae05b22c408e78d6cff37defd68e4ed91ed9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2876
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
This patch implements support for vboot firmware selection. The vboot
support is comprised of the following pieces:
1. vboot_loader.c - this file contains the entry point,
vboot_verify_firmware(), for romstage to call in order to perform
vboot selection. The loader sets up all the data for the wrapper
to use.
2. vboot_wrapper.c - this file contains the implementation calling the vboot
API. It calls VbInit() and VbSelectFirmware() with the data supplied
by the loader.
The vboot wrapper is compiled and linked as an rmodule and placed in
cbfs as 'fallback/vboot'. It's loaded into memory and relocated just
like the way ramstage would be. After being loaded the loader calls into
wrapper. When the wrapper sees that a given piece of firmware has been
selected it parses firmware component information for a predetermined
number of components.
Vboot result information is passed to downstream users by way of the
vboot_handoff structure. This structure lives in cbmem and contains
the shared data, selected firmware, VbInitParams, and parsed firwmare
components.
During ramstage there are only 2 changes:
1. Copy the shared vboot data from vboot_handoff to the chromeos acpi
table.
2. If a firmware selection was made in romstage the boot loader
component is used for the payload.
Noteable Information:
- no vboot path for S3.
- assumes that all RW firmware contains a book keeping header for the
components that comprise the signed firmware area.
- As sanity check there is a limit to the number of firmware components
contained in a signed firmware area. That's so that an errant value
doesn't cause the size calculation to erroneously read memory it
shouldn't.
- RO normal path isn't supported. It's assumed that firmware will always
load the verified RW on all boots but recovery.
- If vboot requests memory to be cleared it is assumed that the boot
loader will take care of that by looking at the out flags in
VbInitParams.
Built and booted. Noted firmware select worked on an image with
RW firmware support. Also checked that recovery mode worked as well
by choosing the RO path.
Change-Id: I45de725c44ee5b766f866692a20881c42ee11fa8
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Here's the great news: From now on you don't have to worry about
hitting the right io.h include anymore. Just forget about romcc_io.h
and use io.h instead. This cleanup has a number of advantages, like
you don't have to guard device/ includes for SMM and pre RAM
anymore. This allows to get rid of a number of ifdefs and will
generally make the code more readable and understandable.
Potentially in the future some of the code in the io.h __PRE_RAM__
path should move to device.h or other device/ includes instead,
but that's another incremental change.
Change-Id: I356f06110e2e355e9a5b4b08c132591f36fec7d9
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This configures power management registers according to
the 1.2.0 reference code drop. There are many inconsistencies
with the documentation and I tried to note those with ?.
This does not do the same for LynxPoint-H yet.
Change-Id: I9b8f5c24a8b0931075a44398571c9b0d54cce6a6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2819
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This uses the new helper function added earlier.
Change-Id: Icdb5d5c51f70eeb7e39e11062276ceb3eb3d9473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2818
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is updated to handle LynxPoint-H and LynxPoint-LP
and a new wake event is added for the power button.
Boot, suspend/resume, reboot, etc on WTM2
and then check the event log to see if expected events
have been added.
Change-Id: I15cbc3901d81f4fd77cc04de37ff5fa048f9d3e8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2817
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This makes use of the new functions from pmutil.c that take
care of the differences between -H and -LP chipsets.
It also adds support for the LynxPoint-LP GPE0 register block
and the SMI/SCI routing differences.
The FADT is updated to report the new 256 byte GPE0 block on
wtm2/wtm2 boards which is too big for the 64bit X_GPE0 address
block so that part is zeroed to prevent IASL and the kernel
from complaining about a mismatch.
This was tested on WTM2. Unfortunately I am still unable to get an
SCI delivered from the EC but I suspect that is due to a magic
command needed to put the EC in ACPI mode. Instead I verified that
all of the power management and GPIO registers were set to expected
values.
I also tested transitions into S3 and S5 from both the kernel and
by pressing the power button at the developer mode screen and they
all function as expected.
Change-Id: Ice9e798ea5144db228349ce90540745c0780b20a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2816
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The kernel ACPI was not happy with the Add inside a
ResourceTemplate (or perhaps within the IO declaration)
Instead make a buffer of IO reservations and turn _CRS
into a method that updates the buffer depending on the
chipset type.
This adds an \ISLP() method that checks the chipset LPC
device ID to see if it is -LP or -H.
It also increases the PM base reservation to 256 bytes
and moves both GPIO and PM base to above 0x1000 on -LP
chipsets.
Change-Id: I747b658588a4d8ed15a0134009a7c0d74b3916ba
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This was put in for debugging and experimentation on i945
and has been copied around since. Drop it from lynxpoint.
Change-Id: I0b53f4e1362cd3ce703625ef2b4988139c48b989
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2814
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There are subtle yet significant differences in some of the
registers in the power management region between LynxPoint-H
and LynxPoint-LP.
In order to reduce code that is accessing these registers and
would need special cases this adds a number of helper functions
that can be used in both ramstage and SMM.
This commit just adds the new functions, subsequent commits will
start to use them.
Change-Id: I411da75da519f5b3198a408078cbf3114e426992
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
These base addresses are used in several places and it
is helpful to have one location that is reading it.
Change-Id: Ibf589247f37771f06c18e3e58f92aaf3f0d11271
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2812
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add a helper function pch_is_lp() that will return 1 if
the current chipset is of the new "low power" variant used
with Haswell ULT.
Additionally these functions are added to SMM so it can
be used there.
Change-Id: I9acdea2c56076cd8d9627aba66cf0844c56a38fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2811
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order to be able to talk to an EC via standard path.
Change-Id: I3fe76882dec9a0596cbc1c844afa2ddb03ed771c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2810
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
I'm not sure if I screwed this up originally or the Intel docs changed
(I didn't bother to go back and check). According to ME BWG 1.1.0 the give
up bit is in the host general status #2 register.
Change-Id: Ieaaf524b93e9eb9806173121dda63d0133278c2d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2808
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
So it can get used in both romstage and ramstage.
Change-Id: Ief9eaafdd91df2a7b668de1a9b83aea3af3ff894
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2802
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
SPI accesses can be slow depending on the setup and the access pattern.
The current SPI hardware setup to cache and prefetch. The alternative
cbfs_load_payload() function takes advantage of the caching in the CPU
because the ROM is cached as write protected as well as the SPI's
hardware's caching/prefetching implementation. The CPU will fetch
consecutive aligned cachelines which will hit the ROM as
cacheline-aligned addresses. Once the payload is mirrored into RAM the
segment loading can take place by reading RAM instead of ROM.
With the alternative cbfs_load_payload() the boot time on a baskingridge
board saves ~100ms. This savings is observed using cbmem.py after
performing warm reboots and looking at TS_SELFBOOT_JUMP (99) entries.
This is booting with a depthcharge payload whose payload file fits
within the SMM_DEFAULT_SIZE (0x10000 bytes).
Datapoints with TS_LOAD_PAYLOAD (90) & TS_SELFBOOT_JUMP (99) cbmem entries:
Baseline Alt
-------- --------
90:3,859,310 (473) 90:3,863,647 (454)
99:3,989,578 (130,268) 99:3,888,709 (25,062)
90:3,899,450 (477) 90:3,860,926 (463)
99:4,029,459 (130,008) 99:3,890,583 (29,657)
90:3,834,600 (466) 90:3,890,564 (465)
99:3,964,535 (129,934) 99:3,920,213 (29,649)
Booted baskingridge many times and observed 100ms reduction in
TS_SELFBOOT_JUMP times (time to load payload).
Change-Id: I27b2dec59ecd469a4906b4179b39928e9201db81
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2783
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
At some point, compiles with USB Debug port stopped working. This change makes
a trivial reordering in the code and adds two makefile entries to make it build
without errors. It also works on stout.
Build and boot as normal. Works. Enable CONFIG_USB, connect USB debug hardware
to the correct port (on stout, that's the one on the left nearest the back) and
watch for output.
Change-Id: I7fbb7983a19b0872e2d9e4248db8949e72beaaa0
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/2784
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Rather than have to repeat this bit in every mainboard.
Also, remove the reset of the RTC power status from here.
We had done this in TOT for current platforms but did not
carry it back to emeraldlake2 where this branched from.
If we clear the status here then we don't get an event
logged later which can be important for the devices that
do not have a CMOS battery.
Change-Id: Ia7131e9d9e7cf86228a285df652a96bcabf05260
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2683
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit adds support for using the SMM modules for haswell-based
boards. The SMI handling was also refactored to put the relocation
handler and permanent SMM handler loading in the cpu directory. All
tseg adjustment support is dropped by relying on the SMM module support
to perform the necessary relocations.
Change-Id: I8dd23610772fc4408567d9f4adf339596eac7b1f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2728
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Some initialization steps were done twice
- One step was missing for Panther Point HDA
- Added a 1ms delay after reset
- Increased timeout to 1ms for all codec operations
Change-Id: Ib751f1a16ccd88ea2fbbb2a10737f76277574026
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2518
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
There was a mix of setup code sprinkled across the various components:
southbridge code in the northbridge, etc. This commit reorganizes the
code so that northbridge code doesn't initialize southbridge components.
Additionally, the calling dram initialization no longer calls out to ME
code. The main() function in the mainboard calls the necessary ME
functions before and after dram initialization.
The biggest change is the addition of an early_pch_init() function
which initializes the BARs, GPIOs, and RCBA configuration. It is also
responsible for reporting back to the caller if the board is being
woken up from S3. The one sequence difference is that the RCBA config
is performed before claling the reference code.
Lastly the rcba configuration was changed to be table driven so that
different board/configurations can use the same code. It should be
possible to have board/configuration specific gpio and rcba
configuration while reusing the romstage code.
Change-Id: I830e41b426261dd686a2701ce054fc39f296dffa
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2681
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Certain SATA devices claim to support SATA 6 Gbps, but in fact have
bugs. For these devices, add a config option to force the SATA link
speed to something other than default.
Change-Id: I2dc1793cd58771298a392345162d39d20eb0afbb
Signed-off-by: Shawn Nematbakhsh <shawnn@google.com>
Reviewed-on: http://review.coreboot.org/2765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This enables power management and clock gating on XHCI.
Change-Id: I124ea6c5aca034b7ec4b5286d971c2adfce25c88
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
objcopy -B provides symbols of the form _binary_<name>_(start|end|size).
However, the _size variant is an absoult symbol. If one wants to
relocate the smi loading the _size symbol will be relocated which is
wrong since it is suppose to be a fixed size. There is no way to
distinguish symbols that shouldn't be relocated vs ones that can.
Instead use the _start and _end variants to determine the size.
Change-Id: I55192992cf36f62a9d8dd896e5fb3043a3eacbd3
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The bd82x6x requires some additional setting on S3/S4 entry.
Change-Id: I24489ab94dd7cd5a4a64044f25153f5b01a45b77
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2759
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add the PCH function to SMM for follow-on SMM patches that
require these functions.
Change-Id: I7f3a512c5e98446e835b59934d63a99e8af15280
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
These enables are hidden behind IOBP for some reason.
Boot to linux with SDIO disabled and see that
the SDIO driver does not load and crash the system.
Change-Id: Icfbfa117e9e57a51d32db7f6366a9d0d790adcf0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2695
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit updates the Lynx Point resource reservations before
the coreboot allocator assigns resources. There is no need to mark
anything as subtractive decode because there are no devices/buses
linked to the LPC device.
The I/O range reservations consists of claiming the first 4KiB
of I/O space. The PMBASE, GPIOBASE, and LPC generic I/O decode
ranges are checked against the default claimed range. If those
ranges overlap or fall outside of the default range then those
resources are added.
The MMIO range reservations consist of claiming everything from
the I/O APIC to 4GiB. The RCBA and the LPC Generic Memory range
register are then conditionally added if they fall outside of
the default MMIO range.
Change-Id: I0f560a03814a2b15961fdbe61e4164cd54cff7a5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2682
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Add ME device ID for Lynxpoint LP
- Add GPU device IDs for ULT
- SATA init tweaks from checking against DXE reference code
- Remove the ICH7 from the SPI driver so it works on all lynxpoint
without having to add more LPC device ID checks
- Add function disable for audio dsp and xhci, remove PCI bridge
- Add interrupt route registers for new devices (needs romstage setup)
Change-Id: Idb48f50d0bacb6bf90531c3834542b9abb54fb8a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2680
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Add device IDs for lynxpoint mobile and LP variants.
- Update the clock gating setup based on BWG
- Update the SATA programming based on BWG
- Add a DEVSLP0 mux config register
Change-Id: Icf4d7bab7f3df7adef5eb7c5e310a6995227a0e5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2649
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
The low power variant of the chipset introduces a completely
new interface to the GPIOs.
This is a 1KB region and so needs to be moved as well so it does
not conflict with other IO regions.
Also expose the gpio_get functions to ramstage and move the
prototypes to pch.h so they can be used for both GPIO interfaces.
Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2648
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
There are enough subtle differences that it is useful to have
a Kconfig entry to differentiate the ULT/LP chipet from the
desktop/mobile versions.
Change-Id: I04ca1bc6f90bcf9e6994ea7125c98347e8def898
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2645
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit contains a bevy of updates:
- PCI device id is updated to match Lynx Point EDS in the ME driver.
- Allocate the memory to store the consumption of the MBP.
- me_bios_payload structure is now a structure of pointers that point
into the allocated memory.
- The ICC profile structure was updated to correctly reflect the
documentation.
Verfied that output of MBP reading can handle unknown items.
Change-Id: I43cc45e6b797444c105e7c842eb5684e9c104687
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2641
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
According to the 0.8.0 ME BWG this is a new state. It's not very clear
what exactly it entails, but the Basking Ridge CRB was tripping it when
MRC_DEBUG was enabled (presumably because of a DID timeout).
Instead of 0x17 one can now see the proper message for this state.
Change-Id: I5bda1de7d3d957d38a4760a02dcd170ec48782e9
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2640
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is no longer tied to a GPIO but has a proper chipset pin.
Change-Id: Iba70338e8c67e3c3c1cb32e69bfea1282fda8cb5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2643
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that MMCONF_SUPPORT_DEFAULT is enabled by default remove
the pcie explicit accesses. The default config accesses use
MMIO.
Change-Id: I8406cec16c1ee1bc205b657a0c90beb2252df061
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2618
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The register that controls global reset is named the Power
Mangement Initialization Regiser (PMIR). Update the defines
to reflect the documentation.
Additionally, there is no core well reset control according to the
EDS. There is, however, a CF9 lock field to lock this register down.
Change-Id: I773c33bec63a06cdb869eb9f94553d476e492798
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2619
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The ME9 requirements have added some registers and changed some
of the MBP state machine. Implement the changes found so far in
the ME9 BWG. There were a couple of reigster renames, but the
majority of th churn in the me.h header file is just introducing
the data structures in the same order as the ME9 BWG.
Change-Id: I51b0bb6620eff4979674ea99992ddab65a8abc18
Signed-Off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2620
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
In order for coreboot to assign resources properly the pci
drivers need to have th proper device ids. Add the host controller
and the LPC device ids for Lynx Point.
Resource assignment works correctly now w/o odd behavior because
of conflicts.
Change-Id: Id33b3676616fb0c428d84e5fe5c6b8a7cc5fbb62
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2638
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This follows the new method outlined in the LPT BWG.
It is also very pedantic about its operation so it
is easier to read and compare against the docs and
the reference code implementation.
Change-Id: I235d634cded0c75ec0e9f53488f5b366107a18fa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2694
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Haswell parts use a PCH code named Lynx Point (Series 8). Therefore,
the southbridge support is included as well. The basis for this code is
the Sandybridge code. Management Engine, IRQ routing, and ACPI still requires
more attention, but this is a good starting point.
This code partially gets up through the romstage just before training
memory on a Haswell reference board.
Change-Id: If572d6c21ca051b486b82a924ca0ffe05c4d0ad4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2616
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The current default is IDE mode which is slower compared to AHCI
mode. Therefore use AHCI mode by default.
A similar change was made for AMD Persimmon in commit
»Enable SATA AHCI for faster boot with SeaBIOS.« (96be74c7) [1]
but was indirectly reverted by »sb800: Add sata ahci/raid mode
kconfig option« (d4a0e7d0) [2].
[1] http://review.coreboot.org/220
[2] http://review.coreboot.org/225
Change-Id: I4fa31b0a3280891e7a3f37675ae8415205818947
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2661
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Add PEI updates and ACPI updates for supporting EHCI to XHCI
USB port support.
Change-Id: I9ace68a1b3950771aefb96c1319b8899291edd9a
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/2519
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
The power up default for the 14M_25M_48M_OSC switchable clock output ball of
the SB800 chipset is 14 MHz. sb800/bootblock.c changes this to 48 MHz,
which is the correct value for almost all SIOs. However, not for
'smscsuperio' (SMSC SCH311x), which needs the original 14 MHz and is not
configurable for other clock speeds. A wrong SIO clock supply results in
funny RS232 output (wrong bit speed) and non-working PS/2.
We could switch back to 14 MHz in the mainboard's romstage.c, but then the
clock frequency would change twice. The resulting short 48 MHz burst causes
a handful of rubbish characters on RS232 on every boot until the SIO clock
has stabilized again.
This patch skips the SB800 clock switch if the SIO Kconfig requests 14 MHz.
This does not affect any boards currently in the repository (yet).
Change-Id: Icff41fd88dc41c08f3700ab4f786852f04eff2a4
Signed-off-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-on: http://review.coreboot.org/2454
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
In the file `COPYING` in the coreboot repository and upstream [1]
just one space is used.
The following command was used to convert all files.
$ git grep -l 'MA 02' | xargs sed -i 's/MA 02/MA 02/'
[1] http://www.gnu.org/licenses/gpl-2.0.txt
Change-Id: Ic956dab2820a9e2ccb7841cab66966ba168f305f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2490
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
According to both Haswell and the SandyBridge/Ivybridge
BWGs the save state area actually starts at 0x7c00 offset
from 0x8000. Update the em64t101_smm_state_save_area_t
structure and introduce a define for the offset.
Note: I have no idea what eptp is. It's just listed in the
haswell BWG. The offsets should not be changed.
Change-Id: I38d1d1469e30628a83f10b188ab2fe53d5a50e5a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/2515
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Adding RTC init code to the Southbridge initialization
code in 'lpc_init'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This is the same edit made to the CIMX SB800 titled
'AMD/Persimmon: Add RTC init to CIMX SB800' with commit
ID: c4d3d which can be viewed here:
http://review.coreboot.org/#/c/2488/
Change-Id: Iddb7a3cbabe736b511cde03d7dc0a4a0b1c7fd90
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2510
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Adding RTC init code to the Southbridge initialization
code in 'late.c'. This initializes the RTC so that the
Date Alarm register is set to a valid value (0x00) at
startup. By setting the Date Alarm register to 0x00,
it does not get evaluated along with the seconds,
minutes, and hours when running 'fwts s3'.
Information about fwts (Firmware Test Suite) can be
found here:
https://wiki.ubuntu.com/Kernel/Reference/fwts
This was tested on a Persimmon but will apply to
other mainboards as well.
Change-Id: I9a11bc3f9e3f53c46e7a4d72e62ebb0a4ba1bfe4
Signed-off-by: Mike Loptien <mike.loptien@se-eng.com>
Reviewed-on: http://review.coreboot.org/2488
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Currently the size of the volatile storage for S3 reserved in the
image is hardcoded to 32768 bytes. Make that configurable by
introducing the Kconfig 'S3_DATA_SIZE'.
As the storage space is needed for storing non-volatile, volatile and
MTRR data, add a check if the size is big enough.
Change-Id: I9152797cf0045c8da48109a9d760e417717686db
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2383
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
For whatever reason tabs got inserted in the license header text.
Remove one occurrence of that with the following command [1].
$ git grep -l 'MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.'$'\t' | xargs sed -i 's,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.[ ]*,MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.\ \ ,'
[1] http://sed.sourceforge.net/grabbag/tutorials/sedfaq.txt
Change-Id: Iaf4ed32c32600c3b23c08f8754815b959b304882
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2460
Tested-by: build bot (Jenkins)
Reviewed-by: Jens Rottmann <JRottmann@LiPPERTembedded.de>
Reviewed-by: Cristian Măgherușan-Stanciu <cristi.magherusan@gmail.com>
REQUIRES_BLOB assumes that all blob files come from the 3rdparty directory,
builds failed when all files were configured to point to other sources.
This change modifies the blob mechanism so that cbfs-files can be tagged as
"required" with some specification what is missing.
If the configured files can't be found (wrong path, missing file), the build
system returns a list of descriptions, then aborts.
Change-Id: Icc128e3afcee8acf49bff9409b93af7769db3517
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2418
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Marc Jones <marcj303@gmail.com>
S3_DATA_POS defines address where the whole S3 data is stored.
Change-Id: I4155a0821e74a3653caaead890e5fec5677637aa
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2438
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The name lapic_cluster is a bit misleading, since the construct is not local
APIC specific by concept. As implementations and hardware change, be more
generic about our naming. This will allow us to support non-x86 systems without
adding new keywords.
Change-Id: Icd7f5fcf6f54d242eabb5e14ee151eec8d6cceb1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/2377
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The name pci_domain was a bit misleading, since the construct is only
PCI specific in a particular (northbridge/cpu) implementation, but not
by concept. As implementations and hardware change, be more generic
about our naming. This will allow us to support non-PCI systems without
adding new keywords.
Change-Id: Ide885a1d5e15d37560c79b936a39252150560e85
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/2376
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since there are and will be other files in nb/sb folders, we change
the general spi.h to a file name which is not easy to be duplicated.
Change-Id: I6548a81206caa608369be044747bde31e2b08d1a
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2309
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The "system is legacy free" question accidentally escaped
from the hudson Kconfig where it was intended to stay and
went coreboot-wide. This puts it back inside the boundries
of the hudson southbridge where it belongs.
I also commented the endif statements to make it easier to
tell where things belong.
Change-Id: I49f7a5eadb96d40c6101a93bc390e644617a5654
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2179
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Go through southbridge/amd/agesa/hudson, thatcher and parmer
mainboard directories and change all references to sb800 to
reference hudson instead.
This is just cleanup and should make no functional difference.
Change-Id: Icd6a9a08c4bbf5e1aed394362d24c05811ed1fba
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2177
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Add Kconfig option for Legacy free and hook it into the parmer
AGESA initialization as well as the FADT code. This should really
be done inside the southbridge wrapper and not in the mainboard,
but for now the code to attach it to is inside the mainboard.
Update Kconfig for parmer and thatcher to default to legacy free.
Change-Id: Ib899bd02ddc5506caae4aca2c589cc2526638cb8
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/2157
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Update the southbridge/amd/agesa/hudson FADT generation for ACPI
3.0 compliance similar to what was done for cimx/SB800/fadt.c in
commit 9aa4389.
commit 9aa43892e6
Author: Martin Roth <martin@se-eng.com>
Date: Fri May 25 12:23:32 2012 -0600
Update SB800 CIMX FADT
According to the datasheet, PMA_CNT_BLK is no longer available
and PM2_CNT_BLK should not be used. Setup for these has been
removed from the table and .h file.
Change-Id: Ied8eb1f26b4aa364d051ec5f7ed6f482bb440957
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2140
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The cimx/sb800 IMC Firmware location Kconfig option has
a typo which would could set it to the wrong location.
Change-Id: I38016bebd1bfe6ad6d3f1c02cb1960712fbf4ab2
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/2120
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
That code will be used to disable the internal GFX card and enable the
external PCIe card.
The following lines from function `rs780_internal_gfx_enable()` are
taken and reversed.
/* Disable external GFX and enable internal GFX. */
l_dword = pci_read_config32(nb_dev, 0x8c);
l_dword &= ~(1<<0);
l_dword |= 1<<1;
pci_write_config32(nb_dev, 0x8c, l_dword);
It has been tested on the M4A785T-M with the following card inside the
PCIe 16x slot:
02:00.0 VGA compatible controller: nVidia Corporation GT218 [GeForce 210] (rev a2)
Change-Id: I7bd412b987fde98c97464175e2c7a384a8f0fb84
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: http://review.coreboot.org/2065
Tested-by: build bot (Jenkins)
If a 3rd party blob option is selected, make sure that it makes the
user select CONFIG_USE_BLOBS as otherwise the build will fail.
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Change-Id: I04429f23137946525c8577dd9c979bd4a0d17cdc
Reviewed-on: http://review.coreboot.org/2080
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Since SB800, USB2.0 debug port is dev 0x12, func 2.
Change-Id: Ie0e33cb2f0833b0baeef81323e1a0634242fbe55
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1880
Tested-by: build bot (Jenkins)
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
We ship it in the 3rdparty repository.
Change-Id: Ida52bc7e813f8468910c4ea7838ebb863c52b88a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/2060
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Add prefix coreboot_ to let make clean find it and delete it.
Change-Id: Ieba9c0e7ca3d2afec311d64159b22746ba5825c4
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/2029
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Add configuration for AMD's IMC ROM and fan registers for cimx/sb800
platforms.
- Allows user to add the IMC rom to the build and to configure the
location of the "signature" between the allowed positions.
- Allows for no fan control, manual setup of SB800 Fan registers, or
setup of the IMC fan configuration registers.
- Register configuration is done through devicetree.cb. No files need
to be added for new platform configuration.
- Initial setup is for Persimmon, but may be extended to any cimx/sb800
platform.
Change-Id: Ib06408d794988cbb29eed6adbeeadea8b2629bae
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1977
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The file generated when the IMC or XHCI binaries are included in the rom
was named $(obj)/hudson_romsig.bin. The problem with this is that it
doesn't get deleted when the user does a make clean.
changing the name to coreboot_hudson_romsig.bin makes this happen.
Change-Id: I19a40042fbf0f7b5633d7b35339c05ed90d3243b
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1978
Tested-by: build bot (Jenkins)
Reviewed-by: Zheng Bao <zheng.bao@amd.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
There was already a special case for the SPI base address in
lpc_set_resources for southbridge/amd/cimx/sb800 and
southbridge/amd/agesa/hudson, but it needed to be modified
to keep from killing the IMC rom during initialization. As
soon as the BAR is disabled by setting the new base address,
the IMC dies. The fix is to make sure it's still enabled
when setting the new base address instead of setting the new
address then re-enabling it.
Change the name SPIROM_BASE_ADDRESS to SPIROM_BASE_ADDRESS_REGISTER
to more accurately describe what we're using.
Change-Id: I216d75b722c4332c239d487111a9880eabf59e91
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1975
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
The SB800 and Hudson now support adding the IMC ROM which runs from the same
chip as coreboot. When the IMC is running, write or erase commands sent to
the spi bus will fail, and the IMC will die. To fix this, we send a request
to the IMC to stop fetching from the SPI rom while we write to it. This
process (in one form or another) is required for writes to the SPI bus while
the IMC is running.
Because the IMC can take up to 500ms to respond every time we claim the
bus, this patch tries to keep the number of times we need to do that to a
minimum. We only need to claim the bus on writes, and using a counter for
the semaphore allows us to call in once to claim the bus at the beginning
of a number of transactions and it will stay claimed until we release it
at the end of the transactions.
Claim() - takes up to 500ms hit
claim() - no delay
erase()
release()
claim() - no delay
write()
release()
Release()
Change-Id: I4e003c5122a2ed47abce57ab8b92dee6aa4713ed
Signed-off-by: Martin Roth <martin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1976
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Remove the old, unflexible code for storing S3 data in SPI flash.
Refer to flashrom. Tested on Parmer.
Change-Id: I60a10476befb4afab2b4241f01a988f4a8bb22cd
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1920
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
As we move to supporting other systems we need to get rid of assembly
where we can. The log2 function in src/lib is identical to the assembly
one (tested for all 32-bit signed integers :-) and takes about 10 ns
to run as opposed to 5ns for the non-portable assembly version. While speed
is good, I think we can spare the 15 ns or so we add to boot time
by using the C version only.
Change-Id: Icafa565eae282c85fa5fc01b3bd1f110cd9aaa91
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/1928
Tested-by: build bot (Jenkins)
This broke because those components were not yet
committed when the patch to drop the driver class
was made.
Change-Id: I29948223503a6c4b196eafa169c064cd26da1be1
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1934
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: Ib4401897570f9e4d31c18d05144b5deb6f4523bc
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1873
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marc Jones <marcj303@gmail.com>
The use of ramstage.a required the build system to handle some
object files in a special way, which were put in the drivers
class.
These object files didn't provide any symbols that were used
directly (but only via linker magic), and so the linker never
considered them for inclusion.
With ramstage.a gone, we can drop this special class, too.
Change-Id: I6f1369e08d7d12266b506a5597c3a139c5c41a55
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/1872
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Add support for ICH9 southbridge
Change-Id: I70612431101bf48d9dcc96ee1b37d257c9ad2ee2
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/1690
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
e.g.
-#if CONFIG_LOGICAL_CPUS == 1
+#if CONFIG_LOGICAL_CPUS
This will make it easier to switch over to use the config_enabled()
macro later on.
Change-Id: I0bcf223669318a7b1105534087c7675a74c1dd8a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1874
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
hard_reset was indeed consolidated and moved into the southbridge
code a while ago, but the config variable was still kept alife, with
some duplicate code.
Change-Id: I60d4a87de916667f6e89353dfbe1a7b9eca380f7
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1837
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
The search for save state was comparing the entire RAX
value when it needs to just operate on the bottom byte
so it can find the GSMI command in bits 7:0 but not the
extended command code in bits 15:8.
Change-Id: I526c60e6b3732fa3680a17a4bed2a2ef23ccf94f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1774
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Instead of hijacking some random memory addresses to
relay the GNVS pointer to SMM we can use EBX register
during the write to APM_CNT register when the SMI is
triggered.
Change-Id: I79a89512c40353d72ad058cbf2e6a23a696945da
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Using global variables with the TSEG is a bad idea because
they are not relocated properly right now. Instead make
the variables static and add accessor functions for the
rest of SMM to use.
At the same time drop the tcg/smi1 pointers as they are
not setup or ever used. (the debug output is added back
in a subsequent commit)
Change-Id: If0b2d47df4e482ead71bf713c1ef748da840073b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1764
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is currently used by the ELOG GSMI interface but is a
good way to pass data to SMM so move the current searching code
to a separate function and make it a bit more versatile with the
checks it does to find a match so it can be used in other
situations.
Change-Id: I5b6f92169f77c7707448ec38684cdd53c02fe0a5
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1763
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The SMM GNVS pointer is normally updated only when the
ACPI tables are created, which does not happen in the
resume path.
In order to restore this pointer it needs to be available
at resume time. The method used to locate it at creation
time cannot be used again as that magic signature is
overwritten with the address itself. So a new CBMEM ID
is added to store the 32bit address so it can be found
again easily.
A new function is defined to save this pointer in CBMEM
which needs to be called when the ACPI tables are created
in each mainboard when write_acpi_tables() is called.
The cpu_index variable had to be renamed due to a conflict
when cpu/cpu.h is added for the smm_setup_structures()
prototype.
Change-Id: Ic764ff54525e12b617c1dd8d6a3e5c4f547c3e6b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
For reasons of security and testing we want to be able to
enable/disable ME section locking through a config option.
Change-Id: I341c577cdae86be62c0e3d32bbd6b3333c004a5f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1798
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Right now coreboot's build process produces images that are
not booting on actual hardware because they are smaller than
the actual flash device and also don't have an IFD nor an ME
firmware in them. In order to produce bootable images, you
needed a wrapper script / extra step until now. With this
change, the resulting coreboot.rom is actually bootable.
Change-Id: I82714069fb004d4badc41698747a704bd9fed4da
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1771
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This is a basic romstage driver that can be used for the
MRC cache code on systems where we do not have the MRC cache
stored in a flash region that is memory mapped.
It uses the hardware sequencing interface to avoid having
to know anything about the flash chip itself.
BUG=chrome-os-partner:15031
BRANCH=stout
TEST=manual: this was tested with debug code added to romstage
that attempted to read the MRC cache at offset 0x3e0000.
SPI READ offset=003e0000 size=64 buffer=ff7fba00
SPI ADDR 0x003e0000
SPI HSFC 0x3f00
SPI READ: 0=4443524d
SPI READ: 1=00000bb0
SPI READ: 2=00008e24
SPI READ: 3=00000000
SPI READ: 4=001c8bbb
SPI READ: 5=0c206466
SPI READ: 6=0a043220
SPI READ: 7=000058b4
SPI READ: 8=00000000
SPI READ: 9=00000000
SPI READ: 10=00100000
SPI READ: 11=00100005
SPI READ: 12=20202025
SPI READ: 13=000e0001
SPI READ: 14=00000000
SPI READ: 15=00000000
Change-Id: I5f78f53111f912ff5dda52bbf90fdc1824b82681
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1777
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
- Fix handling of 5-byte Fast Read command in the ICH SPI
driver. This fix is ported from the U-boot driver.
- Allow CONFIG_SPI_FLASH_NO_FAST_READ to be overridden by
defining a name for the bool in Kconfig and removing the
forced select in southbridge config
- Fix use of CONFIG_SPI_FLASH_NO_FAST_READ in SPI drivers
to use #if instead of #ifdef
- Relocate flash functions in SMM so they are usable.
This really only needs to happen for read function pointer
since it uses a global function rather than a static one from
the chip, but it is good to ensure the rest are set up
correctly as well.
Change-Id: Ic1bb0764cb111f96dd8a389d83b39fe8f5e72fbd
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1775
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
The Intel PCH can override the ASPM settings via the MPC2 register.
Add a chip override for F0-F7. Mainboards may implement this as
needed.
This also fixes the final PM setup being done too early. It was
being done prior to the PCIe ASPM setup, which happens in the
bridge scan.
Change-Id: Idf2d2374899873fc6b1a2b00abdb683ea9f5bd6b
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/1796
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Right now the SPI bus is getting set to 20mhz for transactions
initiated with the software sequence interface.
In order to be able to do reasonable fastread/write/erase we
can bump this up to a higher value at boot before it gets
locked at 20mhz.
To do this read out the speed set in the SPI descriptor for
hardware sequencing and apply it to software sequencing.
Change-Id: I79aa2fe7f30f734785d61955ed81329fc654f4a4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1773
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The chips we are using do not use BE52 (block erase 0x52)
so we can use that opcode menu location to enable fast read.
Change-Id: I18f3e0e5e462b052358654faa0c82103b23a9f61
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/1772
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
And move the pre-hardwaremain post code to 0x79
so it comes before hardwaremain at 0x80.
Emit these codes from ACPI OS resume vector as well
as the finalize step in bd82x6x southbridge.
Change-Id: I7f258998a2f6549016e99b67bc21f7c59d2bcf9e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1702
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The sleep type is 5 for S3 and 7 for S5.
Change-Id: I7ffdb3d27b6994ac4a12a343caf4d7abb82fe6ca
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
These bits are used by the IGD OpRegion code
Change-Id: I89a11fc5021d51e0c1675ba56f6a3bc3b79bb8aa
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1751
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
In order to support Intel's IGD Opregion standard, we need
an additional set of flags shared between firmware, ACPI, SMM, and the
graphics driver.
Change-Id: I1a9b8dff5e5ee8d501b6672bc3bcca39ea65572e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1750
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
If the driver is initialized before the lockdown then it will
fail to work after the lockdown bit is set.
Change-Id: Idc05d33d8d726bf29cb3c9b1b4604522bd64170a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1745
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In case tseg_relocate() is called again on a pointer we should not
relocate it again.
Change-Id: Ida1f9c20dc94b448c773b14d8864afe585369119
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1740
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
We are seeing ME disabled and ME error events on some devices
and this extended info can help with debug.
Also fix a potential issue where if the log does manage to get
completely full it will never try to shrink it because the only
call to shrink the log happens after a successful event write.
Add a check at elog init time to shrink the log size.
Change-Id: Ib81dc231f6a004b341900374e6c07962cc292031
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The handling of write enable was not entirely correct,
the opcode needs to be skipped when the controller is
locked down.
Addresses were not getting set properly for erase commands
which seemed to mostly work when the previous command had
set an address.
Tested by adding events to the event log at runtime on a
freslhy flashed device (with locked down SPI controller)
until the log log shrink happens to ensure it does not hang:
hexdump -C elog.event.kernel_clean
00000000 01 00 00 00 ad de 00 00 00 00
for x in $(seq 1 232); do
cat elog.event.kernel_clean > /sys/firmware/gsmi/append_to_eventlog
done
mosys eventlog list | tail -6
154 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
155 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
156 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
157 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
158 | 2012-09-01 13:54:43 | Log area cleared | 1030
159 | 2012-09-01 13:54:43 | Kernel Event | Clean Shutdown
Change-Id: I3a50dae54422a9ff37daefce3632f8bcbe4eb89f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1717
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Now that WREN prefix is handled properly ELOG is able to write
when the SPI controller is locked down.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: If6d0dced7cb0f5ca7038b3d758f31b856826d30b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1712
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
The code that attempts to use the opmenu needs to have a special
case for write enable now that it is handled as an atomic prefix
and not as a standalone opcode.
To test, ensure that runtime SPI write via ELOG is successful by
checking the event log for a kernel shutdown reason code:
5 | 2012-08-27 11:09:48 | Kernel Event | Clean Shutdown
6 | 2012-08-27 11:09:50 | System boot | 26
7 | 2012-08-27 11:09:50 | System Reset
Change-Id: I527638ef3e2a5ab100192c5be6e6b3b40916295a
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1710
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
This appears to fix an infrequent resume hang on Ivybridge.
Tested on 2 devices with 15k suspend/resume cycles each
Change-Id: I53618bc7966824413f1720a2be3cbd2550e29473
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/1704
Reviewed-by: Marc Jones <marcj303@gmail.com>
Tested-by: build bot (Jenkins)
Every line of text after a 'help' label in a Kconfig
file must have the same whitespace preceding it, otherwise
it's no longer considered help text.
Change-Id: I97093bee72b295b315d78d4c26d7186bf1017fda
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1687
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Unfortunately the reference tool chain was updated
without ever even testing it on an abuild run. This
broke a number of ports.
This change gets coreboot at least compiling again
for all supported systems.
Change-Id: I92c7cbc834de6d792fdab86b75df339e2874c52e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/1670
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
HPET's min ticks (minimum time between events to avoid
losing interrupts) is chipset specific, so move it to
Kconfig.
Via also has a special base address, so move it as well.
Apart from these (and the base address was already #defined),
the table is very uniform.
Change-Id: I848a2e2b0b16021c7ee5ba99097fa6a5886c3286
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/1562
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Also deletes files not included in build:
src/southbridge/amd/cimx/sb700/chip_name.c
src/southbridge/amd/cimx/sb800/chip_name.c
src/southbridge/amd/cimx/sb900/chip_name.c
Change-Id: I2068e3859157b758ccea0ca91fa47d09a8639361
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/1473
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Marc Jones <marcj303@gmail.com>
Some 32 bit machines print integer higher than 0x80000000
as negative number.
Change-Id: Ieb512ed2a7499ce7e91e45e4075d4f119780b57d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1547
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Try
sh> printf %d 0x005500AA | LC_ALL=C awk '{printf("%c%c%c%c", \
$1 % 256, $1/256 % 256, $1/65536 % 256, $1/16777216);}' | \
od -Ax -t x
On Linux with gawk, we get
000000 005500aa
000004
On FreeBSD with nongnu-awk, we get
000000 000055aa
000002
In awk, all the numbers are floating point number. So division doesn't
round the result from 0.75 (3/4) to 0.
And, There is a fact that, for the FreeBSD awk,
sh> awk 'BEGIN {printf("%c", 0.75)}';
produces nothing, instead of 0.
Here we need to convert the floating point number to
integer by int(X), which is an awk built-in function, instead of GNU
extension.
Change-Id: I3470d5f13e7ea59a978d5575a54c0d56368dc78d
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1529
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>
TRACE has redefined warnings in src/southbridge/amd/cimx/sb700/Platform.h,
so we do some changes to remove such warnings.
Change-Id: I24979e08b83434f91a8fa37cd9f16303fa0b298d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Reviewed-on: http://review.coreboot.org/1499
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
Command expr in some systems only take 32bit as integer, which
value is at 0x7FFFFFFF ~ -0x80000000. Use awk as alternate way to
calculate.
And some system doesnt take hex value in Makefile, even in awk instruction.
Change-Id: Ie35d6a5b96eea4192bd9cab857af4d4dcb37b9ed
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1527
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
Forgot to change the code back after debugging.
Change-Id: Iaf58d65c14d53ca77958080faf6ab85d60992226
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/1491
Tested-by: build bot (Jenkins)
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Prior to this change the setting would be zeroes and
would cause a BSOD in 64 bit versions of Windows.
Change-Id: I2d422ef9667457af53f9fd055799e489ed2b25db
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/1475
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
Kyösti Mälkki