The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Move the memory strap gpios to variant/gpio.h, as the memory straps
are different for helios.
Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All usage of pci_read_config8 was removed in commit d44d4f0f with
Change-Id Ia959eb5b747846048396e66d4c926c96c27f3878 ("mb/lenovo/*:
Remove useless smihandler code"). So we don't need this include anymore.
Change-Id: Ic4f038c80e17799016ae7e92a5675cfe7c71e400
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Helios has a number of GPIO changes w/r/t to its baseboard.
Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452
BRANCH=none
TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change tcc offset from 0 to 10 degree celsius for bloog.
BUG=b:135225497
BRANCH=octopus
TEST=Build and verify test result by thermal team.
Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Memory id's are 1-indexed for DDR4, so we need to check that the SPD
index is non-zero before converting it to the 0-indexed value in the
bitmap.
Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1387028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing
devices to wake up on pen insertion instead of removal. Changed to
EV_ACT_DEASSERTED.
BUG=b:134547896
BRANCH=none
TEST=Verified in OS, device only wakes up on pen removal
Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One variant is asking for support for 16G 2666 LPDDR3, so adding
generic SPD for that.
BUG=b:133455595
BRANCH=None
TEST=None as this is not being used yet
Change-Id: If16a101119aabc30d6ea83e95e9ded2e089a982d
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
One variant is asking for support for 8G 3200 DDR4, so adding generic
SPD for that.
BUG=b:132920013
BRANCH=None
TEST=None as this is not being used yet
Change-Id: I89cd3287aaf0baf384c4fe82d0881b0c48e09753
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33258
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Select ONBOARD_VGA_IS_PRIMARY in driver/lenovo/hybrid_graphics to fix
disabling iGPU in 'Dual Graphics' on Lenovo T430.
* Remove ONBOARD_VGA_IS_PRIMARY in mainboards that already select
DRIVERS_LENOVO_HYBRID_GRAPHICS.
Change-Id: I6594fbb957c9a8135fe670d38b5755adf29d2dff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The values are generated from the respective VBTs.
Change-Id: Ic74e9dac898c17ce64a94b06682997a39daeff69
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30247
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Thomas Heijligen <src@posteo.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add PRESERVE flag to preserve the VPD data.
Change-Id: I78ab4de31030465345c5ae58813bfed5e27494fb
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33020
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
AMD devices traditionally have the LPC-ISA bus at 14.3 and the
definition has been very consistent. Relocate the feature from
stoneyridge into common/block.
BUG=b:131682806
Change-Id: I8d7175b8642bb17533bb2287b3e3ee3d52e85a75
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32653
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The banked GPIO functionality in the AcpiMmio block has been consistent
since the Mullins product. Move the basic support into a common
directory.
Each product's pin availability, MUXes, and other details must remain
specific to the product.
The relocated source also drops the weak configure_gevent_smi() that
reports SMI is not available. The stoneyridge port relies on SMI
to do its initialization, similar to modern soc/intel devices. This
is the plan for future soc/amd ports, so make a missing function a
build error instead of a runtime warning.
BUG=b:131682806
Change-Id: I9cda00210a74de2bd1308ad43e2b867d24a67845
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
* Add initial board commit based on HP8200 SFF.
* Add documentation.
* Serial and PCIe slot are working.
Tested on HP Z220.
Change-Id: I75987a7ea9a008a64281f0d5ab27e5148d36a4ec
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33207
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Because of some differences to the baseboard this board variant needs
its own GPIO table.
Change-Id: Ie3424cb0b867c5d43cd7db9e9ae654196cef5e90
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This automatically detects whether the southbridge supports AHCI.
If AHCI support is selected it will be used unless "sata_no_ahci" is
set in the devicetree to override the behavior.
Change-Id: I8d9f4e63ae8b2862c422938f3103c44e761bcda4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30822
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The RW_LEGACY section needs to be minimum 1M. For the 16MB BIOS
region, we had this region set too small, which was causing the
firmware_FMap FAFT test to fail.
BUG=b:133857135, b:129464811
BRANCH=None
TEST=test_that -b hatch <IP> firmware_FMap
Change-Id: Ie6311613ca3bb08e7f058a41d12f9a1153dc9c5e
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Initial support for Facebook FBG-1701 system.
coreboot implementation based on Intel Strago mainboard.
Configure 'Onboard memory manufacturer' which must match HW.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.15+ kernel on Facebook FBG-1701
Change-Id: I28ac78a630ee705b1e546031f024bfe7f952ab39
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Some variants only support 4 PCIe ports so there is no need to have
those unavailable ports in the devicetree.
Change-Id: I154cae358fb7f862fc0c8eaa620474b37b5e6484
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30821
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:133389422
TEST=check SSD's power off sequence to meet PCIE requirement.
SSD's reset should be cleared before clearing SSD's power EN Pin.
Change-Id: Ia106b805deafb8a442b56bcce91b51135cb32988
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33182
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable LTR for NVMe and WiFi PCIe ports so that they can use ASPM L1.2
BUG=b:134195632
TEST=Verified L1 substate with lspci on hatch:
Before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
After: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I7fce60897b78dde12747ac7fb857c988d16118ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33161
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setting up the SIO serial console is done in the bootblock.
Change-Id: Ideaf8f3dc0ee067e96d3fb5046071551c6d45329
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32985
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It is possible that cbfs_boot_map_with_leak() and malloc() could fail,
so detect those conditions and print error messages if they do.
Change-Id: I34951da0b73028c4c89446cb1779a72422997325
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1399147
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Xiang Wang <wxjstz@126.com>
This fallthrough is intentional (see commit 2257a35862 - Perform PL2
setting for syndra), so add a comment to make that explicit.
Change-Id: I57fe1e08f59aed12544cd2a71f1e0464f432f03b
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1397063
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.
Change-Id: Ia959eb5b747846048396e66d4c926c96c27f3878
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33138
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code was already orphaned since its hook-up was removed
with a6be58fece (nb/intel/sandybridge: Remove the C native
graphic init).
Change-Id: Ia554c457e2f3a2dc42965ac5cded0be8e82311fb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
All Baytrail boards have the same GPU PCI ID, so set it
here to avoid having to set it in each board's config.
Move the VGA_BIOS_FILE config from google/rambi into soc/baytrail
since it likewise applies to all Baytrail boards.
Change-Id: Id1e0580b55e3590d868cb839987f06c49bb07cf5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33026
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Buddy's WLAN ACPI code was equivalent to, but formatted
differently from the other auron variants. Since only
differnce is root port used, have buddy use common
WLAN ACPI and use preprocessor guards to set the root
port correctly.
Test: build/boot Buddy, verify Windows 10 boots
without ACPI BIOS ERROR.
Change-Id: I78d994f2bb3981d4d10cb534cd6e0ae673f73527
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30523
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Create the Kindred variant of Hatch by taking a copy of the Hatch files
as placeholders. Kindred-specific changes will happen in future CLs.
BUG=b:133181366
BRANCH=NONE
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_KINDRED
Change-Id: I09ad3da0505d599fc3797d7fa24b4dc170dcd18b
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These boards don't need a default FMAP. Moreover, having a default FMAP
disables automatic integration of optional regions like `CONSOLE`.
Also, these files contain an error: `COREBOOT` isn't placed at the top
of the image. Resulting in default builds without a reset vector ;)
Change-Id: If6331e19955034c02828e88902a5934c34d3e784
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33110
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
<types.h> is supposed to provide <stdint.h> and <stddef.h>.
So when <types.h> is included, <stdint.h> and/or <stddef.h> is removed.
Change-Id: I3b1a395cfe8b710fb6b468e68f4c92e063794568
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32811
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This gets rid of the boilerplate back and forward calls between the
SOC/FSP-driver code and mainboard code.
Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Also adapt all users of these symbols
Change-Id: Ibf924a283d438de49a93ce661b0d9ca1a81cd6d1
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32956
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
When clapper was upstreamed, the devicetree was pulled from
the wrong firmware branch, leading to some incorrect settings
and touchpad, touchscreen, and audio not working.
Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B
Test: build/boot google/clapper, verify touchpad/touchscreen/audio
functional under Linux (GalliumOS 3.0/kernel 4.16.18).
Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Legacy Google mainboards (pre-Skylake) shipped with the
SMBIOS manufacturer set to GOOGLE, which many Linux drivers
rely on for application of DMI quirks. Set it as the default
to avoid having to do so for each board's config
Change-Id: I61b0217f3535852d7d6e24a1ac78075c20c0825a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The Gigabyte GA-B75M-D3H/D3V mainboard trees share a lot of duplicate
code, and can serve as a base for porting other Gigabyte 7 series
motherboards. Switch the Gigabyte GA-B75M-D3H/D3V mainboard trees to a
variant setup, defining ga-b75m-d3v as a variant of ga-b75m-d3h.
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: Ia175207a2568aefe1aa9bd8d4d990de6a26f1657
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Use the mainboard post code hook to inform the wilco EC driver of the
every stage.
BUG=b:124401932,b:133466714,b:133600566
BRANCH=sarien
TEST=Remove DIMM module, confirm diagnostic LED pattern for memory
failure (2 amber, 4 white).
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: Ic71e4a6e62b63ca2fd189957c4d6f49b61b934de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Even fingerprint device probe failed on non-fingerpint boards,the CRFP driver
still register the device that cause the GPE#1 as wake source every time.
Override devicetree for non-fingerpirnt variants to avoid unexpected wake
event(GPE#1).
BUG=b:129650040
BRANCH=firmware-nami-10775.108.B
TEST=Boots to OS and check no GPE#1 wake event from eventlog when S0ix exit.
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I6fa96e04a34e296889414b96a8c604fc61b8a236
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33017
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Due to we turn off SSD power in S5. CB:32952
Based on M2 spec we have to turn on SSD power
before RST assert.
BUG=b:133389422
TEST=verify warm boot and cold boot are boot
successfully.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5b78bab4be675bbb8795361bcfa5af52cb54bb1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33029
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Turn off SSD power in S5.
BUG=b:133389422
TEST=measure H13 is low in S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I40b5381cac33b0eac962a7730ee5c57e60e6d375
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32952
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Modify reset delay to 20ms of touchscreen to address
i2c hid driver rebind failed issue after auto update of
touchscreen firmware
BUG=b:132211627
TEST=Touchscreen works after auto update and no re-bind
driver failed issue
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: If17afbd160a2c97beb69d0cb50e4a7dc654775f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
TODO in followup patch: Some not mainboard specific things should be
moved out of mainboard_smi_apmc.
Change-Id: Ifc2d8f7755ace598e66b162d071d472093e4656e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This adds a file i82801gx/bootblock_gcc.c since other targets that
don't yet C_ENVIRONMENT_BOOTBLOCK still use the romcc compiled
bootblock.c.
Tested on Foxconn D41S.
Change-Id: I7e74838b0d5e9c192082084cfd9821996f0e4c50
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30939
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Unify thermal handling across Lenovo boards (except g505, which is
different). Namely, do the following:
* Move thermal levels from acpi_tables to thermal.h (and create if
necessary).
* Don't use board-specific ifdef guards.
* Set thermal levels using dedicated acpi_update_thermal_table function
as almost all Lenovo boards do.
* Update list of authors in comments. Merge all author's entries.
* Minor whitespace and formatting.
This makes diff -ruw between the Lenovo boards smaller.
Change-Id: If569f67c932b7fbf14893b890a5588df4994daeb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29659
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There are indeed two temperature sensors hooked up to the EC, but they
are indexed as 0 and 1, not 1 and 2.
BUG=b:132999028
TEST=Boot hatch with hardened EC, observe no more index overflows
Change-Id: Ia7f503bc1dc941635db52fce40f217bf34da6d2b
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Required for automatic onboard device detection in the next patch.
Change-Id: I3087de779faf8d006510c460b5372b22ae54b887
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32909
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Works:
- bootblock, romstage, ramstage
- Serial console UART0, UART1
- SPI flash console
- iGPU init with libgfxinit
- LAN1, LAN2
- USB2, USB3
- HDMI, DisplayPort
- eMMC
- flashing with flashrom externally
WIP:
- Documentation
- VGA
For some reason Seabios can not find the CBFS region
and therefore it can't load seavgabios, but generally
it is working as soon as Linux is booted.
- ACPI
Works not:
- Devices needs proper configuration
- Seabios can't find CBFS region
Untested:
- GPIO pin header
- 60 pin EXHAT
- Camera interface
- MIPI-CSI2 2-lane (2MP)
- MIPI-CSI2 4-lane (8MP)
- SATA3
- USB3 OTG
- embedded DisplayPort
- M.2 slot
- mini PCIe
- flashing with flashrom internally using Linux
Change-Id: Ia913534ec176fc600fcd4ce3af335ebe682b0ed4
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit creates a garg variant for Octopus. The initial settings
override the baseboard was copied from variant bobba.
BUG=b:132668378
BRANCH=master
TEST=emerge-octopus coreboot
Change-Id: I9a36bc5dc3d2b891b1bce86015aa264894d1434b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Currently, GPP_H0 gpio input rout is set to GPI_INT.
So, ACPI_GPIO_IRQ is required for GPP_H0 in devicetree
This change also aligns hatch's setting.
BUG=b:131742713
TEST=headset is working
Change-Id: Ie1264641bc4dfa5f98b6dab2d6f2133a6f9cbdb8
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested:
- Ethernet NIC
- Wifi RFKill
- USB
- LVDS, VGA with libgfxinit
- Booting with dock attached (COM1)
- Keyboard, trackpoint
- SeaBIOS 1.12
- S3 resume
- Tested in descriptor mode, with vendor FD and ME
- Add VBT to ACPI OPregion
Untested:
- SATA (likely works)
- Trackpad (my cable is broken, likely works)
- Displayport (likely works)
- Descriptorless mode
- DVD drive
- Extra battery
- model with ATI GPU
Does not work:
- Dock hotplug
- Quad core CPU (hangs during AP init, probably needs hardware mod)
- Hotplugging the expresscard slot (works with 'echo 1 | sudo tee
/sys/bus/pci/rescan')
TODO:
- proper dock support
- documentation
note: This board was hard to flash, I had to desolder the flash.
TESTED: on a R500 with an Intel iGPU, SeaBIOS 1.12, Debian 9,
Linux 4.9 from USB
Change-Id: I9e129b2e916acdf2b8534fa9d8d2cfc8f64f5815
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
All variants (t400, r400, t500, w500) use the same OPROM for the IGD.
Change-Id: I1b9db7b29b22809542f80f60a5e2eb3283fe1c02
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
sarien/arcada:
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D18 IRQ mapped for H1 TPM.
hatch:
GPIO_COMM_0/1/2/3: Enable gpio community all PM configuration
GPIO_COMM_4: Disable RCOMP clock gating due to GPP_C21 IRQ mapped for H1 TPM.
BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: Ia4d5483847a4d243b9038119d4bb5990591cc754
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO_COMM_0/2/3/4: Enable gpio community all PM configuration.
GPIO_COMM_1: Disable RCOMP clock gating due to GPP_D16 IRQ mapped for H1 TPM.
BUG=b:130764684
TEST=H1 TPM interrupt working find and able to boot from fixed boot media
Change-Id: I1f83f938f201c6574367960b1027555767cf6f3d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Apply commit d7b88dcb (mb/google/x86-boards: Get rid of power button
device in coreboot) to AMD Brazos boards [1]:
> As per the ACPI specification, there are two types of power button
> devices:
> 1. Fixed hardware power button
> 2. Generic hardware power button
>
> Fixed hardware power button is added by the OSPM if POWER_BUTTON flag
> is not set in FADT by the BIOS. This device has its programming model
> in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this
> power button device by default if the power button FADT flag is not
> set.
>
> On the other hand, generic hardware power button can be used by
> platforms if fixed register space cannot be used for the power button
> device. In order to support this, power button device object with HID
> PNP0C0C is expected to be added to ACPI tables. Additionally,
> POWER_BUTTON flag should be set to indicate the presence of control
> method for power button.
[..]
> This change gets rid of the generic hardware power button from all
> google mainboards and relies completely on the fixed hardware power
> button.
The same problem exists with the AMD Hudson devices in coreboot.
For AMD Hudson (2) and Yangtze based devices this was removed in commit
44f2fab8 (AMD hudson and yangtze boards: Let mainboard declare power
button) [2].
Two devices are detected.
$ dmesg | grep Button
[ 0.209213] input: Power Button as /devices/LNXSYSTM:00/LNXSYBUS:00/PNP0C0C:00/input/input0
[ 0.209254] ACPI: Power Button [PWRB]
[ 0.209332] input: Power Button as /devices/LNXSYSTM:00/LNXPWRBN:00/input/input1
[ 0.209349] ACPI: Power Button [PWRF]
$ sudo evtest
No device specified, trying to scan all of /dev/input/event*
Available devices:
/dev/input/event0: Power Button
/dev/input/event1: Power Button
[..]
[1]: https://review.coreboot.org/5546
[2]: https://review.coreboot.org/27272
Change-Id: I0cbecb72f7e1bf3d051d3b7656c6af4d6f43b497
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/27496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The system should boot fine to OS on pressing power button before the
system enters G3. However, on hatch, we observe that the system waits
for few seconds at "Starting kernel" and then resets, with SD card tray
inserted and SD_CD# pad reset config set to DEEP. Hence configuring SD_CD#
pad reset config to PLTRST.
BUG=b:129933011
TEST=Built and verified on hatch.
Change-Id: Ic4466b96332f095ff39b28d98607e95fc3d12d6a
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set the system serial number from the VPD key "serial_number" and
the mainboard serial number from the VPD key "mlb_serial_number".
BUG=b:132970635
TEST=check serial number is set in SMBIOS based on VPD, and if there
is no VPD key found then it is empty.
Change-Id: Ia8f1486dcb1edc968b8eb1e6d989b10c05913aca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
- Enable LPC TPM support in Kconfig and add pc80/tpm to devicetree
- Enable VBT support in Kconfig and add VBT files extracted from
vendor firmware
- Remove IGPU VBIOS entries from Kconfig
- Remove unused PS2 definitions in superio.asl
- Add PWRB ACPI device entry to mainboard.asl
- Remove duplicate chipset register initialization from mainboard.c
- Move ITE Super I/O configuration to mainboard_config_superio in
romstage.c
Signed-off-by: Alex James <theracermaster@gmail.com>
Change-Id: I2d11c55dc809b920bccf55f5f745d9f29b18bbb6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
That's how we do it these days.
Change-Id: I6bf6460440d0f2e6973734ba8894a4be981d03c5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32812
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The FSP will lock down the configuration of GPP_A12, which
makes the configuration of the GPIO pin on warm reset not
work correctly.
This is only needed for the Arcada variant since it is the only variant
that uses ISH.
BRANCH=sarien
BUG=b:132719369
TEST=ISH_GP6 now works on warm resets on arcarda
Change-Id: Icb3bae2c48eee053189f1a878f5975c6afe51c71
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32831
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the stoneyridge AcpiMmio code into soc/amd/common.
The SB800 southbridge introduced the MMIO hardware blocks at 0xfed80000
commonly known as AcpiMmio. Implementations beginning with Mullins
enable decode in PMx04. Older designs use PMx24 and allow for
configuring the base address. Future work may support the older version.
Comparing the documentation for AMD's RRGs and BKDGs, it is evident that
the block locations have not been reassigned across products. In some
cases, address locations are deprecated and new ones consumed, e.g. the
early GPIO blocks were simpler at offset 0x100 and the newer GPIO banks
are now at 0x1500, 0x1600, and 0x1700.
Note: Do not infer the definitions within the hardware blocks are
consistent across family/model products.
BUG=b:131682806
Change-Id: I083b6339cd29e72289e63c9331a815c46d71600d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32649
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This allows for serial console during the bootblock and enables
bootblock console by default.
Change-Id: I7746e4f819486d6142c96bc4c7480076fbfdfbde
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Previously broadwell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
With a separate verstage the romstage becomes an RW stage.
The mrc.bin however is only added to the RO COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I900233cadb3c76da329fb98f93917570e633365f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30384
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds a workaround for Samsung C-die 2G/4G memory chips.
For unknown reasons, some boards with Samsung LP3 memory chips
could not pass early CS/CMD training. MRC has to change the
granularity from 16 ticks to 8 ticks, which implies bad margin
with this memory chip. Another way is to enhance the drive
strength for CS. This patch is to enhance the drive strength for CS
and CMD. Enhancing the drive strength for CMD could gain margin abaout
3 more ticks. Root cause needs to be further investigated with memory
vendor.
BUG=b:131177542
BRANCH=None
TEST=USE=fw_debug emerge-atlas chromeos-mrc coreboot chromeos-bootimage
& check the MRC log to ensure correct Rcomp values are passed to
MRC. Tested with board ID #8 and #11.
Change-Id: I9ea3ceda8dc8bf781063d3c16c7c2d9b44e5ddd6
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Call the raminit from a common location instead of from the mainboard
specific code.
Change-Id: I65d522237a0bb7b2c032536ede10e2cf93c134d8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32760
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To improve the bootflow, the scope of the pei_data needs to be
extended.
Change-Id: Ic6d91692a7bf9218b81da5bb36b5b26dabac454e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
This also links the gpio configuration instead of including it as a
header.
Change-Id: I9309d2b842495f6cff33fdab18aa139a82c1959c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Move the onboard SPD to second channel as native raminit does and workaround
mrc expecations in northbridge code.
Required to move pei data to devicetree and to use the same code for mrc and
native raminit.
Tested on Lenovo T520:
Other fields then spd_data[0] are ignored.
Change-Id: If1910e82a4bd178c2a6c2991c91e09782122888e
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The GPIO invert registers are already defined in the PCH code, so
just use the 8-bit versions of the registers instead of creating
a new GPIO field for the single bits.
This allows us to get rid of the Field(GPIO...) code that's causing
problems with IASL version 20190509.
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Iac5dfb71b3a2b5a25c05a403cf5f403c7acecaaf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
The gpio table is only used by depthcharge, and depthcharge rarely
has a need for the "recovery" gpio. On a few boards it does use the
gpio as a signal for confirming physical presence, so on that boards
we'll advertise the board as "presence".
All these strings probably should have been #defines to help avoid
typos (e.g., the "ec_in_rw" in stout seems questionable since everybody
else uses "EC in RW").
Cq-Depend: chromium:1580454
BUG=b:129471321
BRANCH=None
TEST=Local compile and flash (with corresponding changes to depthcharge)
to 2 systems, one with a "presence" gpio and another without. Confirmed
that both systems could enter dev mode.
Change-Id: Id6d62d9e48d3e6646cbc1277ea53f0ca95dd849e
Signed-off-by: Matt Delco <delco@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
A12 is not current set for ISH_GP6 so the ISH_LID_CL#_TAB
signal is not making it to the ISH properly. Enable the second native
function instead of the first.
BRANCH=none
BUG=b:131785573
TEST=gpioget on ISH now shows the correct gpio level
Change-Id: Ib3a654ae659037263aa9aa29d45b42ca67b7955b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32738
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We keep the support, though. Just now that `libgfxinit` is fixed, we
don't need the distinction anymore. Causally, we also don't need
CPU_INTEL_MODEL_306AX any more.
TEST=Played tint on kontron/ktqm77. Score 606
Change-Id: Id1e33c77f44a66baacba375cbb2aeb71effb7b76
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The Kconfig MAINBOARD_FAMILY sets the family field of SMBIOS entry 1.
Match what vendor firmware does and use the same value as in the
version field.
Required for fwupd which uses the family field to generate a GUID.
Change-Id: I0033c42c5eac6b9d47d0acd16c67467b6d419534
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Leakage power is observed from TOUCH_SCREEN_PD# (GPP_E7 which is connected
to RESET pin of Wacom controller) during S5.
To avoid leakage power, GPP_E7 needs to be turned off before S5 entry.
BUG=b:129899315
TEST=Measure leakage power in S5 from both Arcada and Sarien
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie4229477b7149c0a75f4a8c6c7c453a37cc1c78c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Add vbt files for nami variants and select Kconfig option
to utilize them. The default vbt is automatically added
by the Kconfig selection and so does not need to be
specified in the makefile with the others.
Test: boot vayne and akali nami variants, verify
display functional and correct vbt loaded.
Change-Id: Iaf49bdee7ae82a0a61192327351267f098eb5ab1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set tcc offset value to 1 degree celsius for Arcada system.
BRANCH=None
BUG=b:122636962
TEST=Built and tested on Arcada system
Signed-off-by: Bonnie Lin <bonnie_ty_lin@wistron.corp-partner.google.com>
Change-Id: I3ca4be2f7b92e29fb133ecc32023526b177d2ac2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Correct Micron MT40A512M16TB-062E:J SPD CRC to 0x5330 to fix post hang
in AGESA TestPoint:05 TpProcMemSPDChecking.
BUG=b:127394249
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Change-Id: I8fa49e6e938b3195945b3199438cc53f3e9c92e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.
BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A subsequent patch will move the AcpiMmio support into amd/common.
Take this opportunity to rename the blocks in the 0xfed8xxxx region
with more consistency.
Change-Id: I9a69a6ecfc10f78b4860df05a77a061d2fc8be7d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable VBOOT support on all devices that have a 8 MiB flash, using a
single RW_MAIN_A partition, allowing the use of tianocore payload in
both RW_MAIN_A and WP_RO.
* Add VBNV section to cmos.layout
* Add FMAP for VBOOT and regular boot
* Select Kconfigs for VBOOT
* Enable VBOOT_SLOTS_RW_A by default
Also build test VBOOT on Lenovo T420.
Tested on Lenovo T520 using Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6.
Change-Id: Icb7b263ed86551cc53e1db7babccaca6b3ae2fe6
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32585
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Mark all known PCIe root ports as ExpressCard slot.
Tested on Lenovo T520.
Change-Id: I43fb481512a54ee054c6fd0189053028fb3c3ec2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32309
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill SMBIOS type 9 fields for both sarien and arcada platform.
BUG=b:129485789
TEST=Boot up into OS and check with dmidecode -t 9 to we do have entry.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I47a697131b7aeeb64e0c4b4c0556842f1cb1b02e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
`pei_data` was a struct with blob parameters from pre-FSP times.
Somehow, it sneaked into upstream FSP1.1 support (probably because
early board ports were written for a different blob). When added
upstream, its usage was already perverted. It was declared at SoC
level but mostly used to pass mainboard data from mainboard code
to itself and FSP data from FSP code to itself. Now that no board/
SoC code uses it anymore, we can finally drop it.
Change-Id: Ib0bc402703188539cf2254bdc395cca9dd32d863
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
never consumed anywhere again. So just merge the used code into
`romstage.c` where it's effectively used.
Change-Id: I499b3cfcdd5400ea132749555d433a2d8a9471a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I040f4a55b4f4bad3f6072920e5e2eceded4cb9bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
The provided solution locates the SPD data in CBFS again to fill SMBIOS
tables. This is not perfect. OTOH, this code isn't mainboard specific
and doesn't belong here anyway.
Change-Id: Ib6103d5b9550846fe17c926631a013ff80b9598f
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
`chip.h` is usually used as devicetree interface.
Change-Id: Ied30927d68927b86758a84ccf3f5fbd8cce632f1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32592
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: I399dd89f85ccea43fdf90bd895e71324f4b409cc
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The SoC specific `struct pei_data` was filled with values that were
later only consumed by the mainboard code again. Avoid jumping through
this hoop and fill FSP UPDs directly.
Change-Id: Ibc013ccea9f83ef29f22fe2da4c0d12096308636
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The MacBook Air 4,2 uses eDP, according to the schematics.
Change-Id: Ifc98eab343fd89b8512e92e01fddf34ef8447d5f
Signed-off-by: Evgeny Zinoviev <me@ch1p.io>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32606
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Turn off camera power when s0ix for power saving.
BUG=b:129177593
TEST= measure camera power comsumption is 0mV under s0ix
Change-Id: I5a9b7ec1e95cc9931d8d5f2dc1254805c9d0ffed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
A13 and A15 need to set low before H12 reset. Change
the program sequence for fit HW requirement.
BUG=b:131876963
TEST=boot up and check SD card functional
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I2f1752070f24833aaaab75dea8493caf2ed7f157
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch fixes up all code that would throw a -Wtype-limits warning.
This sometimes involves eliminating unnecessary checks, adding a few odd
but harmless casts or just pragma'ing out the warning for a whole file
-- I tried to find the path of least resistance. I think the overall
benefit of the warning outweighs the occasional weirdness.
Change-Id: Iacd37eb1fad388d9db7267ceccb03e6dcf1ad0d2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32537
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove the Librem 13v3 as a separate board; instead build a
single firmware image for the 13 v2/v3 boards.
Clean up Kconfig options:
- remove entries for 13v3 board
- fold entries into a single line where possible
- remove redundant MAINBOARD_VERSION option (will default to 1.0)
- remove unused microcode length/location (only needed for FSP CAR)
Test: build/boot Librem 13 v2/v3 boards with same image
Change-Id: Ic09b8ec5c576f4c4c48ef30ee3f60a4c2c286cd3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Run CPU at the highest freqency (1989MHz) to speed up the boot time.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui
Change-Id: I703ffcb99367f87e6792a72485f5634e0505e5ac
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32466
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updated GPP_A8 to be a GPI and SCI source, to support both wake and
notifications.
BUG=b:128941098
BRANCH=none
TEST=Compiles, simulated pen eject with PCH_INT_L signal. Both evtest
and waking from s0ix confirm this works. The output of /proc/interrupts
confirms the correct interrupt is triggered.
Change-Id: I080fb3cbfb3e2f55209ca31824b00ca820d70f78
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Due to PCB limitations the SD-Card interface is not able to operate
with the highest frequency reliably. The OS driver will switch to
the highest mode if a SD-Card is attached which supports this high
frequency mode. In order to work around this PCB limitation disable the
high frequency modes in the controller capabilities (SDR104 and HS400
mode) and leave SDR50 and DDR50 enabled.
Change-Id: Ia5fed5fb70b027de34170b49620927614a00fb7a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
IASL reports warning 'Control Method should be made Serialized'.
Change _CRS method to Serialized.
BUG=N/A
TEST=Build Google Banon and Google Cyan
Change-Id: Iffa097a2100cfa91efa3b617311500b83f839bce
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32331
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
CB acts as I/O handler for QCLib (e.g. DDR training data)
This interface allows bi-directional data flow between
CB and QCLib
Tested and working interfaces:
DDR Training data
QCLib serial console output
DDR Information (base & size)
limits cfg data
TEST=build & run
Change-Id: I073186674a1a593547d1ee1d15c7cd4fd8ad5bc1
Signed-off-by: T Michael Turney <mturney@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The current Braswell FSP 1.1 header in vendorcode/intel, for
which there is no publicly available FSP binary, contains silicon
init UPDs which are not found in the publicly available header/binary
in the FSP Github repo. This prevents new boards from being added
which use the public Braswell FSP header/binary.
To resolve this, move the UPDs not found in the public header from
the soc's chip.c to ramstage.c for the boards which use them. Add
a Kconfig option to use the current non-public FSP header and
select it for boards which need it (google/cyan variants); set the
public FSP option as the default. Use the Kconfig option to set
FSP_HEADER_PATH to ensure the correct header is used.
Test: build google/cyan and intel/strago using non-public and
public FSP header/binaries respectively.
Change-Id: I43cf18b98c844175a87b61fdbe4b0b24484e5702
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.
BUG=b:131144464
TEST=waveform test and hardware validation result pass.
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I395b2fc527705ab207325cfd7147e6af5f300fce
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32521
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Main objective for this change is to export the bluetooth reset
gpio to the kernel for use in an rf-kill operation.
To do so, we enable USB acpi and define all of the USB2 devices,
which includes bluetooth's reset gpio information.
BUG=b:122540489
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage
$cat sys/firmware/acpi/tables/SSDT > /tmp/ssdt.dat &
retrieve ssdt.dat from DUT &
$iasl -d ./ssdt.dat & check the HS03 node is with "reset-gpio"
under _DSD object
Change-Id: I411ef707782655361bd1b8ac2b914b8ae64defeb
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Caveh Jalali <caveh@google.com>
This patch adds code to initialize two USB DWC3.0 controllers
and its associated QUSB V2 10nm PHYs to the SDM845 SOC, and uses them to
initialize USB3.0 on the cheza mainboard.
Synopsis controller initialization and configuration sequences taken from
USB 3.0 HPG chapter 2.2 and refer PHY HPG chapter 10.2 for QUSB phy
programming.
Includes Super speed mode support.
TEST=USB keypad and mass-storage device enumeration tested with this patch
Change-Id: I475a7757239acb8ef22a4d61afd59b304a7f0acc
Signed-off-by: Chandana Kishori Chiluveru <cchiluve@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25213
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Chromebook doesn't require support wake on LAN in S5.
Disable it by default for power saving.
BUG=b:131571666
TEST= check LAN indicator is off under S5
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia90c9d2f3ea9b3580e9a7bbfb47c917dd51e3c03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
a 1M CBFS size is inadequate when adding the FSP binary to
image due to default FSP location in CBFS, so bump to 2M
to ensure autobuilds succeed.
Change-Id: I0683bea43cc71fad32bc42bfbd72f3913256d53c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Patch corrects IRQ and GPIO configuration for RT5682 codec's Jack INT.
Switching IOAPIC to GpioInt because ACPI Interrupt() doesn't support
jack triggering on both edges.
BUG=b:130180492
TEST=build and boot on a CML EVT board.
Use evtest & verify headset jack detection functions as expected.
Change-Id: Ia9bf8d554b54554f9ac1e78fd44a508964c8a14d
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Suggested-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32474
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the GBB flag forcing manual recovery now that we can read
the manual recovery from H1.
Enable the GBB flag to skip EC software sync, since images built
from coreboot.org do not include the EC binaries by default.
Change-Id: I0e1d6304e3e29eda68c7b807cf0774275c37d710
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We do not want the RX signal to be floating on the board as that could
cause the ISH to remain in a higher power state (because there is logic
to keep the ISH in an higher power state when there is an active UART).
Add an internal 20K pull up on the RX line. In normal configuration this
will burn an additional 544uW.
BRANCH=R75
BUG=b:131241969
TEST=verify that ISH console still works with rework
Change-Id: Ifc9621bcafe4c86edfa9cd6d58b307254d3a81ca
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This patch adds the setting of psys_pmax to 136W. According to the
design, Rpsys is 11.8Kohm. Here is the equation to come out the
Psys_pmax value: Psys_pmax * 1.493uA/W * 11.8Kohm / 2 = 1.2V
Hence, Psys_pmax is 136W.
BUG=b:124792558
BRANCH=None
TEST=emerge-sarien coreboot chromeos-bootimage & Ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Id3f6be5f0c2346a7763195a992c0ae45faede056
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
The ACPI code of LPE device is included regardless of the
availability of the LPE controller.
Linux remains requesting the status of device LPEA even if
this device is disabled.
Include ACPI LPE controller code at Braswell mainboards with
LPE enabled.
BUG=N/A
TEST=Linux 4.17+ on Portwell PQ7-M107
Change-Id: Ic8acf9ea9e9b0ba9b272e20beb2023b7a4716a73
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
The dqs_map array is used only for LPDDR3 and LPDDR4. It is not used for
DDR4, and so it can be removed from the baseboard memory initialization
code.
BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Change-Id: I07fac3097d68f37b4630d3f0010f987da2f03bd7
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32484
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
First configuration supported is 8 GB system memory:
4 x 2 GB (K4E6E304ED-EGCG).
BRANCH=none
BUG=b:129706819
TEST=ensure the firmware builds without error; I don't have hardware
available to test this just yet.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: Ibd92d585118ff75492e8a7188dcdb2a286836d56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Changes includes:
- enable TPM1 + add entry in devicetree
- configure LPC IO to make IPMI work + add entry in devicetree
- introduce DSDT and SMBIOS entries for IPMI to make it detectable
by ipmi_si driver
Signed-off-by: Lukasz Siudut <lsiudut@fb.com>
Change-Id: Ia975643064075f1f861f4ead6f24ed71f345ea04
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Enable LTR for NVMe so it can use ASPM L1.2.
BUG=b:127593309
TEST=build and boot on sarien and check L1 substate with lspci
before: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+
after: L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+
Change-Id: I9842beda6767f758556747f83cfcedbd00612698
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32456
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Roy Mingi Park <roy.mingi.park@intel.com>
This patch revises the AC/DC loadline settings because some major
layout changes between proto and evt boards.
BUG=b:130740639
BRANCH=None
TEST=emerge-atlas coreboot chromeos-bootimage and boot to the OS.
Change-Id: Iea12c621e7fab427a0de8f43f0290bf01d0c5a09
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Add FP_RST_ODL to early GPIO table, configured as low, so that the FPMCU
will get reset when coreboot enters bootblock.
BUG=b:130229952
BRANCH=none
TEST=Compiles (no Hatch device w/FP to test)
Change-Id: I8a8d8cc2c560f6518337f7500575fdc2265b6347
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32419
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Lynx Point switched to doing mainboard-specific super I/O setup in the
bootblock with commit d893a2635f ("sb/intel/lynxpoint: Enable LPC/SIO
setup in bootblock"). The X10SLM+-F was added while that commit was in
review, and hence did not receive the necessary changes to SIO setup.
This patch has not been tested on hardware.
Change-Id: I7a648ec967dea2113cbbde1a93c1963ca6dd3c88
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
On EC end, we want to change this pin from push-pull to open-drain.
And since there is no external pull-up resistor on the board, we'll
have to configure this pin as internal-pull-up on AP end.
BUG=b:129306003
TEST=None
Change-Id: Ibc1f89fc25773220db009c6571400b01390dd756
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Not all Hatch variants utilize the SoC's native SD card support. Move
the support to board-specific variants instead of the base device tree.
BUG=none
BRANCH=none
TEST=compiles (no Hatch device to test with)
Change-Id: Iae24114aad2c4d042c25da6f8cb740ccc8960082
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32417
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to hatch(CB:32278), this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in
FSP.
This change also adds a device to kohaku override tree to ensure that
the settings in it take effect.
BUG=b:130310626
Change-Id: Ia25b45811be26d55fc0019e4cd22eb7310b5a4c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32398
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Enable acoustic noise mitgation for arcada platform,
the slow slew rates for Ia and Gt are fast time dived by 8.
BUG=b:131144464
TEST=waveform test and hardware validation result pass.
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Change-Id: I37315ecfa245fce3085e62d1566ff037d8aa8ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32403
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Disable the POWER_OFF_ON_CR50_UPDATE option on sarien/arcada. This is
needed so that platform properly boots after doing a Cr50 firmware
update when running on battery.
BUG=b:126632503
BRANCH=none
TEST=Build coreboot on sarien/arcada.
TEST=Perform Cr50 firmware update on Sarien, confirm the platform boots
normally after sending TURN_UPDATE_ON to the Cr50.
Change-Id: I0b687285eb95070eaffb68611a7d98eb8434ce2c
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.
BUG=b:129899315
TEST= Measure touchscreen power from Sarien during S0iX
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I48419132ba734f20ad5cf484c2dda609570a6dd0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32330
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Sarien will change Melfas from HID to I2C and change address from
0x10 to 0x34. So we don't need VPD to separate Elan and Melfas
anymore.
BUG=b:131194574
TEST=boot up and check no Melfas HID device exist
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic002f61b226743e1c18dbdbc51ce8b733916d8a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32437
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We want to disable touch for non-touch sku. We can use
strap pin GPP_B4 to identify it is connected with touch
or not.
touch sku: GPP_B4 is low
non-touch sku: GPP_B4 is high
BUG=b:131132419
TEST=boot up and check no touch device exist
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If6681262c25e4b01e061a8520e38905d40345509
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32438
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SSD reset pin had been added on DVT2, the power sequnence requires
toggle in boot stage.
BUG=b:130741066
TEST=Boot up with simulated DVT2 platform and confirm SSD can be
detected during warm reboot.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie734875a49b8b61f8b813c473d30cbcaf4dd13d1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32434
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C params for I2C buses 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:131132499, b:128998988
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Ie8cfba72a0654402ccb0274c00b44fbfa2deea21
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This allows for serial console during the bootblock and enables
console in general for the bootblock.
Change-Id: I5c6e107c267a7acb5bf9cbeb54eb5361af3b6db4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30315
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change will save touchscreen power leakage 2-3mW in S0iX and
increase T2 display time delay to meet display panel requirement.
BUG=b:129899315
TEST= Measure touchscreen power from Arcada during S0iX
Change-Id: I4b8f3fdc0d107b080c5febe6fa5d29ea5d1ed0fc
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Include pch.h in the source files instead in sandybridge.h.
Tested on Lenovo T520 (Intel Sandy Bridge).
Still boots to OS, no errors visible in dmesg.
Change-Id: I9e5b678e979a8d136d8d00b49486d0a882f77d81
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The pci_or_configx function makes the code shorter and more readable.
Change-Id: Ic1ba250f8ac9fb75cf3252aec18af80842bda7dd
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Droid/Blorb supports keyboard backlight feature, so enable the ASL code.
BUG=b:130330141
BRANCH=octopus
TEST=Build and boot to OS, verify that the string 'KBLT' is in the DSDT.
Change-Id: I74684e3905d34b61fa4b851798dbca018f986e5a
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When the components like LCM ID are not installed (i.e., NC), ADC will
return some value with much larger variation from standard value (out of
the tolerance we set). To support that, we should check tolerance only
on non-NC voltages.
Also improve the error messages so we can see the ADC raw values
instead of simple assertion error (which makes debugging more difficult
since we have to build another firmware image just to print the values).
BUG=None
TEST=Booted on Kukui and got correct SKU ID for NC LCMID.
BRANCH=None
Change-Id: I8d00956e0e3b48ddbcaa505dd3ade24720c3b4ad
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32353
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, Arcada only supports D3hot during S0iX and there is leakage
power around 5~10mW depending on SSD vendors.
To support D3cold for SSD during S0iX, one MOSFET will be added on DVT2
and two GPIOs are required to be configured.
GPP_H13 is to control SSD_SCP_PWR_EN(power enable) and GPP_H12 is to
control SSD reset.
BUG=b:130741066
TEST=Measure SSD power during S0iX from Arcada(DVT2)
Change-Id: I868590e9e85d5df07930a3681884e3fc3a5c4d50
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32361
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Previously Haswell used a romcc bootblock and starting verstage in
romstage was madatory but with C_ENVIRONMENT_BOOTBLOCK it is also
possible to have a separate verstage.
This selects using a separate verstage by default but still keeps the
option around to use verstage in romstage.
Also make sure mrc.bin is only added to the COREBOOT fmap region as it
requires to be run at a specific offset. This means that coreboot will
have to jump from a RW region to the RO region for that binary and
back to that RW region after that binary is done initializing the
memory.
Change-Id: I3b7b29f4a24c0fb830ff76fe31a35b6afcae4e67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/26926
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
I2C 1 is not being used in any of the octopus variants, so disable it.
BUG=none
BRANCH=octopus
TEST=Verify on meep and bloog
reboot and s0ix suspend successfully
Change-Id: I7ed5065cfd0b9780d13feb27cc78b8090d7a03a6
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32349
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
arcada is designed to operate at max power of 140 Watt. Hence set psys_max to 140W.
BUG=b:124792558
TEST=Build and boot arcada.
Change-Id: I280dfb81b3e25c7619a68db487e2b18867f52fda
Signed-off-by: nathan chen <nathan_chen@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Ensure Kohaku GPIO pins are configured correctly w/r/t Hatch. Implement the
base/override model for GPIOs (regular and early). The 'hatch' baseboard
contains the base GPIOs, and variants can override individual pads.
BUG=b:129707481
BRANCH=none
TEST=Compiles for all variants.
Change-Id: Ie5c83a0538d367ea11e9499f21cea41891d7a78e
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Match SMBIOS type 17 device locator with motherboard silk screen,using
"DIMM-A" and "DIMM-B" instead of "Channel-0-DIMM-0" and
"Chaneel-1-DIMM-0".
TEST=Boot up with sarien platform and run dmidecode to check SMBIOS
type 17 have expected output.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie2125c0381bd24d96f725f68cde93a53da8c94c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
GPIO pin GPP_C23 is used as level trigger but not edge trigger, also it
is not inverted, correct it here. According to board schematic, GPP_C23
connected with 3.3v pull up, so the pin is low active.
BUG=b:128554235
TEST=Boot up arcada platform with stylus keep on touching the screen,
the touch screen is still functional once in OS stage. Without change,
touch screen is not functional at same scenario.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I2bee664198057e3997dda181a16b9a0388067036
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32347
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable the Kconfig option to automatically read the board ID
and populate it into the SMBIOS tables.
BUG=b:123261132
TEST=verify current board id from the OS:
cat /sys/class/dmi/id/board_version
rev1
Change-Id: Id41631bfaa627ca9d5034e2ebe93f8ace2ffdad8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32277
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set default configuration to low for gpio_178, and can remove the
override setting for bobba/bloog/fleex/meep/phaser.
For ampton, Change-Id I64a67f73564188ad0548a1a770169ef2bca47453 (
mb/google/ampton: Fix polarity of EN_PP3300_WLAN_L signal.)
modified the pin setting.
TEST=verified that boot into OS on meep board.
suspend/resume, reboot, and no failure found.
Change-Id: I7668ff4817edfca5c6cea63db779fcea21c7af92
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32247
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Write protection (get_write_protect_state) was hard-coded to 0 and
should be fixed to read from correct GPIO (PERIPHERAL_EN0 from
schematics).
BUG=b:130681408
TEST=make -j; boots on Kukui Rev2.
BRANCH=None
Change-Id: I75b98b1d587abe5e8cdf3df28ea661bc1ffa19f9
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Kukui is using MIPI display panel and needs some identifier to tell
payloads which LCD module is installed, and to select right kernel
device tree. Following Scarlet, the decision is to embed LCD module ID
as part of SKU ID.
The LCM ID is using a different voltage mapping table from the rest.
Considering the complexity in computation of SKU ID, it is better to
move the cache logic from get_index to caller.
Also revise the mapping table since ADC on 8183 only supports 12
levels.
BUG=b:129299873
TEST=make -j; boots on Kukui Rev2 unit.
Change-Id: Ib0c00bc8ce3c71c445c5c4561403ce8ef4dd5844
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32263
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The external RTC was removed on the mainboard as it is not needed.
Remove the usage of the driver for RX6110SA as well.
Change-Id: Ia476e58c0b0f343d4e9e4fa6039bf82b194a87d3
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
With commit
'4074ce0cc7 (intel/apollolake: Add HDA to disable_dev function)'
FSP is now requested to switch off HDA PCI device if it is disabled in
devicetree. Doing so results in a warm restart. Normally this event
will be stored in CMOS RAM (if the descriptor is configured to do so)
and therefore no further resets are requested by FSP on the next boots
as long as CMOS RAM is kept alive.
The Siemens mainboards based on Apollo Lake do not have a CMOS battery
and therefore the CMOS is not backed up. This leads to reset requests
from FSP after PCI enumeration on every boot. To avoid this reset enable
HDA in devicetree for these mainboards. Though we do not have any usage
of HDA it should not be an issue that the HDA device is now enabled. The
benefit is though that no reset is requested anymore by FSP.
Change-Id: I637c7c01d73350700c6066fee74fecbb5b93b221
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32295
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Based on the power rail discharge times measured on hatch,
update the assertions widths that have to be programmed in SoC.
BUG=b:129328209
TEST=warm/cold reboot and S3 are working fine on hatch.
Change-Id: I3c6dce0a942e6dcd9e55ef5e58a7e9e8d2b0a1e3
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32266
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Laser would prefer to use different SAR values. Since Laser
sku id is 5.
BUG=b:130381493
BRANCH=octopus
TEST=build
Change-Id: I5cce38a191edfb235e274db3c788c58b65e0ebe1
Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32296
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use common code to detect ACPI S3.
Tested on Thinkpad X60.
Change-Id: Ia759a9ed141efc8130860300f2a8961f0c084d70
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32041
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Use common code to detect ACPI S3.
Untested.
Change-Id: I2264c087b317f70506817b5458295a17e83b1efc
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32038
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Restore Goodix devicetree config because of the
missing Goodix config when moving from baseboard
devicetree to board level overridetree. And move
PENH from I2C#2 to I2C#1.
BUG=b:124460799
BRANCH=None
TEST=local build and tested with Goodix touch screen
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic028c5d7b687a069d7f0510897bea91dca58e91f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change uses GPIO IRQ instead of IOAPIC for GPP_A0 pad which is
the interrupt line for sx9310. This is required because IRQ# used by
GPP_A0 is allocated for PIRQ which does not allow IRQ# sharing.
Additionally, this change also configures GPP_A6 for GPIO IRQ. GPP_A6
is currently unused in the devicetree.
BUG=b:129794308
TEST=Verified that there are no interrupt storms on GPP_A0.
Change-Id: Ibb510a647391c0d9cb854d23656bb4b1cb7756ab
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This change configures reset config for all pads routed to IOAPIC as
PLTRST. This is required to ensure that the internal logic of the GPIO
gets reset any time the platform enters S3 or powers off and avoids
any interrupt storms on boot-up.
BUG=b:129933011
TEST=Verified that there are no interrupt storms on boot-up from S5.
Change-Id: Ib790280c9f1410fa18746d4d7d2a5027afd7585b
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add the new configuration 'Krane' that will need at least its own EC.
There's currently no difference in coreboot side.
BUG=b:130011505
TEST=make menuconfig; make -j # select board=Krane
BRANCH=None
Change-Id: Ibb2ec42b08f9a51b22c22f3fe99b203f5eb31627
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Three GPIOs are not being used and this change will save 2-3mW
power during S0iX and this power saving is only for Arcada
BUG=b:129990365
TEST= Measure total platform power during S0iX from Arcada
Change-Id: Ie0208bd6c7affb2e87fd76005b727ea7effdf434
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
WiFi enable signal was configured and driven as active-high, but the signal is |To start the server in this Emacs process, stop the existing
actually active-low
BUG=b:130196983
BRANCH=none
TEST=Verified WiFi still works after boot, and also after a suspend/resume cycle. Device powers down correctly using "poweroff".
Change-Id: I64a67f73564188ad0548a1a770169ef2bca47453
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32255
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The "write protect" GPIO's cached value is never actually
read after entering depthcharge. Ensure the value from
get_write_protect_state() is being transferred accurately,
so that we may read this GPIO value in depthcharge without
resampling.
The cached value of the "recovery" GPIO is read only on certain
boards which have a physical recovery switch. Correct some of
the values sent to boards which presumably never read the
previously incorrect value. Most of these inaccuracies are from
non-inverted values on ACTIVE_LOW GPIOs.
BUG=b:124141368, b:124192753, chromium:950273
TEST=make clean && make test-abuild
BRANCH=none
Change-Id: Ic17a98768703d7098480a9233b752fe5b201bd51
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For Kukui CR50_IRQ pin, we're going to replace external pull-up with
internal pull-up. This change won't break older boards, so we can just
always do that when setting up GPIOs.
BUG=b:124821269
BRANCH=none
TEST=Waveform looks correct.
Change-Id: Ib1a90dce583a6aa0cec8ac8ba96d1362f50c16a8
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
ODM reported issues that some systems can't be shutdown to S5 very
occasionally.
ODM found issue is gone if they remove the WLAN card.
So, this change to disable WLAN before system enters S5.
This change is validated by ODM and it does help issue.
BUG=b:129377927
Change-Id: Ib8e81022b8c9b63bc75e5cc14121233222da7595
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32246
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chen Wisley <wisley.chen@quantatw.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This pin should be set to its alternative function SRCLKENA0 instead of
GPIO, so that SPM (a power management component of MT8183) can control
it.
BUG=b:113367227
BRANCH=none
TEST=1. Boot. Run 'powerinfo' in EC console and see power state in S0.
2. Run 'powerd_dbus_suspend --wakeup_timeout=10', and then
run 'powerinfo' in EC console and see power state in S3.
3. Wait until AP resume.
4. Run 'powerinfo' in EC console and see power state back to S0.
Change-Id: I0a7e34f95381dec17eb6d166d6552c12e021bd9a
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32120
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.
BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'
Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Expose the Bluetooth BT_DISABLE_L signal in Hatch's devicetree,
on both USB2 port 5 and 10.
BUG=b:123293169
BRANCH=none
TEST=compiles, verified kernel is able to find the reset-gpio
Change-Id: I6e4d9786e44f12da71533b6740fdd390f3a57e40
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32216
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The dev pointers were being dereferenced before the null
check. Move the checks so they are done earlier.
Found-by: Coverity Scan, CID 1241851 (REVERSE_INULL)
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Change-Id: Ie578787c3c26a1f3acb4567c135486667e88a888
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
There is no device on I2C0 which requires a lower clock rate.
Change-Id: Iaf01be5ea4839c54eb2f0ba95bca272970c24bdb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Set new tcc_offset value to 10 degree C. This configures the Thermal
Control Circuit (TCC) activation value to 90 degree C. It prevents
any abrupt thermal shutdown while running heavy workload. This helps
to take early thermal throttling action when CPU temperature goes
above 90 degree C.
Change-Id: Ica77264782b4a3f3e72e73e1b8cb8b2e464fb033
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a support melfas touch panel with i2c address:0x34.
BUG=b:122019253
TEST=tested with new melfas touch panel and worked
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I27f5c47517d093c819cbbbcdafd85d74145887e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32169
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support PCIe Gen 3 with 8GT/s link speed for PEG x16
slot. All parameters for FSP are set during initialization in
romstage. Now there is no need to additionally configure the FSP
before building the ROM image.
Tested on Intel Core i5-6600 processor with the following devices:
- LP11000e Fibre Channel HBA (Gen2 x8);
- PEX8734 PCIe Fabric/Switch (Gen3 x16);
- NVIDIA GeForce GTX 1060 GPU (Gen3 x16).
GPU works with an nouveau and proprietary driver under Ubuntu 18.04.2
(4.15.0-46-generic GNU/Linux kernel). Discrete graphic card is used
as primary device for display output. Dynamic switching is not yet
supported.
Tianocore (edk2-stable201811-216-g51be9d0) is used as the payload.
Change-Id: Ia4f29df47d76de5069fe53120434cc7c2ab6f044
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31948
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If an external graphics card is inserted in the PEG, it will be used
as the primary display device (as in the AMI BIOS)
Change-Id: Iea846179fc309c2b98093de37c05ceb332081f4f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32172
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The InternalGfx option in devicetree.cb is not used to enable iGPU.
The patch removes this option from chip.h and mb/*/devicetree.cb
files for all boards with skl/kbl processor.
Change-Id: I41ecca3fdfb1d4b20ee634a13263ff481dcf440e
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This change moves the I2C/SPI devices and configs which do not apply
to all variants to override tree. Currently, there are just two
variants. However, as we prepare to add more variants, these devices
need to be moved out of the base devicetree.
BUG=b:129728235
TEST=Verified that I2C/SPI devices are present in static.c for hatch
and hatch_whl.
Change-Id: I9426f6bf5f8514de5f1889e22e57105749fd92de
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32138
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In S3 the PCH is driving the DEVSLP signal low, assuming that the SATA device
is already powered off. However on hatch the SATA power is still enabled. And,
since DEVSLP is low, this causes the SATA device to not enter low power state.
The fix here is to set the pad config to be reset on PLTRST assertion which
will cause the pin to be high impedance state and will be pulled up by the
SATA device.
BUG=b:126611255
BRANCH=None
TEST=Make sure that S3 and S0ix is working fine on hatch.
And also make sure that DEVSLP is pulled high in S3.
Change-Id: Ifb6a71a72244522c8dd8d48e9b9f8dc6feef8981
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch provides a clock on Pin PMU_SUSCLK. This is necessary for correct
function of the SMARC module.
Test=mc_apl4 flashed, booted into Linux, ckecked CLK with scope
Change-Id: Ieb1d66b5a09363c9bed2b19e7a204f206ee04158
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32168
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set GPP_B4 to low in S5 to meet touch panel power sequence
BUG=b:124197348
BRANCH=master
TEST=Verify GPP_B4 is low.
Change-Id: I65deb33a45fdc0c0ce64deaa29c2790029dc1d12
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
CMLRVP.
BUG=none
TEST= Tested that eDP works on CMLRVP.
Change-Id: If8c8480eaf2d63cec0b5598b5af3088c630dd78a
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32140
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adding Kohaku as a variant of hatch.
BUG=b:129706980
BRANCH=NONE
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
make sure HATCH_KOHAKU is built as well.
Change-Id: I5b451f421f6d353005e6b73eac180dcec2e8b0c0
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This option is duplicated in depthcharge:
https://crrev.com/c/1545144
BUG=b:124141368, b:124192753, chromium:943150
TEST=make clean && make test-abuild
CQ-DEPEND=CL:1545144
BRANCH=none
Change-Id: I48e20ad21cdcb948a23387d3e5fcf142723b0c82
Signed-off-by: Joel Kitching <kitching@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32135
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Follow thermal table for second tunning.
BUG=b:129509918
TEST=Built and tested on sarien system
Change-Id: I64844b84891dc3ab7abe9378cdca5dcf57b3e433
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
