It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The newline lint check just went in, and immediately broke the build
due to a commit that went in earlier today.
This fixes the build.
Change-Id: Ic4ba8ce0c8085861bc6c654afdee3fea9f4621fc
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Fix regression introduced by commit 7ffb329f.
The default value for usb_always_on is no longer sane and is replaced
by the same default that is used on all other boards (disabled).
Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable SOC_INTEL_COMMON_GFX_OPREGION for all FSP versions.
Allows to get rid of opregion.c, as it's no longer needed.
Change-Id: I39190488e12917a09dbf7ee3947a33940ebc290b
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Function copied from i82801gx with offsets fixed for i82801lx.
Change-Id: Ib420c69470c3190cc1eac234ce68a18382fbc04a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19253
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage for both is line-for-line identical.
Merge both into P2B-DS so it benefits from my
modernization efforts.
Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The romstage for both is line-for-line identical.
Merge both into P2B-LS so it benefits from my
modernization efforts.
Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Romstage of many 440BX boards included headers that are not used.
Remove them as part of a bigger cleanup effort.
Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
I am able to complete a board-status run over onboard ethernet
(ie. it works) without this entry, so it's not necessary.
Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are 4 routines used in RAM init that most if not all
i440bx mainboards call in the same order. Implements a single
RAM init routine for them to allow for future consolidation.
Boards to be changed to use this one routine in a future change.
Change-Id: Ib553b07b117de12b7982586bce0f9355f55013a0
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This move makes the NB macro more widely available,
in preparation for implementing get_top_of_ram().
Change-Id: Icd8e82cfdfdccb662b2139d0e5d1d5af72cbae7f
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20675
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The variable p was going out of scope while still being pointed to by
*cpu_name.
Fix coverity ID 1378215 (Pointer to local outside scope)
Change-Id: I6ad7b1919104b4d97869efe5065e39c2a43de638
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.
BUG=b:62322846,b:62240755
Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.
BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.
Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This reverts commit 399c022a8c.
This was merged too early. I'll repost it.
Change-Id: Iabac0aaa0a16404c885875137cf34bf64bf956f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20686
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit dbe7f893c0.
This was merged too early. I'll repost it.
Change-Id: Ife56f45e91c0b961d0fad0e1872c6df3f9e18973
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20685
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This chipset was just added and had a few places that needed to be
fixed.
Change-Id: Ief048c4876c5a2cb538c9cb4b295aba46a4fff62
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20684
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The following changes can make system call into FSP siliconinit and exit
from that until payloads.
1. Add frame to call fspsinit.
2. Temporarily set all the USB OC pin to 0 to pass FSP siliconinit.
Change-Id: I1c9c35ececf3c28d7a024f10a5d326700cc8ac49
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This does the following:
* Clarify that settings are set to the same value for each rank;
* Allows to program coarse
* Fix some style issues like white spaces between arithmetic
operators.
Change-Id: I3a9e28cfec915a0bb15789c23bea259f621b5096
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This does not use loops to compute timings but uses DIV_ROUND_UP.
Another thing affected by this patch are minimum timings. Presumably
those only need to be guarded against on DDR3. With this change
timings are set up like vendor (with tWTR below previous minimum)
TESTED on Intel D510MO
Change-Id: Ia374f26e5bbb8b90d90c24ae6c20412ba53bd7b6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch is to provide an additional read LPC pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I308c0622d348fc96c410a04ab4081bb6af98e874
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch is to provide an additional read SPI pci offset register
BIOS_CONTROL (BC) - offset 0xDC to ensure that the last write is
successful.
Change-Id: I3b36c1a51ac059227631a04eb62b9a6807ed37b1
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The gpio numbers are global, but they have their respective place
within each community and the group within their community. For
all the calculations open coding this calculation convert them to
use the helpers.
Change-Id: I0423490ae1740ef59225a70fea80a7d91ac2a39a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
A pad number is passed into gpi_status_get() to determine if its
associated bit is set from a generated event. However, the
implementation wasn't taking into account the gpi_status_offset
which dictates the starting offset for each community. Additionally,
the max_pads_per_group field is per community as well -- not global.
Fix the code to properly take into account the community's
gpi_status_offset as well as the max_pads_per_group.
Change-Id: Ia18ac6cbac31e3da3ae0ce3764ac33aa9286ac63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20652
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
`CONFIG_PRE_GRAPHICS_DELAY` was only applied on a dead code path in
`igd.c` that is guarded by always selected `CONFIG_ADD_VBT_DATA_FILE`.
Nobody missed it for nearly a year, plus, it's not applied on the GOP
path, let's drop it.
Change-Id: I0b70cce3a3f2b50cb4e72c4d927b35510ff362a2
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This quirk was superseded a view lines above. Also the whole path is
guarded by `CONFIG_ADD_VBT_DATA_FILE` which is always selected for
nearly a year now.
Change-Id: I7fc5184d6e81e4588616e0302dee410e74bdab5a
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
It looks like this code was written with completely different semantics
in mind. Controllers, channels and DIMMs are all presented in their phy-
sical order (i.e. gaps are not closed). So we have to look at the whole
structure and not only the first n respective entries.
Change-Id: I8a9039f73f1befdd09c1fc8e17cd3f6e08e0cd47
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20650
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
At a process _start, the stack is expected to be aligned to a
16-byte boundary. Upon entry to any function the stack frame
must have the end of any arguments also aligned. In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).
Align the stack down inside _secondary_start and preserve proper
alignment for the call to secondary_cpu_init.
Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.
1) http://wiki.osdev.org/System_V_ABI
See "Initial Stack and Register State" and "The Stack Frame"
in the supplements.
BUG=chrome-os-partner:62841664
Change-Id: I72b7a474013e5caf67aedfabeb8d8d2553499b73
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20537
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When configuring i2c frequency to I2C_SPEED_FAST_PLUS, observed frequency
was I2C_SPEED_FAST.
This was due to incorrect register programming.
TEST= Build for Soraka, I2C frequency during firmware execution was
I2C_SPEED_FAST_PLUS when configured for I2C_SPEED_FAST_PLUS.
Change-Id: Ib0e08afe0e1b6d8c9961d5e3039b07ada9d30aa3
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The OS of this mainboard needs the _PIC method for the selection of the
type of interrupt routing.
Change-Id: Ic82ba1b368aff0030422d9602ebc882247a2191b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20618
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
The _PIC method is called by the OS to choose between interrupt routing
via the i8259 interrupt controller or the APIC.
Change-Id: I2bc16f9c096c095c02de3692e76c0906cec54cb5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following minimal changes are needed to make system boot until FSP
memoryinit got called.
1. Program SA BARs
2. Assume previous power state is S0.
Change-Id: Iab96b27d4220acf4089b901bca28018eaba940a1
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch adds the necessary changes to support Scarlet revision 1.
Since the differences to revision 0 are so deep, we have decided not to
continue support for it in the same image. Therefore, this patch will
break Scarlet rev0.
All the deviations from other Gru boards are currently guarded by
CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we
introduce more variants based on the newer Scarlet board design.
Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=none
BRANCH=reef
TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/20633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Always enable tp-smapi and thermal managment.
The devicetree already configures the correct values. This patch makes
sure that invalid user-settings are ignored.
The tp-smapi bit is required for the SMM handler.
The thermal bit should be set to allow the EC to monitor thermal state
of the platform.
Change-Id: Ia5aa50e0b1148a7cc8e51480623368ee62edb849
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19864
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
SDCARD is not used on this mainboard.
Change-Id: I28d23cdb3652bf736b19daf67c7057c396230e24
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
HECI2 and HECI3 devices are “function disable” during FSP
Silicon Init phase. Device will not be visible over PCI bus
hence removing these devices from wake source list.
Change-Id: I0de665e039d74e49e5a22db9714bc9fee734e681
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c. Build these into romstage from the makefile, and remove
the #includes.
Add a Kconfig option for platforms that do not use the
early smbus code.
Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
With EARLY_CBMEM_INIT, this is defined from ACPI layer
instead for ENV_RAMSTAGE.
Change-Id: Ia9c1be4d3acaa0fa8827350558e6578c39b71602
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Some configurations of AGESA boards fail to boot after commit
61be360 AGESA: Fix UMA calculations
Implementation of cbmem_find() for ENV_ROMSTAGE expects
that CBMEM has already been initialized. In the case of
LATE_CBMEM_INIT boards, this is not the case and cbmem_top()
returned NULL prior to the offending commmit.
By definition LATE_CBMEM_INIT does not have known cbmem_top()
in ENV_ROMSTAGE except for possible ACPI S3 resume path.
Change-Id: Icb8f44661d479e5ad43b123600305dcbc3ce11e1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
New post codes are
POST_FSP_MEMORY_EXIT
POST_FSP_SILICON_EXIT
This patch will make it more consistent to debug FSP hang
and reset issues.
Bug=none
Branch=none
TEST=Build and Boot on eve
Change-Id: I93004a09c2a3a97ac9458a0f686ab42415af19fb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
1. Explicitly add LOGICAL to the reset macro name to make it explicit
that the values are logical.
2. Reword some of the comments and combine them into single comment
instead of scattering the comments throughout.
3. Use c99 struct initializers for the reset mapping array.
4. For the chipset specific values use literals that match the hardware.
5. Use 'U' suffixes on the literals so we don't trip up compiler being
over zealous on undefined behavior.
6. Use unsigned and fixed-width types for the reset mapping structure
since the code is reliant on matching up with a register definition.
7. Fix formatting that can fit < 80 cols.
Change-Id: Iaa23a319832c05b8a023f6e45c4ee5ac06dd7066
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20589
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Sadly, small core and big core are not aligned with the OS driver's
expectation on the number of ACPI devices used for each community.
Big core uses a single device while small cores use one ACPI device
per community. Allow for this distinction within the common gpio
implementation and ensure apollolake is utilizing the new option
to retain the correct behavior.
Change-Id: I7c7535c36221139ad6c9adde2df10b80eb5c596a
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20588
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It should never be globally exposed. Remove the global symbol
and make it static.
Change-Id: I3b85f3bbf6a73d480cdefdcdec26e137e3a3f75f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
It should never be globally exposed. Remove it.
Change-Id: I90e201ddd4df2cda89e7d3e4cb81bdc2a81cac83
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The function find_fsp() parses the FSP header and returns either a valid
pointer to the FSP_INFO_HEADER or an error code. The caller of
find_fsp() only takes care about a NULL-pointer but not about a possible
error code. This leads to memory access violations in case of error when
FspTempRamInit is called.
To avoid this and to let the user know that there was an error while
parsing the FSP header show an error message and the error code.
Change-Id: I67fef0a53fb04c8ba5d18b5d4ef2fdc1aeba869e
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We don't need another level of indirection for these
hardware accesses.
Change-Id: Ic567d8272e5dd943ce19babbd7ad57ba5d86c354
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This patch adds a new kind of compile-time assertion based on Linux'
compiletime_assert(). The difference to the existing use of
_Static_assert() in coreboot (which should continue to be used where
appropriate) is that this new assertion only hits if the call to it is
not optimized out at compile time. It is therefore ideal to assert that
certain code paths are not included in the image if a certain Kconfig
option is (not) set. For example,
assert(!IS_ENABLED(CONFIG_THAT_MAKES_THIS_INAPPROPRIATE));
can be rewritten as
if (!IS_ENABLED(CONFIG_THAT_MAKES_THIS_INAPPROPRIATE))
dead_code("This code shouldn't be built for config X");
to turn it into a compile-time check.
Change-Id: Ida2911e2e4b3191a00d09231b493bf755e6f0fcb
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20585
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
As "var" is not a pointer but a variable there is no need to cast it to
a pointer before using the value.
Change-Id: I7f8e3ceadaa4301c50c5f5480cccab2be904aa9a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The function prototype isn't used any more, remove it.
Change-Id: Ie5bd4e4ec8f28bc0768d5427cf734ef77855a15e
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change register preservations and fix comments about register
usage accordingly. Do this to avoid use of %mm0-2 registers inside
macros defined in gcccar.inc, as future implementation of
C_BOOTBLOCK_ENVIRONMENT will use them as well.
Adjust caller side accordingly.
Change-Id: Ic76fcc31ae714baf5259d17c41b62a3610aa947b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Clean up commentary on AMD_DISABLE_STACK to be clear that
it does a wbinvd to preserve coreboot CBMEM and
value of car_migrated.
Change-Id: I0f5e9c807f7990fcd5ca85f77b9d92312e775d3e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20578
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After modifications:
f12 and f14 are identical
f10 is f14 with invd -> wbinvd modification added to HOOK_F10
f15 is f10 with invd -> wbinvd modification added to HOOK_F15
f15tn is f15 modified to use with TN / KV / KM
Change-Id: I4006fe09c134e5b51f3ee3772d6d150321d27b57
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Remove register preservations that are not required and
fix comments about register usage accordingly.
Change-Id: Ibc9ed982ac55e947c100739250db122033348a82
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20576
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clean up commentary on AMD_DISABLE_STACK to be clear that
it does a wbinvd to preserve coreboot CBMEM and
value of car_migrated.
Change-Id: I1265ed3d1bdf4b22f1a56f68bc53e18cfadc44b2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Including <fsp/gop.h> in util.h causes issues with
redeclarations when using SOC_INTEL_COMMON_GFX_OPREGION
along with FSP 1.1. Separating it out and including
directly in vbt.c has no negative side effects.
Change-Id: I2d82c2da40b067272d876929fc73b97f490146a7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These are places that were missed on the first pass.
Change-Id: Ia6511f0325433ab020946078923bf7ad6f0362a3
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20358
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I4e5e585c3f98a129d89ef38b26d828d3bfeac7cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ib3a1cf04482a8f19b159c31cfb16a7b492748d91
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The FSP 2.0 path uses postcar to decompress ramstage. Since postcar
is entirely RAM based there's no need to have an excessively large
stack for the lzma decompression buffer. Therefore, reduce the stack
required to 1 KiB like apollolake.
Change-Id: I45e5c283f8ae87e701c94d6a123463dddde3f221
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
At process _start, the stack is expected to be aligned to a
16-byte boundary. Upon entry to any function the stack frame
must have the end of any arguments also aligned. In other words
the value of %esp+4 or %rsp+8 is always a multiple of 16 (1).
Align the stack down and change the method for executing
car_stage_entry from jmp to call which should preserve proper
alignment regardless of a 32- or 64-bit build.
Although 4-byte alignment is the minimum requirement for i386,
some AMD platforms use SSE instructions which expect 16-byte.
1) http://wiki.osdev.org/System_V_ABI
See "Initial Stack and Register State" and "The Stack Frame"
in the supplements.
BUG=chrome-os-partner:62841664
Change-Id: I8a15514f551a8e17e9fe77b8402fe0d2b106972e
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All other Sandy/IvyBridge google boards have this function,
which is required by nb/sandybridge/raminit_mrc.c. Without it,
compilation fails when using MRC vs native ram init.
Change-Id: I3318700c540e97baf0a75aafb73f160aaae6703f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
AMD_S3_PARAMS is no longer defined with all binaryPI.
Guard these as a build fix to share the header nevertheless.
Change-Id: I725ed43991dc1c3e30d236bde4282176819f4cf4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There will be more follow-up changes.
BUG=b:63537905
BRANCH=None
TEST=emerge-nefario coreboot libpayload
Change-Id: I6bb80723ea2573df617026a4a5740adb89331892
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/20522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: Id98aa5f6dbdcbb8da4616d4fce6e7388f3ba4656
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Rename the guard to better match the new directory structure.
Add include files containing typedefs used in the file.
Change-Id: I5fe23ce6994603b0ace99fd6ffc5f3eded2880af
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20525
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Needs the ramstage configuration enabling of SuperIO GPIO pnp devices
for BSEL straps.
Also needs VSBGATE# to be on for ram to be powered during S3.
TESTED with 800MHz and 1067MHz FSB CPUs at the correct straps when
resuming from S3.
Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enable Azalia controller, HD Audio DSP and select
the HDAudio IoBuffer Ownership for rvp3.
Check if device is enabled in HDA codec init function
to avoid failure when Azalia controller is disabled in
the devicetree.cb.
BUG=None
TEST=Build for kblrvp3, Make sure booting is fine irrespective of HDA
enable/disable.
Change-Id: I87212fe16ecc6053d6d00372904a5fd5d6f6b209
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ic7132cd1848a75043d10f32ac5d0e6b45d2e0fe4
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I1944fcca91ee1a0ad8df5c8b6f402e907de5e78f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20285
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: I772d680774890c32ca6dc9b1e2143b3ab3bf6513
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use new GMA driver method to set ASLS on S3 resume, too.
Move gma_enable_swsci to init method as it should always be run.
Change-Id: Ifc921d7aa2d5b771fc4eaf3ec776c3a13f5496eb
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new method to restore ASLS on S3 resume.
Use new interface introduced in last commit.
Change-Id: I254683081cbaf3a5938794dcba140ac9ee07f48a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add and use new interface to set and get GNVS' ASLB register.
To be used by Intel's gma driver to set ASLB at ACPI table
creation and to get ASLB on S3 resume.
Change-Id: If30c6b2270069783b0892774802f47406404da5f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use new GMA driver method to set ASLS.
Change-Id: I872ff86a778497df76ad7f9b1b6910c4e7c5941f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add a new method to set ASLS register that holds the
ACPI OpRegion base address.
Change-Id: I4850500ac6d58f80b0eddc81514053c87774405c
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20281
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
1. Due to reset signal, PMIC loses its internal register state. This
causes PMIC to be in improper state after sleep.
2. The intent of reset signal is to reset internal state of PMIC (which
happens once during power on), hence avoid asserting reset signal
when not needed.
3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode
when not in use to save max possible power.
To fix the same, do not reset PMIC while entering sleep.
By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto
3.63uW (Max). Refs: TPS68470 datasheet.
Measured value: 0.66uW
TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check
whether PMIC internal registers state are preserved.
Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This reverts commit 5535cead (intel/skylake: Disable SaGv in
recovery mode).
Commit 5535cead disables SaGv in recovery mode to save few seconds
booting time as we were doing memory training on every recovery flow.
Now we don't need to perform MRC training on every recovery boot
due to RECOVERY_MRC_CACHE implementation in place. Hence we don't
need to define different SaGv policy between Normal (developer) mode
and recovery mode to save few seconds.
Using different SaGv parameters between recovery and all other mode
has some significent drawbacks over warm reboot cycle. We are seeing
a MRC traning hang in eve/soraka/poppy devices with below use case.
Step 1: Boot system in developer mode (first time RW_MRC training)
Step 2: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 3: System will perform recovery mode MRC training and boot to
OS (first time RECOVERY_MRC training)
Step 4: Issue “reboot” from OS console.
Step 5: System wil boot in developer mode (using RW_MRC cache)
Step 6: Set recovery_request=1 (using crossystem) and issue “reboot”
from OS
Step 7: System will pick RECOVERY_MRC_CACHE and will hang during
MRC training.
This patch fixes issue mentioned above and ensures system boot to
OS without any hang if we change mode (dev<->recovery) over warm
reset.
BUG=b:63515071
BRANCH=none
TEST=manual stress testing of dev<->recovery mode over warm boot.
No MRC hang with this fix on eve/soraka/poppy devices.
Change-Id: I8d094a8b6d78ea3bf8f929870a4a179495c29c78
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Don't need this additional 2ms delay as PCR read after sideband write
help to fix original hard hang issue.
This reverts commit d4b6ac19b0.
Change-Id: I4232cba5b92e17f728795f7c282af6161e385e9b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20462
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BIOS must ensure to read same PCR offset after PCR write operation
is done.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<->D3 transition on eve failing
unit. No hard hang with this fix.
Change-Id: Id3d567aab517b16ff99a526fc29c2d71bf4042d0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/20461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
These sources are no longer part of build-tests and transition
to soc/ appears to be completed.
Change-Id: I9bc2212f44d79c795e5b8f6d62b6ee3c42de779a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The macro FPGA_SET_PARAM was introduced to make the setting of different
FPGA registers with the appropriate values from hwinfo more
transparent. The hwilib takes care about the size of the provided buffer
where the requested value should be stored in. The fields in hwinfo have
not always the same size as the matching registers in the FPGA. So to
avoid errors resulting in a too small buffer when calling hwilib_get_field()
the buffer is now fixed to 32 bit and will be casted to the destination
type when the value is written into the FPGA register.
Changing the field size in hwilib would be the wrong way as the defined
lengths are specified this way to be expandable in the future.
In addition the number of maximum supported temperature sensors is
increased to 8 as the FPGA now supports more.
Change-Id: I0c697106783158420708a973c3cff2be90fa4fce
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The PMC of PCH-H requires a different destination id.
TEST=Run on kontron/bsl6 and observed that PM registers are correctly
dumped at start of romstage.
Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Move the generic I/O decode range setup before the console init.
TEST=Run on kontron/bsl6 which requires 0xa80/0xa81 decoded to
initialize serial ports. Serial console works from boot-
block on.
Change-Id: I9829f188c80eb73f6cd91b0c22e1c07da5745ad6
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
We remove this particular header file already while remaining
of include fixes is longterm and pending work.
Change-Id: I869d426c1344290a00e2df60e07e9a4a3ae26887
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix undefined behavior found by clang's -Wshift-sign-overflow, find,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I5240a19647c8ad59f64925f3e1c199446a886d2d
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20466
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: I10db2566199200ceb3068721cfb35eadb2be1f68
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Chell doesn't have a touchscreen, so remove the driver
definition from devicetree. Leave the PCI device function 0
enabled since disabling results in the touchpad (function 1)
being disabled as well.
Change-Id: I32619b7618bc0cdd99fa54fdda9bf2b5c1bb79a4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
CONFIG_SOC_INTEL_COMMON_BLOCK_SGX controls building. The SGX feature
is still enabled from devicetree.cb. As of now this SGX init supports
only KBL (SKL not tested). Support of SGX for new SOCs would be added
incrementally in this common code base.
Change-Id: I0fbba364b7342e686a2287ea1a910ef9a4eed595
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/20173
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Checking for NULL here doesn't help here. We *rely* on cdb_dev to exist
directly before this check. Coverity had found this:
*** CID 1376664: Null pointer dereferences (REVERSE_INULL)
/src/soc/amd/stoneyridge/northbridge.c: 666 in cpu_bus_scan()
660 * this silicon. It is an SOC and can't have >= 16 APICs, but
661 * we will start numbering at 0x10. We also know there is only
662 * on physical node (module in AMD speak).
663 */
664
665 lapicid_start = 0x10; /* Get this from devicetree? see comment above. */
CID 1376664: Null pointer dereferences (REVERSE_INULL)
Null-checking "cdb_dev" suggests that it may be null, but it has already been
dereferenced on all paths leading to the check.
666 enable_node = cdb_dev && cdb_dev->enabled;
667 cpu_bus = dev->link_list;
668
669 for (j = 0; j <= siblings; j++ ) {
670 apic_id = lapicid_start + j;
671 printk(BIOS_SPEW, "lapicid_start 0x%x, node 0x%x, core 0x%x, apicid=0x%x\n",
Change-Id: Ic6a53df8b8d1596ad0eb1d8f0fa200cccf9509cf
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
With the existing SSID, the driver loaded by Windows results
in the headphone jack and internal mic being non-functional.
With the new SSID, the a functional driver is loaded and
everything works correctly. Linux works correctly with
either SSID so the change has no impact there.
New SSID extracted from Windows drivers (.inf).
Change-Id: I4195d00d6b18dcd0039747d9883cdf8e1a76f461
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Returing FSL# for _STA causes Windows to BSOD. Re-work _STA to instead
return 0/1 based on FLVL, using google/beltino as a model.
Also correct serialization type for _CRS.
Change-Id: Ibf3af15bab3590f7c1c4401e1978dbcf2a495216
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20482
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This is a follow-on to the superio IS_ENABLED() patch:
https://review.coreboot.org/#/c/20351/1
Change-Id: I7d070e3964609947959de60e2686dfe59fe77e1c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I763cbbc31dcd4cdd128c04793a742ab6daaf5f0c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20345
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The current code doesn't work for field with size > 0x3f.
Fix that by using the correct syntax, reverse engineered using iasl.
Refactor to reuse existing code.
Tested on GNU Linux 4.9 and iasl.
Change-Id: Iac3600f184e6bd36a2bcb85753110692fbcbe4b6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Port commit f1395d82: "ec/lenovo/h8: Add USB Always On"
to other Thinkpad boards, as it seems to work fine on all
generations.
Change-Id: I6dcbfaae2a444d9a679ecb64a87dc2a59b8fd281
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add support for UAO AC only mode.
Needs tests on all platforms.
Change-Id: Ib52aab427ff687b00129024cde65b78060d21e32
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
- Update all symbols to use IS_ENABLED()
- Update non-romcc usage to use 'if' instead of '#if' where it
makes sense.
Change-Id: I5a84414d2d1631e35ac91efb67a0d4c1f673bf85
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20005
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix undefined behavior found by clang's -Wshift-sign-overflow, grep,
and source inspection. Left shifting an int where the right operand is
>= the width of the type is undefined. Add UL suffix since it's safe
for unsigned types.
Change-Id: Id1ed2252ce3ed052730dd10b24c453c34c2ab4ff
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20465
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fix undefined behavior found by clang's -Wshift-sign-overflow. Left
shifting an int where the right operand is >= the width of the type
is undefined. Add UL suffix since it's safe for unsigned types.
Change-Id: Ieacf83d052bf4abfad639ef8e592bd8de17d16e6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Regarding the "System Management BIOS Reference Specification"
Version: 3.1.1, Date: 2017-01-12, Laptop system enclosure is 0x09
and for Notebook it is 0x0a
Change-Id: I5538be0b434eed20d76aef6f26247e46d1225feb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Idcea3f8b1a4246cb6b29999a84a191a3133e5c78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add I2C debugging support:
* Add I2C_DEBUG Kconfig value to enable debugging
* Display I2C segments before the transfer
* Display errors that occur during the transfer
* Display the number of bytes transferred for successful transfers
TEST=Build and run on Galileo Gen2
Change-Id: Ia17be8b4213b13fd6c6a367d081414d0f21fbb0f
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
* Split the existing cflags to a second line to stay under 80 characters
* Correctly identify the libagesa "Stage" by adding the __LIBAGESA__
define to the files when they're compiled. This matches stage
defines such as __BOOTBLOCK__, __ROMSTAGE__, and __RAMSTAGE__. This is
needed to have printk actually show console information on whatever
interface the user has selected, such as the serial port, speaker,
SPI rom, or something else that hasn't been thought of yet.
Change-Id: I2a64414491130275ba06e5bd76e0b01e450174e8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Nothing in the amdlib.c file actually uses the StdHeader structure, so
remove the asserts verifying that it's not null, and remove references
to it from calls.
For now, I've left it in the parameters for the functions for
compatibility, but we might want to remove these at some point as well.
Change-Id: Ib13e9209c8119fdcc3720470aaa9dcdbde6ac388
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
DIMMB's DDR width is in bit 20, not bit 19.
Change-Id: I48866d9243c2a576a02519724429801ae47c5644
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
Remove unnecessary memset().
Change-Id: I1362a3eb8c97f5c7e848d75f8d1a219968a7ef9e
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: If2d34e4f05494c17bf9b9dec113b8f6863214e56
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that is not aligned to the size of access is undefined behavior.
Change-Id: Ia3c95e36e8b7f88ed69d5339e299c40934cb87da
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
In order for this (seemingly unnecessary) status assignment to stay, let's
explain it in a comment.
Change-Id: I0a364539c37005cfd637b75c8cc23b84e274294d
Signed-off-by: Martin Kepplinger <martink@posteo.de>
Reviewed-on: https://review.coreboot.org/20411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: If80e0c4e1c9911b44853561b03aef1c741255229
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20339
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Fix reports found by undefined behavior sanitizer. Left shifting an int
where the right operand is >= the width of the type is undefined. Add
UL suffix since it's safe for unsigned types.
Change-Id: I755b3c80a8d1b6cb6b6e5f411c6691e5dd17c266
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add files for supporting the BIOS->PSP communication not
covered by AGESA. The first command implemented notifies the
PSP that DRAM is ready.
This patch also introduces the amd/common/block directory
structure similar to intel/common/block.
Change-Id: I34b2744b071aa3dfb1071b2aabde32ddb662ab87
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19753
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Toggle LEDs after successful dock and undock.
On boot the LED will light up and on undock button
press the LED will turn off again.
Tested on Lenovo T500.
Change-Id: Ib5851f4abcedf4041faae6b3b810102012f488cd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The flag FF_FreezeDis marks if this feature is disabled. For a better
readability rename freeze_mode to freeze_disable and invert the meaning
of this information.
Change-Id: I648b2392d2c8046965479511fde485a9cb934378
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The two flags FF_FanReq and FF_Freeze_Dis should be treated as
8 bit values and not as 32 bit. Change the length of these fields to
1 byte and adjust the offset and mask for FF_FanReq.
Change-Id: If5e9e8b16491a33997cc39c3dd9b80f97682adc6
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20431
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This patch basically does two things -
1) Remove unnecessary setting of flex_ratio to TDP nominal:
Factory configured (default) Max Non-TURBO ratio(P1) is already cofigured
in MSR_PLATFORM_INFO(0xCE).
If this Maximum Non-TURBO Ratio(P1) needs to be modified, it should be done
using MSR_FLEX_RATIO (0x194).
Here, in this code, the FLEX_RATIO is being modified by the TDP Nominal
Ratio, reading the MSR_CONFIG_TDP_NOMINAL(0x648). But this value is
actually less than the factory configured Maximum Non TURBO Ratio (P1).
So, this code is actually not required.
Also, the Bit 12 in PCH Soft Strap Register is already set in descriptor.
This Bit implies Processor Boot Max Frequency -
0 = Disable Boot Max Frequency
1 = Enable Boot Max Frequency (Default)
This setting determines if the processor will operate at maximum frequency
at power-on and boot.
Thus this patch will avoid one extra platform warm reset now onwards.
2) Remove wrongly setting Max Frequency in Bootblock phase:
In the function set_max_frequency(), the P-State max ratio was set to
TDP Nominal ratio if C-TDP was enabled, else it was set to Max Non
Trbo ratio.
But, when the cpu gets reset, it will operate with the Max-Non Turbo
ratio only, which is greater than the TDP Nominal ratio.
So, no need to set back the ratio to TDP Nominal which is lower than
the currently operating frequency.
BUG=none
BRANCH=none
TEST=Build and boot poppy
Change-Id: I24bfc86ddf0f038d85da938e41e950382fe2a6c3
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use the new PAD_CFG_GPI_INT macro to specify the headset codec
interrupt as specifically edge triggered (since it is registered
as EDGE_BOTH in the devicetree) in order to prevent the interrupt
from firing unexpectedly when the system is resuming.
Also change the DSP interrupt to edge triggered since the kernel
is registering with IRQF_TRIGGER_RISING in order to prevent an
interrupt storm when it asserts.
BUG=b:35582164
TEST=manual testing on Eve:
1) ensure the headset codec sends interrupt on insert and remove
2) ensure there is only one interrupt counted when DSP asserts irq
Change-Id: I40a8ee667de653e4e70770cd96b6417442c1b0ec
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Make this pin a GPI as it is supposed to be an input from the touch
controller and not driven by the AP.
BUG=b:35581264
TEST=check pin state with a scope
Change-Id: Ife5f84fcc614255b20e44389279d515a12f5751d
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Board changes in rev6+ have a fix to VDDQ that should fix the issue
that was being seen with this SKU, so only lower the memory speed on
older boards.
BUG=b:37172778
TEST=memory stress testing on rev6 boards
Change-Id: I6d6fe730cabd74af23eab3f02feef9da01a35fd4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for waking from and logging device events that
originate in the Embedded Controller. As this device uses
Deep S3 it relies on the EC to wake the AP from the trackpad
and DSP wake sources.
BUG=b:30624430
TEST=manual testing on Eve: wake from Deep S3 via trackpad and
DSP and verify the event log contains the expected device event.
Change-Id: I0d6a9c5bfd4cea85e13446ffaa6fe3dab0db96a2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for the new EC device event interface which is used to
report events from devices that are connected behind the EC.
This can be used to differentiate wake sources from the EC in the case
that the EC has the wake pins from various devices.
This can be used in case the AP is unable to directly wake from the
device itself, for example when using the Deep S3 state on Intel
platforms only a few pins can directly wake the AP.
BUG=b:30624430
TEST=build google/* boards that use chrome EC. Feature is used and
tested further in a subsequent commit.
Change-Id: I5126c6d6ffb6b0ef6e8db8dcd5aec62db925a371
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Replace the unused "thermal overload" event with the new
"device event" and define the first few device events that are
supported by the Chromium EC.
BUG=b:30624430
TEST=build for google/* mainboards
Change-Id: I1f3aeedb87c2aad29a0a67b5c50c29a6961fb45f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update this header from the upstream source so new host
commands can be used in coreboot.
https://chromium.googlesource.com/chromiumos/platform/ec
commit bbb759ceaa843f548f90c35d1668e17c8879bad3
BUG=b:30624430
TEST=build google/* and intel* boards
Change-Id: I56c9f891262d8984b6a9a69d96752c2dd6bb2371
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Chrome EC event for "thermal overload" was never implemented and
is being repurposed as the EC event mask is out of free bits.
Remove this from the boards that were enabling it.
BUG=b:36024430
TEST=build coreboot for affected boards
Change-Id: I6038389ad73cef8a57aec5041bbb9dea98ed2b6e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The architecture is determined by __riscv__ in the LZ4_copy8 function
(located in src / commonlib / lz4_wrapper.c). __riscv exists in gcc7.1.1.
But __riscv__ does not exist.
Change-Id: I38fd41da9afd76c254f0c3d6984579c3790e5792
Signed-off-by: XiangWang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/20125
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Andrew Waterman <aswaterman@gmail.com>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
DISPPLANE_BGRX888 defined in drivers/intel/gma/i915_reg.h
included in i915.h file
Change-Id: I4e9414f39a29e4eac7e325672ce6520a5654d3bc
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/20409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Set RX6110SA RTC backup mode to primary cell. This mode reduces the
backup current consumption of the RTC.
Change-Id: I7c0c26a0ed5d8f48587acc917f8bb1c5c2b8869a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The used RTC6110SA has issues to enter backup mode when the power supply
decreases too slow when the mainboard is turned off. Switch to backup
mode "primary cell" to make sure backup mode will be entered correctly
on power-off. In addition set IOCUTEN to minimize the backup current
consumption of the RTC.
Change-Id: I9733aa9f2981a25f6d42279eff0c4980e5eb5a5a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
According to the datasheet the RTC needs a power rising slope of no more
than 100µs/V to ensure a correct power-on reset. If the mainboard that
hosts the RTC cannot guarantee this, a software reset sequence is needed
in the case where the battery was drained completely.
As the rising slope of the power supply depends on so many parameters
and is highly mainboard specific, refactor the initialization code to
perform a software reset every time a power loss event is recognized by
the RTC.
Change-Id: If64d672e51667523058041bd00e1e50ac047143d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There is no choice, if not leaving it with the default the build
will fail.
Change-Id: Id91e3ce87f8ced3001fcd2125f8f6781b270f5bc
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cannonlake has built-in UART driver as part of LPSS block. However port
mapped decoders are in use as well.
Change-Id: I9f209bf29c1748c5beea31bc6b31cb07a1e14195
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
When the C compiler expects 16-byte alignment of the stack it is
at the call instruction. Correct existing call points from assembly
to ensure the stacks are aligned to 16 bytes at the call instruction.
Change-Id: Icadd7a1f9284e92aecd99c30cb2acb307823682c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the TSC for the Stoney Ridge monotonic timer. Modern AMD
CPUs have invariant timestamp counters. This patch brings the
feature more in line with other devices and allows the use of
typical monotonic timer functions.
BUG=chrome-os-partner:62578062
Change-Id: I07b05fbc7cdea54a45daac01954284a9fd67e42f
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20201
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
There are up to two on-board PCI devices where bus master has to be
enabled in PCI config space. As there is no need for a complete PCI
driver for these devices just set the bus master bit in
mainboard_final().
In a perfect world that would be the task of the runtime driver which
unfortunately don't do that.
Change-Id: Ic2896d5e7568a455737af26b14b2c398caae5f72
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/20403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The ALSB gnvs variable is used to load the OpRegion memory
address into the ASLS register on the S3 resume path, and must
therefore first be set on the normal boot path.
This patch brings Haswell in line with SNB/IVB/Nehalem, which
already save the OpRegion address in ASLB.
Change-Id: Ie062cbfe7e7f60c2a4e2b9111f6b6da87ced7a39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Now that pci_devs.h is part of soc/ and not used for multiple
southbridges:
* Remove devices not present in the Stoney Ridge APU
* Complete the list to include additional devices besides
those in the FCH.
BUG=chrome-os-partner:62578372
Change-Id: I1cd2d5e41473f362bbfd28ee93788a292bc33991
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20370
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Add a memmap file with a cbmem_top() function. Remove the
LATE_CBMEM_INIT, allowing the default of EARLY. Remove calls
to the late-only set_top_of_ram() function.
Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change-Id: Ic2cdfa08cdae9f698eb2f8fa4c4ae061f1a7d903
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I66cde1adcf373889b03f144793c0b4f46d21ca31
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20338
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I82bf68a7ee54ff88f65aacc9eb0dbc30d013aae0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Ie685bbbb1cbf06d32631ea40ad120b6f45374b2e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: I9f4155285529ec28e826637a61436478f648704c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20335
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
- Describe RT5663 headphone codec in ACPI so it can
be enumerated by the OS.
- Supply NHLT binaries for RT5663
BUG=b:62872377
TEST=Apply full patch set and UCM, verify basic audio works.
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Change-Id: I5bbd58b0e660cdf5089e6a6dd35a757ecf8ec076
Reviewed-on: https://review.coreboot.org/20305
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Problem was introduced by fb2f667da2 "nb/amd/amdk8: Link raminit_f.c"
which linked debug.c and was not tested with this option.
Change-Id: I8597a6915c65ea783a864110cb23ecb34ea0611b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Swift Geek <swiftgeek@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
In the code we do the following in a number of places
to pre-initialize an array with a certain value before
overwriting some of the array with other values:
u8 mainboard_picr_data[FCH_INT_TABLE_SIZE] = {
[0 ... FCH_INT_TABLE_SIZE-1] = 0x1F,
}
clang does not like that behavior unless we specify
the option -Wno-initializer-overrides.
Remove the check for gcc in those places, too, because
1) it would silently change array contents between compilers
2) the check isn't sufficient to determine compilation on
clang vs gcc
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Change-Id: I93cc121b6fec099fcdbd5fd1114c2ff7cbc291dc
Reviewed-on: https://review.coreboot.org/20384
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Wow, this one is disliked by clang for the empty for() loop, but
looking at the file just makes my eyes bleed a little bit. I remember
the circumstances under which we let this code go in. It was supposed
to save contributions from a vendor, but that never worked out.
Just to keep the little chunks down, here's an indent run and some of
the cruft removed that doesn't actually contribute to functionality in
any way.
Change-Id: Ie82166ca82f09c4b66decfde5ad194a2d70b0708
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Fix CID 1376472 detected by coverity. Zero extend the capacity instead
of sign extending it.
TEST=Build and run on reef
Change-Id: I6aac422fb1dacb75e0cc44a94ff1f467ce9f529e
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Add a SMM_TSEG_SIZE symbol that can be used in top of memory
calculations.
Change-Id: I26f3b06f85f0cf5613656c1d5df55bd9ea4bbbbc
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19750
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove IDE from the Stoney Ridge source. This APU doesn't have
an IDE controller. The support was left over from pi/hudson.
BUG=chrome-os-partner:62580062
Change-Id: I7316c113a7464089ccfbea6b6cf69787940b9e97
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Remove the pcie.c file. Historically PCIe lanes have been
available from the Gfx and/or the FCH. The integrated FCH in
this APU has no PCIe available.
BUG=chrome-os-partner:62580062
Change-Id: Ie89383dadfaa57c5a6d185e74551ae50ac8d9778
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The Stoney Ridge does not contain this bridge like some of the older
Hudson FCHs. Remove this support from the source.
This moves the Stoney Ridge IRQ setup to the southbridge file, hudson.c.
BUG=chrome-os-partner:62580062
Change-Id: I8f974ba76b8c20f4335dd8872eaf4b8172188ee2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. Some of the lines requiring a >80
break are indented too much currently.
Changes to agesawrapper.c cause the build to change, so this
file is also left as-is. Make hex values consistently lower-case.
BUG=chrome-os-partner:622407746
Change-Id: I0464f0cafac4ee67edc95d377dcf7aab9a90c66b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Correct the majority of reported errors and mark most of the
remaining ones as todo. (Some of the lines requiring a >80
break are indented too much currently.) Some of the alignment
in hudson.h still causes checkpatch errors, but this is
intentionally left as-is.
Also make other misc. changes, e.g. consistency in lower-case
for hex values, using defined values, etc.
These changes were confirmed to cause no changes in a Gardenia
build. No other improvements were made, e.g. changing to helper
functions, or converting functions like __outbyte().
BUG=chrome-os-partner:622407746
Change-Id: I768884a4c4b9505e77f5d6bfde37797520878912
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Soraka uses MPS2949 IMVP8 controller and does not need the VR
workaroud similar to Eve.
BUG=None
TEST=Build & boot on soraka. Ensure IMVP8 controller goes to low power
mode in S3 and S0ix by measuring power.
Change-Id: Ib98bb709ecc9e362a5cef437e7319e41f398a73b
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/20255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Correct the checkpatch errors reported in the asl files and
make other stylistic modifications.
These changes were confirmed to cause no changes in a Gardenia
build.
BUG=chrome-os-partner:622407746
Change-Id: Id8b2620d161062c444e493325d83bb158705b76b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This requires to also unify the calling convention for
AGESA functions from
AGESA_STATUS (*agesa_func)(UINT32 Func, UINT32 Data, VOID *ConfigPtr)
to
AGESA_STATUS (*agesa_func)(UINT32 Func, UINTN Data, VOID *ConfigPtr)
On systems running 32bit x86 code this will not make a difference as
UINTN is uintptr_t which is 32bit on these machines.
Change-Id: I095ec2273c18a9fda11712654e290ebc41b27bd9
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Return CB_SUCCESS and CB_ERR instead of some integer.
Preparation to merge intel/soc and intel/nb opregion implementations.
Change-Id: Ib99fcfe347b98736979fc82ab3de48bfc6fc7dcd
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20220
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some of these can be changed from #if to if(), but that will happen
in a follow-on commmit.
Change-Id: Id5bc8b75b1fa372f31982b8636f1efa4975b61a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
... even though the author of the code probably wished he was
working on a (much faster) broadwell system instead. Let's fix
the header guard to reflect the right SOC.
Noteworthy: clang detected that this was wrong.
Change-Id: I74c217c0471800f40c31a9ac38ba5396f82cd724
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It's pretty obvious that the author did not want to use a logical
and (&&) here but an arithmetical and (&)
Change-Id: Ic1bece86986906b76308bbb46235c22418e27990
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
dual_node is never used in that function. And it is never set
correctly either, because the register f3xe8 is never actually
read either. Just remove the whole useless construct.
Change-Id: If316da89bceae6b162f20e4b632276db2d9ef423
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20385
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The warning -Wstack-usage= doesn't seem to exist on clang, so trying
to disable it makes the compiler unhappy about non-existent pragmas.
Catching this on gcc is good enough, so let's disable it for the clang
case
Change-Id: Ia3716a83ba41743ac1dbe73e70abd170de30d7ab
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
src/vendorcode/amd/agesa/f15/Include/OptionMemoryInstall.h:3688:7: error:
suggest braces around initialization of subobject
Change-Id: Id086a64205dfffa2d1324993f4164508b57b6993
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
If SSE instructions are enabled in the build assume the SMM
modules are compiled with SSE instructions. As such enable
the SSE instructions in SMM mode by setting up the cr4 register.
In addition, provide a place to save and restore the SSE state
in both the relocation handler and permanent handler.
Change-Id: Ifa16876b57544919fde88fba5b8f18e4ca286841
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20244
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fill in acpi_name to return proper ACPI names.
To be used with SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
HDEF is defined in sb/intel/bd82x6x/acpi/audio.asl.
LPCB is defined in sb/intel/bd82x6x/acpi/lpc.asl.
RP0* is defined in sb/intel/bd82x6x/acpi/pcie.asl.
SATA is defined in sb/intel/bd82x6x/acpi/sata.asl.
SBUS is defined in sb/intel/bd82x6x/acpi/smbus.asl.
EHC? is defined in sb/intel/bd82x6x/acpi/usb.asl.
XHC is defined in sb/intel/bd82x6x/acpi/usb.asl.
Change-Id: I08611b11c694ee5034bca11cb321915d5c73c2f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Fill in acpi_name to return proper ACPI names. To be used with
SSDT generators.
The ACPI names have to match those already used in ASL code.
By providing the ACPI name it can be retrieved by the
acpi_device_name() method and doesn't need to be hardcoded in
SSDT generators any more.
GFX0 is used in drivers/intel/gma/acpi/pch.asl.
MCHC is used in nb/intel/sandybridge/acpi/hostbridge.asl.
Change-Id: I19526e334a9c5435fdb19419a671b86c5f6b2be9
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
The ChromeEC board directories for auron and rambi have been removed
from the latest version of ChromeEC. Remove them here so the submodule
can be brought forward.
Change-Id: I763d03009f735d3f8aedbeb44788d03714c86102
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20361
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Update the world facing camera sensor to OV13858 and also
add delay of 5ms after xshutdown rising which indicates system
ready status.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I0cd535e6568f104ffaa1092a13667def646df0eb
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Add clock frequency property into _DSD ACPI object and set it
to 19.2MHz for camera sensors. Upstream camera kernel has added
a check for clock frequency in sensor probe function and without
this property sensor probe fails.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successfull.
Change-Id: I147b3c932a33ae034868f7f9b616500d24ca71e3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20294
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Zero the framebuffer structure so if it is not filled in (either if
no display is present or if there is an error) then it does not
provide garbage data to the payload.
This was noticed when booting a board without a display attached as
the payload wrote to the framebuffer at a random address.
With this change the payload can properly handle the case where a
display is not attached and not corrupt memory.
Change-Id: I8114d88496cd2a4f2e7f07f377fe76f3180a7f40
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20367
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
In the D0 and D3 ACPI methods use word access to the PME status and
control register. This brings the code inline with the Intel reference
code and matches how the kernel handles access to this register.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across multiple devices
Change-Id: I53f7465d6ad5da1780a5641ff52056445ebaca8b
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
For the skylake/kabylake generation of PCH there is an ACPI workaround
for emmc/sd power state that involves disabling and re-enabling dynamic
clock gating after enabling power to the controller, before setting the
power state to D0.
Under certain conditions we have observed that the controller is not
powered and ready by the time the kernel attempts to read the PME
control and status register and so the system will hang while attempting
to read PCI config register 0x84.
To ensure that the controller is ready add a 2ms delay after re-enabling
dynamic clock gating and before setting the power state to D0.
This issue has been observed on eMMC, but the same workaround exists for
the SD card interface so the same delay is added there.
BUG=b:35587084
BRANCH=eve
TEST=manual stress testing of D0<>D3 transition across many devices
shows no hard hang after 2 days.
Change-Id: If0f0323cf5437c54c907c332937b5de9dda2d8f6
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/20363
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Most of these functions go unused most of the time, but in order
to not keep several copies around, let's make sure we are using
the same file everywhere first.
Change-Id: Ie121e67f3663410fd2860b7d619e8a679c57caba
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20325
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Correct all checkpatch errors but leave two errors in place
that are caused by AMD typing.
Change-Id: I9daa374da76ff991de72d16bad0e8b586aa95525
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Switch Garnenia mainboard to single soc/ directory structure.
Change-Id: I095804d603bcccf324d3244965081a9dccba62ae
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy northbridge files from northbridge/amd/pi/00670F00
to soc/amd/stoneyridge and soc/amd/common.
Changes:
- update chip_ops and device_ops
- remove multi-node support
- clean up Kconfig and Makefile
Change-Id: Ie86b4d744900f23502068517ece5bcea6c128993
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy cpu/amd/pi/00670F00 to soc/amd/stoneyridge and
soc/amd/common. This is the second patch in the process of
converting Stoney Ridge to soc/.
Changes:
- update Kconfig and Makefiles
- update vendorcode/amd for new soc/ path
Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Copy the Hudson/Kern code from southbridge/amd/pi/hudson. This
is the first of a series of patches to migrate Stoney Ridge
support from cpu, northbridge, and southbridge to soc/
Changes:
- add soc/amd/stoneyridge and soc/amd/common
- remove all other Husdon versions
- update include paths, etc
- clean up Kconfig and Makefile
- create chip.c to contain chip_ops
Change-Id: Ib88a868e654ad127be70ecc506f6b90b784f8d1b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch updates the coreboot DDR Settings to match the configuration
used by ARM-Trusted-Firmware.
Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20304
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
As per latest BWG, ucode reloading should be done at the end
of Mp Init, i.e., after PRMRR and other features are enabled.
No reloading specifically after SMM Relocation is required.
As, in the Common CPU MP Init code, we are already doing a
uCode load at the end of MP Init Feature Programming, hence,
the uCode loading after SMM relocation can be removed.
Change-Id: Ib1957c5fe5a8c83bb20b978a9841670b0c3e8846
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch contains State Machine callbacks init_cpus()
and post_cpu_init().
Also, it has the SOC call for CPU feature programming.
Change-Id: I5b20d413c85bf7ec6ed89b4cdf1770c33507236b
Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com>
Reviewed-on: https://review.coreboot.org/20189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It does not work to enable the LPC range in the function
mainboard_init() because the LPC bus driver closes the range during PCI
enumeration again. For this reason, enabling decoding of the address
range for COM 3 will be done at a later point in time -
mainboard_final().
Change-Id: I452bca4e430b1ea75e4a327591da84500491fe84
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With enabled XDCI support we are not able to use USB port 0 over XHCI
driver. For this reason, we disable XDCI into devicetree.cb.
Change-Id: I1ed721d9ffd44a920a6f1f16855d5b7ceb1b17c5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
With the do while loop, it can be avoided do use an infinite loop with a
break condition inside.
Change-Id: I030f6782ad618b55112a2f0bac8dda08b497a9f1
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/20269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This fixes improper dram frequency being displayed in sandy bridge
native raminit.
Change-Id: I1fe4e4331f45ce1c21113c039b8433252326293d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
On boards that are able to take two DIMMs per channel the
command rate should be 2T. It is possible to use 1T with
load reduced "1T" DIMMs, but it's not clear how to detect
those DIMMs. Raminit might fail for those who do not have
such DIMMS installed.
Hardcode command rate of 2T to make sure raminit works on
dual DIMM per channel boards (currently only desktop boards).
The command rate of 1T is still tested if only 1 DIMM per
channel is present.
Will decrease performance on quad slot mainboards, if two DIMMs
are installed in one channel and previously 1T have been selected.
Tested on ASRock B75 Pro3-M.
Change-Id: I029d01092fd0e11390cebcd94ca6f23bf0ee2cab
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Maybe we could go on, but cbmem_add() failing is a very bad sign.
Should fix coverity CID 1376384 (Null pointer dereferences
(NULL_RETURNS)).
Change-Id: I330cee6db3540c6a9c408d56da43105de5d075f7
Found-by: Coverity Scan #1376384
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20280
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Fix up for 1b5eda0 (arch/x86/smbios: Fix undefined behavior) which
introduced the variable `tmp` and used it out of scope. Should fix
coverity CID 1376385 (Memory - illegal accesses (RETURN_LOCAL)).
Change-Id: I8d4f664fc54faf6beb432b939dda4ddf93cf5d3e
Found-by: Coverity Scan #1376385
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Bifferboard was the only board that used this chip, and it has now
been removed. Removing the chip as well. If there is desire to
continue work on the board, it can be found in the 4.6 branch.
Change-Id: I33a1e713cdfea47abce71b79f0a9c93562c96d12
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This board can't be found to be tested, and compiles romstage with
romcc. If desired, it can be continued in the 4.6 branch.
Change-Id: I4826c277bbb444c2f0573729d76cd492ade95b4c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
rdrand64() is not clang friendly. Actually it looks like the
function is incorrect on 32bit x86 for all compilers including
gcc, but gcc won't care because the function is never called on
x86:
src/arch/x86/rdrand.c:51:15: error: invalid output size for constraint '=a'
: "=a" (*rand), "=qm" (carry));
^
1 error generated.
Guard the code correctly if ENV_X86_64 is not set.
Change-Id: Ia565897f5e4caaaccfcb02cf1245b150272dff68
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/20298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Use the existing macros for CR0 to set the flags in the
SIPI vector code.
Change-Id: Iad231b7611b613512fd000a7013175e91542ac10
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the existing macros for CR0 to set the flags in the
SMM stub.
Change-Id: I0f02fd6b0c14cee35ec33be2cac51057d18b82c0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20242
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
For sizes and dimensions use size_t. For pointer casts
use uintptr_t. Also, use the ALIGN_UP macro instead of
open coding the operation.
Change-Id: Id28968e60e51f46662c37249277454998afd5c0d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20241
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
The vboot code tries reading rollback protection indices from the TPM,
and if the attempt to read returns TPM_E_BADINDEX, it decides that the
TPM has not yet been initialized for the Chromebook use, and needs to
be taken through the factory initialization sequence.
TPM_E_BADINDEX is an internal representation of the TPM error 0x28b,
generated on attempts to read a non existing NVMEM space.
If the space exists, but has never been written the TPM returns error
0x14a. This condition (the space exists but not written) could happen
if the previous factory initialization attempt was interrupted right
after the space was created.
Let's map this error to the same internal representation
(TPM_E_BADINDEX) so that the Chrome OS device could recover when this
condition occurs.
BRANCH=reef, gru
BUG=b:37443842
TEST=verified that the Pyro device stuck in TPM error state recovered
when this patch was applied.
Change-Id: I6ff976c839efcd23ae26cef3ee428e7ae02e68f8
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/20299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SMI code is very similar across Intel platforms. Move this code to
common/block/smi to allow it to be shared between platforms instead
of duplicating the code for each platform. smihandler.h has already
been made common so all it will contain is name changes and a move
to the common block location. Due to moving smihandler code, APL
changes are bundled here to show this change.
Change-Id: I599358f23d5de7564ef1ca414bccd54cebab5a4c
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/19392
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add SPI driver code for the legacy SPI flash controller. Enable erase
and write support allowing coreboot to save non-volatile data into
the SPI flash.
TEST=Build and run on Galileo Gen2.
Change-Id: I8f38c955d7c42a1e58728c728d0cecc36556de5c
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I87cd0508ed5ed922211a51f43ee96b6f44cf673d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: I6d822165bb9a0cd6f7d4cdcb36333887953110a3
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20053
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enable RT8168_GET_MAC_FROM_VPD in fizz Kconfig.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I00f63dcb56a2c9a4600c8461bc94e06ec5ab2d81
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
If RT8168_GET_MAC_FROM_VPD selected, use r8168
driver with some slight mods to check the VPD
for a mac address. Otherwise, check for mac
address in cbfs. Use default mac address if
cannot find one.
BUG=b:62090148, b:35775024
BRANCH=None
TEST=Boot to kernel. Insert mac address into VPD
vpd -s ethernet_mac=<address>
reboot the system.
Ensure we have ip address and corresponding mac
address with ifconfig.
Ensure ethernet controller shows up with lspci.
Change-Id: I7ff29de2c4c3635dc786686cc071c68d51b0f975
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
By default disabled. Will need to add
FIZZ_USE_SPI_TPM config to enable.
BUG=b:62456589, b:35775024
BRANCH=None
TEST=Reboot and ensure that TPM works in verstage
CQ-DEPEND=CL:530184
Change-Id: I14ce73a1c3745c996b79c4d4758ca744e63a46b4
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20134
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes report found by undefined behavior sanitizer. Dereferencing a
pointer that's not aligned to the size of access is undefined behavior.
The report triggered for smbios_cpu_vendor(). Also fixes the same issue
in smbios_processor_name() found by inspection.
Change-Id: I1b7d08655edce729e107a5b6e61ee509ebde33b6
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Add missing includes to build mmc.c.
TEST=Build and run on Galileo Gen2
Change-Id: I0dea597272e5ece97843704a159aa546a8d77ff0
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Reviewed-on: https://review.coreboot.org/20271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch adds mipi_camera.asl,
* Add TPS68470 PMIC related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
BUG=b:38326541
BRANCH=none
TEST=Build and boot poppy. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/19621
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
These delays, adding up to 600 ms, don’t seem to be needed, so remove
them.
TESTED on d510mo, boots fine without.
Change-Id: If089d6677fe95b086eeb00540acfbb66fa2e1c47
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
Fixes 2 reports found by undefined behavior sanitizer. Dereferencing
pointers that are not aligned to the size of access is undefiend
behavior.
Change-Id: Iaa3845308171c307f1ddc7937286aacbd00e3a10
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20155
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use define for SSA base address.
Move EM64T area to 0x7c00 and add reserved area of size 0x100,
as there's no indication that the address 0x7d00 exists on any
platform.
No functional change.
Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The differential signal of DQS needs to keep low
level before gate training. RPULL will connect
4Kn from PADP to VSS and a 4Kn from PADN to
VDDQ to ensure it. But if it has PHY side ODT
connected at this time, it will change the DQS
signal level. So it needs to disable PHY side ODT
when doing gate training.
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I56ace8375067aa0bb54d558bc28172b431b92ca5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: cb024042c7297a6b17c41cf650990cd342b1376f
Original-Change-Id: I33cf743c3793a2765a21e5121ce7351410b9e19d
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/448278
Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com>
Original-Tested-by: Caesar Wang <wxt@rock-chips.com>
Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org>
Reviewed-on: https://review.coreboot.org/18582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
The previous implementation was using a for loop. By it's
very definition the last statement in the for loop declaration
is done at the end of the loop. Therefore, if the conditional for
breaking out of the for loop because of a timeout would always
see a value of 0 for the number of APs accepted. Correct this
by changing to a while loop with an explicit timeout condition
at the end of the loop.
Change-Id: I503953c46c2a65f7e264ed49c94c0a46d6c41c57
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Create Intel Common SCS code. This code currently only contains
the code for SD card SSDT generation. More code will get added up
in the subsequent phases.
Change-Id: I82f034ced64e1eaef41a7806133361d73b5009d3
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/19631
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Use verb table values from AMI firmware, consolidate NID
definitions using azalia macros. Fixes headphone jack detection
and microphone.
Change-Id: Ia31be6efc7afe921ad91b400f66694d951f0a260
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Initialize the audio codec without depending on DSP binary blobs.
The hda_verb.c was copied from the intel/kblrvp rvp7 variant, and the
hda_verb.h file was copied from the purism/librem13.
The IoBufferOwnership FSP option in devicetree has to be 0 for the azalia
driver to work.
Change-Id: Ifa36ac0839daedfa59c497057da0ace04d401f2a
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Some NVMe devices (Intel 600p series for example) seem to lock up
in D3 drive power state (L1.2 PCIe power state).
Disabling L1 substates fixes it.
Change-Id: I00a327dc91d443beb565fe4e72aaf816e40a007c
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Reviewed-on: https://review.coreboot.org/19900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Enable libgfxinit.
Tested on Lenovo T430:
* LVDS
* VGA
* DP (using DP->HDMI adapter)
All three ports are working. The LVDS port is garbled under linux
when VGA or DP is connected, likely due to missing VBT.
Change-Id: I665661e93724072d1e8412cfcc0e818f824c8cb0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Use a GNVS variable to store the trackpad interrupt, in order to
support both SNB and IVB variants from a single build.
Change-Id: I53df35fff41f52a7d142aea9b1b590c65195bcfd
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Add a GNVS variable to store trackpad IRQ for google/parrot, so
that both SNB and IVB variants can be built with the same config
Change-Id: I232da4077e3400b8ef2520dc33fd770c731b7ec3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Existing value was copied from librem13 v1 board, use value
obtained from AMI firmware.
TEST: Observe Windows boots correctly, function keys work
under both Windows and Linux.
Change-Id: I0ea6cc4602ce1047cb803acc65cbca1af1f480b0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Populate a memory_info struct with PEI and SPD data,
in order to inject the CBMEM_INFO table necessary to
populate a type17 SMBIOS table.
On Broadwell, this is done by the MRC binary, but the older
Haswell MRC binary doesn't populate the pei_data struct with
all the info needed, so we have to pull it from the SPD.
Some values are hardcoded based on platform specifications.
Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Update devicetree USB config based on board spec.
Leave OC pins set to skip since the info is unavailable.
Change-Id: I2a4fe17ed7edacbbbaf56969f9d2801b45a20da9
Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm>
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/19940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Don't allow the user to set PCIe configspace base address.
Don't allow the user to set the DCACHE size and base.
Change-Id: I7a42cc5f6098214364624bcfa3cbd93b4903ee84
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20181
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Does not need to changeable in menuconfig.
Change-Id: Id488f7333952d10d10a62ac75298ec8008e6f9b4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
While building poppy board, build failed with following error message:
Writing new image to build/coreboot.pre.new
mv build/coreboot.pre.new build/coreboot.pre
util/me_cleaner/me_cleaner.py -c build/coreboot.pre > /dev/null
This image does not contains a ME/TXE firmware NR = 0)
make: *** [src/southbridge/intel/common/firmware/Makefile.inc:55:
add_intel_firmware] Error 1
Hence keeping CHECK_ME unset by default.
TEST=Succesfully built coreboot for Poppy & booted to OS.
Change-Id: Ib3186498c8da307b686c06c3828e24acbc7f2d17
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/19257
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicola Corna <nicola@corna.info>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The board dutifully registers an int15h handler and provides the
defaults to add a VGABIOS.
That should be good enough to initialize graphics through the VGABIOS
file.
Fixes build on Chrome OS configurations (at least until the Ada toolchain
situation is resolved over there).
Change-Id: I1d956b5a163b7cdf2bd467197fba95f16e5e8fa3
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
As the hardware designed on gru, the AP_I2C_TP_PU_EN (gpio3_b4) controlled
the SCL/SDA status to avoid leakage. And the gpio3_b4 of rk3399 pull
resistor is 26k~71k and 3.3v for supply power, and gpio3_b4 pin connected
2.2k resistor to i2c of TP device.
The default of this gpio status is pulled up during the start to bootup,
it's very weak drive for the TP device that maybe cause to trigger the
recovery process of elan's firmware.
Also, the Elan updated its firmware(102.0.5.0) to delay checking the
i2c of touchpad is greater than 1 second.
So we have to drive the stronger pull-up within 1 second of powering up
the touchpad to prevent its firmware from falling into recovery.
Change-Id: I9a67d1c041afafde24ed9f00716ba41a9b41a8da
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Reviewed-on: https://review.coreboot.org/19863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add method gma_write_acpi_tables.
No need to update GNVS as it doesn't have ASLB.
Change-Id: Ia138cfde2271a298c36b85e999ff69f0f211ba11
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This reverts commit f4835a85c0. It
completely ignores port coalescing and breaks enumeration in many
cases. The code reused to disable and hide the root ports was never
meant to be called that way.
The same effect of power saving can likely be achieved by clock
gating unused ports after enumeration without further, error-prone
function hiding.
Change-Id: I90d8b9236004f0c42d5a2b6bbd39f6dea07bd3d1
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This driver reinvented MAINBOARD_DO_NATIVE_VGA_INIT in a very special
way: If it wasn't set, perform native gfx init in textmode, if it was
set, perform native gfx init in linear framebuffer mode. Test for
LINEAR_FRAMEBUFFER instead and make the native gfx init optional.
Also, make Kconfig reflect the actual behaviour.
Change-Id: If20fd1f5b0f4127b426e8ff94acc61fcd4eb49af
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This was the single spot where VGA_BIOS_ID wasn't guarded by anything.
It resulted in the wrong default id if we didn't chose to add a VGA BIOS
at first but added one later (e.g. a board provided default guarded by
VGA_BIOS wasn't applied then, because the Via/CN700 value was already
set).
Change-Id: Ia16a5e6d194191d8da8c551d6eb3849bc65864a9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
A major regression was introduced with commit 6520e01a
(soc/intel/apollolake: Perform CPU MP Init before FSP-S Init)
where the APs execution context is taken away by FSP-S. It
appears that FSP-S is not honoring the SkipMpInit UPD because
it's been shown with some debug code that FSP-S is compeltely
hijacking the APs:
Chrome EC: Set WAKE mask to 0x00000000
Chrome EC: Set WAKE mask to 0x00000000
CBFS: 'VBOOT' located CBFS at [440000:524140)
CBFS: Locating 'vbt.bin'
CBFS: Found @ offset 2e700 size 1a00
Running FSPS in 4 secs.. 315875 4315875
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
cpu2 Waiting for work
cpu3 Waiting for work
cpu1 Waiting for work
Running FSPS.. 4315875 4315875
ITSS IRQ Polarities Before:
ITSS IRQ Polarities Before:
IPC0: 0xffffeef8
IPC1: 0xffffffff
IPC2: 0xffffffff
IPC3: 0x00ffffff
ITSS IRQ Polarities After:
IPC0: 0xffffeef8
IPC1: 0x4a07ffff
IPC2: 0x08000000
IPC3: 0x00a11000
This is essentially a revert of 6520e01a to fix the previous
behavior.
Change-Id: I2e136ea1757870fe69df532ba615b9bfc6dfc651
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/20215
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
Use common init_igd_opregion method.
Change-Id: Ia10a28d05b611a59f787b53f9736b3b76a19ea4a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Use common init_igd_opregion method.
Change-Id: Ic8a85d1373f04814b4460cce377d6e096bcdc349
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/19907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Martin Roth <martinroth@google.com>
Too low gfx_uma_size can result in problems if the framebuffer
does not fit.
This partially reverts: 7afcfe0 "gm45: enable setting all vram sizes
from cmos"
Change-Id: I485d24198cb784db5d2cfce0a8646e861a4a1695
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/20194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 2e7f6cc introduced the 'no graphics init' option for
FSP 1.1 SoCs using a GOP driver to init the display, but selecting
that option while including a VBT breaks compilation for Braswell
and Skylake devices because the VBT and GOP driver are intertwined.
This patch decouples the VBT from the GOP driver execution,
allowing the 'no graphics init' option to compile (and work)
properly when CONFIG_ADD_VBT_DATA_FILE=y.
Change-Id: Ifbcf32805177c290c4781b32bbcca679bcb0c297
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20210
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
TEST=Verified that board still boots to OS without any error.
Change-Id: I02d2a6cbcab92766a35993bfd20aaeed4ca22c90
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that we dynamically disable TPM interface based on config options,
add support for generation of SPI TPM ACPI node if SPI TPM is used.
Change-Id: I87d28a42b48ba916c70e45a061c5efd91a8a59bf
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Based on the config options selected, decide at runtime which TPM
interface should be disabled so that ACPI tables are not generated for
that interface.
TEST=Verified that unused interface does not show up in ACPI tables.
Change-Id: Iee8f49e484ed024c549f60c88d874c08873b75cb
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20141
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
If I2C device is disabled:
1. BAR for the device will be 0
2. There is no need to generate ACPI tables for the device
TEST=Verified that if an i2c device is disabled statically in
devicetree or dynamically in mainboard, then coreboot does not die
looking for missing resources.
Change-Id: Id9a790e338a0e6f32c199f5f437203e1525df208
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20140
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Initial support for undefined behavior sanitizer in ramstage. Enabling
this will add -fsanitize=undefined to the compiler command line and
link with ubsan.c in ramstage. Code with UB triggers a report with
error, file, and line number, then aborts.
Change-Id: Ib139a418db97b533f99fc59bcb1a71fb6dcd01d8
Signed-off-by: Ryan Salsamendi <rsalsamendi@hotmail.com>
Reviewed-on: https://review.coreboot.org/20156
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>