Previously, we were seeing device boot into the recovery screen with
error code 0x5a. This was root caused to the SATA GPIOs (specifically
DEVSLP) not being initialized early enough, causing the SATA 1 link
detection to time out and the device to reboot into recovery with
0x5a instead of booting into the OS as usual.
BUG=b:69715162
BRANCH=None
TEST=after flashing BIOS, set gbb flags to 0, then type reboot from
the OS.
Change-Id: I53913d5b7adaeb43edd0ef2d24a7cad92052d68a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change makes the Nautilus platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:68686020
TEST=Build, booted nautilus board. Verified kernel reads new strings.
Change-Id: I041f2838f07a2525be7a28fdc69b7f1af46d16f1
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/23648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Previously ECT was disabled in commit 22401, on D0 stepping system and
FSP version 7.x.20.52, disabling ECT will cause memory training failure
and the system is stuck at post code 00D5h.
BUG=b.72473063
TEST=Apply patch and build coreboot image, flash into meowth P0 system
with D0 stepping silicon installed, system can pass memory training and
boot up into OS.
Change-Id: I7dd0a7dfe2993ad9cfaf00050175e5a47468b471
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/23645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This change makes Nami platform update the two fields:
*oem_id* and *oem_table_id*, if the Maxim codec is detected.
Change is made to correct the audio topology file name that is
being read from oem_id fields, loaded and displayed in dmesg.
BUG=b:70646770
TEST=Verify kernel reads new strings.
Change-Id: I513a997f312e2d37d76da0379feb017d1f591f9a
Signed-off-by: Kaiyen Chang <kaiyen.chang@intel.com>
Reviewed-on: https://review.coreboot.org/23670
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The Pmax is calcuated from MAX(Psku1, Psku2), where Psku1, Psku2 are
estimated Pmax power of U42 and U22 skus. For U42 sku, the Pmax is PL4
(71W) + ROPmax (49W) = 120W; for U22 SKU, the Pmax is PL4 (43W) +
ROPmax (49W) = 92W. So Pmax is set to MAX(120W, 92W) = 120W.
BUG=b:71594855
BRANCH=None
TEST=Make sure correct pmax value is being passed into fsp
Change-Id: Ic27fef87c869094b20438e6ee0e1eb0b35122b8d
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23633
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
This change updates the WiFi device wake pin to GPP_E22 from WAKE# (to
match the latest schematic changes).
Since WiFi was the only device using WAKE# pin, DSX_EN_WAKE_PIN is
removed from deep_sx_config as well.
BUG=b:72697650
TEST=Verified:
1. Wake-on-wifi works.
2. Device is able to enter G3 without WAKE# pin causing unwanted wakes
from deep S5.
Change-Id: Ibde81f73cca322f9b8b45baf8ee18ae00521467d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
With the new extra detachable UI elements, we're running out of space in
Scarlet's RO CBFS. Thankfully, the GBB is still massively
overdimensioned, so we can steal another half MB from there.
This patch changes the FMAP for some boards that have already had
production firmware releases. However, all the new changes are to the RO
parts of the FMAP, so there shouldn't be a way this could cause a
problem for updates.
Change-Id: Iec182de3e894e56fec2a64b034c0ca65d78a5522
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/23595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I2C bus rise/fall times were measured as follows. Signals were generated
with:
- bus 0: manual i2c driver in depthcharge
- bus 2,3: i2cdetect -r <bus_number>
and then measured manually with an oscilloscope.
BUG=b:72442912
Change-Id: I291e144249271ec34a93417398e54e68b8e21e23
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
CMOS layout is not used and can be removed. A change to Kconfig is needed in
order not to break the build.
BUG=b:64207749
TEST=Build kahlee.
Change-Id: Ib5d18e80a56111d96c730420db865194c71de1b3
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/23596
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable HotPlug for the PCIe root port that the WiFi device
is on so the OS can re-train the link without needing a reboot
if it goes down unexpectedly at runtime.
BUG=b:72417777
TEST=enable HotPlug on Eve Root Port 0 (WiFi) and check in
linux that it is identified as a HotPlug capable root port.
Change-Id: Id2b7fc92c8c9128f0e28102eb5991bda7fbf6799
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/23512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Pass in fizz-specific adapter-based PsysPl3 and Pl4 values to avoid
brownouts. According to Intel doc #560604, page 74, the max time
window is 64ms (code=6) and the min duty cycle we can set is 4%.
BUG=b:71594855
BRANCH=None
TEST=Boot to OS and check MSRs using iotools for expected values
Change-Id: I06a4c5bc25f6ec036b79f6941f80e26058d64930
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
On EVT, the USB and MIPI cameras share the same power source. As a result,
when the MIPI camera driver turns off the camera once probed, USB camera will
be disconnected. To make USB camera work on EVT devices, we will need a hack in
coreboot to leave the camera power always-on.
BUG=b:72839352
TEST: Verified the MIPI and USB camera function on DUT board
TODO: This power issue will be fixed on DVT build. Will revert this patch
once confirmed power sources for MIPI and USB camera could be supplied
individually.
Change-Id: Icaaf7e17447492f2e2f2d03eb9a35bcc53667f28
Signed-off-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-on: https://review.coreboot.org/23546
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andy Yeh
This patch makes coreboot fetch OEM ID and SKU ID from EC. If it fails,
it falls back to GPIO pins.
BUG=b:70294260
BRANCH=none
TEST=Verify AP log shows expected OEM ID and SKU ID on Fizz.
Change-Id: I06d3a205275b46660b3974bc3673d4be8e13f6d1
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/23548
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cherry-pick from Chromium:
a60ac10 [Lars: Turn on keyboard backlight in romstage]
Use the keyboard backlight to provide indication that the system is
booting. This is useful for determining that a system is in S0 and
is running BIOS code.
TEST=boot on Lars and see keyboard backlight come on early
Original-Change-Id: I4fede6cff85f4487cedfbccf6cc24c6380d905e0
Original-Signed-off-by: Jenny TC <jenny.tc@intel.com>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I4b1fed10d9bd1ae1b265e848417836f816f252f3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Combination of several commits from Chromium tree:
949037c [Lars: coreboot GPIO changes for EVT]
c286789 [Lars: Set USB Type A current limit to 2A]
0f1b26d [lars: set BOOT BEEP GPIO GPP_F_23 to output and Low]
4a0650d [Lili: Support touchscreen]
Disable unused GPIOs based on schematic and
adds GPIO mappings for HSJ_MIC_DET, PCH_BUZZER and AUDIO_INT_WAK.
Set GPIOs USB_A0_ILIM_SEL & USB_A1_ILIM_SEL low to enable 2A
charging from the USB Type-A port.
GPP_F_23 is set to NC currently and is floating, causing the on-board
speaker to have no audio or the audio has noise; set to output/low.
These commits bring lars' GPIO mapping in line with the Chromium tree.
Original-Change-Id: I3bf4aa8599255e5382d99810b4c83b4c97c648b6
Original-Change-Id: I328a8be22dc59492477cbe362a5d5b94aa80a397
Original-Change-Id: I253e55bf2b423363a00347778cabaa4184d85aec
Original-Change-Id: I761f7c5ea5fc7a173c07a8c37da1338a1b2cd269
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Original-Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Balaji Manigandan <balaji.manigandan@intel.com>
Original-Tested-by: Kuen Liu <kuen.liu@quantatw.com>
Change-Id: Ic2d188fbf913a11fbf6ad1f0eb3a5e72ba4cb1cf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium:
99cd8f8 [lars: Update the MAINBOARD_FAMILY string in Kconfig]
This string was left at the default for kunimitsu and should be
updated to indicate the proper mainboard.
Original-Change-Id: Icc0e162d57242e7b0610fb570ef1a8a45ee16e4f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: Ia4b70227c8cfdfe939e40ea6258d494337a2907b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Combination of several commits from Chromium tree:
3b875a2 [Lars: Update Memory ID for DVT board]
b6d7c63 [Lili: Update Memory IDs]
f203f99 [Lili: Add new SPD for Hynix H9CCNNN8GTALAR-NUD]
a6571bf [Lili: Update Memory IDs]
80e1841 [Lili: Update Memory IDs]
58d4487 [Lili: Fix memory string show error in spd data]
These commits bring lars' SPD data in line with the Chromium tree.
Original-Change-Id: I54d0e6d2bbe86d5dc2ee5825f332d36abfa99084
Original-Change-Id: I9431393f369a1d2870bdabba1fc55d9cefae5c39
Original-Change-Id: I3b325a1801f49109429eb647d8d98a5537ce1b7b
Original-Change-Id: Ie8a32d8a26ea1054e2df8432084a95d1cb03f991
Original-Change-Id: I64c73950e3bea57b6c5a90257211b3d6d7f1baab
Original-Change-Id: I0e425fa4f0bae544680d5522c2e05a4f7a3be95a
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I7cc9b01012b0b9ed72804192bb5953243fc859b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit:
af3ec09 [Lars: Add sdmode-delay device property for maxim98357a]
Add "sdmode-delay" as a device property for the maxim98357a codec.
This speaker amp requires both SFRM & BCLK to active and stable
before it is unmuted. If there is a BCLK and no SFRM,
that results in a pop noise.
Adding a configurable delay parameter for all Skylake platforms
to allow sufficient time for the BCLK & SFRM on I2S to be stable
before the amp unmutes itself to avoid a pop noise at the start of playback.
Setting the delay to 5ms since the observed delay between SFRM and unmuting
of the amp is around 2ms.
Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.
Original-Change-Id: I1fff4f86ff816e907553e7a6f1d05713f9d85084
Original-Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change-Id: I8a1c52ccdb08df9a4ab293e12bb266309e08737b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit:
848ee3a [Lars: Add device properties for Nuvoton codec]
Update sar-threshold, sar-compare-time, sar-sampling-time
properties to match values in lars' Chromium branch.
Adaptation needed to account for parameters having moved
from mainboard.asl to devicetree in upstream tree.
Original-Change-Id: Id0c28e50406a29e6f33d04ca78fd2a3e3974fa90
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Change-Id: I2748a315d27eb947197109808b4d5fa8a82c8cf3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium:
55c0eb3 [Lili: Set new thermal parameters]
Set new parameters of DPTF for both Lars and Lili.
The acoustic will have higher 1.6dB in transition mode,
when using Lili fan table on Lars.
Original-Change-Id: I730ac483e2a6d43c8dcfe94da6761194c14f3163
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Change-Id: I3bf16db43bb90a542c6526f3bc891f820da00ca0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/23566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The wifi card was not being powered, and was being held in reset during
PCI enumeration, so it was not being brought up.
BUG=b:72738963
TEST=Verify wlan card shows up in lspci
Change-Id: I5a1e83298af35aa80c67c75cd6ec0a2c3213891e
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23552
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is a line artifact in the lower third of the display with the
current initialization code. So update it with code provided by
Innolux to fix this issue.
BUG=b:69689064, b:72191820
TEST=boot on dru with an Innolux panel and artifact line disappear.
Change-Id: I9679c4f7f706fd6cd2e1dba7ec79e772fe3f227a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
When booting kahlee, there's an error message: "Warning: Can't write PCI
IRQ assignments because 'mainboard_pirq_data' structure does not exist".
This is generated by write_pci_cfg_irqs due to missing mainboard_pirq_data.
BUG=b:70788755
TEST=Build and boot kahlee. Warning message must be gone.
Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The kernel requires the display oprom is loaded *and* ran
in order for the kernel to not panic. Therefore, select the
correct settings such that normal mode works for Chrome OS.
BUG=b:72400950
Change-Id: Ibae5bc6b382cbe71a55c2386a24bb420cb8f313f
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23506
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit adds an entry for H1/Cr50 into the devicetree for setting up
ACPI entries for H1 communication.
BUG=b:69250772
TEST=See probe messages in dmesg
Change-Id: Id55ce3364ea4acdb62782758e5bcb2a167286cb9
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23514
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit removes a manually written asl file in favor of configuring
the trackpad through devicetree.
BUG=b:72121803
TEST=cat /proc/interrupts with trackpad connected
Change-Id: I38afcf89ea64ffaf6a10bb317c41154feda57e50
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23508
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Turn on power for front camera at startup in coreboot (needs
to be set for factory scan).
BUG=b:69011806
BRANCH=master
TEST=none
Change-Id: I2f31b19dfef5fe386b485dd675f0ff981288acf4
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/23503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change GPIO settings for meowth rev 2 boards.
Changes include:
- GPP_B7 set to no-connect
- GPP_C1 set to no-connect
- GPP_D8 set to no-connect
- GPP_D9 (PP3300_WLAN_EN) set as output with initial value high
- GPP_E9 (DCI_CLK) set to no-connect
- GPP_E10 (DCI_DATA) set to no-connect
BUG=b:72202352
BRANCH=none
TEST=none
Change-Id: I2e6d049faaa0a70b40ceb47aaf81a81d820dd4c1
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Set USB2 port 0 & 1 to use OC2 and OC3 respectively. Previous settings
were causing false overcurrent conditions as OC0 and OC1 were used for
other purposes.
Remove initialization of unused usb3 ports, and configure the ports we
use (usb3 ports 0 & 1) to use OC2 and OC3, respectively.
BUG=b:72250084
BRANCH=none
TEST=Verify meowth can recognize and boot off a kernel on USB drive.
Change-Id: I528b67d80a1da84e5307facb40de545089979f57
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change selects EC tablet event and provides trip point
temperatures for tablet and non-tablet mode so that DPTF can
be supported depending upon device mode.
BUG=b:65467566
TEST=Verified by changing modes that the trip point temperatures are
updated in the
OS (/sys/devices/virtual/thermal/thermal_zone{2,3,4,5}).
Change-Id: I071868982fa87821550b870a6d8050cf2a030b49
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23463
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
This change decouples EC tablet event and TBMC device by guarding
TBMC definition and notification using EC_ENABLE_TBMC_DEVICE. It
allows mainboards to use tablet events without having to define a TBMC
device.
BUG=b:72554519
Change-Id: Ie38b6d68486e8e644dd0d6d406def3ae7fdb5152
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Since the h1 i2c bus is required for verstage mark the bus
as needing to be initialized early. That way, the bus is initialized
in bootblock prior to verstage.
BUG=b:70232394,b:69250772
Change-Id: Ice8525e08ccb438bc468d4c8bd311f72eddc7eb6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/23498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Innolux didn't deliver a working init sequence yet for devices without
OTP programming. The sequence in this change has been derived from a
register dump of a mostly working panel with OTP. It is not meant to
be final, but to make devices with unprogrammed OTP work, while Innolux
is figuring out a proper sequence. There is a known issue with an
artifact line in the lower third of the display.
Change-Id: I7096506208e4cb29c5f31a7ac502231a6c23ac92
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23311
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Some panels need to transfer initial code, and some of them will be
over 3 bytes, so support LONG_WRITE type in driver. Refactor mipi
dsi transfer function to support it.
Change-Id: I212c14165e074c40a4a1a25140d9e8dfdfba465f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/23299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Set PsysPl2 values to 90% of max adapter power for all types of
adapters (typeC and barrel jack) to account for a 10% power loss from
the adapter to the soc.
BUG=b:71594855
BRANCH=None
TEST=reboot device and make sure Pl2 and PsysPl2 MSRs are properly set
with iotools rdmsr command on both U42 and U22 skus with both
typeC and barrel jack power adapters.
Change-Id: I8425c6d4d669449eccb9324ff58ff6d1662c5c43
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
I measured the rise and fall times for I2C bus 1 from userspace
manually, using "i2cdetect 1" called from userspace and an oscilloscope.
This commit fixes the values there to reflect reality.
BUG=b:72442912,b:70232394
Change-Id: I4f593cb2674006060cad9a77753c23f7d9828c9b
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23459
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fix the values that were off by one.
This was discovered when using postcar stage that prints with
debuglevel BIOS_NEVER.
Change-Id: I73a077950ed0dc735d89c9747a8da0a25f30822d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/23186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change updates the camera power enable GPIOs as per the latest
schematics. With this update, since one of the enable GPIOs is using a
UART0 pin, set UART0 to PchSerialIoSkipInit in devicetree so that
FSP-S does not re-configure the UART0 GPIOs.
BUG=b:68964831
Change-Id: I5d9126ed8ca2b714f6276f4d3a24c243d7654774
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23414
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit adds support for an Elan touchscreen device connected over
I2C via devicetree.
BUG=b:72121803
TEST=Confirm the device is probed for.
Change-Id: Ia9e427dbeab9088f77e3cd751b561f7b9a8cb400
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
I2C bus configuration is generally set up in devicetree.cb. This change
establishes listings for the buses so that they can be used (though
followup changes should update the buses to have correct timings).
BUG=b:72121803
Change-Id: I2b12c82d2bab42ab470aa207880be8876e7cb75f
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23407
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required to add support for I2C devices on Kahlee to ACPI tables
via devicetree.cb. Without this, operations are not emitted for I2C
devices and the proper ACPI table entries are not generated.
BUG=b:72121803
Change-Id: I1cfe12f3cc23e90ec74b739678f5a5a73257c2c2
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Chrome OS reports that "GRUNT TEST XXXX" is an invalid hwid. The 8296
comes from the lower four numbers from running:
$ printf "%d\n" 0x$(crc32 <(echo -n 'GRUNT TEST'))
BUG=b:72436450
Change-Id: Ib0044442396cad65c25c107feb35a30a2f70b769
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23411
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This change disables SATA controller in order to make SATA IP enter
low power status.
BUG=b:72332817
TEST=cat /sys/kernel/debug/pmc_core/pch_ip_power_gating_status
and verify SATA IP enters low power state
Change-Id: I72a98bc3d0b47aebc0d7be534f4a7503084b257f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds AC and DC loadline settings since vr_config_enable is
set. Without correct AD/DC loadline settings, VRs reported incorrect
VID values which caused CPU freqency clipping. The clipping reason
could be retrieved from MSR 0x64F. From VRTT report, the AC/DC
loadline resistances are within spec, we can use default value defined
in Table 6-1, doc #543977.
BUG=b:70646304
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage & Read AC/DC loadline
settings from DCI to ensure the values were programmed correctly.
Change-Id: Id0ce29fa5726ca3711aa4c822fb123e2de7bc48f
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23349
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tune I2C params for I2C bus 5 to ensure that the frequency does not
exceed 400KHz.
BUG=b:65058277
BRANCH=None
TEST=Measured bus frequency for audio <= 400MHz
Change-Id: I18bca023a6a0fe21e6f46f8688264d3c04d77f25
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Kahlee uses LPC TPM while grunt is using Cr50 connected to I2C. Create
the appropriate selection based on selected board, and if grunt then
define the I2C address.
BUG=b:69416132
BRANCH=none
TEST=make all
Change-Id: Ia866f80de0164d8cec84e204a5fe93bb53df547f
Signed-off-by: Chris Ching <chingcodes@chromium.org>
Reviewed-on: https://review.coreboot.org/22960
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0, S3, S5 and S0ix
Change-Id: If56d1de5d1157c8cf9c418e3a9d2396ffcfcb0fd
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21610
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Function platform_FchParams_reset() is now an empty function, remove it,
its header declaration and its use.
BUG=b:64140392
TEST=Build kahlee.
Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Fill up the dummy gpio_set_stage_reset[] and gpio_set_stage_ram[]
with data from agesa_board_gpios[], wrap format and delete
agesa_board_gpios[] and get_gpio_table(). Then remove the
get_gpio_table() call from BiosCallOuts.c. Finally, remove
get_gpio_table() from
google/kahlee/variants/baseboard/include/baseboard/variants.h.
BUG=b:64140392
TEST=Build grunt. Build and boot kahlee, recording serial output. Search
for "stage bootblock" and "stage ramstage", indicating GPIO being
programmed.
Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Create a GPIO programming function that can be called from multiple
stages (bootblock, romstage and ramstage) that will program only the
GPIO specific to the particular stage.
Add dummy table to kahlee, grunt and gardenia to be able to test a build.
BUG=b:64140392
TEST=Build kahlee, grunt and gardenia with GPIO programming call at
bootblock. This call is removed before commit, so bootblock.c is not
committed.
Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Change e1a75d4(soc/intel/skylake: Override KBL IccMax settings)
provides correct iccmax settings for kbl-u based on the SKU. Thus,
there is no need to override these values in devicetree. This change
gets rid of iccmax settings in the nami devicetree.
Change-Id: Ie7220bae71fcc597fc20c5e98793d4ea7af5650e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Most affected boards set the function disabled (FD) register to an
arbitrary state dumped from systems running the vendor BIOS. This
makes it impossible to enable the devices in devicetree and a pretty
big mess of course because nobody cared to keep the register in sync
with the devicetree.
To get completely rid of most of the writes to FD, move setting of
PCH_DISABLE_ALWAYS into the southbridge code where it belongs.
Change-Id: Ia2a507cbcdf218d09738e2e16f0d3ad1dcf57b8b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/23255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hal Martin <hal.martin+coreboot@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Bill XIE <persmule@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
this enables the MRC recovery cache for zoombini & variants.
the Kconfig options are:
HAS_RECOVERY_MRC_CACHE
MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
one note of caution: early board builds will likely fail to boot with:
tlcl_extend: response is 0
tlcl_extend: response is 0
tlcl_lock_nv_write: response is 0
tlcl_lock_nv_write: response is 28b
Failed to lock rec hash space(1f)
Saving nvdata
hard_reset() called!
the fix is to boot into recovery once, then it's business as usual.
using servo, this can be done with:
dut-control power_state:rec
BUG=b:71785303
BRANCH=chromeos-2016.05
TEST=boots on meowth...
Change-Id: I77f36d36a70c8c9c74a7fa3a114d3177f33a708b
Signed-off-by: Caveh Jalali <caveh@google.com>
Reviewed-on: https://review.coreboot.org/23298
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
this adds missing ACPI entries for the EC, CPU, and power button.
also, the EC to AP wakeup pin assignment is fixed.
BUG=b:71819257
BRANCH=chromeos-2016.05
TEST=booted on meowth. /sys/class/power_supply now gets populated.
Change-Id: I0d091bdf25f9a806bd36329d1f17ac34b3115e48
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/23237
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
This patch removes IccMax settings from device tree since they
are handled in SoC code from patch e1a75d.
BUG=b:71369428
BRANCH=None
TEST="USE=fw_debug emerge-fizz chromeos-mrc coreboot
chromeos-bootimage" & ensure the IccMax settings passed
to FSP are from SoC code.
Change-Id: I6b01c50a2589d1722c5bf4aa2f44a9574df818f4
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/23278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Turn on the load switch to the FP MCU at startup, so the kernel can
detect it and use it.
The load switch enable pin is connected to the GPP_A11 PCH pin (aka
PCH_FP_PWR_EN).
BRANCH=none
BUG=b:71986991
TEST=on Meowth, see the kernel detecting a cros_fp device at startup:
[ 2.133456] cros-ec-spi spi-PRP0001:00: Fingerprint MCU detected.
[ 2.157420] cros-ec-spi spi-PRP0001:00: Chrome EC device registered
Change-Id: Id3c40b965a5f018c63481c2e2eea3fc8307352bd
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23329
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Configure the FP MCU interface on GSPI1.
BRANCH=none
BUG=b:71986991
TEST=boot on reworked Meowth with a ZerbleBarn board attached to
GSPI1 and see the cros_ec kernel driver detecting it.
Change-Id: Ib874ddaf4948a766fd05c11f4675dbfdb679059d
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-on: https://review.coreboot.org/23328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for new memory stuffing options that will appear on
the P1 meowth boards.
new strap setting - associated SPD file
----------------------------------------
0b001 - Hynix_H9HCNNN8KUMLHR_1GB.spd.hex
0b010 - Samsung_K4F6E3S4HM_2GB.spd.hex
0b011 - Hynix_H9HCNNNCPUMLHR_4GB.spd.hex
BUG=b:69011806
BRANCH=none
TEST=none
Change-Id: Ief07f3de351d01cbc195b785c36e96de0cbf7ddb
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
* Move code from src/lib and src/include into src/security/tpm
* Split TPM TSS 1.2 and 2.0
* Fix header includes
* Add a new directory structure with kconfig and makefile includes
Change-Id: Id15a9aa6bd367560318dfcfd450bf5626ea0ec2b
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Our current U22 skus (celeron and i3) actually don't support PL2,
but making sure that if we do decide in the future to use it to
make sure PL2 and PsysPl2 values are set appropriately.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 90W with barrel jack for U42
and 65W with barrel jack for U22.
Change-Id: I084d0320128a6e05948023520a30c497c41be23b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable S0ix wake mask programming from coreboot using unified host event
programming interface. Lazy s0ix wake mask helps to configure s0ix wake
mask during boot and EC sets the wake mask during S0ix entry.
BRANCH=none
BUG=b:63969337
TEST=verify masks with ec hostevent command on S0,S3,S5 and S0ix
Change-Id: I65173104fce258d03956bbb0e80073c47fe80fab
Signed-off-by: Jenny TC <jenny.tc@intel.com>
Reviewed-on: https://review.coreboot.org/21086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Right now the poppy baseboard camera topology allows to add maximum of 2
sensors. The sensors can be of different vendors. The current ASL code
structure doesn't allow sensor customization. Moving PMIC specific objects
from sensor objects to PMIC scope and having separate sensor ASL files will
help in unbinding the PMIC and sensor objects and allow some customizations.
BUG=None
BRANCH=None
TEST=Build and boot soraka, make sure both camera's are working fine
and also verify that the generated DSDT looks fine.
Change-Id: I63ae1a685b78bda212c5c48a4c2dc744164a3cb5
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23168
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
The variant boards can have a custom endpoints, splitting the ASL code
aids customizing the endpoints as per the variant board setup.
BUG=None
BRANCH=None
TEST=build boot soraka, verify that the cameras are working fine and
generated DSDT tables are same as before.
Change-Id: I5f1cded25bfb6a7baf18b211f9773dfecdc2f264
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/23167
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
GPIO 90 is being used as a GPIO. The IOMUX register is set correctly,
but these additional registers need to be set to use it as a GPIO.
- Split structures into variant specific versions. These will be
moved into the variant tree in a follow-on patch
- Set GENINT_DISABLE bit
- Disable interrupts for this GPIO.
BUG=b:71867096
TEST=Build and boot grunt. Verify registers are set correctly.
Change-Id: I4b8d12720167b298ee6e0acf80edf414539975b0
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23228
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The GPIOs that are being set low had the wrong value getting set.
FCH_GPIO_OUTPUT_VALUE was being set instead of FCH_GPIO_OUTPUT_ENABLE.
BUG=b:70234300
TEST=Build and boot Grunt
Change-Id: I16792b76252506a43aac92738b04096ae3fde01c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Grunt and Kahlee touchpads are on different i2c busses; I2CC and I2CD,
respectively.
Since grunt is the 'baseboard', put its configuration under baseboard, and
include it from the grunt variant.
BUG=b:71820409
TEST=Boot grunt to kernel, use evtest to test trackpad.
TEST=Boot kahlee to kernel, use evtest to test trackpad.
Change-Id: I1aeacf9a840342e73c1e219a825b39a124b4dd57
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23232
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Grunt and Kahlee have different audio codecs.
Create a new audio .asl for the baseboard for grunt's codec, link
to it from the grunt mainboard, and move the kahlee codec table
from the baseboard mainboard to its own .asl in variant/kahlee.
Note, we can't use the generic drivers due to the PCI scope
expectation. The AMD I2C are not PCI devices.
BUG=b:69397774
TEST=Codec driver loads. Check dmesg.
Change-Id: I1cc245357d1f3d444e5a5012466eaa5d75d637eb
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Reviewed-on: https://review.coreboot.org/23226
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move the apci/ to the baseboard and move mainboard.asl to
each variant.
BUG=b:71873651
TEST=build
BRANCH=none
Change-Id: I8a829f2946e4b280cd78574eb8dbda6c2a9a1028
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/23229
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Meowth uses GPD_2 as a dedicated lan_wake pin, so GPD_2 must
be set to use NF1 instead of gpio.
BUG=b:64395641
BRANCH=none
TEST=none
Change-Id: Iadf7158a792dfae0ea5e824d197a558524cdb5fd
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23222
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fizz has external Lan on PCIE port.
The Lan device on PCH is not used.
BUG=b:70889517
Change-Id: I99894bedec14a44724ac7c22d0c894132a795b78
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Digitizer power is not controlled by SoC. Also, since the digitizer
uses I2C-HID driver in Linux kernel, the device is put into sleep
anytime system is suspended. Thus, there is no need to control the
reset gpio using ACPI power resource.
TEST=Verified that digitizer device is properly detected on boot-up
and after suspend/resume.
Change-Id: Id11b8412d0ac48b2701d53b0a22ad3b747b544ec
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/23212
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Port initializer had been changed from PortDisabled to PortEnabled,
but engine inializer hadn't been updated from PcieUnusedEngine to
PciePortEngine. Update this so the port works.
Also change disabled port to PcieUnusedEngine.
BUG=b:71818026
TEST=PCIe device now shows up on D2F4
Change-Id: I11eb8c1fbad12fa9cf34d758a4ef3c22ef8ba4f7
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23210
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
If using type-C charger, then PsysPl2 may be lower than barrel jack
value of 90W, so need to override value to the max power of type-C
charger.
BUG=b:71594855
BRANCH=None
TEST=Make sure that PsysPL2 value set to 60W with zinger, but 90W
when using proper barrel jack adapter on and i7.
Change-Id: If955b9af0e23f47719f001f1d73ec37113937cea
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/23182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The spd.bin file was not getting generated properly, so moved logic
to variant's makefile.
BUG=b:64395641
BRANCH=none
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully and spd.bin is found when booting.
Change-Id: I4642d6ddb5e65f721d1bde31ca0ca5b4438da554
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/23190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The .spd.hex text is added to the name by the build process. This
was causing a failure because we were trying to add the files:
'file.spd.hex.spd.hex' to the build.
Remove the additional .spd.hex text.
BUG=b:71535311
TEST=Build
Change-Id: I11df7a90c979503676a66c6502900a13f1a8e359
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/23189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chris Ching <chingcodes@chromium.org>
Add support for memory configuration by providing weak implementation
from the baseboard. All SPD files are present under spd/
directory. SPD_SOURCES must be provided by the variants to ensure
that required SPD hex files are included in the SPD binary.
BUG=b:64395641
BRANCH=None
TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a"
compiles successfully.
Change-Id: I449ab56dfc7a75752944b58ba6291b5ee32f81ad
Signed-off-by: Nick Vaccaro <nvaccaro@chromium.org>
Reviewed-on: https://review.coreboot.org/22205
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Since the current hardware revision does not have external pull on the
pen eject signal, this change adds internal pull-up on it.
Change-Id: I426d9833d7efbd8735b6f2b4896d1012b62cb4b8
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/23143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tony Lin <tonycwlin@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rainier, a scarlet derived board, was configured to use spi0 for tpm
driver by default. This patch switches it to spi2 to reflect recent
changes in scarlet-derived boards.
Change-Id: Ib67109786512c068bb957890f456bccff7addc86
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/23129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Grunt's devicetree dropped some entries when it was split from the
kahlee variant. This commit restores:
spd_addr_lookup - memory information for AGESA
dram_clear_on_reset - keeps DRAM contents on reset
uma_mode - needed for vbios
uma_size - needed for vbios
Change-Id: I1d8cdc97594867f1d706318370055087976a5104
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Reviewed-on: https://review.coreboot.org/23099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Martin Roth <martinroth@google.com>
The spd size of DDR4 is 512, but the size empty.spd.hex is 256.
With empty.spd.hex and DDR4, it will cause mainboard_get_spd_data
loads spd data incorrectly due to the offset is wrong.
Change-Id: Iea3f216898525a2a602fabf1835c8a0c1245ee57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change is to enable SataPwrOptEnable.
With this change, we no longer see SError message in kernel during
suspend_stress_test.
BUG=b:70491485
Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/23019
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch revises LED0 Green light behavior from patch 2ecf3f8c.
For 100Mb link speed, LED0 should be OFF.
BUG=b:65437780, b:68284778, b:69950854, b:65808944
BRANCH=None
TEST=Run DUT with 100Mb and 1000Mb ethernet connection and observe
LED0 is behaving as expected.
Change-Id: Ia805c955711b8ce77eba087a28427a005c456fa1
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22964
Reviewed-by: David Wu <david_wu@quantatw.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
New UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure
clock source number of PCIe root ports. This UPD array is set to clock
source number(0-6) for all the enabled PCIe root ports, invalid(0x1F)
is set for disabled PCIe root ports.
BUG=b:70252901
BRANCH=None
TEST= Perform the following
1. Build and boot soraka
2. Verify PCIe devices list using lspci command
3. Perform Basic Assurance Test(BAT) on soraka
Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
firmware test team is requesting that default gbb flags set to 0x39
rather than 0x239 so that it's consistent with the default gbb flags
of other platforms.
BUG=b:70392534
BRANCH=None
TEST=emerge-fizz coreboot chromeos-bootimage
gbb_utility --get --flags image-fizz.bin and make sure
that it returns 0x39 instead of 0x239
Change-Id: Ib73e4619b13f6b7c2d01598c926fbbd7d7eb9bef
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22962
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is a potential IMVP8 issue for KBL that affects Intersil VRs
Fizz is using one of the affected parts. The fix is to use an updated
microcode and also send a mailbox box command from FSP.
BUG=b:65499724
BRANCH=None
TEST=Build and boot Fizz
Change-Id: Iebfda02df88ea0d2aaf79e8449b95c0eb2165c6b
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/22763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It seems that RAM code 0 has been strapped with an incorrect resistor on
Kevin. The resulting voltage divide still puts it well within the ADC
value bucket reserved for that slot, but a little closer to the edge
than necessary. While this doesn't seem to cause any immediate problems
on its own, it still doesn't hurt to fix it (if only for the
documentation value).
On other boards (at least on my Scarlet) the strapping seems to be
correct.
Change-Id: Ic5199834fbeaf734e725ff45b04f45eefe149855
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22891
Reviewed-by: David Schneider <dnschneid@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This patch shifts some comments around to make it easier to replace
values in the ADC strapping bucket table with compile-time conditionals.
Change-Id: Ic51917d3961a51d4e725ff824fb59aeefe149855
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
As per the latest schematics, this change configures GPP_B0 for WLAN
wake and uses corresponding gpe bit in ACPI node for WLAN. This hasn't
been tested yet.
BUG=b:70775494
Change-Id: I5198b8083a87d00f890b45986e5e3f62b81686c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22928
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Similar to other KBL projects, this change enables AER and LTR for
root port 1 on poppy.
BUG=b:65570878
Change-Id: Iadad3d2fc46cbba575a776071305925c529a6760
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change really fixes the SataMode to select non-RAID mode and
enables SATA which was incorrectly disabled in a71276b
(mb/google/poppy/variants/nami: Fix SataMode configuration in
devicetree).
BUG=b:70160119
Change-Id: Ied6adabdc1d2458972bde628616a198cd41f9f3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPP_F3 is not connected on poppy or any of its variants. This change
configures GPP_F3 as NC on poppy and all the variants.
BUG=b:70160119
Change-Id: I303276ab9546d56c846755fa3a6142978f6b8c92
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Nami uses DEVSLP1 and not DEVSLP0. This change updates the GPIO
configuration for DEVSLP to match the latest version of schematics.
BUG=b:70160119
Change-Id: Ifa181322011a4b8947ecd0fa44dcf790b0d8f657
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch enables customized NIC leds as below:
Green Orange (Amber)
100M off blinking
1000M on blinking
BUG=b:69950854
TEST=Boot on fizz dut and observe the LEDs are behaving as expected.
Perform suspend/resume test and the LEDs are still working as expected.
Change-Id: Ic70587a0cd688e74b5e1ce532c5da954c80cf841
Signed-off-by: David Wu <david_wu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Similar to Fizz, SataMode on nami should be set to AHCI. This change
fixes the configuration error done in 903472c
(mb/google/poppy/variants/nami: Add support for nami board).
BUG=b:70160119
Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22845
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Melfas kernel TS driver (melfas_mip4.c) will look up "ce"
GPIO during driver probe in ACPI _DSD.
But FW does not report "ce-gpios" but "enable-gpios" in _DSD.
Kernel will obtain GPIO from _CRS by index "0" without ID.
Melfas driver does not have separate condition
for MIT-410 so driver will set TS IC power off in probe.
FW now may need to add back "reset" pin in order to hack
this condition to let Melfas driver get "useless" GPIO
so TS IC power (VTSP) will be not off during driver probe by itself.
BUG=b:70149336
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/22858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Fizz, the default should be AHCI mode and not RAID
mode. Additionally, there is only one drive connector, so
attaching several drives for a RAID is hard.
BUG=b:70146894
Change-Id: I2a9aa2d6281a916c00ff4659a927f164ba0e0705
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22837
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The overcurrent pins on kahlee weren't mapped correctly, causing
the USB-A port to stop working.
None of the EHCI only ports are used for external connectors, so all
of the overcurrent pins should go to the XHCI connections. This is
also true of the Grunt board.
On Grunt, this also means that we don't need OC3, as it doesn't map
to anything in the XHCI controller, as it's coming from an internal
hub.
BUG=b:70636233
TEST=Build & boot Kahlee, verify USB-A port is working again.
Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22860
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
This change selects Kconfig option to disable native SD card
controller in ACPI tables, since it is not used on nami.
BUG=b:70160119
Change-Id: I6180c2b342c69e6a7c357f10b6297d67ea0211d7
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/22825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add INNOLUX P097PFG panel timing. According to Scalet schematic,
if GPIO3_D4 get low status, it will use INNOLUX P097PFG panel;
if GPIO3_D4 get high status, it will use KD097d04 panel.
Change-Id: I43fa5d859a9a529a84c58a953b37d03953ce648a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22780
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Move AGESA related headers in soc/amd/common to
soc/amd/common/block/include/amdblocks.
BUG=b:69262110
TEST=Build with no error gardenia and kahlee (no code change, headers moved).
Change-Id: I5d3064625ddf8caaf370aabaf93165c6817f1ca0
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change provides implementation of variant_memory_params for
nami. Since it uses DDR4 memory, DQ-DQS mapping table is not
required. Also, Rcomp resistor values are provided based on SDP v/s
DDP memory.
BUG=b:70188937
Change-Id: Ic1d0cfdb7d8b02fa0be0a4c54b20057a4c2fc3ce
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates scl_lcnt value for I2C5 to bring the bus frequency
closer to 400kHz.
BUG=b:65062416
TEST=Verified that I2C5 frequency is between 389-396kHz.
Change-Id: Ibaccab0c797174332633cb75e30d18ff5af76a43
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The following files need to be moved: amd_pci_util.c, amd_pci_util.h and
spi.c. The remaining files are AGESA related and will be part of a separate
issue/commit.
BUG=b:62240201
TEST=Build with no error gardenia and kahlee (no code change, just folder
reorg).
Change-Id: I3f965afa21124d4874d3b7bfe0f404a58b070e23
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Due to a schematic error, our code was written to configure more I2S0
pins than are actually used. We're also pinmuxing the whole bank of pins
over to the I2S controller even though we don't need them all. Restrict
the GPIO initialization and pinmuxing to the pins we really need so the
other ones can be correctly used as SKU ID pins on Scarlet.
Also, move the "audio" IO voltage domain selection to the other such
selections in the bootblock, since that covers two whole banks of GPIOs
and there's no guarantee that they're all used for audio (and thus not
needed before ramstage).
BUG=b:69373077
TEST=Booted Scarlet, confirmed correct SKU ID (7) was detected on rev2.
Change-Id: I9314617e725fe83d254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
These pins need to be pull-ups. I forgot.
BUG=b:69373077
Change-Id: I9314617e01d35898254984529f269d4442e736f1
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Adds Maxim98357a support for Nautilus using the generic driver
in drivers/generic/max98357
BUG=b:68686020
TEST=With entire merged audio should be enabled on max98357
speaker codec.
Change-Id: I958bf7c1395259b3e3fb30332882fd51a48dc0cc
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22458
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Nautilus board uses max989357a speaker codec and 4CH DMIC.
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on Speaker and captures on 4CH DMIC
Change-Id: Ie90af02e0935029f53f9020bd78027b6eb31a187
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the original Chromium source, PcdMemorySpdPtr is only set for
cyan, but none of the other Braswell variants. When upstreamed,
it was left set for all boards as it didn't appear to be problematic.
In wider testing, I came across one reks board for which it caused
FSP memory init to fail, so restricting the parameter to cyan only
as it was originally.
TEST: build/boot google/reks with Micron EDF8132A3MA-JD-F RAM,
observe board now successfully boots where it did not previously.
Change-Id: Iacfbd4bc89fa04717baf85704181d346bca2ed2f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22782
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- The touchscreen interrupt was moved from the GPIO 3, as originally
suggested to GPIO 11. This changes the gevent from 2 to 18.
- Add EMMC reset on GPIO 93.
- Add EMMC bridge PCIe reset on GPIO 40.
- Set device enables to high.
- Remove extra SCI comment from GPIO 130.
- Set individual device PCIe reset pins to high.
- Enable global PCIe reset on GPIO 26.
- Mark LPC_CLK1 as unused.
- Update net names based on latest schematics.
- Set Direction and level/edge correctly for SCIs/SMIs.
- Remove SCI for pen detect.
- Add comments.
BUG=b:70234300, b:69681660, b:69305596
TEST=build grunt
Change-Id: Ib591e4278ed23d0963ecb19ad9c326498b4c7796
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
- Grunt moved the EMMC chip to port 2, where Kahlee had the SD reader on
PCIe port 1, so move the OemCustomize file into the variant directory.
- Add comments in baseboard version so it's easier to understand.
- Update reset pins, put the definitions in gpio.h
BUG=b:70255003
TEST=Build and boot Kahlee. Build Grunt.
Change-Id: I78ec72e9d6fd52b8ac75e7187bd01ee7ddc3ba2a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch makes coreboot set the max current and voltage for barrel jack
adapters.
BUG=b:64442692
BRANCH=none
TEST=Boot Fizz. Use chgsup console command to verify the max current and
voltage are set as expected.
Change-Id: Ifebee09096e0935cc7d3e53920a251b0496d3c55
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/22623
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allow overriding specific GPIOs by SKU ID. Override two GPIO settings
for nasher to save the power consumption when the system in S0ix.
Change as below:
AVS_DMIC_CLK_A1: IGNORE -> Tx1RXDCRx0.
AVS_DMIC_CLK_B1: IGNORE -> Tx1RXDCRx0.
BUG=b:69025557
BRANCH=master
TEST=compile/verify the power consumption change from ~150mW to ~100mW
on clamshell SKU and from ~200mW to ~100mW for convertible SKU.
Change-Id: I9e0674f206426fddb3947273754774b310106334
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
With the old timing, the hblank time isn't large enough,
it may cause display artifacts. So fix it.
BUG=b:70160653
TEST=panel work on Scarlet rev2 board
Change-Id: Ib061f5e215611d20f59e3f24cfe3c7fbc507ebed
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
In preparation to deleting early_setup,c, change early_ec_init() to use new
southbridge.c function sb_set_wideio_range and remove <#ifdef __PRE_RAM__>.
BUG=b:64033893
TEST=Build, boot and check serial output, search for "Covered by wideIO xx",
which should match earlier message "Range assigned to wide IO xx" generated
within modified early_ec_init().
Change-Id: Iaea17f4f636aab6bd8b05b1b3bed53a677164e74
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change updates memory SPD handling code in baseboard poppy to
allow variants to define either LPDDR3 or DDR4 memory types. In
addition to that, it also updates the function to print SPD info
considering offsets that might be different across the two memory
types.
BUG=b:70188937
Change-Id: Iefad01719c62264fb0d7e987904e77647d6026c2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Until now, nautilus was using the DQ-DQS mappings provided by the
baseboard. However, based on schematics, these values are not
correct. This change adds DQ-DQS mapping tables for nautilus.
BUG=b:70188533
Change-Id: Ife6ba19b8fe8873ab8cca977ca8f34a4d86e8e6e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22706
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: shkim <sh_.kim@samsung.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch switches the board_id and ram_code helper framework to use
weak functions rather than Kconfigs to determine whether the board
supplies these IDs. This cuts down on the amount of boilerplate Kconfigs
many boards have to set and also gives them more flexibility, such as
being able to determine at runtime whether a given ID is present.
Change-Id: I97d6d1103ebb2a2a7cf1ecfc45709c7e8c1a5cb0
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22695
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Merge the different coreboot table strapping ID structures into one
because they're really just all the same, and I want to add more. Make
the signature of the board_id() function return a uint32_t because
that's also what goes in the coreboot table. Add a printk to the generic
code handling strapping IDs in ramstage so that not every individual
mainboard implementation needs its own print. (In turn, remove one such
print from fsp1_1 code because it's in the way of my next patch.)
Change-Id: Ib9563edf07b623a586a4dc168fe357564c5e68b5
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The BOARD_ID_MANUAL and BOARD_ID_STRING options were introduced for the
Urara board which is now long dead, and have never been used anywhere
else. They were trying to do something that we usually handle with a
separate SKU ID these days, whereas BOARD_ID is supposed to be reserved
for different revisions of the same board/SKU. Get rid of it to make
further refactoring of other options easier.
Also shove some stuff back into the Urara mainboard that should've never
crept into generic headers.
Change-Id: I4e7018066eadb38bced96d8eca2ffd4f0dd17110
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22694
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Variants nautilus and soraka currently provide the exact same
definition for variant_cros_gpios as provided by the baseboard. This
change removes the function defintions from variants so that the weak
definition in baseboard can be used.
Change-Id: Ic88623f34039792f0f9fb46842b24e4f1290981b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22705
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a new config option VARIANT_HAS_CAMERA_ACPI to allow
variants to define ACPI tables for camera support. It also prevents
boards that do not need this from unnecessarily providing dummy files
for camera ACPI support.
Change-Id: I91f8e407e0f021071eeadbde8c2695e2a6d69e06
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Change the prefix for TPM options from POPPY_USE_* to
VARIANT_HAS_*. This makes it clear that these are variant specific
options.
Change-Id: I6fd120a34a5b0c1f018164d5c2b60548da1d0f61
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to allow variants to select different Kconfig options, this
change adds VARIANT_SPECIFIC_OPTIONS_${VARIANT_NAME} which can be
selected by each variant in Kcnonfig.name.
Change-Id: I15db2fdac5c9e55f9698c8a0c083d6467afae245
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change removes the dynamic disabling of TPM based on config
options. Poppy and its variants will have only one type of TPM
supported and so there is no need to update it dynamically.
Change-Id: Ie82825fcf7092e845583edaac9ba0d3fc9d1dd80
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22704
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the USB over current pins for the Grunt baseboard and
Kahlee mainboard. Removes the ACPI ASL OC code, which is not
used on Stoney Ridge SOC.
BUG=b:69229635
TEST=Build and boot Kahlee. Not tested with OC test fixture.
Change-Id: I5a9b3409d9c91b89fd02f8eecf9e04c435f14342
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22679
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There is some confusion with old RAMID table, make it clear,
and let's no longer tangle it in future.
Change-Id: I44215b4a6668074575a5df691ac1ff8fa3d15492
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This patch enables WOL feature.
BUG=b:69290148
BRANCH=None
TEST=powerd_dbus_suspend && sudo etherwake -i eth0 $MAC to make sure
the system could be woken up by WOL packet.
Change-Id: I1178a776db2cdb448fe6650d49ae6c0281ac1128
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22606
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Lava numbers are in.
BUG=b:69990330
BRANCH=none
TEST=verified that USB signal is within spec
Change-Id: I7416ec8d058271700ebe43f8d92af61c6c0d6b42
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/22661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These files aren't needed for the overcurrent functionality.
BUG=b:69305596, b:69229635
TEST=Build Grunt & Kahlee. Overcurrent wasn't yet enabled so no other
testing was needed.
Change-Id: I8dcd50a249e387ccf1142949b359cee09942460a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Update the variable ${CONFIG_VARIANT_DIR} to use parens instead. Either
is valid, but since we use parentheses everywhere else, it's better to
be consistent.
BUG=b:69691210
TEST=Build grunt & kahlee
Change-Id: Ieffabaae5516a893f1dc1f7195a17c4cdeae8853
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22656
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This change disables DPTF until the support is properly added in
dptf.asl
Change-Id: I68f2442e00718a4edbb34661d31d3a415d41c29f
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
PMC logic shuts down the thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold in case Dynamic Thermal Shutdown in
S0ix is enabled.
BUG=b:69110373
BRANCH=none
TEST=Ensure Thermal Device(B0: D20: F2) TSPM offset 0x1c[LTT (8:0)]
value is 0xFA.
Change-Id: I6246300a4376a0194950d4de277af040b10b6c1f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/22628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add synaptics touchscreen in the device tree so that the correct ACPI
device is created.
BUG=b:66462881
BRANCH=master
TEST=compiled/verify the touchscreen works
Change-Id: I6e89a5db0e9f8ae777eed661f3bf89d653a937e6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the mainboard_spd_read function in romstage and call the variants
function. Grunt is the baseboard and has soldered down memory, so add
it for the default weak SPD functions and build the SPDs in cbfs.
Kahlee overrides the weak SPD function and falls back to the soc
I2C SPD functions.
BUG=b:67845441
TEST=Build and boot Kahlee.
Change-Id: I789002bfadc1a2b24f9046708986d29c0e2daf33
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
The GPIOs used in board_id are meant to indicate the memory
configuration. Rename board_id to memory_skus.
Report the board_id received from the EC.
BUG=b:69649438
Change-Id: I84bacead3daf829c97f595c4c11a243953243c29
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22561
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This change disables camera devices until camera support is properly
added for nautilus.
Change-Id: I7de37cbf9c32fa063f55a2e54986e33b66acfa3b
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change adds infrastructure to allow variants to define their own
camera.asl file.
- Poppy and soraka use the one provided by baseboard.
- Dummy file is added for nautilus since it does not have camera
support enabled yet.
TEST=Verified that DSDT table remains the same with and without this
change.
Change-Id: I0f0b489e74739aa4708283d58d8b7626b77a89a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: shkim <sh_.kim@samsung.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Support kd097d04 dual mipi panel on Scarlet.
Change-Id: Ie8bc0cbb79840f1924a8cc111f2511292203731f
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
it uses backlight enable pin as backlight gpio currently,
correct it and define the right backlight gpio.
Change-Id: I7c5abfd5bbbae015b899f3edc8892ea32bf82463
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Refactor the mipi driver, so we can support dual mipi panel.
And pass the panel data from mainboard.c, that we can
support different panel with different board.
Change-Id: Id1286c0ccbe50c89514c8daee66439116d3f1ca4
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/22471
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add "speed_config" for each I2C port configuration to set speed to
400KHz.
BRANCH=master
BUG=none
TEST=compiled/verified
Change-Id: Icb48733b87cefc92577547b1eab661a8cbb12be6
Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/22589
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On shutdown, Soraka enters Deep S5 and not S5 state. Setting
pad reset config of a gpio to RSMRST will not preserve
the gpio config across deepSx and the gpio should be configured again.
The WLAN_PE_RST signal should be brought up early in the bootflow
for giving the device enough time to initialized before PCIE init in FSP-S.
Hence, the gpio WLAN_PE_RST (GPP_B8) pad configuration is done in
early pad configuration in bootblock also.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S5, S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I5c7a4a3871a3bff69c1136379c78a8368c6258a6
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
- Remove SI_ALL section. This is no longer needed as the PSP dirctory
is placed into the RO coreboot section.
- Add 1MB Legacy section.
- Add Memory cache section. These sections are called "MRC", which is
an Intel term, but AMD platforms will use the same regions for saving
the same sort of data.
BUG=b:65497959, b:67035984
TEST=Build & boot kahlee
Change-Id: I5e41a0aa6bd4b29b8014c6559126a29cd7ed45d8
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Follow the schematic and Doc 573387 to correct the rcomp and
rcomp target settings for fizz
TEST= boot ok and the system can enter and resume from S3.
Change-Id: Iffa90461509cfadaca20e335a6655e549e79e749
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We are disabling tpm over i2c, so the configs are not needed
anymore.
BUG=b:65056998
BRANCH=None
TEST=emerge fizz and make sure can still boot up.
Change-Id: Id88f32fa952801749544534442fc15d85fc1a892
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As cr50 has now switched to using SPI, no need to enable the i2c1
anymore. Additionally, disabled unused I2C devices -- I2C0, I2C2 and
I2C3.
BUG=b:69374421
BRANCH=None
TEST=test on fizz celeron. Make sure /dev/tpm0 created on (many)
reboots. cat /proc/interrupts. Make sure # interrupts for 16
after booting is reasonable (not > 10k) and idma64.0,
i2c_designware.0 are not listed with that interrupt line anymore.
Should look something like this:
16: 1174 0 IO-APIC 16-fasteoi i801_smbus, snd_soc_skl, AudioDSP
Change-Id: Iac3e31264a937a1d7ed6bd41632e7e065317781b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some Google boards are missing this selection, leading them to being
incorrectly identified as type 'Desktop' in SMBIOS type 3 table.
Correct this by adding 'select SYSTEM_TYPE_LAPTOP' to the boards'
Kconfigs.
TEST: boot Linux and check correct chassis type listed via dmidecode
Change-Id: Ib1145e314812a3f300cfd1a435a687aa0862158a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
These typos were found through manual review and grep.
Change-Id: Ia5a9acae4fbe2627017743106d9326a14c99a225
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Currently, mosys just returns "fizz" as model/chassis values.
Returning proper OEM IDs so that mosys can return the proper
variant.
BUG=b:67732053
BRANCH=None
TEST=mosys platform model; mosys platform chassis;
Make sure returns the right variant string and not fizz.
Change-Id: I42e293e833b0f7c9870dc275561ad13256836e60
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
ChromeEC is getting ready to bump up the hostevents and wake masks to
64-bits. The current commands to program hostevents/wake masks will
still operate on 32-bits only. A new EC host command will be added to
handle 64-bit hostevents/wake masks. In order to prevent individual
callers in coreboot from worrying about 32-bit/64-bit, the same API
provided by google/chromeec will be updated to accept 64-bit
parameters and return 64-bit values. Internally, host command handlers
will take care of masking these parameters/return values to
appropriate 32-bit/64-bit values.
BUG=b:69329196
Change-Id: If59f3f2b1a2aa5ce95883df3e72efc4a32de1190
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Rainier is a scarlet-derived board but uses eDP as opposed to MIPI. Using
GRU_BASEBOARD_SCARLET is enough, except for display related logic. In
those cases, use board specific logic instead of baseboard.
Change-Id: I596f7ca6bc26312ecaeb261c96cebd46974c2cdf
Signed-off-by: Ege Mihmanli <egemih@google.com>
Reviewed-on: https://review.coreboot.org/22542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Request from commit 519680948b (move carrizo_fch.asl code to soc), merge
several includes into a single file in soc directory.
Rename soc_fch.asl to sb_fch.asl. Rename fch.asl to sb_pci0_fch.asl.
Then copy the required section from dsdt.asl into a new soc.asl.
Affected boards: amd/gardenia and google/kahlee.
BUG=b:69368752
Change-Id: I83d850cf9457f7c2c787336823d993ae2e9d28ce
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22541
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Commit c09c2a4 [mb/google: Add Chromebook marketing names] added
marketing names for many ChromeOS devices; add some that were left out,
correct some errors, and try to format model names/numbers consistently
(or as consistently as the manufacturers allow).
Change-Id: Ia13858e2e6ba7d7e025f25fad33e6338250498e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22520
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Enable separate MRC cache for recovery mode. This requires change in
flash layout to accomodate another region for RECOVERY_MRC_CACHE.
BUG=b:69473883
TEST=Verified following scenarios:
1. Boot into recovery does not destroy normal mode MRC cache.
2. Once recovery MRC cache is populated, all future boots in recovery
mode re-use data from the cache.
3. Forcing recovery mode to retrain memory causes normal mode to retrain
memory as well.
Change-Id: Icdfac3698507d89d98a51cfc3d756a56d2a2d648
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is merit in having new boards use the pinouts and controls
in scarlet. This adds a config so new scarlet-derived boards can
easily use scarlet structure without going through every file
and adding new logic.
TEST=Run "emerge-scarlet coreboot"
Signed-off-by: egemih@chromium.org
Change-Id: I5808f93f4563033ce93050e1eedb6eac2b52c3b3
Reviewed-on: https://review.coreboot.org/22517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Remove ugly camel case in the soc/amd/common and Stoney Ridge
SPD files and functions. Update the related mainboards.
Also, remove a unreferenced function prototype, smbus_readSpd().
Change-Id: I51045b6621f0708d61a570acbdcb4e6522baa1ea
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The mainboard directory is included through the PI makefile - most
mainboard directories aren't in the include path at all. Move the
ec.h file into the baseboard/variant directory that is already in
the include path.
BUG=b:69220826
TEST=Build
Change-Id: I89d361b700c66ba576de724927574fdab9461fc6
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
All AGESA headers should be included only through agesawrapper.h
I missed this file in the Kahlee cleanup.
BUG=b:66818758
TEST=Build gardenia; Build & boot kahlee
Change-Id: Id9b303cb3cee8088fb5cca5257566c033d28c692
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This fixes some issues with the initial implementation that was copied
from reef.
- The board ID value shouldn't be size_t - it's not a size.
- Kahlee doesn't even need the memory.c file - it uses an SoDIMM.
BUG=b:68293392
TEST=build stoney platforms, boot kahleebo
Change-Id: Ife5660d36912e887edfd0365a9f16c5a172c9c86
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22515
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's sometimes hard to find the code name of a Chromebook. Add the
marketing names to Kconfig, since they are easily available.
Information (mostly) taken from:
https://www.chromium.org/chromium-os/developer-information-for-chrome-os-devices
Unknown boards (unreleased, etc.):
* Fizz
* Foster
* Nasher, Coral
* Purin
* Rotor
* Rowan
* Scarlet, Nefario
* Soraka
* Urara
* Veyron_Rialto
Baseboards:
* Glados
* Gru
* Jecht
* Kahlee
* Nyan
* Oak
* Poppy
* Rambi
* Zoombini
White label boards:
* Enguarde
* Heli
* Relm, Wizpig
TODO: How does this interact with the board_status code?
Change-Id: I20a36e23bd3eea8c526a0b3b53cd676cebf9cd86
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/22404
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Set the EC SCI reporting mask to include the power plug reporting.
BUG=b:65637324
TEST=Check power_supply_info on AC/DC.
Change-Id: I58814fc495081ffe8e47162da0fa4fbeba49d67b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Code within carrizo_fch should be SOC specific instead of board specific.
BUG=b:64034810
Change-Id: I5de2020411794bfcd3730789f62af9c9834a018b
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/22455
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This feature was enabled at the kernel level, but that is triggering an
issue where FSP expects it to be disabled so it forces a cold reboot on
every warm reboot. Since we want this enabled anyway just set it this
way in the BIOS so it matches what the kernel expects.
BUG=b:68666100
TEST=pass firmware_FWtries on Eve with R63 OS image
Change-Id: I294e34d25406365d591da06ce4c931b710cfbbaa
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: I964d3d30392d130e808f37a661f2c89ec926cf58
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/749733
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tune PCH I2C4 hold times to ensure the frequency is always <400KHz.
BUG=b:67029862
TEST=boot on eve and measure I2C4 at Tp262 to be 385KHz
Change-Id: Ie93c5c40bc74069b285f6c3ee311f1bd7cefcaf1
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Iceabc806a17b9e6a144a4f6288c6cca790d03950
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/739841
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/22448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
AER and LTR must be enabled individually on ports that need it,
in this case it should be enabled for WiFi and NVMe.
BUG=b:65457528
TEST=Wifi team verified that the performance is better with these changes.
Change-Id: I0d688fe07a1f3117c1ca617c2ce78e0d024a3510
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ib059517fa782ccc18ba5ef1f76058a1898b7bf7a
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/671211
Original-Reviewed-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use the rt5663 driver and provide values for the offsets which are
needed for providing manual values to compensate the DC offset for
L and R channels between headphone and headset.
BUG=b:62712227
TEST=build and boot on eve and ensure rt5663 is functional.
Change-Id: I88113616e4b7c79cff840168b7c54ae754dfa75f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ica4090636c1ff29f0298114e62c9cc6fe167a425
Original-Signed-off-by: Duncan Laurie <dlaurie@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/611606
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-by: Hsinyu Chao <hychao@chromium.org>
Reviewed-on: https://review.coreboot.org/22446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change the touchscreen power control back to coreboot instead of
under the ACPI _ON/_OFF methods, and switch the TOUCHSCREEN_STOP_L
pin back to an output.
This reverts previous changes to touchscreen GPIOs that were made
to get back to a known good/working state. Having ACPI control these
pins was resulting in a small percentage of touchscreen not being
discovered at boot. This platform is not intending to use S0ix so
the ACPI control is not needed.
BUG=b:63718744
TEST=manual testing on Eve devices.
Change-Id: I3fd64a435a053da1558ef736fe7baceee3c8f3a0
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Change-Id: Ia1e2ae7ca2a8b668c60fbda2aa50373e580646b2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/572692
Original-Reviewed-by: Duncan Laurie <dlaurie@google.com>
Original-Commit-Queue: Duncan Laurie <dlaurie@google.com>
Original-Tested-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/22445
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All Stoney AGESA headers should be included only through agesawrapper.h
BUG=b:66818758
TEST=Build and boot tested
Change-Id: I642f5caf8a37ae4042c32fec3a92e0995193cb7a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Instead of getting the address of the GPIO function with an extern,
add a getter function and make the GPIO arrays static.
TEST=Build Grunt; Build & boot Kahlee
BUG=b:69164070
Change-Id: I3defcb66696459b915d7d4f43234d5c08ab7d417
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
mainboard.h only had a single function definition. Move it into
baseboard/variants.h and get rid of the file.
TEST=Build grunt/kahlee
BUG=b:69164070
Change-Id: I6b7d50d5c949733d77c42b4daf56ed1f97ed6954
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update common files and add files for grunt to the variant directory.
BUG=b:68293392
TEST=Build only
Change-Id: I7b80e470058872d6613e66e64c8dd1494942e9b9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22186
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Several SPD hex files for chell were missing from upstream coreboot
(as compared to the Chromium tree/branch), which resulted in the
incorrect type and amount of RAM being reported on chell boards
with > 4GB RAM. Add these missing files and their Makefile entries.
TEST: boot google/chell m7/16GB config and observe correct RAM
type and amount reported via dmidecode and cbmem console log.
Change-Id: I37d708c96e754b438e40fc413420aa64bf234c29
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22402
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set the UMA memory size to 128 MiB. This value was empirically tested
by AMD as the lowest value one could use.
BUG=b:64927639
TEST=default, and 64, 128, 256, 384MB non-legacy configurations.
Change-Id: I2bc808d8b402c3eb16a1a5962f3fa9d6b224cf52
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21335
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a #define for MB_DIMM_SLOTS and verify it doesn't exceed the max
supported for the device. AGESA's DRAM procedures follow the BKDG and
may vary depending on the number of slots on the motherboard. DIMM
numbering and ordering is also affected by this value.
Replace hardcoded integers with defined values for DIMM slots and
number of channels.
Change-Id: I4f7336da80b4e3d7f351502a63de0652e9ff5395
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/21853
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee needs to keep its DRAM contents after a reset. Move this
override out of the OemCustomize.c file to a devicetree register
setting.
Change-Id: I3196cb8b94bec64e8ce59e4285cf8d97f442bd3d
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21858
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Astronaunt, after the system enters the S5 power state, there is a
10-second timeout before the system transitions the power state from S5
to G3. The EN_PP3300_DX_LTE_SOC signal, which is controlled by GPIO_78
on the APL platform, remains on during that period. If the system is
powered back on before going to G3, the built-in modem won't go through
a power cycle as EN_PP3300_DX_LTE_SOC is never de-asserted.
Keeping the modem, and indirectly the SIM, powered during a quick system
power cycle may sometimes be undesirable. For instance, we would like a
SIM with PIN lock enabled to require unlocking each time the system is
powered on. After the SIM receives a PIN, it may remain unlocked until
its next power cycle.
Also, it is often desirable to power cycle the modem when the system
goes through a power cycle. For instance, a user may power cycle the
system to recover a wedged modem.
BUG=b:68365029
TEST=Tested the following on an Astronaunt device:
1. Verify that the modem is powered on after the system boots from cold.
2. Suspend the system to S0ix. Verify that the modem remains powered on
when the system is in S0ix. After the system goes back to S0, verify
that the SIM with PIN lock enabled doesn't request unlocking, and the
modem can quickly reconnect to a network.
3. Configure the system to suspend to S3 instead of S0ix, and then
repeat (2).
4. Perform a quick system power cycle, verify that the modem is powered
cycle and the SIM with PIN lock enabled requests unlocking.
Change-Id: Ie60776d5d9ebc6a69aa9e360bd882f455265dfa2
Signed-off-by: Ben Chan <benchan@chromium.org>
Reviewed-on: https://review.coreboot.org/22415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch enables customized NIC leds as follows:
Green Orange (Amber)
100M off blinking
1000M on blinking
BUG=b:65437780, b:68284778
TEST=Make sure the registers are programmed as expected and observe the
LEDs are behaving as expected. Perform suspend/resume test and the
LEDs are still working as expected.
Change-Id: I9bb1367a4c742c2755d620e14ee6dfe70ee7f34b
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/22293
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This compares to the acpi directory in other variants.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: I05d402995b280d6f020bc2575063dbffefa30670
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Even though this GPIO isn't used for Kahlee, it needs to be defined
so that the weak version of the variant_board_id() function can
compile.
BUG=b:68293392
TEST=Build and boot kahlee
Change-Id: Ia8daf70fbafe02ec37c6b5eb8421cdb11de3be8b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that recovery button has been enabled through cr50,
we can add VBOOT_PHYSICAL_REC_SWITCH config and treat
the recovery button like on any other chromebox.
BUG=b:37751915, b:63893483
BRANCH=None
TEST=With DUT in normal mode, boot into recovery, press ctrl+d
followed by pressing the recovery button. Should successfully
boot into dev mode.
CQ-DEPEND=CL:737477
Change-Id: I72fb42508083295e317dd06900796dc0cda753f6
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/22368
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Nautilus board uses Dialog da7219 headset codec,
Select the appropriate NHLT blob to be packaged in CBFS.
Also generate the required ACPI NHLT table for codec
and the supported topology in nautilus.
Removes unwanted DMIC blob pick for nautilus
BUG=b:68686020
TEST=With the required driver support in kernel verify that
the Audio plays on headset and recording on headset mic
Change-Id: I104889f54da1de38854bcb72aabbc88b739d6c09
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Reviewed-on: https://review.coreboot.org/22325
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On older Grus, GPIO0_A2 was an audio voltage rail enable line. On
Scarlet, we instead moved the audio codec enable (previously on
GPIO1_A2) there. Unfortunately the code still had some hardcoded
leftovers that were overlooked in the initial port and make our speakers
smell weird.
This patch fixes the incorrect GPIO settings and adds the speaker enable
pin to the GPIOs passed through the coreboot table, so that depthcharge
doesn't have to keep its own definition of the pin which may go out of
sync.
Change-Id: I1ac70ee47ebf04b8b92ff17a46cbf5d839421a61
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/22323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
Reviewed-by: Alexandru Stan <amstan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Current VBT setting for T8 is only 1ms which is under Innolux
N116BCA-EA1 panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
CQ-DEPEND=CL:*496012
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
Change-Id: I580567decfccd78366c37181255015ac2cd76493
Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com>
Reviewed-on: https://review.coreboot.org/22306
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quantatw.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
From what I can tell FILECODE isn't used at all in this file.
Remove it.
Change-Id: Ie88140e63a4917f470f42119c1fe4e8c7d2584ca
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22317
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
In skylake based platforms, setting GPIO pad reset config
to DEEP will reset the gpio configuration across warm reset,
set it to RSMRST to preserve the configuration across warm resets.
Also, moving the configuration from early to late as appropriate.
BUG=b:64386481
BRANCH=none
TEST= WiFi functionality across S3, DeepS3, S0ix and warm/cold reboot.
Change-Id: I38940b7c7d71e60bf0e51d6978a00be148ad61bc
Signed-off-by: Divya Chellap <divya.chellappa@intel.com>
Reviewed-on: https://review.coreboot.org/22174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adapted from Chromium commit 12ad5b5: Reks : override USB2 Phy settings...
Base on Intel recommendation, override following
settings for USB2 port 1/2/3 on BSW D-stepping SOC.
1. Set USB[1] register for right side to 7321
2. Set USB[2] register for left side to 7021
3. Set USB[3] register for CCD to 7021
Original-Change-Id: I04240a010e875f29c47f4fea83ff918f180b0273
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iabd6312576e9897315c4e4dbf19341380d9d1414
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit 6ee6f3d: Reks: To set the RX ODT limit...
Override RX ODT and DRAM geometry for Micron part MT52L256M32D1PF-107.
Use get_ramid() to determine if override is necessary.
Original-Change-Id: I41f3aba030a00152e1217533ef953338ac396605
Original-Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Original-Reviewed-by: Kane Chen <kane.chen@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Keith Tzeng <keith.tzeng@quantatw.com>
Change-Id: Iea8c3c67e5afb21285dc15ad665474ad5f192423
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/22268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
ASL+ Optimizing Compiler/Disassembler version 20170831 shows the remark
below.
```
dsdt.aml 87: Method (_CRS, 0x0, NotSerialized)
Remark 2120 - ^ Control Method should be made Serialized \
(due to creation of named objects within)
```
So, serialize the method.
Fixes: commit 4a51ea8470 (google/kahlee: Add ASL for Elan touchpad)
Change-Id: I664f493318cbfd80d91565c0d29ec918278c4906
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/21901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Move files that are particularly specific to the mainboard into the
variant directory. Files that only have small areas of mainboard
specific pieces use #if to separate between the boards.
Add memory.c to split out the variant board id into a weak function.
Add baseboard/gpio.h to satisfy the build - this will be updated in the
next commit.
BUG=b:68293392
Change-Id: I7c1beb45f571f2547f3b5b0d7ec78923d0cec761
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current VBT setting for T8 is only 1ms which is under Innolux N116BCA-EA1
panel's spec.
Modify T8 to 100ms.
(Innolux's panel's spec requires T8 needs to be greater than 80ms)
BUG=b:67756548
BRANCH=master
TEST=emerge-coral depthcharge coreboot chromeos-bootimage
Run on DUT and check panel sequence meets spec.
CQ-DEPEND=CL:*493633
Change-Id: I7934b0f6d40b15796c55d360995c5eb0c5049222
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/22294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is to enable SPD word access to reduce boot time. It can save
80 ~ 100 ms per DIMM.
BUG=b:67021853
BRANCH=None
TEST=system boot, and boot time is reduced
Change-Id: Ic527a539ed634e15b939b18fff4b4e08ebb3ec57
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/22267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
For Raydium, export reset GPIO as well as PowerResource.
Let EN_PP3300_TOUCHSCREEN signal will goes to low at S3 mode.
BUG=b:67879912
BRANCH=coral
TEST=emerge-coral coreboot
Change-Id: Ibf501b40ecfc957fd8be7ebffd2357dfa0e07757
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/22252
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to have these separated.
BUG=b:64932381
Test=Build & Boot
Change-Id: I22898d3bf95d5e9a8fc2643bfccae1e2f5b29e44
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit just moves the vboot sources into
the security directory and fixes kconfig/makefile paths.
Fix vboot2 headers
Change-Id: Icd87f95640186f7a625242a3937e1dd13347eb60
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/22074
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the missing device and ensure it shows up in the devicetree prior
to PCI enumeration.
Change-Id: Ia2c4ba1200422b36c533e86065a4fcd10c4b2722
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22055
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add GPE configuration table.
Remove GPE3 from the power button ASL and set the EC to GPE3(AGPIO22).
Set the EC and PCIE/WLAN SCI GPIO signals.
Set GPE ASL methods for:
PCIE/WLAN 8h
EHCI 18h
XHCI 1fh
Note EC GPE3 methods are in the EC ASL.
BUG=b:63268311
BRANCH=none
TEST=Test lidswitch powers the device on and off at the login screen.
Change-Id: I27c880ee84b6797d999d4d5951602b654ede948e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22096
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set PL2 based on either 90% of usb c charger's max power or sku id if
using a barrel jack.
BUG=b:37473486
BRANCH=None
TEST=output debug info for different skus and make sure
PL2 set correctly.
Change-Id: I487fce4a5d0825a26488e71dee02400dbebbffb3
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Stoney Ridge has one EHCI controller and one XHCI controller.
Also, update the Kahlee and Gardenia mainboards ASL to match.
Change-Id: I5749ca0640796732e74e551147f8c4446317b77e
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/22097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In the original AGESA headers, these tables are not defined as const.
Cast them to void * so that they'll work with either version of the
headers.
BUG=b:64766233
TEST=Build in cros tree and upstream coreboot, with old headers
and updated headers.
Change-Id: I75387b57caf5a3c6c25655120aafd942254b5c73
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22059
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There was no reason to have the AGESA callout tables in each mainboard,
so move them to soc/amd/common.
Move chip specific functions into the stoneyridge directory:
- agesa_fch_initreset
- agesa_fch_initenv
- agesa_ReadSpd
Combine agesa_ReadSpd and agesa_ReadSpd_from_cbfs, and figure out which
to use.
Soldered-down memory still needs to be supported in a future commit, as
stoney supports both DDR3 & DDR4. A bug has been filed for support for
the upcoming Grunt platform.
BUG=b:67209686
TEST=Build and boot on Kahlee
Change-Id: Ife9bd90be9eb0ce0a7ce41d75cfef979b11e640b
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch skips SPD data reading when system resumes from S3 since
MRC cahce is adopted and validated in fsp_memory_init.
BUG=b:67021596
TEST=Run suspend/resume on Fizz and make sure the systems are
working well when system resumes from S3. Checked dmidecode
information and SMBIOS type 17 data is the same with cold
boot.
Change-Id: I1692fca8456290d1471973b746537b5fec504e03
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Remove IRQ and MP tables. Modern OS use ACPI instead of legacy tables.
Use Kconfig for reversable configuration if using old OS.
BUG=b:62241143
Change-Id: I5fc833c8af47b5f6fad757e129250e6202810dbb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/21963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
For Kahlee, the AMD firmware directory should be in the 1MB location
so that it's in the RO cbfs section.
BUG=b:65484600
TEST=Build & boot
Change-Id: I650d8bc0bfa773f5fb5dc11167fe3db3b9550b68
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/22003
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add support for google/wizpig (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new wizpig variant
- Add new shared SPD file to the baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: I424d2256eb79ca3ea0a62620954c57c09ae0c0b2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/ultima (Lenovo Yoga 11e G3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new ultima variant
Sourced from Chromium branch firmware-ultima-7287.131.B,
commit 3ef9e73: Revert "Revert "soc/intel/braswell: Put SERIRQ in quiet mode""
Change-Id: Ib38b110f50f4d6ae6eda40e787cd3c1c8dd5ece7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/setzer (HP Chromebook 11 G5) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new setzer variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ibcebebeb469c4bd6139b8ce83a1ca5ca560c2252
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Support the required AGESA_DO_RESET in bootblock.
BUG=b:64719937
BRANCH=none
TEST=Check AGESA reset request in booblock does a reset in the serial
console or ec console.
Change-Id: I462a1f81b8d209c15417946a314f2bfb9b226e4d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
We are changing the bootstraps in the EVTs so that the SOC
communicates with cr50 over SPI instead of cr50. SPI is more reliable
than I2C. Thus, disabling cr50 over I2C and enabling cr50 over SPI.
BUG=b:65056998, b:62456589
BRANCH=None
TEST=make sure that we can boot into kernel
run cold_reset and warm_reset and make sure both
boot successfully.
CQ-DEPEND=CL:714237
Change-Id: I85b9a61f0305e3c7ccada79d7702234a285a6d2a
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/21970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add support for google/relm (white label Chromebook) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new relm variant
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: Ife10f5f75435f356cd896588dd6f425e54f3c88e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Add support for google/kefka (Dell Chromebook 11 3180) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new kefka variant
- Add new shared SPD file to baseboard
Sourced from Chromium branch firmware-strago-7287.B,
commit ef41a46: Kefka: Modify USB2 settings to match the eye diagram
Change-Id: Ic6c8c5e5b6029bb99039c64b0182214e93552fa2
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
Fix typos in determining single/dual channel in cyan variants
which resulted in all boards being reported as 4GB/dual channel
in the cbmem console log.
These typos were found and fixed in yet-to-be-merged variants;
this patch applies the same fixes to already-merged boards.
Change-Id: I615463668e77bd817d5270f0f04d4d01f74e3b47
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21917
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Depthcharge was complaining that the GPIO for this flag wasn't set.
The GPIO also needs to be an input, not an output.
BUG=b:67614692
TEST=Depthcharge no longer complains that there is no GPIO set for flag5.
The system boots again.
Change-Id: Ib854e97b0a3aa42a95ceb8a42a9776f0345ff8b1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
This patch is to enable the support of device sleep
for SATA port 1 and disable unused SATA port 0.
BUG=b:65808359
BRANCH=None
TEST=Ran "suspend_stress_test -c 2500" and passed the test.
Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21765
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Shelley Chen <shchen@google.com>
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all
skylake boards to use common gpio driver. Common gpio code
defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for
skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This
resulted in Linux kernel failing to configure all GPIO IRQs since the
ownership was not set correctly. (Observed error in dmesg: "genirq:
Setting trigger mode 3 for irq 201
failed (intel_gpio_irq_type+0x0/0x110)")
This change fixes the above issue by replacing all uses of PAD_CFG_GPI
in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER.
BUG=b:67507004
TEST=Verified on soraka that the genirq error is no longer observed in
dmesg. Also, cat /proc/interrupts has the interrupts configured
correctly.
Change-Id: I7dab302f372e56864432100a56462b92d43060ee
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The mainboard_memory_init_params() and mainboard_silicon_init_params()
methods already have weak definitions in drivers/intel/fsp1_1,
so having them declared as weak in the cyan baseboard has the effect
of them not being called at all unless overridden at the variant level.
Therefore, remove the weak declarations in the baseboard and ensure
that each variant has its own init functions if needed.
TEST: build/boot google/cyan
Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time)
removed the delay after taking device out of reset since it seemed
unnecessary in system resume case (because there is enough time after
taking device out of reset and before communication with device
starts).
However, without the delay, kernel driver runs into issue while
talking to the device during boot-up and runtime
suspend/resume. (Observed this error in dmesg: "i2c_hid
i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms
delay after taking device out of reset. Verified on multiple Soraka
system that with 10ms delay, kernel driver does not run into any issue
talking to the WCOM device during boot-up, runtime suspend/resume and
system suspend/resume.
BUG=b:65358919
TEST=No more errors talking to WCOM device in kernel dmesg.
Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21910
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
mainboard_ec_init implemented by all x86-based mainboards using
chromeec performed similar tasks for initializing and recording ec
events. Instead of duplicating this code across multiple boards,
provide a library function google_chromeec_events_init that can be
called by mainboard with appropriate inputs to perform the required
actions.
This change also adds a new structure google_chromeec_event_info to
allow mainboards to provide information required by the library
function to handle different event masks.
Also, google_chromeec_log_device_events and google_chromeec_log_events
no longer need to be exported.
Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Adapt code to latest schematic changes, revision 1.1.
Configure GPD2 for EC_PCH_WAKE_ODL,
GPP_D5 for EC_I2C_SENSOR_SDA,
GPP_D6 for EC_I2C_SENSOR_SCL,
GPP_D7 for WWAN_SAR_INT_ODL,
GPP_D9 for touchscreen power enable,
GPP_D10 for wifi power enable,
GPP_D11 for wwan power enable,
GPP_D13 change to "No Connect" (was VOL_UP_ODL),
GPP_D14 change to "No Connect" (was VOL_DOWN_ODL).
BUG=b:66265441
BRANCH=None
TEST=None
Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/21900
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has
to be configured in early_gpio_table.
BUG=b:67030973
BRANCH=none
TEST=Verify by wpsw_boot and wpsw_cur match.
Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21876
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch removes checks that ensure EC to be in RO for recovery
boot. We do not need these checks because when recovery is requested
automatically (as opposed to manually), we show 'broken' screen where
users can only reboot the device or request recovery manually.
If recovery is requested, Depthcharge will check whether EC is in RO
or not and recovery switch was pressed or not. If it's a legitimate
manual recovery, EC should be in RO. Thus, we can trust the recovery
button state it reports.
This patch removes all calls to google_chromeec_check_ec_image,
which is called to avoid duplicate memory training when recovery
is requested but EC is in RW.
BUG=b:66516882
BRANCH=none
CQ-DEPEND=CL:693008
TEST=Boot Fizz.
Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-on: https://review.coreboot.org/21711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently the WCOMCOHO registers a reset delay of 110ms to execute their
_ON_ asl power on method. This seems to be correct as per WACOM product
design specifications but it introduces an unwanted delay in overall system
resume time. This delay should be removed from ACPI critical path since the
entire kernel resume gets blocked on this sleep call unless this is over. In
the kernel I2C communication with WACOM driver starts with the resume
callbacks of I2C HID driver which gets triggered after display is completely
resumed. The display resume process takes at least 230ms so it's safe to
reduce the delay from coreboot and unblock the critical ACPI path.
BUG=b:65358919
BRANCH=None
TEST=manual testing on Soraka board to ensure that touchscreen works at boot
and after suspend/resume. Also verify that the overall S3 resume time is
reduced by 110ms.
Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Reviewed-on: https://review.coreboot.org/21692
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V
or 3.0V. We thought this mechanism was disabled by default, but it turns
out it wasn't. We want to use that pin as an output GPIO on Scarlet so
we need to reconfigure the respective SoC controls before we do that. It
seems that we also need to explicitly pinmux the pin away from that
special function (to normal GPIO) or weird things happen on some boards.
BUG=b:66534913
TEST=Sprinkled several long udelays, poked test points with a
multi-meter on Scarlet.
Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Hook the new required AGESA callout functions into the callouts tables.
BUG=b:66690176
TEST=Build and boot Kahlee - see the functions get called.
Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/21708
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Modify the HID to align with ACPI spec. Add the DSD object
for the device tree support in kernel which will probe
the DW9714 device based on the HID.
BUG=b:65423422
CQ-DEPEND=CL:654383
BRANCH=none
TEST=Build and boot soraka. Verified that the VCM device
probe is successful.
Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We need support two touchpad for Robo project,
so adding Synaptices touchpad to coral.
BUG=b:63134907
TEST=Compiled, verified by ODM
Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50
Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/21696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use a single define and set the CROS GPIO ASL device to match the
Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN
field in the GPIO ASL. This addresses the TEST indicated below.
BUG=b:65597554
BRANCH=none
TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030.
Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required to transmit button information from EC to kernel.
BUG=b:65980005
BRANCH=None
TEST=Verified using evtest that kernel is able to get button
press/release information from EC.
Change-Id: I3cd524aec47ca988d6044cb089e7aa7636e64ab2
Signed-off-by: Kevin Cheng <kevin.cheng@intel.com>
Reviewed-on: https://review.coreboot.org/21633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17
is insufficient to use.
Using VPD to control could prevent H/W change.
BUG=b:65339688
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I55ab741354797e022dd945da9c8499ee5e041316
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
variant_board_sku() callback exists to allow some of the variants to
report the sku id differently based on board implementation. However,
there are cases where there are multiple ways to encode the sku id, but
the original way should be used as a fallback. As such expose a helper
function, sku_strapping_value(), such that there isn't code duplication
for the common fallback case.
BUG=b:65339688
Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update I2C5 bus parameters to obtain clock frequency <400kHz.
BUG=b:65062416
TEST=Verified using an oscilloscope that I2C5 bus frequency
in factory is ~397kHz.
Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
There have been discussions about removing this since it does not seem
to be used much and only creates troubles for boards without defaults,
not to mention that it was configurable on many boards that do not
even feature uart.
It is still possible to configure the baudrate through the Kconfig
option.
Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19682
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add support for google/celes (Samsung Chromebook 3) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new celes variant
- Add new trackpad I2C device to the baseboard for potential
reuse by other variants
Sourced from Chromium branch firmware-celes-7287.92.B,
commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21572
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/banon (Acer Chromebook 15 CB3-531) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new banon variant
Sourced from Chromium branch firmware-strago-7287.B,
commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF)
Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/terra (Asus Chromebook C202SA/C300SA) as
a variant of the cyan Braswell baseboard.
- Add board-specific code as the new terra variant
- Add code to the baseboard to handle terra's unique thermal management
- Add new shared SPD files to baseboard
Sourced from Chromium branch firmware-terra-7287.154.B,
commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Enable LTR for Root port 0, where wifi card is connected.
BUG=b:65570878
TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported
by AER driver for root port 0.
Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/21548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajat Jain <rajatja@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The Linux Pstore area must not be cleared on a reboot. Set the option
to not clear the memory in AGESA.
BUG=b:64193190
BRANCH=none
TEST=Memory clear isn't called in AGESA.
Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21596
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Kahlee has a single memory channel, not two. This corrects DMI type 17
reporting and the memory clear functions.
BUG=b:65403853, b:64193190
BRANCH=none
TEST=AGESA DMI reports the correct number of DIMMs.
Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21595
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add lens_focus property with reference to VCM device for OV13858
camera module to register the corresponding v4l2 sub-device
asynchronously.
BUG=b:64133998
BRANCH=none
TEST=Build and boot soraka. Dump DSDT and verified that it has the
required entries and verified the camera functionality.
Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/21512
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Set keyboard backlight to 75% on boot, except when resuming
from S3. This enables the backlight at a reasonable level
prior to the OS driver taking over, providing early proof-of-life
and enhanced usability in grub etc.
Uses same method as other google boards with a keyboard backlight
(chell, link, samus). 75% value determined based on user feedback.
TEST: boot google/lulu,gandof boards, observe keyboard backlight
enabled in pre-OS environment.
Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21330
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/reks (Lenovo Chromebook N22/N42) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new reks variant
- Add new I2C touchscreen device and SPD files to the baseboard
for potential reuse by other variants
Sourced from Chromium branch firmware-reks-7287.133.B,
commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1""
Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21128
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add support for google/edgar (Acer Chromebook 14 CB3-431) as
a variant of the cyan Braswell basebaseboard.
- Add board-specific code as the new edgar variant
- Add common code to the baseboard which will apply to all
variants other than cyan
Sourced from Chromium branch firmware-edgar-7287.167.B,
commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data
Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Setup cyan to be the baseboard for other Google Braswell
boards, to be added in subsequent commits:
- Keep code common to all Google Braswell boards in the baseboard,
and separate out the board-specific bits into the new cyan variant.
- Define the I2C ACPI devices such that they can be easily reused for
other variants.
- Switch the trackpad/touchscreen interrupts from edge to level,
for better performance/compatibility, as was done with all previous
Google boards.
- Add code to the baseboard to allow optional variant-specific
parameters to be used for both memory and silicon init.
- Remove superfluous includes, replace some hardcoded values with
variables, and correct typos/formatting errors.
Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Fine tune usb 2.0 strength for port 4 to pass eye diagram.
BUG=b:65306272
TEST=build on soraka, measure usb2.0 eye diagram, and result is pass.
Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The RO_VPD region is required for ChromeOS.
BUG=b:65408869
TEST=Build and check coreboot.rom with fmap_decode.
Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/21473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
We've decided to move control for the 3.0V rail (technically 3.3V on
Scarlet, but who cares about millivolts) back to a GPIO on the AP for
Scarlet rev2. This patch adds the necessary code to enable it and make
ARM TF aware of its existence. Since the pin had previously not been
connected to anything, we shouldn't really need to guard this by board
ID... older Scarlets will just be twiddling an empty pin.
Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/21328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
This patch adds imon and vmon slot numbers for Maxim 98927 driver.
These values are used to confiure IV feedback for audio playback on speakers.
BUG=b:36724448
TEST=After boot, the register dump for Max98927 codecs should have
imon and vmon slots numbers set in 0x1e register.
Change-Id: I4382da4f984507d147751c168e8177b58c88a70f
Signed-off-by: Harsha Priya <harshapriya.n@intel.com>
Reviewed-on: https://review.coreboot.org/21196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently PMIC (tps68470) is in active state even when cameras are not
in use. PMIC is put into SLEEP mode only when entering S3 via
smihandler.
With this change PMIC will be put into SLEEP mode as soon as sensors &
VCM voltage outputs are turned off. This will allow run time power
saving when camera is not in use.
PMIC will be reset in first boot & across S3 & S0ix cycles.
Also, remove the smi handler for PMIC power management & handle it as
part of sensor and VCM ACPI PowerResource.
BUG=b:63903239
TEST= Build for Soraka. Check Camera probe, Capture image across
S3 & S0ix cycles.
Also checked the following & found no regression:
1. Typical camera use cases
2. Stability tests related to camera
3. Reliability tests related to camera
4. PnP tests related to camera
5. Latency related tests with camera
Change-Id: I23b0c0a887c9eb5d29b89f14aebba273b01228e0
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch adds the DPTF settings specfic to the mainboard and enables
the CPU and other thermal sensors as participant device for fizz.
It also enables the DPTF flag in the device tree for fizz.
BUG=b:64915426
BRANCH=None
TEST=emerge-fizz coreboot and run DPTF observation tool to make sure
DPTF is up and running.
Change-Id: Ic7d125a763f539158aa425fbba1d8a000a3465ca
Signed-off-by: Tsai, Gaggery <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/21147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
We have no wacom digitizer on I2C#3, so remove it.
TEST=build and boot on soraka.
Change-Id: I3f5a1b9ece6fc9a9443477c7a7aa77dbcdf6a703
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21309
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Do not assert GPIO1_B3 otherwise BT would be disabled on Nefario.
Also, remove DVS support for CENTERLOGIC.
BUG=b:64702054, b:63537905
TEST=build coreboot
Change-Id: I350db2c080f2e41ae56413f5f895557978ef0ba8
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/21176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
BUG=b:64987428
TEST=Verified that touchscreen works on boot-up and after
suspend/resume. No power leakage via stop gpio in suspended state.
Change-Id: Ia260eb444081dbe1646c90e82c2725661e7306bc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
We no longer use this touchscreen device, so get rid of it.
BUG=b:64987428
Change-Id: I67af787d231317a80998fb483eed5674de19aeb4
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Update cyan's SPD-related functions to more closely mirror
those of other Braswell boards, in order to simplify the upcoming
baseboard/variant setup for Braswell ChromeOS boards.
TEST: boot google/cyan, observe SPD correctly identified in
cbmem log, RAM-related data correct in SMBIOS tables.
Change-Id: Iafe99ec0795764f645e0a91f5b321be5b4c6fd88
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add a 16ms delay to DMIC init by the kernel driver in order to
prevent an audible 'pop' noise when starting to record.
BUG=b:63413023
TEST=manual testing to ensure this device property is present in SSDT:
Name (_DSD, Package () {
ToUUID ("daffd814-6eba-4d8c-8a91-bc9bbf4aa301")
Package () {
Package () {
"realtek,dmic-init-delay",
0x10
}
}
})
Change-Id: If9160ce6992153ba49719029de336595bbf4ae72
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/21271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot
Change-Id: Ifdea897ef66dd10f29a8a0e72f9406d316fbe8c7
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tune I2C params for I2C buses 0, 1, 2, 4 and 5 to ensure that the
frequency does not exceed 400KHz.
BUG=b:35948024
TEST=Verified for 25 iterations that the frequency on each bus ranges
<= 400KHz.
I2C0: 375 - 400
I2C1: 377 - 400
I2C2: 377 - 400
I2C4: 375 - 397
I2C5: 375 - 397
Change-Id: Ie30e1a12b66c4660b648a585c4dfd66faf004129
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/21208
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The LED polarity was set incorrectly, fix using values derived
from original Chromium sources:
branch firmware-mccloud-5827.B, ToT
src/mainboard/google/mccloud/smihandler.c
src/mainboard/google/mccloud/romstage.c
TEST: boot google/mccloud, observe power LED on normally,
blinking in S3/S4, and off in S5.
Change-Id: Ia1f63eebbccb48fcf8543188db390b23045d843e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Commit 0562783182 applied
this change to other Google boards, but cyan was left out.
Bring cyan in line with other Google boards.
Change-Id: Id86bea538a7b82367ea6ddbd3fe3efb1b1c0078d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Cleaning up code to remove support for pre-EVT rev of cyan board.
Analogous to what was done for intel/strago in commit 103f00d.
Change-Id: I29b32da8064e0743cc9c5df02ce7d3441459ee8f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit a162348.
Remove the hard coded IRQ number for the keyboard interrupt.
IRQ number can change based upon the gpio bank index ordering.
Hence pass the gpio bank and index number so that kernel calculates
the IRQ number.
Original-Change-Id: Icfe5c3995007164bf617575b541758c18ee63a1d
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I81ff19e3060c533ee76023c7651f741294e9db30
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21177
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Adapted from Chromium commit dc59188.
Disable L1 sub state to prevent WiFi randomly disappear condition.
Original-Change-Id: I8975bb4bbbc2fc89b91b06ae02716367890c672d
Original-Signed-off-by: T.H. Lin <T.H_Lin@quantatw.com>
Original-Reviewed-by: Rajat Jain <rajatja@chromium.org>
Original-Reviewed-by: Vincent Wang <vwang@chromium.org>
Oriignal-Tested-by: TH Lin <t.h_lin@quanta.corp-partner.google.com>
Change-Id: I51a1bcca6431e6bc28baf9b09433cec13db925c3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit 1138727.
Elan touchscreen driver expects the first gpio resource in asl
to be the reset line.
The driver considers the gpio based irq line as reset gpio resource
and changes the direction to output.
This will cause irq registration to fail.
Solution is to pass Interrupt resource for touchscreen irq
instead of GpioInt.
Original-Change-Id: Ia72d4ad80117f3c0014098113c9027416026e65e
Original-Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: I1c4b029851e321feeedf713186976fbec42dd82e
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Cherry-pick from Chromium commit e49deb1.
Configuring UPD PcdCaMirrorEn. This is a board specific parameter.
CA mirror is the Command Address mirroring option that is board
specific.
Original-Change-Id: I05174e18d650332d838e5036c713e91c4840ee75
Original-Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Ibd0c811d41cb592634f7785edb83ad2f423546c5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/21169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch to provide new config options to perform LPC and SPI
lock down either by FSP or coreboot.
Remove EISS bit programming as well.
TEST=Build and boot Eve and Poppy.
Change-Id: If174915b4d0c581f36b54b2b8cd970a93c6454bc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/21068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
In order to pass type C USB2 eye diagram for sku Santa,
USB2 port#1 PHY register needs to be overridden.
port#1:
PERPORTPETXISET = 7
PERPORTTXISET = 2
BUG=b:64880573
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage
Change-Id: I07c0b7b0f08263a348befb7d6fd8d01028314470
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/21199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Sync file with southbridge/amd/common/sleepstates.asl.
SSFG was meant to be used as a mask to enable sleepstates
_S1 thru _S4. However as a logical instead of bitwise 'and'
operation was used, all the states were enabled if only
one was marked available.
Change-Id: I674953f1a5add74e16ddd84c252e8d21501ffefd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/21092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Kahlee has an ambient light sensor connected to the EC.
TEST=Can see the device in /sys/bus/iio
BUG=b:62030268
Change-Id: Id1138a0fc5270489a734bdf8b1f4ac02d358c0df
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/21146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch assigns the code of coral family, such that,
the 'mosys platform family' returns 'Google_Coral'.
BUG=b:64467244, b:64501879
BRANCH=none
TEST=Examine 'mosys platform family' w/ new firmware.
Change-Id: I1d8f8ca2166a1d80855608cf5b64b0cc7bf3dc93
Signed-off-by: Harry Pan <harry.pan@intel.com>
Reviewed-on: https://review.coreboot.org/21136
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Current coreboot does not create ACPI device for OS to recognize Raydium
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64821783
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: I8852e38f01f82b80c2c9718b93baf5894dbd745b
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Current coreboot does not create ACPI device for OS to recognize MELFAS
touchscreen.
List the touch screen in the devicetree so that the correct ACPI device
are created.
BUG=b:64779224
BRANCH=reef
TEST=emerge-snappy coreboot
Change-Id: If2bc910d641e0cf2b120ed883c5788542959f568
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/21067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Split `i2c.h` into three pieces to ease reuse of the generic defi-
nitions. No code is changed.
* `i2c.h` - keeps the generic definitions
* `i2c_simple.h` - holds the current, limited to one controller driver
per board, devicetree independent I2C interface
* `i2c_bus.h` - will become the devicetree compatible interface for
native I2C (e.g. non-SMBus) controllers
Change-Id: I382d45c70f9314588663e1284f264f877469c74d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The Giantec semiconductor GT24C16S and ON semiconductor CAT24C16
are the industrial standard electrically erasable programmable
read only memory (EEPROM's) and this patch adds ACPI objects
and power resources for NVMEM device.
Update DOVD method to set sensor IO LDO voltage and remove repetitive
code from OVFI, VCMP and NVMP power resources.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Read the NVMEM content via sysfs interface.
Change-Id: If49ed33b7e1de1eabf317b31ceed8568dfca0aae
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20495
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
BUG=b:64705535
BRANCH=master
TEST=emerge-coral coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I777247a6b58d3d50b72f12ca2fcab49a06ed5431
Signed-off-by: Pan Sheng-Liang <Sheng-Liang.Pan@quantatw.com>
Reviewed-on: https://review.coreboot.org/21027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
BUG=b:64468585
BRANCH=none
TEST=with the other sku-id related patches applied, coreboot obtains the
right SKU ID from EC
Change-Id: I96a0e030bbc5f1c98165e70353340c413f8dc352
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.
BUG=b:64181150,b:62726961
Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.
Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move mainboard_ec_init out of mainboard enable to the more
appropriate mainboard init phase.
Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
