While FORCE_PWR is set high, it prevents retimer from entering low power
state. S0ix failure occurs while USB4 Gatkex is connected on Port-0.
This change sets FORCE_PWR(GPP_H10) low. This FORCE_PWR GPIO will be
toggled by kernel through DSM method while updating retimer firmware.
BUG=b:174166586
Cq-Depend: chromium:2594438
TEST=Verifed s0ix cycles with USB4 Gatkex connected on Port-0.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Ie4b442e1078379c522a94bfdc00cd99e6f9b8170
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48649
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Separate GPIO define into gpio_defs.h, then we can use it in asl include.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If2a779eae228f621e77610889205853de2fb179a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49216
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
With Intel CPX-SP FSP ww01 release, CidBitMap field is added to
DimmDevice struct in hob_memmap.h.
The copyright statements were updated to accomodate year 2021.
gpio_fsp.h is not needed any more as coreboot takes over GPIO
configuration.
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I3242c8b50401757a28de8a9e9c71fb95bc0515dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Update v 3444 FSP headers for Tiger Lake platform to include the
below 2 UPDs to control TC cold support usb connect or not.
FSPS:
Usb3ComplModeEnable
DisableTccoldOnUsbConnected
BUG=b:173054070
TEST=Build and boot on delbin.
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I68b32730293fc83b5088074f71fa215220574748
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Zhao <john.zhao@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
To work around various bugs running KVM enabled, copy page tables to
DRAM in assembly before jumping to x86_64 mode.
Tested on QEMU using KVM, no more stange bugs happen:
Tested on host
- CPU Intel(R) Core(TM) i7-7700HQ
- Linux 5.9
- qemu 4.2.1
Used to crash on emulating MMX instructions and failed to translate
some addresses using the virtual MMU when running in long mode.
Tested on host
- CPU AMD EPYC 7401P 24-Core Processor
- Linux 5.4
- qemu 4.2.1
Used to crash on jumping to long mode.
Change-Id: Ic0bdd2bef7197edd2e7488a8efdeba7eb4ab0dd4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49228
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The xHCI controller supports waking the system from S1-S4.
Thus specify that the deepest sleep state is S4 in _PRW.
Tested on Prodrive/hermes. The board now wakes from S4 as well by
pressing a key on the USB keyboard.
Change-Id: I0bb266e70ee6b4eb8922671b7d0078db0d29a1da
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49224
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Wrap `r` in parentheses to avoid unexpected behavior with compound
expressions. This prevents `CxDRBy_BOUND_MB(r+1, base)` from triggering
undefined behavior when `r = 2`, as the shift would be greater than 32.
Change-Id: I14235b2708ab502d842da677451c14203a469b45
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49261
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Platform can now select VGA_ROM_RUN_DEFAULT Kconfig to perform graphics
initialization for PCI-E based discrete card through VGA OpRom
(SoC or Mainboard user can't select VGA_ROM_RUN directly because
it's part of choice option).
(Note: Some payloads, like SeaBIOS, are also able to run Option ROMs,
so coreboot does not need to enable VGA_ROM_RUN Kconfig)
For payload like depthcharge, create VGA_ROM_RUN_DEFAULT Kconfig
for mainboard to select design with DGPU where OpROM is embedded
inside the DGPU card.
Allow auto selection of VGA_ROM_RUN_DEFAULT from VGA_BIOS Kconfig.
Also NO_GFX_INIT Kconfig to avoid running VGA_ROM_RUN
by default in case SeaBIOS is used.
TEST=Able to get Pre-OS splash screen with AMD Radeon RX 5700 PCI-E
DGPU when mainboard user selects VGA_ROM_RUN_DEFAULT.
Change-Id: Iecb2fcdb105af449bc20ad727759cdef17d5e376
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49016
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
List of changes:
1. Create new Kconfig MAX_CPU_ROOT_PORTS and MAX_PCH_ROOT_PORTS as per
EDS.
2. Add new chip variable to enable/disable CPU PCIE RPs from mainboards.
3. Rename PcieRpEnable to PchPcieRpEnable.
4. Enable CPU RPs as below in mainboard devicetree.cb
RP1: PEG60 : 0:6:0 : CPU SSD1
RP2: PEG10 : 0:1:0 : x8 CPU Slot
RP3: PEG62 : 0:6:2 : CPU SSD2
Change-Id: I92123450bd7cfb2e70aae8de03053672a7772451
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49136
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is needed to allow switching to Haswell CPU code in the future.
Change-Id: Ic642f32f9c4a269a66ac470b7a7217f20ff8bfba
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46886
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Name the common part of GNVS initialisation as soc_fill_gnvs().
It is also moved before the call to acpi_create_gnvs(), which
followup will rename to mainbord_fill_gnvs() to reflect that
implementation is under mb/.
Change-Id: Ic4cf1548b65a86212d6e45d460fcd23bb8036365
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48706
Reviewed-by: Lance Zhao
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These boards without ChromeEC do not set ACTIVE_EC_RW
flag as part of the gnvs_assign_chromeos() function.
Create abstraction to avoid <vendorcode/chromeos/x> include.
Change-Id: Ic6029e1807fcfe7dd2c766ce8221e347b6b096f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48777
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Already done in common gnvs_get_or_create() implementation
once gnvs_chromeos_ptr() is defined for platforms.
Change-Id: I90fa2bc28ae76da734b3f88be057435aed9fe374
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48703
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Allocation now happens prior to device enumeration. The
step cbmem_add() is a no-op here, if reached for some
boards. The memset() here is also redundant and becomes
harmful with followup works, as it would wipe out the
CBMEM console and ChromeOS related fields without them
being set again.
Change-Id: I9b2625af15cae90b9c1eb601e606d0430336609f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48701
Reviewed-by: Lance Zhao
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of hard-coding function names in strings, use the __func__
constant for better maintainability.
Change-Id: I151560cd5a135e00f494eda3f9d3b592ee9d984a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add a space after each comma to fix linter issues.
Change-Id: I5533c4fc7aa0e986da4350ec56b84903b3111a07
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49198
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Macros should not use a trailing semicolon.
Change-Id: Ibbcd589c7afa72e9e468e5f4b557bb2c665bbec0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49192
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Align the bytes of picr_data[] and intr_data[] with 8 bytes per line and
add spaces after commas so that the linter doesn't complain.
Also, remove spaces before the postfix '++' operator.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I90bec7fdfabca6f8afd1508c673241e0742e2ee9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49191
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop VR configuration since it matches the platform defaults.
Change-Id: I92007f4ff9d093c9573bb1ee13e64eb2f38af4f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Two USB2 ports 4 and 9 are assigned to type C connectors on Delbin
board. This update configures these USB2 ports for Type C which will
allow USB2 port reset message upstream from PCH to CPU to recover a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Booted to kernel on Delbin board and verified usb2 port reset
message enable bits through pch xhci_mmio_base + R_XHCI_MEM_U2PRM_U2PRDE
where the offset register R_XHCI_MEM_U2PRM_U2PRDE has value 0x92f4.
Validated various USB3 devices enumeration.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idb3ce949e1ecf3adc7615e0af79a38a0cc9be18f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49202
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
BUG=b:174118027
BRANCH=octopus
TEST=adjust SSFC value of CBI to select RT5682 or DA7219 then check
whether device tree is updated correspondingly by disabling unselected
one.
Signed-off-by: Marco Chen <marcochen@google.com>
Change-Id: Id37c4c5716ade0851cfcb24e12b390841e633ac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48795
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
This change adds internal USB camera into devicetree for sasuke
BUG=None
TEST=Built and checked camera device existence with lsusb
Change-Id: I51b9bb174205d984f1d060afd603f1d087095645
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49162
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds ELAN touchpad into devicetree for sasuke.
BUG=None
TEST=Built and verified touchpad function
Change-Id: If9c25f23ee1c0e88382fff036f77a6753775b81e
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change adds DA7219 audio codec and MAX98360A amplifier for sasuke.
BUG=None
TEST= Built and heared speaker sound on OS
Change-Id: Ib48eb74fbfe171d46d0d23859057ba169b56bde2
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Drop DEVICETREE from Kconfig since it matches the default value.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: Idbcd49cca6494ae2da0f364c24638d7ca11911da
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
It doesn't make sense to configure that filename in Kconfig, since the
filename can be changed by the user. So remove it.
Change-Id: I3eed05637da29096bc1d134505d7335db5db1439
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49138
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
An API is added to get SSFC value from cros EC.
BUG=b:174118027
BRANCH=octopus
TEST=check SSFC value from EC is correct compared to value in CBI
Change-Id: Ifd521514bbc2e90c789f3760b72e8326e614e2b1
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48791
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
uart_common_init is not used outside of
soc/intel/common/block/uart.c. This change restricts the scope to this
file and drops the declaration from uart.h
Change-Id: I499a53506f9b2e91ecc7334bf9b023d342e802fc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49211
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the parameter passed into `lpss_set_power_state()`
from struct device * to pci_devfn_t. This allows the users in the
early stages to use pci_devfn_t instead of having to walk the device
tree to get a pointer to the relevant device structure. It is
important for optimizing out unnecessary components of the device tree
from the early stages.
Change-Id: Ic9e32794da65348fe2a0a2791db47ab83b64cb0f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49210
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change drops the parameter `struct device *dev` from the function
`soc_get_gen_io_dec_range()`. This function uses the parameter dev to
get a pointer to config structure for extracting the decode ranges
configured by mainboard in device tree. However, there is no separate
chip driver for the LPC device which means that the SoC code can use
`config_of_soc()` to get to SoC chip config instead of using the LPC
device.
This change is being done in preparation to clean up the device
tree/chip config access in early stages that allows for optimizing
the inclusion of device tree elements in the early stages.
Change-Id: I3ea53ddc771f592dd0ea5e5e809be2d2eff7f16d
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This change uses append operation (+=) instead of assignment (:=) for
smm-c-deps to ensure that any earlier assignment is not
overwritten.
Change-Id: Ic1d62b414cfe3f61ee2b80b026b7338faa186904
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
USB3 is in CPU and USB2 in PCH on Tigerlake. Cross die messaging is
implemented between CPU and PCH through the IOSF SB bridge. a PCH xHCI
USB2 port reset event issued by the xHCI driver shall trigger a message
upstream to CPU to wake it from the low power state which allows a USB3
device that downgraded to USB2 to upgrade back to USB3.
BUG=b:176575892
TEST=Built and booted to kernel on Voxel board.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I672f30a117980bc10bd71e9b77c5fa76286b9f5f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49052
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Different from mt8183, mt8192 doesn't need to trigger EC reboot on HW
initiated watchdog reset. Therefore, ec_reset_flags cannot be used to
determine AP watchdog reset. Instead we check the cause of the last AP
reset.
BUG=b:174443398
TEST=emerge-asurada coreboot
TEST=crash.WatchdogCrash passed on asurada
BRANCH=none
Cq-Depend: chromium:2607150
Change-Id: I761ecdd8811e5612b39e96c73442cc796361d0f0
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49113
Reviewed-by: Nicolas Boichat <drinkcat@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change copies ec_commands.h directly from the Chromium OS EC repo
at SHA afffc28f2, with the exception of changing the copyright header
to SPDX format.
Change-Id: Ie02e0295312050e803a7d701ec4eed1dadfa6c9a
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
The _CST method is supposed to return a package. If a mainboard used
zero for all ACPI C-states, the generated _CST would return nothing,
which is invalid. Instead, return a package with no C-state entries.
This change is a no-op, since all mainboards have at least one valid
ACPI C-state. This is what `acpigen_write_CST_package()` does, too.
Change-Id: I1f531e168683ed108a8d6d03dee6f5415fd15587
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49092
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Just a small change to follow the code style.
Change-Id: Ie838b82e12627478ea721f426efc4d557feb6ae3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49166
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add memory table to "mem_list_variant.txt", and command to generate files:
go run ./util/spd_tools/lp4x/gen_part_id.go src/soc/intel/tigerlake/spd src/mainboard/google/volteer/variants/copano/memory/ src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt
DRAM Part Name ID to assign
MT53D512M64D4NW-046 WT:F 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
BUG=b:175896481
BRANCH=firmware-volteer-13672.B
TEST=emerge-volteer coreboot
Signed-off-by: hao_chou <hao_chou@pegatron.corp-partner.google.com>
Change-Id: I2ace17e8fff12d3f5de15a35f609265d8b6ed6b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48948
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the _PRT generates a GNB IO-APIC routing table we no longer
need to route the PCI interrupts through the FCH IO-APIC. This change
unmaps the IRQs since they are no longer used.
BUG=b:170595019
TEST=Boot with `pci=nomsi amd_iommu=off` and verify /proc/interrupts
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I3467934bfcac14311505bec49a12652490554e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
At the moment neither verstage nor romstage has a generated assembly
stub. This was used when CAR was set up in romstage which is not the
case anymore.
Change-Id: Ia4a952f269cc2b3edf1290c80b7a63619c8c6c95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
These fields were originally added for compatibility with the
proprietary ITE EC firmware, but the System76 EC firmware does not use
them. Take the opportunity to document most of the fields as well.
Change-Id: I5581437c67ec67705ce16ba20254183a0261fd83
Signed-off-by: Jeremy Soller <jeremy@system76.com>
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49129
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Trying to do multiple operations on the same CBFS image at the same time
likely leads to data corruption. For this reason, add BSD advisory file
locking (flock()) to cbfstool (and ifittool which is using the same file
I/O library), so that only one process will operate on the same file at
the same time and the others will wait in line. This should help resolve
parallel build issues with the INTERMEDIATE target on certain platforms.
Unfortunately, some platforms use the INTERMEDIATE target to do a direct
dd into the CBFS image. This should generally be discouraged and future
platforms should aim to clearly deliminate regions that need to be
written directly by platform scripts with custom FMAP sections, so that
they can be written with `cbfstool write`. For the time being, update
the legacy platforms that do this with explicit calls to the `flock`
utility.
Signed-off-by: Julius Werner <jwerner@chromium.org>
Change-Id: I022468f6957415ae68a7a7e70428ae6f82d23b06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Furquan Shaikh <furquan@google.com>
As part of acoustic noise mitigation calibration, we need to enable
FastPkgCRampDisable upd along with slew rate = 1. This values has been
derived based on noise calibration done.
Please refer document 575216 for procedure.
BUG=None
BRANCH=dedede
TEST=correct value has been programmed and slew rate measurement
is correct on scope.
Change-Id: Ie42c8ab647ff42fa043b6f717a9834f9b9c551f6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49134
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
We need to fill Acoustic noise mitigation related UPDs only in
case when acoustic noise mitigation is enabled. This will also
clarify the user that they need to enable Acoustic noise
mitigation while using this config in mainboard.
We're only filling UPD for domain VR index 0 since there is only
one VR domain for JSL (VCCIN VR).
Reference: JSL EDS (Document# 613601) (Chapter 3.4)
BUG=None
BRANCH=dedede
TEST=UPD values are getting filled correctly when Acoustic noise
mitigation is enabled.
Change-Id: I0cf4ccfced13b0d32b3d20713eace63e66945332
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
USBSUSPGQDIS is a disqualifier bit which will allow platform
to enter s0ix even if USB2 PHY SUS is not power gated. Disabling this
bit will ensure that USB2 PHY SUS is power gated before entering s0ix.
BUG=b:175767084
BRANCH=dedede
TEST=s0ix works on drawcia and USB wake from s0ix works fine.
Change-Id: I20bad3f79141799c88a16272ea822b9e3dede504
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49012
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
This was used as a guard to not raise SMI with
APM_CNT_GNVS_UPDATE. The handler has been removed
now completely.
Change-Id: I7726367fd16630aa4b4b25b24b05f740645066db
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add GRXS and GTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I1aa6a8f44f20577e679336889c849dd67cb99f2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add STXS and CTXS into gpiolib. We can align with Intel ACPI method
for the better usage. This benefits acpi.c to be more clear, too.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the Goodix touchscreen functional.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: If4fcd68496a712fdccf44b91a6192ef58a0a9733
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48943
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original Stamp_boost parameter will cause boost time over 2500sec(3960sec)
To pass balance performance and skin temperature test, decrease stamp_boost:
2500 -> 1640
BUG=b:175364713
TEST=1. emerge-zork coreboot
2. run balance performance and skin temperature test
Change-Id: I44f086af6b5dd552efd2bd1ef4db0d69b652826d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49109
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This functionality only exists on legacy TXT.
Change-Id: I4206ba65fafbe3d4dda626a8807e415ce6d64633
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
For arch/x86 the realmode part has to be located within the same 64
KiB as the reset vector. Some older intel platforms also require 4 KiB
alignment for _start16bit.
To enforce the above, and to separate required parts of .text without
matching *(.text.*) rules in linker scripts, tag the pre-C environment
assembly code with section .init directive.
Description of .init section for ELF:
This section holds executable instructions that contribute to the
process initialization code. When a program starts to run, the
system arranges to execute the code in this section before calling the
main program entry point (called main for C programs).
Change-Id: If32518b1c19d08935727330314904b52a246af3c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47599
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is just to ease merging with Broadwell.
Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical.
Change-Id: I9239489fe48f04714e6626b57ef07ca8b3013024
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46910
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The MAINBOARD_POWER_ON_AFTER_POWER_FAIL symbol was removed in
Commit 9faae2b939.
The default is currently to keep power off after a power failure.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ib2ef450f5c64f663b9aa88f8870250e92898e308
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47671
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainboard user can select VGA_ROM_RUN_DEFAULT Kconfig hence
no need to have another ENABLE_DISPLAY_OVER_EXT_PCIE_GFX Kconfig to
load/execute VGA OpRom.
Change-Id: Id87f82d9c3657afad9db94b1ec0917121edfe2bb
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49023
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Make EC_GOOGLE_CHROMEEC_SWITCHES depend on VBOOT, rather than force
selecting it.
Change-Id: If96b2a935d2f7388a24be7d8e65c7dfc2c89a0fc
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Make GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC depend on VBOOT,
rather than force-select it.
Change-Id: I0ec418d4182865636b6350f1ee151420d8e02c33
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Make CHROMEOS_DSM_CALIB depend on CHROMEOS, rather than force-select it.
Change-Id: I4c3fd04ec00e0787381c58810938dd48f414635c
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The CSE lite SKU has 2 CSE firmware boot partitions vs 3 for the "normal"
SKU; this has nothing to do with building for ChromeOS or not, and by
having this dependency, boards with select the CSE lite SKU are unable to
build with CONFIG_CHROMEOS unset due to Kconfig dependency issues.
Test: build google/wyvern with CONFIG_CHROMEOS not set.
Change-Id: I6959f35e1285b2fab7ea1f83a5ccfcb065c12397
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
I2C0 has amplifier connection, thus set it to PchSerialIoPci.
BUG=b:170273526
BRANCH=puff
TEST=Build and check PCH serial IO config is set I2C0 to Mode 1
Change-Id: I9540f7b5538d37de53bcf43531488d714874a565
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
This MSR will be used in the follow-up changes.
Change-Id: Ia6f74861502d4a9f872b2bbbab2e5f1925a14c4d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49044
Reviewed-by: Lance Zhao
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove these comments, because it does not contain useful information
that helps to understand the circuit, which we do not have.
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: I8a8450493ceebe97ac03b4134adc46b01328a1b6
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Configure the I2C bus high and low times for port0,2 and 4 I2C buses.
BUG=b:176519792
TEST=Measured the I2C bus frequency lower than 400 KHz.
Change-Id: Ieed038c93f0972c06cb3fa311742dd22ac2e875d
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Configure the I2C bus high and low time for all enabled I2C buses.
BUG=b:168783630
TEST=Measured the I2C bus frequency reduce to 387 KHz.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I37403dd3ac3c9320398207d2111e1ddb73d6a130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Config I2C high / low time in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
These tuning value is applied from touchpad as a base line,
and EE measured touchscreen/audio runs at 399/396.7kHz after tuning.
BUG=b:173709409
BRANCH=dedede
TEST=Build and check after tuning I2C clock is under 400kHz
Change-Id: I970d69e6361d7cf6fcfc4e5b0b3c5fbfa885367c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49020
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
According Goodix GT7375P Programming Guide_Rev.0.6, increase the stop
delay time from 100 ms to 160 ms.
The power sequence is not met with the latest guide_rev.0.6.
BUG=b:176270381
BRANCH=zork
TEST=Confirm the measured waveform complies with Goodix touchscreen spec.
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Change-Id: I687ffa2eb13a9ddecb3045c5e1540b94417329ec
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48907
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All Broadwell boards use 8 for MAX_CPUS, so this option can be factored
out into SoC Kconfig.
Change-Id: I311b95ea75a7c6b76b32c7197a0cec86db644234
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49122
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure MAX_CPUS in SoC Kconfig with 8 as default value and remove it
from every mainboard where 8 is used.
Change-Id: I825625bf842e8cd22dada9a508a7176e5cc2ea57
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49105
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Haswell and Broadwell have at most 8 threads.
Change-Id: Idcccf22addb6e15d7c55b9816141af47d6186cca
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46952
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On Voema port 0 (MB PORT) does not have a retimer so the port needs
to be configured for the SOC to handle Aux orientation flipping.
BUG=b:176462544
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I3d31a5b848f56126f8ffe2babb29085471e8224f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=None
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ifcc406591abf88ebdb5ed972614c3a6901721bac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This table was wrong. It's also produced by the SoC code now.
BUG=b:170595019
TEST=Verify PCI IRQ: log messages
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I008b6896064672f9d45a8e12f6cfc62c0cc41536
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The PCI interrupt line registers are used as a last resort if routing
can't be fetched from either ACPI or the MPTable. This change correctly
sets the registers. It overrides the pirq_data set by the mainboards
since the routing is fixed in AGESA.
BUG=b:170595019
TEST=Boot ezkinil with `pci=nomsi,noacpi amd_iommu=off noapic`
Verified all PCI peripherals are still functional.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: If5d4d8f613c8d0fa9b43cefa804824681c3410d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The original routing table did not handle all 8 INTx interrupts.
Additionally it also didn't take the swizzling into account.
Now that we know how AGESA programs the routing table we can correctly
generate it.
We still route the PCI interrupts through the FCH IOAPIC. A follow up
will have the GNB IOAPIC handle the PCI interrupts.
There is still work to be done to fix the legacy PCI_IRQ register for
each PCI device. We can then remove the mainboard_pirq_data from each
mainboard.
BUG=b:170595019
TEST=Used ezkinil
Boot kernel with `pci=nomsi amd_iommu=off noapic` and
`pci=nomsi amd_iommu=off` then verified system
was usable and verified /proc/interrupts looked correct.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I2b2cce9913081d5cd456043ba619a79c1dfd4a8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The set_resources field in the root_complex_operations struct shouldn't
be NULL, but a pointer to noop_set_resources instead. This fixes the
error "PCI: 00:00.0 missing set_resources".
Change-Id: I2d9f3850b3051c92cd9c0f52f8570f4fd6133070
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49120
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
When configuring a GPIO pin as output the value should be written before
it gets configures as an output to avoid a possible glitch on the output
when the GPIO pin was an input before and the output value was different
from the one that got written afterwards.
Change-Id: I2bb5e629ef0ed2daadc903ecc1852200fe3a5cb9
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
The functions to configure a GPIO as input with pull-up/down need to
clear the output enable bit, so that the direction will be input. If the
pin was configured as output before, the pin direction was still output
after this call which is at least unexpected.
Change-Id: Id1fa1669195080b34fd62324616825415728b0b4
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
If the pin was configured as pull-up/down before this wouldn't get
cleared when calling gpio_input before.
Change-Id: I17d5eccb7492138e64abaecbd7cb853adb8c4d2d
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Since there's only one set of values, the if-clause is unnecessary.
Change-Id: I2fb4582377fe2f204d2cee0dc513a4d5d24feabe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49090
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
They aren't specific to AC power operation anymore. Also adapt autoport.
Change-Id: Ib04d0a08674b7d2773d440d39bd6dfbd4359e0fb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49089
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All mainboards use the same values for AC and battery, even desktop
boards without a battery. Use the AC values everywhere and drop the
battery values. Subsequent commits will rename the AC power options
accordingly, and will also clean up the corresponding acpigen code.
This is intentional so as to ease reviewing the devicetree changes.
Also update util/autoport accordingly.
Change-Id: I581dc9b733d1f3006a4dc81d8a2fec255d2a0a0f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
It is not used anywhere. Drop it.
Change-Id: I92a72a46db237cf855491a664cdfadca34306f6c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49087
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To allow adjusting the phase shift of the various I/O signals, the
memory controller contains several PIs (Phase Interpolators). These
devices subdivide a QCLK (quarter of a clock cycle) in 64 `ticks`,
and the desired phase shift is specified in a register. For shifts
larger than one QCLK, there are `logic delay` registers, which allow
shifting a whole number of QCLKs in addition to the PI phase shift.
The number of PI ticks in a QCLK is often used in raminit calculations.
Define the `QCLK_PI` macro and use it in place of magic numbers. In
addition, add macros for other commonly-used values that use `QCLK_PI`
to avoid unnecessarily repeating `2 * QCLK_PI`, such as `CCC_MAX_PI`.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: Id6ba32eb1278ef71cecb7e63bd8a95d17430ae54
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch updates CPU microcode patch base address/size to FSP-S
UPD to have second microcode patch loaded successfully to enable
Mcheck flow.
This is new feature requirement for ADL as per new Mcheck initialization
flow.
BUG=b:176551651
TEST=Able to reach beyond PC6 without any MCE.
Change-Id: I936816e3173dbcdf82b2b16b465f6b4ed5d90335
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48847
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC generates EC_MKBP_EVENT_DP_ALT_MODE_ENTERED when USB-C
connections enter DP alt mode, which should wake the system from S3.
Configure S3 wake events to include MKBP so this actually wakes
the system.
BUG=b:174121852
BRANCH=zork
TEST=Generating DP event on MKBP via EC console wakes morphius
Change-Id: I8100c6253e8e5cae91586c4f2f45d66c15fecc6d
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.
BUG=b:170595019
TEST=Verify ezkinil still boots
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f5b6f535597149f28dd8c8322acc2e988f11505
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I1f07b5851ece6d0943faa9c90fc518805880a27d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49060
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Daniel Maslowski <info@orangecms.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built chili/base with BUILD_TIMELESS=1, coreboot.rom remains the same.
Change-Id: I5e2a09db80232457b2f78ad9b100c468d281f753
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Rework Kconfig file so that each variant has its own config option with
their specific selects / configuration and move common selects to a
seperate config option, which is used as base for each variant.
Built kontron/boxer26 with BUILD_TIMELESS=1, coreboot.rom remains the
same.
Change-Id: I08bd68aa2f98f93b8c5daf1ab2f3c1bbce521c53
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49061
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: Ibc6833d9256800d0e50651cac18a4e81ddbe6895
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48144
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move include directories from carriers and variants to mainboard level
being able to reuse them later. Also, rename guards so that they fit
their usage.
Built with BUILD_TIMELESS=1, coreboot.rom remains the same.
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Change-Id: I55af05cb84b97d567ce1fc3b6151c34d1eda183f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48142
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
All platforms moved to initialise GNVS at the time
of SMM module loading.
Change-Id: I31b5652a946b0d9bd1909ff8bde53b43e06e2cd9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48699
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add ACPI backlight support for boards selecting BOARD_GOOGLE_BASEBOARD_HATCH.
PUFF-based variants do not have an internal panel, so do not need this.
Test: build/boot Windows 10 20H2 on google/akemi, verify
display backlight controls functional.
Change-Id: I5ce4c6e1c78299e89760a1356da452d56ba0aee6
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49058
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Converts bit field macros to target PAD_CFG_*() macros. To do this,
the following command was used:
./intelp2m -n -t 1 -file ../../src/mainboard/razer/blade_stealth_kbl/
gpio.h
This is part of the patch set
"mb/razer/blade_stealth_kbl/gpio: Rewrite pad config using intelp2m":
CB:43857 - 1/3 Decode raw register values
CB:43858 - 2/3 Exclude fields for PAD_CFG
CB:43411 - 3/3 Convert field macros to PAD_CFG
Tested with BUILD_TIMELESS=1, Razer Blade Stealth, remains identical.
Change-Id: Ie9da1246b784578c1e29acc5c61a918841de7468
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add functions to read the system and mainboard serial numbers
from VPD tables stored in flash.
Remove board-specific implementations for google/drallion and
google/sarien and select the new Kconfig instead.
Test: build/boot google/akemi with RO_VPD region persisted from
stock Google firmware, verify system/mainboard serial numbers
present via dmidecode.
Change-Id: I14ae07cd8b764e1e22d58577c7cc697ca1496bd5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49050
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently, use of the VPD driver to read VPD tables from flash
requires the use of a custom FMAP with one or more VPD regions.
Extend this funtionality to boards using the default FMAP by
creating a dedicated VPD region when the driver is selected.
Test: build qemu target with CONFIG_VPD selected, verify entry
added to build/fmap.fmd.
Change-Id: Ie9e3c7cf11a6337a43223a6037632a4d9c84d988
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The LPEA device memory resources, required by Windows drivers,
were not being set. Allocate required resources using
soc/intel/braswell/acpi/southcluster.asl as a reference.
This patch alone is not sufficient for working audio under Windows
on Baytrail ChromeOS devices, but it is a necessary component.
Test: boot Windows 10 on google/swanky, observe LPEA device working properly.
Change-Id: I7994d9b2c6e134c01b05cd7c61d309b6ba6e88e5
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48745
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The (now removed) ID_SECTION_OFFSET=0x80 was actually the
secondary address flashrom and FILO are looking for. The
primary was 0x10, just below .reset.
If .id does not collide with .fit_pointer, use the higher
of the two locations.
Change-Id: I0d3a58c82efd3bbf94f4bc80ec5bbc97d5b1c109
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48499
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
intel_txt_memory_has_secret() checks for ESTS.TXT_ESTS_WAKE_ERROR_STS
|| E2STS.TXT_E2STS_SECRET_STS and it looks like with CBNT the E2STS
bit can be set without the ESTS bit.
Change-Id: Iff4436501b84f5c209add845b3cd3a62782d17e6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47934
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There's no need to use `memset` here.
Change-Id: I0478bc3ff25b75bf0b554aa83ead6a63fcbd975c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Remove index0 DRAM assignment since it doesn't use in any build.
Add Hynix DDR4 DRAM H5ANAG6NCJR-XNC, index was generated by gen_part_id
BUG=b:175911098
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: I853a316c266afafeecff67b263005a77be316e2b
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48723
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PUFF-based Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot WYVERN variant, ensure boot splash/menu prompt visible
regardless of display init type used.
Change-Id: Ie6d2151d28058501498a4c501bb221919b4e1b39
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
These Chromeboxes need more than the 2s default in order to init
an external display and show the boot splash/menu prompt.
Test: build/boot one of each variant, ensure boot splash/menu
prompt visible regardless of display init type used.
Change-Id: Ib90136b7e564451aff638af4d42abd97e42b3c19
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add struct i915_gpu_controller_info for boards to supply info needed
to generate ACPI backlight control SSDT.
Hook into soc/common framework by implementing intel_igd_get_controller_info().
Add Kconfig entries to set the correct register offsets for backlight
frequency and duty cycle.
Change-Id: Ia62a88b58e7efd90f550000fc5b2cef0cb5fade7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40593
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the panel settings dumped from vendor firmware and hook up
drivers/intel/gma, which will be required for brightness control.
Keyboard brightness control still requires ACPI code. This will be done
in a separate change later.
Test: Panel gets enabled when the payload starts on Clevo L141CU.
Change-Id: I7977a2271da72c142b025b4631318d1a39adfb13
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48750
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add a new macro `GMA_DEFAULT_PANEL(ssc)` as shortcut for specifying one
internal panel at port A (0) in the devicetree.
Change-Id: I5308b53667657d0b255ae5bc543f1a00431f5818
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49054
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Move CPUID definitions out of msr.h into new cpuid.h header.
BUG=b:155307433
BRANCH=Zork
Change-Id: I2ed5e0a5a6dbdb38fce8bf3e769f680330718653
Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48533
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
There are multiple different devicetree setting formats for graphics
panel settings present in coreboot. Replace the ones for the platforms
that already have (mostly) unified gma/graphics setup code by a unified
struct in the gma driver. Hook it up in HSW, BDW, SKL, and APL and adapt
the devicetrees accordingly.
Always ensure that values don't overflow by applying appropriate masks.
The remaining platforms implementing panel settings (GM45, i945, ILK and
SNB) can be migrated later after unifying their gma/graphics setup code.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I445defe01d5fbf9a69cf05cf1b5bd6c7c2c1725e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48885
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
For easier review of the switch to a new register struct in the
follow-up change, the panel delay times get converted from destination
register raw format to milliseconds representation in this change.
Formula for conversion of power cycle delay:
gpu_panel_power_cycle_delay_ms =
(gpu_panel_power_cycle_delay - 1) * 100
Formula for all others:
gpu_panel_power_X_delay_ms = gpu_panel_power_X_delay / 10
The register names gain a suffix `_ms` and calculation of the
destination register raw values gets done in gma code now.
Change-Id: Idf8e076dac2b3048a63a0109263a6e7899f07230
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
SoC will transmit the EoTp (End of Transmission packet) when
MIPI_DSI_MODE_EOT_PACKET flag is set.
Enabling EoTp will make the line time larger, so the hfp and
hbp should be reduced to keep line time.
BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Shaoming Chen <shaoming.chen@mediatek.corp-partner.google.com>
Change-Id: Ifadd0def13cc264e9d39ab9c981fbdc996396bfa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Some bridge chip or panel requires dsi signal output before dsi
receiver works.
BUG=b:168728787
BRANCH=kukui
TEST=Display is normal on Kukui
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Change-Id: I3bded27087490f32ee233e615cfad1fd05fb582d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47380
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
The flash controller driver can be shared among mt8173 and mt819x.
TEST=boot to kernel on Asurada
boot to kernel on Hana (w/o BL31)
Change-Id: I4e5213563189336496122a0f2d8077b3e5245314
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
To get better PI linearity, perform 8 phase calibration to do
MCK 0/180/45 training and select the best PI settings.
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ib4ccaa8d43b8382cbc64cf82de86ad1ac16cb89a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44709
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
which select INTEL_GMA_ACPI. Rework brightness level includes and
platform-level asl files to avoid duplicate device definition for GFX0.
Include gfx.asl for Skylake/Kabylake, since all other soc/intel/common
platforms already do. Adjust mb/51nb/x210 to prevent device redefinition.
Some OSes (e.g. Windows, MacOS) require/prefer the ACPI device for
the IGD to exist, even if ACPI brightness controls are not utilized.
This change adds a GFX0 ACPI device for all boards whose platforms
select INTEL_GMA_ACPI without requiring non-functional brightness
controls to be added at the board level.
Change-Id: Ie71bd5fc7acd926b7ce7da17fbc108670fd453e0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
eint event mask register is used to mask eint wakeup source on mt8192.
All wakeup sources are masked by default. Since most MediaTek SoCs do
not have this design, we can't modify the kernel eint upstream driver to
solve the issue 'Can't wake using power button (cros_ec) or touchpad'.
So we add a driver here to unmask all wakeup sources.
BUG=b:169024614
Signed-off-by: G.Pangao <gtk_pangao@mediatek.com>
Change-Id: I8ee80bf8302c146e09b74e9f6c6c49f501d7c1c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46409
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add the right register values for backlight control to CNL's Kconfig.
To make iasl happy about the reversed register order, split the field.
Change-Id: I05a06cc42397c202df9c9a1ebc72fb10da3b10ec
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Replace the mainboard-specific code for "POST complete" signalling with
devicetree entries for using the newly introduced IPMI driver
functionality.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Change-Id: I3441c2a971cfb564b34b3a419beceb949fe295b1
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver and set the pad's initial value to 0 since the signal is active-
high and shall be set by the IPMI/BMC driver.
Also add the pad to early gpio config, since it is expected to have an
external pull-up like X11SSM-F, which is wrong and would confuse the BMC.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Change-Id: If344b2271bfc8d50b8b64847109818f96f2abbcb
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48711
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Configure the "POST complete" gpio in the devicetree for the BMC/IPMI
driver.
Also add the pad to early gpio config, since it has an external pull-up,
which is wrong and would confuse the BMC. Set the pad's initial value to
zero since the "POST complete" signal is active-high and shall be set by
the IPMI/BMC driver.
Test: Boot the machine via the BMC web interface and check that sensors
get read correctly by the IPMI firmware when the payload starts.
Tested successfully.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I6409b2aca90585e44ee5d32df0ae73b259443f32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Set `bmc_jumper_gpio` to the JPB1 gpio to enable/disable BMC/IPMI
according to its value.
Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.
Tested successfully.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8581556d915cbad2c743a79db273479ba55798fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some server boards like OCP Tiogapass and X11-LGA1151 boards use a gpio
for signalling "POST complete" to BMC/IPMI. Add a new driver devicetree
option to set the gpio and configure a callback that pulls the gpio low
right before jumping to the payload.
Test: Check that sensor readings appear in BMC web interface when the
payload gets executed.
Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.
Change-Id: I34764858be9c7f7f1110ce885fa056591164f148
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Some boards, like the Supermicro X11SSM-F, have a jumper for enabling or
disabling the BMC and IPMI. Add a new devicetree driver option to set
the GPIO used for the jumper and enable or disable IPMI according to its
value.
This gets used in a follow-up change by Supermicro X11SSM-F.
Test: Boot with jumper set to each enabled and disabled and check debug
log if IPMI gets enabled/disabled accordingly.
Successfully tested on Supermicro X11SSM-F with CB:48095.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Icde3232843a7138797a4b106560f170972edeb9c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48094
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This change adds the required gpio operations struct to soc/common gpio
code and hooks them up in all socs currently using the gpio block code,
except DNV-NS, which is handled in a separate change.
Also, add the gpio device to existing chipset devicetrees.
Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.
Change-Id: I81dbbf5397b28ffa7537465c53332779245b39f6
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48583
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct the mask for the power cycle delay from 0xff to 0x1f, to
represent the actual maximum value according to Intel graphics PRM for
Haswell, Volume 2c and Intel graphics PRM for Broadwell, Volume 2c.
Change-Id: Ib187f1ca6474325475e5ae4cc1b2ffbce12f10bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48957
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Follow TGL chipset.cb to add alias for TCSS and USB ports.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I803dad0af09b26a55ffb767826ba79cf61de04ca
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48793
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Kaby Lake PCH can have up to 24 PCIe root ports. Thus, add 4 missing
root ports to the chipset devicetree.
Change-Id: I443fb736873d47f1b6fe7718a10e1bb4ae5df2a6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48947
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
On commit 64c03e3c ("mb/google/poppy: Fix race condition in acpi"),
we introduced a new Power Resource common to all the camera modules,
in order to resolve a race condition when both modules were in use
(e.g. during startup).
The nautilus variant also used the Power Supply I2C2.PMIC.OVTH, which
requires the new common PR, but the new dependency was not added.
Depend on the new Camera Common Power Resource.
Fixes: 64c03e3c ("mb/google/poppy: Fix race condition in acpi")
BRANCH=poppy
BUG=b:174941580
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: Ifa6c70b7c02aec0112189eca573e76e53175d70d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: shkim <sh_.kim@samsung.com>
Initiate peripheral buses based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I3a828bfb3ba4ee9a9b41cd4e83701672e5ef85bf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48295
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We don't know exactly for what the GMM PCI device is used for or how it
is used. Thus, remove it to fallback to default-disable.
Change-Id: I4b8b33b16527cbcc21168b995cbfdb54a2fa3cac
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48920
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.
Change-Id: I7c537bba75d66badf854f9e7b6799303a7af018e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add the register PNP_IO4, which will be used by IT5570E in CB:48894.
Change-Id: Ic820295247323f546d4c48ed17cfa4eab3dc5e92
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48924
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Introduce a new device `gpio` that is going to be used for generic
abstraction of gpio operations in the devicetree.
The general idea behind this is that every chip can have gpios that
shall be accessible in a very generic way by any driver through the
devicetree.
The chip that implements the chip-specific gpio operations has to assign
them to the generic device operations struct, which then gets assigned
to the gpio device during device probing. See CB:48583 for how this gets
done for the SoCs using intelblocks/gpio.
The gpio device then can be added to the devicetree with an alias name
like in the following example:
chip soc/whateverlake
device gpio 0 alias soc_gpio on end
...
end
Any driver that requires access to this gpio device needs to have a
device pointer (or multiple) and an option for specifying the gpio to be
used in its chip config like this:
struct drivers_ipmi_config {
...
DEVTREE_CONST struct device *gpio_dev;
u16 post_complete_gpio;
...
};
The device `soc_gpio` can then be linked to the chip driver's `gpio_dev`
above by using the syntax `use ... as ...`, which was introduced in
commit 8e1ea52:
chip drivers/ipmi
use soc_gpio as gpio_dev
register "bmc_jumper_gpio" = "GPP_D22"
...
end
The IPMI driver can then use the generic gpio operations without any
knowlege of the chip's specifics:
unsigned int gpio_val;
const struct gpio_operations *gpio_ops;
gpio_ops = dev_get_gpio_ops(conf->gpio_dev);
gpio_val = gpio_ops->get(conf->bmc_jumper_gpio);
For a full example have a look at CB:48096 and CB:48095.
This change adds the new device type to sconfig and adds generic gpio
operations to the `device_operations` struct. Also, a helper for getting
the gpio operations from a device after checking them for NULL pointers
gets added.
Successfully tested on Supermicro X11SSM-F with CB:48097, X11SSH-TF with
CB:48711 and OCP DeltaLake with CB:48672.
Change-Id: Ic4572ad8b37bd1afd2fb213b2c67fb8aec536786
Tested-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The register `ESR` conflicts with the `Exception syndrome register` in
UDK2017. To resolve the conflict, drop the unused `ESR` register from
gma registers. It can be readded and prefixed or renamed if it's
required at a later point.
Change-Id: Icfdd834aea59ae69639a180221f5e97170fbac15
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48758
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
We missed that Cannon Point, the PCH usually paired with Coffee, Whiskey
and Comet Lake, differs a bit from its predecessors. Hence, libgfxinit
now has a new Kconfig setting for the PCH.
Change-Id: I1c02c0d9abb7340aabe94185ee5e17ef4c2b0d36
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48764
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
All known on-chip PCI devices are documented in chipset devicetree now
and default to disabled. There is no need to keep disabled PCI devices
in the mainboard's devicetree. Thus, remove them.
Change-Id: I0f78dadd9e55a8f002394dc07ab514ca13f4e963
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Add rtc MT6359P driver for rtc init and rtc eosc calibration. Refactor
mt8173 and mt8183 code by extracting common API. Move rtc_read and
rtc_write to each SoC folder, because mt8173 and mt8183 access rtc via
pmic wrapper, while mt8192 accesses it via pmif.
Reference datasheet:
Document No: RH-D-2018-0101.
Signed-off-by: Yuchen Huang <yuchen.huang@mediatek.corp-partner.google.com>
Change-Id: I57d6738fdec148c7458b2024a0a8225415ca2f3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Add basic devapc (device access permission control) drivers.
DAPC driver is used to set up bus fabric security and data protection
among hardwares. DAPC driver groups the master hardwares into different
domains and gives secure and non-secure property. The slave hardware can
configure different access permissions for different domains via DAPC
driver.
Change-Id: I2ad47c86b88047c76854a6f8a67b251b6a9d4013
Signed-off-by: Nina Wu <nina-cm.wu@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
src/northbridge/amd/pi/00660F01/Kconfig does not exist. Remove the
source statement.
Also, no kconfig files under src/soc/intel/common/basecode/. Clean
that up.
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I10917b76ff6c2a9d5a97d5c7dfa9e8925cd8c8a4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Now that CHAP device is declared in chipset devicetree, hook it up to
devicetree configuration.
Change-Id: Icc51f7b9cda32d5058dce958e386921b6d3d8ffb
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48323
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The code in soc/amd/common has an implementation of
GPIO register space that is compatible with the hardware
sb/amd/pi/hudson supports.
Change-Id: I86ae40a3cdf335263d7e9e3dcfdd588947cdd9b1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
The Sandy Bridge steppings appear in the BWG, and Ivy Bridge steppings
appear in reference code. Add them for the sake of completeness.
Change-Id: I7d17cdd04a771ca319c908fc757f868e95ea7944
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The steppings correspond to the CPUID bits 3:0, so move them to the CPU
scope, and include the CPU header from files using the stepping macros.
Change-Id: Idf8fba4911f98953bb909777aea57295774d8400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48409
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Rewrite some constants to make their meaning somewhat clearer.
Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change.
Change-Id: I321f5e61d7c695ae77e61b84728e34930f69d400
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Native raminit only supports 1.5V operation, but there are DIMMs which
request 1.65V operation in XMP profiles. Add an option to force XMP to
be used when the requested voltage isn't supported, which will run the
DIMMs at 1.5V with XMP timings. Consider this to be overclocking.
Change-Id: I64bfac8f72dadf662ceadfc7998daf26edf5a710
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
We need this to happen prior to SMM module loader. If
there is some debugging output it's better they do not
appear in the middle of CPU bringup.
Change-Id: I45b4b5c0c5bf8bee258a465d1e364bfe98190e44
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Structure with chromeos_acpi_t is expected to have size
0x1000. Only ones with device_nvs_t have size 0x2000.
Change-Id: I2eaa3a008566853b4144fa34ccffaa232d5d8e24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Rename to graphics_soc_panel_init, to more accurately convey
operations performed by the function. Guard execution so we
don't attempt to reconfigure the panel after FSP has already
done so.
This fixes FSP/GOP display init on APL/GLK, which was broken by
attempting to configure the panel after FSP had already done so.
Change-Id: I8e68a16b2efb59965077735578b1cc6ffd5a58f0
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48884
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add a new driver for OEM commands and select it from x11-lga1151-series.
The driver communicates the BIOS version and date to the BMC using OEM
commands. The command should be supported on all X11 series mainboards,
but might work with older BMC, too.
Tested on X11SSH-TF:
The BIOS version strings are updated on boot and are visible in the
BMC web UI.
Change-Id: I51c22f83383affb70abb0efbcdc33ea925b5ff9f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Only one EEPROM is used to store the board settings, and its I2C address
is constant. Thus, there's no need to pass its address as a parameter.
In addition, reduce the scope of the `I2C_ADDR_EEPROM` definition, since
using it outside of eeprom.c would bypass the API's abstraction layer.
Change-Id: I958304e6ed6df05af923139d44ff4fd1de204738
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Drop chipset register definitions in mainboard code in favor of existing
definitions in a header. These definitions are not mainboard-specific.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I29d6f35ec27bff43cf52ae697e905b6a7b48a8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch add SSD D3 cold support for lindar.
BUG=b:172405687
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ie343bbff3bde4ff2a7e89bd384d5661af372b560
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48651
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:169356808
TEST=tested on voema
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I28ef074225c533e1a97b6ec4a1a5dd1dcc198168
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48848
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Leverage existing `ch_dimms` value and use constants for brevity.
Change-Id: I4e08166c8e9fbd15ff1dcd266abb0689e4b159f7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Pointers to structs can be very useful, especially when they point to an
array element. In this case, changing one pointer allows the function to
be rewritten more concisely, since most redundancy can be eliminated.
Tested on Asus P8Z77-V LX2, still boots. No functional difference.
Change-Id: I7f0c37ea49db640f197162f371165a6f8e9c1b9c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Ensure that IOSAV is finished before continuing. This might solve some
random failures on the I/O and roundtrip latency training algorithm.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic08a40346b6c60e372bada10f9c4ee42eb974f9f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48403
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Most ofte, `iosav_run_once` precedes a `wait_for_iosav` call. Add a
helper function to reduce clutter. The cases where `iosav_run_once`
isn't followed by `wait_for_iosav` will be handled in a follow-up.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: Ic76f53c2db41512287f41b696a0c4df42a5e0f12
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48402
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These comments were helpful before the massive IOSAV refactoring, but
they are no longer needed since the function names are clear enough.
Change-Id: Ieb9bdf3f7fc72f63a8978f2b98e0bc8228c55868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48401
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print delay values in a suitable format for human consumption.
Change-Id: I0d86187d3e458ee2cb3fd11ec896ac363b8d3249
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48400
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Now that the purpose of each training algorithm is clear, replace the
last instances of the original names in comments and print statements
with the current, correct names. Also, print which channel has failed
command training, for completeness and consistency with other errors.
Change-Id: I9cc5c4b04499297825ca004c6bd1648a68449d2c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48601
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on Asus P8H61-M PRO, still boots.
Change-Id: I147ba0ade8a5317a0fe76e9ea84947fd91d794b4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47773
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Refactor in preparation to split up `program_timings`.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I68410165f397d8b4f662e40e88fb6a58ab1c5cff
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47772
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use absolute values for the Rx and Tx bus timings instead of values
relative to the CA (Command/Address) bus timing. This makes the
calculations more accurate, less complex and less error-prone.
Tested on Asus P8H61-M PRO, still boots. Training results do not seem to
be affected by this patch, and the margins roughly have the same shape.
Change-Id: I28ff1bdaadf1fcbca6a5e5ccdd456de683206410
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47771
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This file was being written to the root src directory. It is the only
file being written to src during a normal build, while all others are
being written to $(obj). I added a new variable to allow specifying the
xcompile path. This allows generating a single file if building multiple
boards. I also moved the default location into $(obj) so we don't
pollute the src directory by default.
I also cleaned up the generation of xcompile by removing the unnecessary
eval and NOCOMPILE check.
I also left .xcompile in distclean so it cleans up stale files.
Since .xcompile is written into $(obj), `make clean` will now remove it.
The tegra Makefiles are outside of the normal build process, so I just
updated those Makefiles to point to the default xcompile location of a
normal build. The what-jenkins-does target had to be updated to support
these special targets. We generate an xcompile specifically for these
targets and pass it into the Makefile. Ideally we should get these
targets added to the main build.
BUG=b:112267918
TEST=ran `emerge-grunt coreboot` and `make what-jenkins-does`
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: Ia83f234447b977efa824751c9674154b77d606b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Commit 56fcfb5 misused the PCH_DEVFNs passed to the XHCI elog driver, by
passing them directly to pci_s_read_config32. This is incorrect, as it
is the wrong PCI devfn encoding to pass to that function.
BUG=b:175996770
TEST=abuild
Change-Id: Id7c146c1f50ee64a725bd50f9f11a7f159013a2b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48827
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Current implementation uses CPUID 0Bh function that returns the number
of logical cores of requested level. The problem with this approach is
that this value doesn't change when HyperThreading is disabled (it's in
the Intel docs), so it breaks generate_cpu_entries() because `numcpus`
ends up being zero due to integer division truncation.
- Use MSR 0x35 instead, which returns the correct number of logical
processors with and without HT.
- Use cpu_read_topology() to gather the required information
Tested on Prodrive Hermes, the ACPI code is now generated even with
HyperThreading disabled.
Change-Id: Id9b985a07cd3f99a823622f766c80ff240ac1188
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Following up 3ccae2b7, this patch adds Iccmax and AC/DC
loadlines and iPL2 for CML-S CPUs. The information is from
CML EDS volume 1, doc #606599 and pdg #610244.
Change-Id: Id2797a979a8b6a52a34baae66f95c7136ed1dc72
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38288
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
According to doc# IHD-OS-BXT-Vol 2b-05.17 the cycle delay is in the bit
range 8:4 of register PP_CONTROL. The current code writes the value to
bits 4:0, though. Correct that by shifting the value left by 4 bits.
Change-Id: If407932c847da39b19e307368c9e52ba1c93bccd
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The CHROMEOS option was never used with ibexpeak, code was copy-pasted
and forked from bd82x6x. Since a custom ibexpeak/nvs.h was already made,
an accompanying globalnvs.asl is added here too without chromeos_acpi_t.
Change-Id: I16406516b51c13d49593bc8a3e1e5b868eea6f24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48766
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Files under sb/ or soc/ should not have includes that tie those
directly to external components like ChromeEC os ChromeOS
vendorcode.
Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
psp.h was first included when Stoney Ridge began loading the first
SMU firmware. That step was later moved from bootblock to romstage.
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: Id646390ce377143d09455f797de1b149dbb615b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48797
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Move gpio early init to bootblock_mainboard_early_init to make the
bootblock console work as early as possible.
Change-Id: I619f7d0e15adae284b606dd20c3c1f04f3eafd7b
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48801
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 1a0071c711.
Reason for revert:
UART pad configuration should not be done in common code, since it
could cause short circuits if the user configures a wrong UART index.
Change-Id: I6022935eaab748f82c6330be0729ff72f4880493
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Add enable acp_i2s_use_external_48mhz_osc flag and then
WWAN sku will use external clock source at next build.
BUG=b:174121847
BRANCH=zork
TEST=build vilboz and check MISC_CLK_CNTL1.
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Memory PLL is used to provide the basic clock for dram controller
and DDRPHY. PLL must be initialized as predefined way.
First, enable PLL POWER and ISO, wait at least 30us, release ISO, then
configure PLL frequency and enable PLL master switch.
At last, enable control ability for SPM to switch between active and
idle when system is switched between normal and low power mode.
TEST=Confirm Memory PLL frequency is right by frequency meter
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: Ieb4e6cbf19da53d653872b166d3191c7b010dca6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44702
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Use the common block ACPI to further reduce the duplicate code.
Change-Id: If28d75cbb2a88363d70e3ae6a2cace46cb6bbbab
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48248
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit ccceb2250e.
Reason for revert:
UART pad configuration should not be done in common code, since it
could cause short circuits if the user configures a wrong UART index.
Change-Id: Idc268debc60a027ed2f5a76e0de8ea2d1cde0fc4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48327
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Test results show that USB signals look better with these settings.
Yes, there's a macro in the devicetree now. All ports use the same
settings except for the overcurrent pin, so this avoids redundancy.
Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The latest version defined by TCG is 1.3.
Change-Id: Idb12e2212d6d38c720c8fe989678724c871af6ef
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45569
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implement the ACPI PPI interface as described in
"TCG PC Client Physical Presence Interface Specification" Version 1.3.
Add a new Kconfig that allows to use the full PPI instead of the stub
version compiled in.
This doesn't add code to execute the PPI request, as that's up to the
payload with graphical UI support.
Tested on GNU/Linux 5.6 using the sysfs interface at:
/sys/class/tpm/tpm0/ppi/
Change-Id: Ifffe1d9b715e2c37568e1b009e86c298025c89ac
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45568
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add supported memory parts in the mem_parts_used.txt and generate the
SPD ID for the memory parts. The memory parts being added are:
MT53E512M32D2NP-046 WT:E
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
H9HCNNNCPMMLXR-NEE
BUG=None
TEST=Build the storo board.
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Update devicetree and gpio driving of boten that enable stylus
PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel
driver expects the pad to be owned by GPIO controller (i.e. configured for
GPIO IRQ), it cannot be configured for ACPI (i.e. SCI).
Thus, this change updates the GPIO configuration for GPP_C12 to
PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to
use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active
low in the device tree entry to indicate to the kernel driver that the signal
is inverted.
Not dual routing the signal results in wake source not being added to
eventlog when pen removal results in wake from S0ix.
BUG=b:160752604
BRANCH=dedede
TEST=Build and check behavior is expected.
Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com>
Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Don't depend on the MTRR setup left over from FSP-M ExitTempRam.
Change-Id: I299123b3cd3c37b4345102c20fda77bf261892a2
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:161270810
TEST=tested on eldrid
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Add a hook for SOCs to provide an IOAPIC MADT table. If the
SOC doesn't provide a table then a standard setting is used.
Change-Id: Ic818a634e4912d88ef93971deb4da5ab708c9020
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change static calculate_power() function to global and update the name
to common_calculate_power_ratio() for SOC ACPI code use.
Change-Id: I0e2d118ad52b36859bfc6029b7dee946193841f4
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48739
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
When a different FSP binary was chosen in menuconfig, the split fd files
do not get updated. Thus, make them depend on `.config` to trigger a
rebuild when the config changes.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I54739eae50fa1a47bf8f3fe2e79334bc7f7ac3d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Falling back to default values for Imon slope and offset for Drawcia
This is as per recommendation from ODM based on calibration
This reverts commit 2ac88f2347.
BUG=b:175629526
BRANCH=dedede
TEST=Debug FSP confirms that values are reverted to default
Change-Id: I605acdcd0de2c5dfc28af2aea8cefc6b629c0925
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable Acoustic noise mitigation for madoo and set slew rate to 1/8
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:173765599
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.
Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
UART pads already get configured in bootblock by the UART driver in soc
code. Thus, drop the duplicated code from the mainboard.
Tested successfully on Clevo L141CU.
Change-Id: I05a459b0af79c75c31b1bb26ea1a1a40857ef9bf
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Move sb_clk_output_48Mhz out of acp. It should be called unconditionally.
We may have another device need this clock e.g. superio chip.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I30ad6c60066f17cc83e7feb40675610f4853a022
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
If we have use external clock source for I2S, we don't need to enable
internal one. Add acp_i2s_use_external_48mhz_osc flag for the project
which uses external clock source.
BUG=b:174121847
BRANCH=zork
TEST= build passed
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ica68ee2da5a05231eb6db0218bd0f19907507273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This still uses the common GPIO code that supports setting up SMI/SCI
support for the GPIOs in all stages, which will get removed in future
patches, so for now the SoC's gpio.c needs to be included in all stages.
Change-Id: I6c12d1d6c605b7eb063eef62a1f71860f602f8dd
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48565
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The `azalia_set_bits` will mask out all bits, so just use zero for
clarity. The resulting behavior is the same in both cases.
Change-Id: I27777f1e836fa973859629d48964060bec02c87a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48357
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
coreboot already unconditionally enables CLKRUN_EN in SoC common code.
Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN]
of LPC is still enabled.
Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5
Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Many uses of `azalia_set_bits` are used to toggle the reset bit. To
avoid having to repeat the register operations and the corresponding
comment, create two helpers with self-explanatory names. They will be
put to use in subsequent commits, with one change for each function.
Change-Id: If0594fdaf99319f08a2e272cd37958f0f216e654
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The `4` here doesn't have to do with the size of u32. Instead, it is
because the verb header contains the number of jacks, which is the
number of four-verb groups.
Change-Id: I3956ce5ec2a7abc29982504cf75b262a1c098af5
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This function is equivalent to `azalia_find_verb` in its current form,
so replace them. Also, adapt and move the function description comment.
Change-Id: I40d1e634c31b00bd7808a651990d9bd6f0d054e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Allow to specify which table should the verb list be read from.
Change-Id: Id1bc40c4364cda848f416bad9eeab1b8ca3e9512
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48350
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
To allow dropping copies of this function, make it non-static. Also,
rename it to `azalia_find_verb` as the function is now globally visible.
Finally, replace the copies in chipset code with `azalia_find_verb`.
Change-Id: Ie66323b2c62139e86d3d7e003f6653a3def7b5f2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The other five copies of this function in the tree do not have these
debug prints. Remove them from here for consistency. Note that this
information is already printed elsewhere, so nothing is being lost.
Change-Id: I999032af1628bf8d66a057dc72368f02ef6eb8d1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
There's many copies of this function in the tree. Make the copy in
azalia_device.c non-static and rename it to `azalia_set_bits`, then
replace all other copies with it. Since azalia_device.c is only built
when AZALIA_PLUGIN_SUPPORT is selected, select it where necessary.
This has the side-effect of building hda_verb.c from the mainboard
directory. If this patch happens to break audio on a mainboard, it's
because its hda_verb.c was always wrong but wasn't being compiled.
Change-Id: Iff3520131ec7bc8554612969e3a2fe9cdbc9305e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
One of the variants lacks an hda_verb.h, and hda_verb.c can't be built.
Follow-up changes will make mainboard hda_verb.c files always get built
through AZALIA_PLUGIN_SUPPORT, and breaks building this contraption.
Turn the headers into standalone compilation units to prevent this
issue. Since they contain definitions, including them from multiple
compilation units wasn't a good idea anyway.
Change-Id: I00d968563539a4e1b8d1e12145293439d8358555
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48360
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum)
in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0.
TXVREFTUNE0: 0xf -> 0xd
BUG=b:172687208
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
For arch/arm[64], the offsets to board identification strings and
CONFIG_ROM_SIZE inside .id were never really used; it was only a
convenience to have the strings appear near the start of image.
Add the same strings in an uncompressed file in CBFS.
Change-Id: I35d3312336e9c66d657d2ca619cf30fd79e18fd4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47602
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The strings in .id are expected to match the build for
the purpose of identifying the binary image. There is
no identified use for the offsets.
The files id.ld and prologue.inc were unused.
Change-Id: Ida332671e0ace3f6afd11020474ffda04614bad5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The location is hardcoded inside flashrom and FILO.
Only two offsets are supported, 0x10 and 0x80.
Change-Id: I8348f2ac0cab969ab78ecb50a55de486eee0cf9b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47598
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change enables PCIEXP_HOTPLUG to support resource allocation for
TCSS TBT/USB4 ports.
Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543
Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Guybrush is a new Google mainboard with an AMD SOC.
BUG=b:175143925
TEST=builds
Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on
xeon_sp and denverton_ns. This allows to set test config UPDs from
mainboard code as well.
Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple indepent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or
fb_new_framebuffer_info_from_edid.
Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
On SKX FSP-M does not return if this is set too early.
Tested on OCP/Tiogapass, boots.
Change-Id: Ib8ef7bab36bfd4b62988768753d10b4d7b7d567f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48657
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is
accessed to read out or reconfigure the HPET and PCH IOAPIC BDF.
Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The local function names were chosen such that they don't
collide with <gpio.h> so the prefix is unnecessary.
Change-Id: I4799a6d6b87e8081324d88b0773e61cbda0d4cfb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Followup work forces gdtptr and gdt towards the top of
bootblock. They need to be realmode-addressable, i.e.
within top 64 KiB or same segment with .reset.
Change-Id: Ib6f23b2808d0a7e0d277d00a9b0f30c49fdefdd5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
We have identical gdtptr16 and gdtptr. The reference in
gdtptr_offset calculation is not accounted for when
considering --gc-sections, so to support linking
gdt_init.S separately add dummy use of gdtptr symbol.
Realmode execution already accessed gdt that was located
outside [_start16bit,_estart16bit] region. Remove latter
symbol as the former was not really a start of region,
but entry point symbol.
With the romcc bootblock solution, entry32.inc may have
been linked into romstage before, but the !ENV_BOOTBLOCK
case seems obsolete now.
Change-Id: I0a3f6aeb217ca4e38b936b8c9ec8b0b69732cbb9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add wifi sar for magolor and maglia:
Using tablet mode of fw config to decide to load custom wifi sar or not.
same wifi sar value for magolor and maglia (shared firmware)
BUG=b:173001370, b:173001251
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Cq-Depend: chrome-internal:3453724
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds memory part used by variant sasuke to
mem_part_used.txt and generates DRAM ID allocated to the part.
BUG=b:172104731
Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451
Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The voltage of vm18 should be microvolt instead of millivolt.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: Iea5b46c1df358dc350506d29cc033d01631b37b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48110
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Keep the CONN MCU in reset state to prevent CONN from asserting the
clk26m request to SPM.
TEST=clk26m request from conn has been released.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia1b706da497ba2827341051459c3628e2ae9240f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Newer kernels can re-schedule new acpi command calls during a Sleep().
This causes that the following trace fails to detect the cameras:
[ 15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start
[ 15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start
[ 15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start
[ 15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start
[ 15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end
ERROR!!
[ 16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end
Which can be triggered more frequently if the Sleep() commands in OVTH
_ON Method are increased.
To avoid the race condition, we create a new Power Resource that
handles the common resources of both cameras and make both cameras
depend on that resource. This also simplifies the acpi table by removing
a Mutex.
BRANCH=poppy
BUG=b:171955583
TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then break; fi; ssh $DUT reboot; sleep 30 ; done
Signed-off-by: Ricardo Ribalda <ribalda@chromium.org>
Change-Id: I25df0225699759c1828b8791c5bdee66529858a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48631
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
After checked, this project doesn't need this feature.
BUG=b:173066178
BRANCH=zork
TEST=check no WRDD method in acpi.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I9a662953f3047d771f2df919ac80d0440842738e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48621
Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use a FMAP region to cache SPD data, providing improvements in boot
time and detection of change in DIMM population (which FSP will
sometimes fail to detect / fail to invalidate the MRC cache).
Adapted from implementation used in google/hatch.
Test: build/boot Librem Mini v2, verify SPD cache used, changes
in DIMM population properly detected.
Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48549
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds support zinitix touchpad for casta/bluebird.
BRANCH=firmware-octopus-11297.B
BUG=b:175618033
TEST=built and verified touchpad worked on casta
Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
UFS reference clock (refclk) is enabled by default, which will cause
the UFSHCI to hold the SPM signal and lead to suspend failure. Since
UFS kernel driver is not built-in, disable refclk in coreboot stage.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Chaotian Jing <chaotian.jing@mediatek.com>
Change-Id: If11c1b756ad1a0b85f1005f56a6cb4648c687cf0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
GEVENT_MASK should cover all GEVENT pins, but was missing
SMITYPE_G_AGPIO9 and SMITYPE_G_AGPIO8.
Change-Id: Ia676476e2d2cf468d82d6d90e9fc11d34f56f153
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48483
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Base address symbols for ACPIMMIO banks that would not get
assigned at runtime must not resolve at linker-stage either.
The build of PSP-verstage should pass without the preprocessor
macros that have x86-centric view of memory space.
Change-Id: I3cb1b5a90023ebc4359835be716c5e3f9451df60
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The file seems to be all about PCI configuration access.
Change-Id: I1e64d3d7df3caa33ee92961fe7246d03f2707ab4
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43328
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The region top_of_ram -> cbmem_top is used by FSP and cbmem, but is
also just regular DRAM. Marking it as such improves the final MTRR
solution a lot and fixes MTRR starvation depending on the setup.
Change-Id: I19ff7cf2d699b4cc34caccd91cafd6a284d699d3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47868
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While the Librem Mini (v1/v2) are more than capable of higher
PL1/2, they currently ship with a 40W power supply, so set PL1/2
accordingly to avoid power spikes above the PSU rating (which can
result in unexpected showdowns/reboots)
Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kukui based devices may use different speaker amplifiers, for example
MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying
which component was installed on board, we want to pass the speaker GPIO
in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME.
BUG=b:174534548
TEST=emerge-kukui coreboot depthcharge chromeos-bootimage
BRANCH=kukui
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Program IA32_CR_SF_QOS_MASK_x MSRs under CAR_HAS_SF_MASKS config
option. Select CAR_HAS_SF_MASKS for Tigerlake.
During CAR teardown code, MSRs IA32_L3_MASK_x & IA32_CR_SF_QOS_MASK_x
are not being reset to default as
per the doc NEM-Enhanced-Mode-Whitepaper-Tigerlake-draft-WW46.5.
Resetting the value of IA32_PQR_ASSOC[32:33] to 00b is sufficient.
Bug=b:171601324
BRANCH=volteer
Test=Build and boot to ChromeOS on Delbin.
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Change-Id: Iabf7f387fb5887aca10158788599452c3f2df7e8
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
SF Mask MSRs' Programming which was done under this config
selection will be moved under a new config option called
CAR_HAS_SF_MASKS. This segregates the eNEM programming
sequence based on sub features supported in each processor.
Bug=b:171601324
BRANCH=volteer
Test=Build volteer build and boot on Delbin EVT.
Change-Id: If4d8d1ec52b7b79965fe1a957c48f571ec56dc63
Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Using `pci_dev_read_resources` works just as well on bd82x6x (the
allocator does the same) and allows dropping the i82801gx check.
Change-Id: I1cb05131a82ebb7c45827eff8e09e445d9c695b3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48538
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
* Drop PcieRpSlotImplemented on internal slots
* Add PCIe port 15 that connected to CNVi/M.2 E
Change-Id: Iaa05affa760b447fc1725e674b12366684a63720
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This patch sets up cse_fw_sync() call in the romstage. The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Tigerlake platform
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Ib485a4d1d15989b162105deb32bb317d7a0f2856
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48281
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch sets up cse_fw_sync() call in the romstage.The cse_fw_sync()
must be called after DRAM initialization.
BUG=b:174694480
Test=Verified on Drawlet
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I43030e77f6ede53c23e6c9e65d34db85c141e13a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48280
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The patch sets up the CSE Lite driver in the romstage instead of ramstage.
With this change, CSE Lite driver sets CSE's boot partition and triggers
CSE FW update in the romstage. The cse_fw_sync() must be called after DRAM
initialization as HMRFPO_ENABLE HECI command (which is used by
cse_fw_sync()) is expected to be executed after DRAM initialization. With
this change, it improves the cold boot time by ~154ms.
Test=Verified on JSL and TGL platforms
BUG=b:174694480
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I2fd562a5c6c8501226abbcb68021d9356bcf0b73
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48279
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch modifies CSE Lite driver to use 'if' C-lanugage construct
instead of #if macro and adds 'if SOC_INTEL_CSE_RW_UPDATE' to the prompts
of CSE Update related KConfigs to prevent appearing them in the menu.
TEST=Built the code for drawcia
Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: Iecd5cf56ecd280de920f479e174762fe6b4164b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
SoC selects HAVE_SMI_HANDLER, so TsegSize is always set to 8 MiB. Also,
use SMM_TSEG_SIZE in place of a magic number.
Change-Id: I139e1073426051fea5d30b6ce3dd9746e0e985a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48578
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Only Google Eve uses a non-zero value, but it overwrites in C code.
Drop the devicetree setting, since no mainboard uses it.
Change-Id: I14e0e0cb9baa2b1f8f795e6bc6ffbee300f2243d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
TESTED on ocp/tiagopass: Microcode updates are properly applied (via
FIT). Tested with out of tree patches to report the revision.
Change-Id: I05ddc64090424aa333848d9a0f54f21538faf94c
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The upcoming Librem 14 variant won't use the same SATA HSIO adjustments
as the Librem Mini, so move these settings into a variant-specific file.
Rename existing gpio.h to variant.h, move to board root directory, and
use for all variant-specific declarations; adjust references as needed.
Add newly-created variant.c to Makefile.
Test: build/boot Librem Mini, verify SATA functionality unchanged.
Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Configure DPR to span the region between cbmem_top and TSEG base.
This region was already unavailable to the OS.
Change-Id: Ia0d34e50b3d577f19172619156352534f740ea6b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46818
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Packing bootblock sections is somewhat easier to understand
when these all appear in one .ld file.
Change-Id: Ie8629a89fa47a28db63ecc33c631b29ac5a77448
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Currently, the option to cache DIMM SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Add a Kconfig option for the region name, replacing the existing hard-
coded instance in spd_cache.h. Change the inclusion of spd_cache.c to
use this new Kconfig, rather than the board-specific one currently used.
Lastly, have google/hatch select the new Kconfig when appropriate to
ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Also tested on an out-of-tree Purism board.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Currently it's not possible to add multiple graphics drivers into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics drivers can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel+Aspeed on server platforms or
Intel+Nvidia on consumer notebooks.
The goal is to remove duplicated fill_fb_framebuffer(), the advertisment
of multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Replace all duplications of fill_fb_framebuffer and provide a single one
in edid_fill_fb.c. Should not change the current behaviour as still only
one graphic driver can be active at time.
Change-Id: Ife507f7e7beaf59854e533551b4b87ea6980c1f4
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39003
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Unset devicetree options already default to zero. Note that this setting
is not referenced anywhere else, and will be removed in a follow-up.
Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Update USB & PCIe devices in ASL files as per EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I8b567127fbdd880ccc0a5e0ca334162f9f4f5164
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Add I2C #6 & #7 and remove GSPI #3 as per EHL EDS.
Also update device function number for GSPI #2 in asl file.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: If166fefe567a857ca29527d0367197139efbf6c7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48540
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For EHL, SpiProtectionMode is added to HFSTS register #1.
The original Manufacturing Mode is detected via FpfSocConfigLock
instead. If FpfSocConfigLock=1, means it is in Menufacturing Mode,
and it is in EOM (End Of Manufacturing) when FpfSocConfigLock=0.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9d1d004a6b5b276e33be80f02cd1197b88d379ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48539
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The mt8183 dsi driver can be shared with mt819x SoC.
Move dsi.c to common/ folder and rename it to dis_v2.c to
differentiate it from mt8173's dsi driver.
TEST=emerge-kukuki coreboot
Change-Id: I722d3e67f230ab8eb729900cdf15b922eb91a072
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Add I2C controller for MT8192, and revise the common I2C driver
to support I2C controller running in APDMA async mode. In that
case we have to initiate a different handshake protocol and reset
I2C differently.
BUG=b:155715435
TEST=Asurada boots up to shell
Signed-off-by: Qii Wang <qii.wang@mediatek.com>
Change-Id: I13835e00eb674a93aa5496a9870d1e601e263368
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47800
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.
BUG=b:175386410
Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
The code can likely be factored out to common code, but since I'm not
entirely sure yet that there will be no differences, I'll copy for now
instead.
Change-Id: I5fc158518cf9534ab9727f3305abeb4b34049e76
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48517
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Clarify the clock, command and control programming sequence.
Tested on Asus P8Z77-V LX2, still boots.
Change-Id: I1aa4144197dc25dc8d6ef1d23e465280bddd95a3
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47770
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
John Zhao