Any platform should need just one of these.
Change-Id: Ia0ff8eff152cbd3d82e8b372ec662d3737078d35
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34820
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Get rid of this function and its dangerous, weak implementation.
Instead, call pmc_set_power_failure_state() directly from the SMI
handler.
Change-Id: I0718afc5db66447c93289643f9097a4257b10934
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Needed some Makefile changes to be able to compile for SMM.
Change-Id: Ibf218b90088a45349c54f4b881e895bb852e88bb
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31352
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is a consolidation of the respective feature in `soc/intel/*lake/`,
including additional support for MAINBOARD_POWER_STATE_PREVIOUS.
For the latter, firmware has to keep track of the `previous` state. The
feature was already advertised in Kconfig long ago, but not implemented.
SoC code has to call pmc_set_power_failure_state() at least once during
boot and needs to implement pmc_soc_set_afterg3_en() for the actual
register write.
Change-Id: Ic6970a79d9b95373c2855f4c92232d2aa05963bb
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34724
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently SPI bus id is used to map to the controller in order to set
the controller state. In certain platforms SPI bus id might not be
exactly the same as GSPI bus id. For example, in Intel platforms SPI bus
id 0 maps to fast spi i.e. SPI going to the flash and SPI bus id 1 .. n
map to GSPI bus id 0 .. n-1. Hence using SPI bus id leads to mapping to the
GSPI controller that is not enabled. Use the GSPI id bus so that the right
controller is set to active state. This fixes the regression introduced
by CB:34449
BUG=b:135941367
TEST=Boot to ChromeOS.
Change-Id: I792ab1fa6529f5317218896ad05321f8f17cedcd
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This is declared weak so that platforms that do not
have smm_subregion() can provide their own implementation.
Change-Id: Ide815b45cbc21a295b8e58434644e82920e84e31
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No need to limit these declarations to FSP. Both
PARALLEL_MP_INIT smm_relocate() and TSEG_STAGE_CACHE
can be built on top of this.
Change-Id: I7b0b9b8c8bee03aabe251c50c47dc42f6596e169
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34701
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Add an API to check if device is a LPSS controller. This API can be
used for IRQ assignments for LPSS PCI controllers, since the LPSS
controllers have a requirement of unique IRQ assignments and do not
share same IRQ# with other LPSS controllers.
SOC code is reponsible to provide list of the LPSS controllers
supported and needs to implement soc_lpss_controllers_list API,
in case it needs to use this common implementation.
Change-Id: I3f5bb268fc581280bb1b87b6b175a0299a24a44a
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34137
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This implementation revises the UART PCI device reference in common
UART driver. The SOC functions have been aligned to provide the UART
PCI device reference using pcidev_path_on_root.
The uart_get_device() return type is changed, and files in which
it gets used are updated.
Change-Id: Ie0fe5991f3b0b9c596c3de9472e98e4091d7dd87
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34582
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch ...
- adds the PCH ID for C232 chipset,
- renames "Premium" chipset to "HM170" (because of same IDs),
- reorders the Skylake-H PCH IDs ascending by hex values.
Used documents:
- Intel 332690-005EN
Change-Id: I859975fe7bcd3c10dead8fe150a2fbead9c64a51
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
The initial implementation was assigning the devfn as PCI device
reference directly which was incorrect.
Change-Id: Iad57e9bc6b2acf1823ee38116aea8a93feece6f9
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE.
Change-Id: Ibd1e669fcbfe8dc6e6e5556aa5b1373ed19c3685
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33129
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This reverts commit 46445155ea.
Reason for revert: Breaks coreboot. Either no UART working or the
complete boot process stops.
Platform: Intel Apollolake, tested on Up Squared
Change-Id: If581f42e423caa76deb4ecf67296a7c2f1f7705d
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
sequence for CML and ICL platforms.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Set the controller state to D0 during the uart init sequence, this
ensures the controller is up and active.
One more argument struct device *dev has been added
to uart_lpss_init function for the same.
BUG=b:135941367
TEST=Verify no timeouts seen during UART controller enumeration
sequence in CML and ICL platforms.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I0187267670e1dea3e1d5e83d0b29967724d6063e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34447
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All the PCI accesses in the file are now accessed
without SA_DEV_ROOT expanding to function call.
Change-Id: I30d331e9c18a486ea971e8397a6e20a0f82d5f84
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34410
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to the documentation [1], by default the RX Level/Edge Trig
Configuration set to disable (2h = Drive '0') for each pad. Since this
setting doesn't matter for the GPO pad, there is no need to change the
default value for such pads. The patch updates PAD_CFG_GPO* macros to
set trig to disable. It also resolves some problems of creating the
PCH/SoC pads configuration based on information from the inteltool
dump [2,3]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/34337
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
Change-Id: I39ba83ffaad57656f31147fc72d7a708e5f61163
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
In the case there is no the circuit diagram for motherboard, the
PCH/SoC GPIOs config is based on information from the inteltool
dump. However, available macros from gpio_defs.h can't define the
pad configuration from this dump:
0x0440: 0x0000002084000500 GPP_A8 CLKRUN#
0x0448: 0x0000102184000600 GPP_A9 CLKOUT_LPC0
0x0450: 0x0000102284000600 GPP_A10 CLKOUT_LPC1
To convert these raw DW0/DW1 register values to macros, the following
parameters must be set:
func - pad function,
pull - termination,
rst - pad reset config,
trig - rx level/edge configuration,
bufdis - rx/tx (in/output) buffer disable.
The patch resolves the above problem by adding a new macro for the
native function configuration:
PAD_CFG_NF_BUF_TRIG(pad, pull, rst, func, bufdis, trig)
These changes were tested on Asrock H110M-DVS motherboard [2].
It also resolves the problem of automatically creating pads
configuration [3,4]
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
https://www.intel.com/content/dam/www/public/us/en/documents/
datasheets/100-series-chipset-datasheet-vol-2.pdf
[2] https://review.coreboot.org/c/coreboot/+/33565
[3] https://github.com/maxpoliak/pch-pads-parser/issues/1
[4] https://github.com/maxpoliak/pch-pads-parser/commit/215d303
Change-Id: If9fe50ff9a680633db6228564345200c0e1ee3ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34337
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add API to disable USB devices that are not present but are configured
in the device tree either after probing the concerned port status or as
explicitly configured by the variants.
BUG=None
BRANCH=octopus
TEST=Boot to ChromeOS.
Change-Id: Ied12faabee1b8c096f2b27de89ab42ee8be5d94d
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33377
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It feels appropriate to define SoC specific XHCI USB info in SoC
specific XHCI source file and an API to get that information instead of
defining it in elog source file. This will help in other situations
where the information is required.
BUG=None
BRANCH=None
TEST=Boot to ChromeOS.
Change-Id: Ie63a29a7096bfcaab87baaae947b786ab2345ed1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34290
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
- Add CPU, MCH & IGD IDs for new Coffeelake SKUs
- Add PCH, LPC, SPI IDs for CNP-H PCH CM246 & C246
- Make some minor alignments & naming corrections to align with the rest
TEST= build, boot to both Linux & windows OS on CFL H & S platforms
and verified all the device Id's in serial console logs.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I343b11ea8d9c33eb189d7478511a473b145f4ab4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Set the controller state to D0 during the i2c init sequence, this ensures
the controller is up and active.
BUG=b:135941367
TEST=Verify no timeouts seen during I2C controller enumeration sequence
Change-Id: I247ede44b8d1d6871e3e813b63f99a7f6398dd72
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34273
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add function to set the power state of a LPSS controller.
The API implemented can be used to enforce controllers in
active state(D0) during initialization.
BUG=b:135941367
Change-Id: I7540924885350de64caff91d920d6cc234154616
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34272
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These constants are needed in some ASL files, even when
__ACPI__ is defined.
Change-Id: I0f4f00b93d5d45794b7c9e0f72b51f3191eb3902
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34177
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Clang Static Analyzer version 8.0.0 detects that the result of
log2_ceil(bios_size) and log2_ceil(window_size) is undefined if the
value of bios_size and window_size are negative. Add negative value
Check for bios_size and window_size after MIN operation.
Change-Id: I28577b6e0ba0ab45bb7804c17ba1f26c4b078b15
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Only CONFIG_USE_INTEL_FSP_MP_INIT makes a difference whether native MP
init is used or not.
Also make USE_INTEL_FSP_MP_INIT mutually exclusive with
USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI as this option requires
coreboot to set up AP and publish PPI based on it.
Change-Id: I65b80805d3cd7b66f8c9f878d3c741b98f24288d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33357
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per EDS Sata port implemented register is byte width (bits[3:0]) hence
converting required DWORD based read/write to BYTE width read/write.
TEST=Able to boot from SATA device on CML hatch.
Change-Id: I545b823318bae461137d41a4490117eba7c87330
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34070
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
While running the s0ix cycling test, we observed SMM Handler caused
a stack overflow. This error happens during event log access.
This change is to increase the SMM_MODULE_STACK size to 0x800
BUG=b:135551854
TEST=suspend_resume test pass 500+ cycles, originally issue happenes
within 150 cycle
Change-Id: Ib4686b4d2d4fc3976068779314f4ee15ef4a8ae2
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This patch relying on new rule, ENV_PAYLOAD_LOADER which is set
to ENV_RAMSTAGE.
This approach will help to add future optimization (rampayload) in
coreboot flow if required.
Change-Id: Ib54ece7b9e5f281f8a092dc6f38c07406edfa5fa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
The DIMM manufacturing ID was not being initialized and so the DIMMs
were not described in SMBIOS tables properly.
The module type can also be provided, but the SMBIOS code expects
SPD module type values from DDR2 so the DDR3/4 values are adjusted
before sending to SMBIOS.
BUG=b:134897498
BRANCH=sarien
TEST=dump and compare with dmidecode
BEFORE:
Type: DDR4
Manufacturer: Unknown (0)
Form Factor: Unknown
AFTER:
Type: DDR4
Manufacturer: Hynix/Hyundai
Form Factor: SODIMM
Change-Id: Id673e08aa6e3dad196009c3c21a3dda2f40c9e42
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
'else' is not needed after a 'break' or 'return'.
Change-Id: Ib3371ef6edb85a47ed734dd2ff9ce94008aa4e65
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33336
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Vlado Cibic
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures to boot platform without onboard GFX (PCI B0:D2:F0)
enabled from mainboard devicetree.cb.
TEST=Previously platform was dying at "GMADR is not programmed!" with
IGD disabled.
Change-Id: I8c907ee25db4538a84890f2ccc3187afa86604b8
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33449
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch provides an additional option to skip HECI function
disabling using SMM mode for WHL and CML platform, where FSP has
dedicated UPD to make HECI function disable.
User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated
UPD.
Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig
to make HECI disable and WHL/CML has to rely on FSP to make HECI
disable.
Change-Id: If3b064f3c32877235916f966a01beb525156d188
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
As per Icelake EDS PCI device B:D:F (0:0x1f:0) referred as ESPI,
hence modify SoC code to reflect the same.
This patch replaces all SoC specific PCI LPC references with ESPI
except anything that touches intel common code block.
Change-Id: I4990ea6d9b7b4c0eac2b3eea559f5469f086e827
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Skip GT specific programming in coreboot to support early
parts without GT enable.
Change-Id: I231e13367cbfbafbfb0cb4235487dbcbcae76820
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33189
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add Skylake C236 to the PCH Table. The one which was already in there is
actually the CM236 and not the C236. This can be checked in datasheet:
100-series-chipset-datasheet-vol-1 p. 25.
Change-Id: I435927f15e9d3219886375426b09c68632dfe3d9
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33248
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
These are documented in the Intel Datasheet entitled
"6th Generation Intel® Processor Datasheet for S-Platforms"
"6th Generation Intel® Processor Datasheet for H-Platforms" (Volume 2)
Without them, coreboot fails to properly inform the payload of the
amount of available memory.
Signed-off-by: Keno Fischer <keno@juliacomputing.com>
Change-Id: I5b810c6415c4aa0404e5fa318d2c8db292566b8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: ron minnich <rminnich@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add ECC Support and VDD Voltage to dimm_info struct. Now Bus Width
and ECCSupport will be propagated correctly in SMBIOS Type 17 Entry.
Change-Id: Ic6f0d4b223f1490ec7aa71a6105603635b514021
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33031
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Re-add the Kconfig CONSOLE_UART_BASE_ADDRESS. It was lost by accident
on APL at least. It is used outside of soc/intel/ scope, e.g. to con-
figure SeaBIOS.
As we only ever configure a single UART for the coreboot console, we
don't need different addresses for each possible UART. Which saves
us a lot of code.
Change-Id: I28e1d98aa37a6acb57b98b8882fc4fa131d5d309
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Added missing new lines to Debug Output.
Change-Id: I30f208a60661451bc0794c705113e8d19a68b0eb
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33035
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We should only provide this implementation when the Intel LPSS UART is
used. Otherwise, no other UART could be used for the console with these
SoCs.
Change-Id: Iebd89edb3f21d4a68587fd02659b4d529f3f4bbe
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
We only configure the base address for the console UART, the other
addresses are never assigned to the hardware. It seems better to
return 0 for them instead of a spurious value.
Change-Id: I3fa5c99958b56ca5b0b603917c086bdddb677fa2
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
The only path that leads here is guarded by both !DRIVERS_UART_
8250MEM_32 and INTEL_LPSS_UART_FOR_CONSOLE but the latter selects
the former.
Change-Id: I6e0765b028572950991c45b45b2051f4f176a94a
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
gpio_pm_configure clears out all the bits related to PM configuration
in MISCCFG register and sets only the bits requested by mainboard. The
mask as it is set currently results in preserving all PM bits instead
of clearing them. This change updates the mask to ensure that the PM
bits are cleared before setting the ones requested by mainboard.
Change-Id: I5b8c04952775dc1e94fa229328be2f3c1102a468
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Clang Static Analyzer version 8.0.0 detects that log2_ceil(bios_size)
and log2_ceil(window_size) are garbage or undefined if the value of
bios_size and window_size is zero. Check bios_size and window_size after
MIN operation to prevent error.
TEST=Built and boot up to kernel.
Change-Id: Ifc3f3da52d129ef5d6063a46b045603a236be759
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Clang Static Analyzer version 8.0.0 detects the division by zero if
gspi_clk_mhz is initialized to 0. gspi_clk_mhz is referred to speed_mhz
in devicetree. Set gspi_clk_mhz to 1 if it is detected as 0 in order to
prevent the division by zero in DIV_ROUND_UP operation. Then the value
of (ref_clk_mhz - 1) will be fed into GSPI's Serial Clock Rate value.
TEST=Built and boot up to kernel.
Change-Id: I6a09474bff114c57d7a9c4c232bb636ff287e4d5
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
All platforms using this code use NO_CAR_GLOBAL_MIGRATION.
Change-Id: I426dee60521045db4711cd253432c65223a64b93
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: If952ad8129e1fa6e45858cb77ec99c9fec55c4a6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33001
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
All platforms using this code have NO_CAR_GLOBAL_MIGRATION.
Change-Id: I5dfbc718fd82f0511b0049383e4e93c6f15ee932
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32999
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to improve boot time with emmc, add ability to send CMD0
and CMD1 early in romstage. This way, by the time system boots to
payload, we are ready to continue with emmc setup and we don't need
to send CMD0 in payload again, and wait for card to reset and be ready.
BUG=b:78106689
TESTS = Boot to OS
Force early_mmc_wake_hw() to return error, recover in payload
Force an error in payload, make sure system can recover/boot
Change-Id: I3488b077bf5100a1e0f2c879fb1436105607d25e
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25068
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Add a new post code POST_HW_INIT_FAILURE, used when coreboot fails to
detect or initialize a required hardware component.
BUG=b:124401932
BRANCH=sarien
TEST=build coreboot for sarien and arcada platforms
Change-Id: I73820d24b3e1c269d9d446a78ef4f97e167e3552
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This patch adds new function to perform gpio power management
programming as per EDS.
BUG=b:130764684
TEST=Able to build and boot from fixed media on ICL and CML.
Change-Id: I816a70ad92595f013740a235a9799912ad51665e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Fill the DIMM serial number field for SMBIOS from the saved SPD
data that is returned by FSP.
BUG=b:132970635
TEST=This was tested on sarien to ensure that SMBIOS type 17
filled the serial number from the DIMM:
Handle 0x000B, DMI type 17, 40 bytes
Memory Device
Locator: DIMM-A
Serial Number: 41164beb
Change-Id: I85438bd1d581095ea3482dcf077a7f3389f1cd47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
The definition of bootblock_systemagent_early_init was guarded by
!ENV_RAMSTAGE. But it's only called in the bootblock. So guard it
with ENV_BOOTBLOCK instead.
Change-Id: I143cf72e4a63b176e4772575e7a60a2a611e4ad9
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Use CondRefOf to replace config optios for PTS/WAK acpi method dynamic
loading. Then we can move EC PTS and WAK method to be under mainboard.
BUG=N/A
TEST=Build sarien source code, check build/dsdt.dsl have EC.PTS method
included, build whlrvp soure, check build/dsdt.dsl don't have EC.PTS
method. Both able to build pass.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I9f4bd7240832caf070e65039e4ba2d8656371da8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32371
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Added macro named PAD_CFG_GPI_GPIO_DRIVER_SCI, for pads that need to be
configured as GPI, GPIO Driver mode, and SCI interrupt.
Also remove PAD_IRQ_CFG_DUAL_ROUTE macro (subsumed by
PAD_CFG_GPI_IRQ_WAKE).
BUG=none
BRANCH=none
TEST=Compiles
Change-Id: I0332c64e2fa62ce29c772444606adbfdf9c9afc4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32485
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
For GPIO pads that are configured as no-connect (PAD_NC), setting it
as GPI (with Rx enabled) leads to GPE0_STS being set
incorrectly. Though this is not an issue in practice (GPE0_EN is not
set, so no events triggered), it can confuse users when debugging GPE
related issues.
This change configures PAD_NC to have Rx disabled along with Tx to
ensure that it does not end up setting GPE0_STS bits for unwanted
GPIO pads.
P.S.: IOSSTATE config does not have a TxDRxD setting, so leaving that
configuration as is.
BUG=b:129235068
TEST=Verified that GPE0_STS bits are not set for pads that are marked
as PAD_NC.
Change-Id: I726cc7b86a94e7449352cd8a8806d4d775c593dc
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32514
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Add support to reset the GPI Interrupt Status & Enable registers so that
the system does not experience any interrupt storm from a GPI when it
comes out of one of the sleep states.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot up. Ensure that the system boots fine to ChromeOS.
Change-Id: I99f36d88cbab8bb75f12ab1a4d06437f837841cb
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add the offset information for GPI interrupt status and enable register
in the pad_community structure. Populate the concerned information for
individual SoCs. This offset information is required to clear the
interrupt configuration during the bootup.
BUG=b:130593883
BRANCH=None
TEST=Ensure that the interrupt configuration are cleared during bootup.
Ensured that the system boots to ChromeOS.
Change-Id: I8af877a734e8d49b700d720b736da8764985a8f8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Declare plaform level hook method before and after system sleep for
possible power management related usage.
BUG=N/A
TEST=pass with make what-jenkins-does
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ie63711748b6dbb99d34910824f2059464543e162
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32366
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Checking for empty MTRR_DEF_TYPE_MSR as a proxy for proper CPU reset
is common across multiple platforms. Therefore place it in a common
location.
Change-Id: I81d82fb9fe27cd9de6085251fe1a5685cdd651fc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add SMBIOS type 16 table for physical memory array, there's two item had
been left over.ECC and max capacity, as of now we set it to fixed value
as all the platform support by Intel common code don't support ECC
memory and so far the biggest capacity is 32GB.
BUG=b:129485635
TEST=Boot up with Sarien platform and check with dmidecode, the
following is the result:
Handle 0x000D, DMI type 16, 23 bytes
Physical Memory Array
Location: System Board Or Motherboard
Use: System Memory
Error Correction Type: None
Maximum Capacity: 32 GB
Error Information Handle: Not Provided
Number Of Devices: 2
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: If9c5831956ef273c84d831a2b1572b3442eed961
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32286
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures to follow Intel SDM Vol 3B Sec 18.7.3 to
calculate nominal TSC frequency.
As per SDM recommendation:
For any processor in which CPUID.15H is enumerated and
MSR_PLATFORM_INFO[15:8] (which gives the scalable bus frequency) is
available, a more accurate frequency can be obtained by using CPUID.15H
This patch also adds header file to capture Intel processor model number.
BUG=b:129839774
TEST=Boot ICL platform and calculate TSC frequency using below methods
1. TSC freq calculated based on MSR 0xCE
tsc: Detected 1600.000 MHz processor
2. TSC freq calculated based on CPUID 0x15
tsc: Detected 1612.800 MHz TSC
Method 2 actually reduce ~25ms of boot performance time.
Note: Method 2 is recommended from gen 6 processor onwards.
Change-Id: I9ff4b9159a94e61b7e634bd6095f7cc6d7df87c7
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
This patch removes multiple enable/disable function definitions and
make use of single function with argument to know feature status
(enable/disable).
Change-Id: I502cd2497b07e9de062df453ecbb9c11df692f5a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32282
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The policy to identify and log the XHCI wake events is similar between
skylake and apollolake. Hence move the similar parts to a common
location.
BUG=b:123429132
BRANCH=None
TEST=Ensure that the system boots to ChromeOS. Ensure that the wake up
events due to USB are logged into the event logs.
6 | 2019-03-21 09:22:18 | S0ix Enter
7 | 2019-03-21 09:22:22 | S0ix Exit
8 | 2019-03-21 09:22:22 | Wake Source | PME - XHCI (USB 2.0 port) | 9
9 | 2019-03-21 09:22:22 | Wake Source | GPE # | 13
10 | 2019-03-21 09:23:20 | ACPI Enter | S3
11 | 2019-03-21 09:23:30 | Wake Source | PME - XHCI (USB 2.0 port) | 9
12 | 2019-03-21 09:23:30 | ACPI Wake | S3
13 | 2019-03-21 09:23:30 | Wake Source | GPE # | 13
Change-Id: Ia6643342e3292984e422ff3c3fcd4bc0d99f947e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31999
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch ensures to make use of common MP Init Kconfig to
choose desire method to peform MP initialization for platform.
Change-Id: I4ee51276026748e8daf154f89e57095e8fe50280
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
mainboard users can select correct MP Init Kconfig in order to
perform MP initialization.
1. Native coreboot MP Init.
2. FSP to do MP Init.
3. FSP to make use of coreboot MP service PPI to perform MP Initialization
Change-Id: Ifbea463fdaf97d68c21a759c37f49492d58a056b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch removes all local definitions of sub_system functions and make
use of common generic pci_dev_set_subsystem() from PCI bridge and Cardbus
devices as well.
Change-Id: I5fbed39ed448baf11f0e0786ce0ee94741d57237
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Drop 'include <string.h>' when it is not used and
add it when it is missing.
Also extra lines removed, or added just before local includes.
Change-Id: Iccac4dbaa2dd4144fc347af36ecfc9747da3de20
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31966
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Update the Kconfig option for disabling ESPI SMI source
to disable it entirely, not just when ACPI mode is disabled.
For the situations where this is needed (just the sarien
board) it is better to completely stop the EC from sending
any SMI events as no actions are taken.
Change-Id: Id94481bb2f0cfc948f350be45d360bfe40ddf018
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch is a raw application of
find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'
Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This patch adds support H110 chipset (Sunrise Point) for Skylake and
Kaby Lake processor families by adding the corresponding IDs. It has
been tested on ASRock H110M-DVS motherboard (Skylake i5-6600 CPU).
Change-Id: I85ba65ac860687b0f9fd781938e5cac21a1b668d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31602
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds support
1) Intel(R) Xeon(R) E3 - 1200/1500 v5/6th Gen Intel(R) Core(TM) Host
Bridge/DRAM Registers - 191F;
2) HD Graphics 530 Skylake GT2 - Intel integrated graphics processor
https://en.wikichip.org/wiki/intel/hd_graphics/530.
This is required to run coreboot on the Intel Core i5-6600 (Skylake)
desktop processor. It has been tested on ASRock H110M-DVS motherboard.
Change-Id: If47e9ac32813a9f73d3a23f44536f60d1003971d
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31601
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MMIO operations are arch-agnostic so the include
path should not be arch/.
Change-Id: I0fd70f5aeca02e98e96b980c3aca0819f5c44b98
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31691
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Fixes indirect includes that would break with followup work.
Change-Id: I37ca01b904a0b422a4d09475377e755e167a6ab3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31697
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
HDA support did not configure the codecs correclty.
Use Intel common block support to configure the codecs.
To use common Intel HDA support file hda.c file has been
removed and Braswell HDA device ID is added to list of
supported PCI devices in intel/common/block/hda/hda.c.
CONFIG_SOC_INTEL_COMMON_BLOCK and
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA are enabled
to include hda.c in build.
When codec table is available at board level
SOC_INTEL_COMMON_BLOCK_HDA_VERB must be enabled
and a codec table must be supplied.
BUG=N/A
TEST=Facebook FBG-1701 ALC298 configuration
Change-Id: I5c23ec311e5b5a6dfd6f031aa19617407fe8ed63
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/29394
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
New whiskeylake v-0 stepping have changed the graphics device id from
0x3EA0 to 0x3EA1 for celeron, so declare that in common code. Also the
CPUID was changed from 806EB to 806EC, include that as well.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: Ief5213a96507124b90f8dd2eeea2f6bf43843dc6
Reviewed-on: https://review.coreboot.org/c/31433
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
"mosys memory spd print all" returns incorrect memory ranks info.
This patch and 2 upcomming ones (one in FSP) will address the issue.
BUG=b:122329046
TEST=Boot to OS on Bobba variant of Octopus
BRANCH=octopus
Change-Id: I212215040e4786c258a9c604cc5c2bb62867c842
Signed-off-by: Francois Toguo <francois.toguo.fotso@intel.com>
Reviewed-on: https://review.coreboot.org/c/31235
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
According to doc 609208, bit 25 TOL_1V8 in GPP_F4 ~ GPP_F11 DW1
should be clear to prevent unexpected I2C behaviors.
BUG=b:124269499
TEST=boot on nami and check bit 25 TOL_1V8 is clear
Change-Id: I419ef3e89104ad3611e96bbe23a582504b45be0c
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/31368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The default state of the HOSTSW_OWN register in the PCH is zero, which
configures GPIO pins for ACPI ownership. The board variabt GPIO tables
can request specific pins to be configured for GPIO driver ownership.
This change sets the HOSTSW_OWN ownership bit when requested and
explicitly clears the ownership bit if not requested.
BUG=b:120884290
BRANCH=none
TEST=Build coreboot on sarien. Verified UEFI to coreboot transition
boots successfully.
Change-Id: Ia82539dbbbc7cf5dfb9223902d563cafec1a73e5
Signed-off-by: Keith Short <keithshort@chromium.org>
Reviewed-on: https://review.coreboot.org/c/31209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Generate DMAR table if VTd feature is enabled.
Test=Booted into Linux on mc_apl2 and verified the DMAR table contents.
In addition turned off Vtd and verified that no DMAR table is generated
at all.
Change-Id: Ie3683a2f3578c141c691b2268e32f27ba2e772fa
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
In preparation of generating DMAR tables, provide the hook in SoC scope
for the systemagent to write ACPI tables. The complete functionality is
SoC-specific. Therefore the entry hook is defined as a weak function which
can be overridden by SoC code. If the SoC does not have support for
generating DMAR tables this hook will do no harm.
Change-Id: I1333ae2b79f1a855e6f3bb39bf534da170ddc9e1
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/30989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Also make soc_get_tss_table public and weak instead of static
in intelblock so it can be overridden in denverton.
Change-Id: Id9c7da474a81417a5cebd875023f7cd3d5a77796
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vanny E <vanessa.f.eusebio@intel.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
Intel RTC common code driver need to turn on RTC itself.After the
change, cannonlake and icelake platform will have RTC enabled.
BUG=b:123372643
TEST=build and boot up on sarien platform, check .config to see
CONFIG_RTC is set.
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Change-Id: I0c8c5cf9e6f7f338b1f2f784c04254649d257536
Reviewed-on: https://review.coreboot.org/c/31112
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is spotted using "./util/lint/kconfig_lint"
While at it, do the check in C and not the preprocessor.
Change-Id: Icfda267936a23d9d14832116d67571f42f685906
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/31050
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
- Port the existing denverton tables to intelblock
- Add C-States table for denverton
Note: Removed code is functionally identical to corresponding
common code.
Tested-on: scaleway/tagada
Change-Id: Iee061a258a7b1cbf0a69bcfbf36ec2c623e84399
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25428
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
The ratio_max step is appearing twice when (ratio_max - ratio_min)
is evenly divisible by the ratio step.
This is because in this case there are no rounding down of ratio_max in
the for loop.
Thanks Jay Talbott for the step calculation algorithm.
Change-Id: I91090b4d87eb82b57055c24271d679d1cbb3b7a7
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/25429
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Add new helper macros to enable configuring debounce duration for a
GPIO input. Also ensure that the debounce configuration is not masked
out.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the debounce
duration is configured as expected.
Change-Id: I4e3cd7744867bcfbaed7d3d96fed4e561afb2cec
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Currently all the helpers support configuring GPIO_DW0/1 registers. In
some architectures there is an additional configuration GPIO_DW2 register
that can be used to configure debounce duration etc. Add a helper macro
to enable configuring GPIO_DW2 pad register.
BRANCH=octopus
BUG=b:117953118
TEST=Ensure that the system boots to ChromeOS. Ensure that the current
configuration is not disturbed by turning on the GPIO_DEBUG option and
verifying the debug output before and after the change.
Change-Id: I3e5d259d007fdc83940a43cc4cd4a2b8a547d334
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
Reviewed-on: https://review.coreboot.org/c/30449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Some SPI controllers support both READ and WRITE protection
add a variable to the protect API for the callers to specify
the kind of protection they want (Read/Write/Both).
Also, update the callers and protect API implementation.
BUG=None
BRANCH=None
TEST=test that the mrc cache is protected as expected on soraka.
Also tried if the read protection is applied correctly.
Change-Id: I093884c4768b08a378f21242ac82e430ac013d15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/30559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Everything is wrong here, the Kconfig symbols are only the tip of the
iceberg. Based on Kconfig prompts the SoC code performed pad configu-
rations! I don't see why the person who configures coreboot should have
the board schematics at hand.
As a mitigation, we remove the prompts for UART_DEBUG, which is renamed
to INTEL_LPSS_UART_FOR_CONSOLE (because the former didn't really say
what it's about), and for UART_FOR_CONSOLE in case the former is selec-
ted.
Change-Id: Ibe2ed3cab0bb04bb23989c22da45299f088c758b
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Link walkfcbfs.S in the C_ENVIRONMENT_BOOTBLOCK case and also in the
romstage.
This is useful for cbfs access in pre-CAR environments.
Change-Id: I9a17cdf01c7cbc3c9ac45ed1f075731f3e32f64b
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/30681
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
The newest and most useful incarnation was hiding in soc/intel/common/.
We move it into the Mainboard menu and extend it with various flags to
be selected to control the default and which options are visible. Also
add a new `int` config MAINBOARD_POWER_FAILURE_STATE that moves the
boolean to int conversion into Kconfig:
0 - S5
1 - S0
2 - previous state
This patch focuses on the Kconfig code. The C code could be unified as
well, e.g. starting with a common enum and safe wrapper around the
get_option() call.
TEST=Did what-jenkins-does with and without this commit and compared
binaries. Nothing changed for the default configurations.
Change-Id: I61259f864c8a8cfc7099cc2699059f972fa056c0
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29680
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Cases of *dev = PCI_DEV(b,d,f) are invalid. Not caught
because files only build with __SIMPLE_DEVICE__ defined.
Remove cases of testing __SIMPLE_DEVICE__ in files that
are not build for ramstage.
Change-Id: If10a0efa187c9b1d9a5577008aa46f050f0aa309
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/30497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
In some situations the GPIO pad numbers used by the OS are not
contiguous and coreboot must provide a way for ACPI to provide
the expected GPIO number to the OS.
To do this each GPIO group can now have a pad base value, which
will be used as the starting pin number for this group and it
is added to the relative pin number of this GPIO to compute the
ACPI pin number for a particular GPIO.
By default this change has no effect because the existing uses
of INTEL_GPP() will set the pad base to PAD_BASE_NONE and the
GPIO number is used as the ACPI pin number without translation.
BUG=b:120686247
TEST=tested on a sarien(cannonlake) board
Change-Id: I25f73df45ffae18c5721a00ca230a6b07c250bab
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/30131
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch introduces 3 helper function for cpuid(1) :
1. cpu_get_cpuid() -> to get processor id (from cpuid.eax)
2. cpu_get_feature_flags_ecx -> to get processor feature flag (from cpuid.ecx)
3. cpu_get_feature_flags_edx -> to get processor feature flag (from cpuid.edx)
Above 3 helper functions are targeted to replace majority of cpuid(1)
references.
Change-Id: Ib96a7c79dadb1feff0b8d58aa408b355fbb3bc50
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/30123
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Instead of SMMSTORE_APM_CNT use APM_CNT_SMMSTORE and define it in
cpu/x86/smm.h
Change-Id: Iabc0c9662284ed3ac2933001e64524011a5bf420
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30023
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Instead of ELOG_GSMI_APM_CNT use APM_CNT_ELOG_GSMI and define it in
cpu/x86/smm.h
Change-Id: I3a3e2f823c91b475d1e15b8c20e9cf5f3fd9de83
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/c/30022
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cache BIOS region can boost boot performance, however it can't be over
16MB, according to processor EDS vol1(Apollolake/Skylake/WhiskeyLake),
FLASH+APIC LT will be less than 20MB under 4G. Set the maxiam to 16GB
to save numbers of mtrr entries.
BUG=b:119267832
TEST=Build and boot up fine on whiskeylake rvp platform.
Change-Id: I46a47c8bf66b14fb2fcb7b6b1d30d02886c450a4
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/c/29944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add a method to convert from 1/10 Kelvin to Celsius. This
is useful for EC devices where the sensor temperature are
stored in Celsius instead of Kelvin.
Change-Id: I6b1154f5ba13416131a029966d6d5c1598904881
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29758
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to support using the common ACPI code on more platforms
than just Apollo Lake the DPTF code needs to be told what the
PCI address is for the CPU thermal device.
Change-Id: I638f2387330bbc42f64eb0fb676ee32c5df6572e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/29757
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Use acpigen_write_processor_cnot to implement notifications to the CPU.
Change-Id: Id64f9857bbd7db520c94de949db8f823f71d6dae
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/29891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The mentioned bits 14:8 are wrong as the functions always write
bits 15:8. What happens is visible in the written code. There is no need
for an extra comment.
Change-Id: I59b4d24d01a0a8fa74912f9754e7bbb217ca269d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Provide a library function to set the CPU frequency to minimum
value. This will result in the lowest possible CPU clock with
the lowest possible power consumption. This can be useful in mobile
devices where the power dissipation is limited.
This setting can be overruled by the OS if it has an p-state driver
which can adjust the clock to it's need.
Change-Id: I817095b13ab8cbaab82f25c72947b00ee854d549
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/29771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Initially, I wanted to move only the Kconfig DISPLAY_MTRRS into the
"Debug" menu. It turned out, though, that the code looks rather generic.
No need to hide it in soc/intel/.
To not bloat src/Kconfig up any further, start a new `Kconfig.debug`
hierarchy just for debug options.
If somebody wants to review the code if it's 100% generic, we could
even get rid of HAVE_DISPLAY_MTRRS.
Change-Id: Ibd0a64121bd6e4ab5d7fd835f3ac25d3f5011f24
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/29684
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some embedded controllers expect to be sent a command when the OS
calls the ACPI \_PTS and \_WAK methods. For example see the code
in ec/google/wilco/acpi/platform.asl that tells the EC when the
methods have been executed by the OS.
Not all ECs may define these methods so this change requires also
setting a Kconfig option to enable it.
Change-Id: I6bf83509423c0fb07c4890986a189cf54afaed10
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29487
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add an option that will disable eSPI SMI when ACPI mode is enabled,
and re-enable eSPI SMI when ACPI mode is disabled. Additionally it
ensures eSPI SMI is disabled on the ACPI OS resume path.
This allows a mainboard to ensure that the Embedded Controller will
not be able to assert SMI at runtime when booted into an ACPI aware
operating system.
This was tested on a Sarien board with the Wilco EC to ensure that
the eSPI SMI enable bit is clear when booted into the OS, and remains
clear after resume.
Change-Id: Ic305c3498dfa4b8166cfdb070fc404dd4618ba3c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This patch also add new SKL PCH-H device id's in soc platform reporting and
common lpc driver.
BUG=None
TEST=Booted kabylake RVP11 with HM175 SKL PCH-H and verified the device id
in serial logs.
Change-Id: I8c04bf8d9c27caad800427a5c29da869da1d445d
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29432
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides an interface for apollolake to set TCC before
BIOS reset complete happens in romstage.
With this change, we can add code to update Tcc in devicetree.
BUG=b:117789732
TEST=Match the result from TAT UI
Change-Id: I4419d3bbe2628fcb26ef81828d6325fc952dbabc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
ACPI PM timer emulation will be added back as default FSP stops TCO count
for power saving, which will also stop ACPI PM timer within PCH. CPU PM TIMER
EMULATION will help UEFI payload pass, instead of endless loop wait for
ACPI PM timer counter to increase.
BUG=N/A
TEST=Build and boot up fine with whiskey lake rvp board into UEFI shell.
Change-Id: Ie069e815e6244c3f85fabf51e186311621d316fd
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28937
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch adds following changes,
- APL, CFL, DENVERTON soc's using same implementation to setup and
teardown FSP CAR. Hence cache_as_ram_fsp.S from soc folder is
cosolidated into one file and moved to common code CPU car folder.
- exit_car_fsp.S is from APL, DNV soc folder is clubbed into one file
and moved to common CPU car.
- The new file apollolake/fspcar.c is addded to pass tempraminit
parameters.
- Coffee lake Soc uses FSPT to support Intel Security features like
BootGuard verify boot and Measured boot. Add FSP CAR support for CFL
by programming tempraminit parameters and add FSP_T_XIP default if
FSP_CAR is selected.
BUG= None
TEST= Build for both CFL RVP11 & RVP8 and verified for successful CAR setup.
Build for both leafhill and harcuvar platform by selecting CONFIG_FSP_CAR
without errors.
Change-Id: I98d2dd9711ddc0d7ea7d1672fba700259ee3a3a9
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29209
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds new macros to GPIO common library helpers to allow
a GPI pad to be dual routed using PAD_CFG_GPI_DUAL_ROUTE. It also adds
a helper macro to configure a pad for IRQ and wake.
Above macros are guarded using a newly added Kconfig option
SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT that is selected only
by SoCs that have been validated to allow dual route of
GPIs. Currently, this config is selected only for APL/GLK/SKL/KBL that
have been validated to work with dual-routing of GPIs for IRQ and
wake.
BUG=b:117553222
Change-Id: Iaa623d2d78a50f1504e3abe9a47a5a663693aead
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29188
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates various PAD_CFG_GPI* macros to configure Tx as
Disabled in IO Standby state. This is done to ensure that the Tx
setting is same in IO Standby state as it was in active state i.e. Tx
disabled.
BUG=b:17553222
Change-Id: If462aee3884cc61a519fb358b84867c695ace251
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Make use of the common CF9 reset in SOC_INTEL_COMMON_RESET. Also
implement board_reset() as a "full reset" (aka. cold reset) as that
is what was used here for hard_reset().
Drop soc_reset_prepare() thereby, as it was only used for APL. Also,
move the global-reset logic.
We leave some comments to remind us that a system_reset() should
be enough, where a full_reset() is called now (to retain current
behaviour) and looks suspicious.
Note, as no global_reset() is implemented for Denverton-NS, we halt
there now instead of issuing a non-global reset. This seems safer;
a non-global reset might result in a reset loop.
Change-Id: I5e7025c3c9ea6ded18e72037412b60a1df31bd53
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29169
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch selects common HDA driver and adds audio controller device id
to enable audio on coffee lake platforms.
BUG= None
TEST= boot to yocto linux and windows os on CFL RVP11 & RVP8, verified audio
functionalities.
Change-Id: I4a60a4d7d8babcd0c14664a304ca81d47c668a6c
Signed-off-by: Praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29145
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Cannon lake PCH-H is added to support coffee lake RVP11 and coffee lake
RVP8 platforms.
- Add new device IDs for LPC, PCIE, PMC, I2C, UART, SMBUS, XHCI, P2SB,
SRAM, AUDIO, CSE0, XDCI, SD, MCH and graphics device.
- Add new device IDs to intel common code respectively.
- Add CPU, LPC, GD, MCH entry to report_platform.c to identify RVP11 & RVP8.
- CNL PCH-H supports 24 pcie root ports and 4 I2C controllers, hence chip.c
is modified accordingly.
- Add board type UserBd UPD to BOARD_TYPE_DESKTOP for both RVP11 & RVP8.
BUG=None
TEST=successfully boot both CFL RVP11 & RVP8, verified all the enabled devices
are enumerated and cross checked devices ids in serial logs and UEFI shell.
Change-Id: I4b6af88d467382250aecb4102878b1c5af92ccd4
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/28718
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove assert() and instead use if statement to check if
comm->groups is NULL.
Found-by: klockwork
BUG=None
TEST=Boot to OS
Change-Id: I85a6bc700b52d04c61ca8f2baac62000f40cf2cb
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/28940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
It exposes an interface that is as generic as possible, so payloads
and/or kernels can use it for their data.
Change-Id: I9553922f9dfa60b9d4b3576973ad4b84d3fe2fb5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25182
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change sets scan_bus operation for HDA to scan_static_bus to
allow enumeration of static devices under HDA.
BUG=b:112888584
TEST=Verified that devices added under HDA get enumerated on Nocturne.
Change-Id: I20759c2b702b2f107f0913e7ce92a82c6070ddc4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28807
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:
1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.
2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.
3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.
4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.
Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.
BUG=b:112888584
Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This patch ensures I2C controllers are out of reset without any
assumptions.
BUG=b:116191230
BRANCH=none
TEST=Dump MMIO offset 0x204 to check if I2C host controller is NOT
at reset (by reading Bit 0-1 as 3)
Change-Id: I4b335a834333e01cfa2d802e4aad0735d0212dcc
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/28762
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Use of device_t has been abandoned in ramstage.
Change-Id: If2d643eafea854563f56a7f867b7b492b6d09a19
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28631
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Mainly update headers to build.
Added option PMC_GLOBAL_RESET_ENABLE_LOCK to remove
function configuring the global reset through PMC base.
On denverton the global reset lock is not in PMC base
but in the PCI registers so this code cannot be shared.
Change-Id: I9ace70862cab63f8355252d034292596c7eab1fd
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/25426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Evandro Luiz Hauenstein <kingsumos@gmail.com>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Add a function to set the Bios Interface Lock Down bit (bit 31)
in RTC Configuration register (0x3400). This bit when set prevents
the top swap enable bit (bit 0) in the RTC BUC register (0x3414)
from being changed.
Change-Id: Iacaeeb0d6cabcf0c2c46a58948457ab832351476
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
The firmware of devices connected to LPC should deassert the LPC CLKRUN#
signal when there is no bus activity on LPC.
Necessary changes:
- Enable LPC CLKRUN#
- Enable LPC PCE (Power Control Enable)
- Enable LPC CCE (Clock Control Enable)
- Remove I/O decoding range on LPC for COM 3
- Disable I/O UART driver
Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/28268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Most FADT report using ACPIv3 FADT table. Using the get revision
function keeps the table versions in sync.
Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/28277
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Since we can retrieve the address of ACPI GNVS directly
from CBMEM_ID_ACPI_GNVS, there is no need to store and
update a pointer separately.
TEST=Compile and run on Eve
Signed-off-by: Joel Kitching <kitching@google.com>
Change-Id: I59f3d0547a4a724e66617c791ad82c9f504cadea
Reviewed-on: https://review.coreboot.org/28189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This patch moves uart functions which are common across multiple soc to
block/uart. This will remove redundant code copy from soc
{skylake/apollolake/cannonlake}.
BUG=b:78109109
BRANCH=none
TEST=Build and boot on KBL/APL/CNL platform.
Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26164
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There are two SKUs of Whiskey Lake W0, 2-core and 4-core.
Change-Id: Ia9b2707568702a5fbae3e9495ca53df34613a542
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/28111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
src/soc/intel/common/block/cpu/mp_init.c
Function init_cpus: Pointer dev checked for NULL may be
dereferenced.
src/soc/intel/common/block/graphics/graphics.c
Function graphics_get_bar: Pointer dev returned from
call may be NULL and will be dereferenced.
BRANCH=None
TEST=Built & booted Yorp board.
Change-Id: I5e7caa15a3911e05ff346d338493673af5318a51
Signed-off-by: John Zhao <john.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h
2. Add entry to identify CFL U GT and CPU to respective files
3. Add entry to identify CFL U to report_platform.c
BUG=none
BRANCH=none
TEST=Boot to CFL U RVP board with this patch and check if coreboot is
able to enumerate various devices and display correct component names properly
in serial logs.
Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed
Signed-off-by: Maulik <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/27522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This implementation updates the chip select control register
programming in gspi controller setup call to program the correct
bit fields for chip select state.
Change-Id: Ifab37b0003f09a680024d5b155ab0bb157920a53
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/27889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Specifically PCI device ID for graphics and PCI device ID for northbridge.
Change-Id: Ide237d3274df0543409c8a23b9bb50c8e0a6b7a3
Signed-off-by: Krzysztof Sywula <krzysztof.m.sywula@intel.com>
Reviewed-on: https://review.coreboot.org/27519
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Kin Wai Ng <kin.wai.ng@intel.com>
RTC BUC control register provides a software interface to
configure the top swap feature. This patch adds implementation
to enable/disable top swap feature and gets it accessible in
romstage as well.
The top swap control functions are exposed only if INTEL_HAS_TOP_SWAP
is selected.
To use the topswap feature a second bootblock has to be added
to the cbfs. Below configs aid in doing that,
INTEL_HAS_TOP_SWAP
INTEL_ADD_TOP_SWAP_BOOTBLOCK
INTEL_TOP_SWAP_BOOTBLOCK_SIZE
Enabling and Disabling topswap, using the added API enables user
to boot alternatively from either bootblock.
Change-Id: Iea31b891f81e76d4d623fcb68183c3ad3dcadbad
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/25805
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This function adds support for gpio_configure_pads_with_override
which:
1. Takes as input two GPIO tables -- base config table and override
config table
2. Configures each pad in base config by first checking if there is a
config available for the pad in override config table. If yes, then
uses the one from override config table. Else, uses the base config to
configure the pad.
This is done to allow sharing of GPIO tables across baseboard-variants
for various boards i.e. Each board can have a base config table which
is provided by the baseboard and an optional override config table
that can be provided by a variant to configure certain GPIOs
differently. It is helpful when the variant GPIO diff list is not very
huge compared to the baseboard.
BUG=b:111743717
TEST=Verified that the GPIO config for phaser is same with and without
this change.
Change-Id: I1c5dc72c8368957201ab53d2e8398ff861341a4c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27640
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
An ACPI RMRR table is requried for IOMMU to work properly with an
iGPU (without using passthrough mode), so create one along with the
DRHD DMAR table if the iGPU is present and enabled.
Test: build/boot google/chell and purism/librem13v2 with kernel
parameter 'intel_iommu=on' but without 'iommu=pt;' observe integrated
graphics functional without corruption.
Change-Id: I202fb3eb8618f99d41f3d1c5bbb83b2ec982aca4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/27270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
add an unused param so that mca_configure can be called
by mp_run_on_all_cpus to run it on all cores.
Change-Id: I2395ee7fbedc829f040959b0021967f800693eeb
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/26391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Call to pmc_disable_all_gpe is required before enabling SMIs to ensure
that we do not end up in a recursive SMI handler loop as mentioned in
change 74145f7 (intel/common/pmc: Disable all GPEs during
pmc_init). Thus, this call was added at the end of
pmc_fill_power_state as we want to ensure that all the GPE registers
are backed up before being cleared for identifying the wake source in
ramstage.
This resulted in a side-effect on APL where pmc_fixup_power_state was
called much later in the boot process. Even though we have got rid of
pmc_fixup_power_state, this change moves the call to
pmc_disable_all_gpe to happen just before enabling SMIs. This helps to
keep the disabling of GPEs logically before the enabling of SMIs and
any clean ups that happen in pmc or soc-specific code should not
affect the state of GPEs.
BUG=b:110836465
TEST=Verified that wake sources are correctly identified on KBL and
APL. Also, no SMI handler issues observed when resuming.
Change-Id: I122a8118edcec117f25beee71a23c0a44ae862ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Now that APL does not need pmc_fixup_power_state, this function can be
removed from the PMC common code as well.
BUG=b:110836465
Change-Id: I94de41f3e52228bca4b7a5579afe5a23719429be
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/27250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
SoC users from IOTG team is looking forward for a solution to skip
coreboot AP initialization flow and make use of FSPS-UPD to
perform AP reset.
TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs
out of reset.
Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26644
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Select all Kconfig belongs into Intel SoC Family basecode/stage files
and include required headers from include/intelbasecode/ files.
BUG=None
BRANCH=none
TEST=Code is compiling with cannonlake configurations and also booting
on cannonlake RVP.
Change-Id: Iac99b4346e8bf6e260b00be9fefede5ad7b3e778
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Use of device_t is deprecated.
Change-Id: I6adc0429ae9ecc8f726d6167a6458d9333dc515f
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Register 0x1fc (MSR_POWER_CTL) deserves a proper mask for the C1E
enable bit. Define POWER_CTL_C1E_MASK to be used subsequently.
Change-Id: I7a5408f6678f56540929b7811764845b6dad1149
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/27035
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pch lockdown functionality can be used by supported PCH.
Right now pch lockdown functionality is applied for SPT
(Skylake SOC) and CNP(Cannon Lake SOC) PCH.
BUG=b:78109109
BRANCH=none
TEST=Build and boot KBL and CNL platform.
Change-Id: I0b81bbc54f737cb4e7120f44bbe705039b45ccb3
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Adding common chip config structure which will be used to return data to
common code. When common code requires soc data, code used to fetch
entire soc config structure. With this change, common code will only get
the data/structure which is required by common code and not entire
config.
For now, adding i2c, gspi and lockdown configuration which will be used
by common code.
BUG=none
BRANCH=b:78109109
TEST=compile code for APL/SKL/CNL. Boot using SKL/APL/CNL and check
values are returned properly using common structure.
Change-Id: I7f1671e064782397d3ace066a08bf1333192b21a
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/26189
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch is intended to make Intel common PCH code based on
Gen-6 Sunrisepoint PCH (SPT).
All common PCH code blocks between Gen-6 till latest-PCH should be
part of soc/intel/common/pch/ directory.
A SoC Kconfig might select this option to include base PCH package
while building new SOC block. Currently majority of
common IP code blocks are part of soc/intel/common/block/ and
SoC Kconfig just select those Kconfig option. Now addition to that
SoC might only selects required base PCH block to include those
common IP block selections.
BUG=none
BRANCH=b:78109109
TEST=soc code can select PCH config option
Change-Id: I2934e3b1aed9d692eb00df18ce69a7fcd3096f6b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26348
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To support generating USB devices in ACPI the platform needs to
know how to determine a device name for each USB port, and for
any root hubs that may be present.
Recent Intel platforms route all ports to an XHCI controller
through a root hub. This is supported by considering the root
hub to be USB port type 0, the USB 2.0 ports to be type 2, and
the USB 3.0 ports to be type 3.
This was tested with a Kaby Lake platform by adding entries to
the devicetree and checking the resulting SSDT.
Change-Id: I527a63bdc64f9243fe57487363ee6d5f60be84ca
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/26174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
The intelblock code is common code already used by appololake and
cannonlake platform. The denverton platform also use a similar gpio
controller so the intelblock code can be used as well.
Change-Id: I7ecfb5a3527e9c893930149f7b847a41c5dd9374
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/24928
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch ensures that user can pass a function with given argument
list to execute over APs.
BUG=b:74436746
BRANCH=none
TEST=Able to run functions over APs with argument.
Change-Id: I668b36752f6b21cb99cd1416c385d53e96117213
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Instead of both featuring their own VBT loaders, use a single one.
It's the compression-enabled one from soc/intel/common, but moved to
drivers/intel/gma.
The rationale (besides making all the Kconfig fluff easier) is that
drivers/intel/gma is used in some capacity on all platforms that load a
VBT, while soc/intel/common's VBT code is for use with FSP.
BUG=b:79365806
TEST=GOOGLE_FALCO and GOOGLE_CHELL both build, exercising both affected
code paths.
Change-Id: I8d149c8b480e457a4f3e947f46d49ab45c65ccdc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/26039
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It's pretty well compressible which helps when space is tight.
The code encodes the assumption that the VBT is 8kb or less. Haven't
seen a larger one yet.
BUG=b:77971803,b:78541692
TEST=build, see that vbt.bin is compressed, boot, check log that the
reported VBT size is correct.
Change-Id: Ie25bca21d9edc408f441a292bbe2ab0459948ec4
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/25927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Currently the thermal event handler method TEVT is defined as an extern,
then defined again in platforms with thermal event handling. In newer
versions of IASL, this generates an error, as the method is defined in
two places. Simply removing the extern causes the call to it to fail on
platforms where it isn't actually defined, so add a preprocessor define
where it's implemented, and only call the method on those platforms.
Change-Id: I64dcd2918d14f75ad3c356b321250bfa9d92c8a5
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/25916
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This change uses the newly added vboot_can_enable_udc to decide if it
is okay to enable xDCI in vboot developer mode.
BUG=b:78577893
BRANCH=poppy
Change-Id: Ia83b91ce17eec782faf5bb318ad8c00c09e2db05
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/25848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The EFER and PAT MSRs are x86 architecturally defined. Therefore,
move the macro defintions to msr.h. Add 'paging' prefix to the
PAT and NXE pae/paging functions to namespace things a little better.
BUG=b:72728953
Change-Id: I1ab2c4ff827e19d5ba4e3b6eaedb3fee6aaef14d
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Move inline function where they belong to. Fixes compilation
on non x86 platforms.
Change-Id: Ia05391c43b8d501bd68df5654bcfb587f8786f71
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/25720
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Check same IO ranges get programmed first, if so just skip it to avoid double
programming.
BUG=b:77944335
TEST=Boot up with mewoth board, and check serial log, there's no error
message about "LPC: Cannot Open IO Window: ".
Change-Id: I89f9bb70320f91b16c6084384c4a0a53ede3760c
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/25667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To avoid rounding errors with the current data types, the formula in
this function must be converted.
Change-Id: I75d05165fd9e5a0992330df00f8665a05d2daeb3
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/25584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This is required for clock parameter settings to take effect.
BUG=b:75306520
BRANCH=None
TEST=On Octopus, used a scope to check that spi_clk fed to tpm is
1 MHz
Change-Id: Icdb617aa4aa944d46b3a56dab88d2008b01dea0d
Signed-off-by: Shamile Khan <shamile.khan@intel.com>
Reviewed-on: https://review.coreboot.org/25573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Intel internal graphics preallocated memory size should be selected from
below lists as per Intel FSP UPD header:
0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB,
0xF0:4MB, 0xF1:8MB, 0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB,
0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB, 0xFA:44MB, 0xFB:48MB,
0xFC:52MB, 0xFD:56MB, 0xFE:60MB
This patch ensures that coreboot can report the same preallocated
memory range for intel grapics during memory layout calculation.
Note: Today all existing SoCs(except Cannonlake) are supported under intel
common code block design may not need to use any other values than 0x0-0x05
for GFX DSM range. DSM memory ranges between 0xF0-0xF6 are majorly for
early SoC samples and validation requirement. This code block to justify
all differnet possible ranges that FSP may support for a platform.
TEST=Set IgdDvmt50PreAlloc UPD with different ranges between 4MB-60MB
and coreboot could able to calculate GFX DSM range accordingly.
Change-Id: I99735e9a2ee57626bd9d7258e700f7f39ef02e58
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/25562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Apparently Intel had decided to use different clock speeds for
some of its IP blocks in some of its designs. The i2c designware driver
has already been moved into common code allowing for its own Kconfig
value. That currently leaves SPI (UART isn't using the clock currently).
Therefore, remove SOC_INTEL_COMMON_LPSS_CLOCK_MHZ and add
SOC_INTEL_COMMON_BLOCK_GSPI_CLOCK_MHZ to allow for the different clock
speeds present in the system for the various IP blocks.
BUG=b:75306520
Change-Id: I6cb8c2de0ff446b6006bc37645fca64f2b70bf17
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/25608
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
