This removes the "ifdef ACPI" which is not needed here as we currently
don't include gpio.h in any asl file.
Change-Id: I803bbee5933eda9423a9bc9fcaea9e905e3ac78e
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35543
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This fixes the warning that power_on_after_fail could not be found,
adds a default config and adds the parameter hyper_threading.
Change-Id: I10b0aa71fa7916b01e93e16cbd81e427fd14f6a4
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35526
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The CONFIG_GBB_HWID can be generated automatically now so we can remove
the test-only HWIDs set in board config files.
BUG=b:140067412
TEST=Built few boards (kukui, cheza, octopus) and checked HWID:
futility gbb -g coreboot.rom
Change-Id: I4070f09d29c5601dff1587fed8c60714eb2558b7
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35635
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: Iee12a5d1781c869b20bc14a52ecbf23474caa3fd
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Internal pull up need to be enabled for GPD3 as power button pin for
PCH according cometlake pch EDS vol1 section 17-1. Without that pin will
stay floating and hook up XDP can cause system shutdown as power buttone
event will trigger.
BUG=N/A
TEST=Hook up XDP on drallion platform, able to boot up into OS and stay
at power up state.
Change-Id: Idd1befeb14a251b7c0542ca1f99049d07b28fb98
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35666
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
Per google/stout.
Tested with SanDisk SSD U110.
Change-Id: I7cc9837f572236acac2007e95990e64c25a5d6e2
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Based on schematic and register dumps.
Change-Id: I91fc47022988cfe986fb8c1ed21dc073ee7d16bc
Signed-off-by: James Ye <jye836@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The vendor id option set here is useless as most SSVID registers get
filled with 0x8086 (their VID) by default, anyway.
Besides that the Kconfig option isn't meant for retrofit ports, cf.
commit 7e1c83e31b (Add Kconfig options to override Subsystem Vendor and
Device ID). The right place would be the devicetree.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: If67c679bb342f63096902535734106e4f1651118
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35524
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Most of the X11 boards with socket LGA1151 are basically the same boards
with just some minor differences like different NICs (1 GbE, 10 GbE),
number of NICs / PCIe ports etc.
There are about 20 boards that can be added, if there is a community for
testing.
To be able to add more x11 boards easily like x11ssm (see CB:35427) this
restructures the x11ssh tree to represent a "X11 LGA1151 series". There
were multiple suggestions for the structure like grouping by series
(x10, x11, x...), grouping by chipset or by cpu family.
It turned out that there are some "X11 series" boards that are
completely different. Grouping by chipset or cpu family suffers from the
same problem. This is why finally we agreed on grouping by series and
socket ("X11 LGA1151 series").
The structure uses the common baseboard scheme, while there is no "real"
baseboard we know of. By checking images, comparing logs etc. we came to
the conclusion that Supermicro does have some base layout which is only
modified a bit for the different boards.
X11SSH-TF was moved to the variants/ folder with it's gpio.h. As we
expect the other boards to have mostly the same device tree, there is a
common devicetree that gets overridden by each variant's overridetree.
Besides that some very minor modifications happened (formatting, fixing
comments, ...) but not much.
Documentation is reworked in CB:35547
Change-Id: I8dc4240ae042760a845e890b923ad40478bb8e29
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35426
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Modify IRQ pin from D21 to A21 and support wake-up from touchpad
BUG=b:141519690
TEST=build bios and verify elan touchpad works fine
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6cc5b780ffcee24f1f2a04e88c30628ceb5904e8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35551
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
new DDR particle:
1. Samung K4A8G165WC-BCWE
2. Hynix H5AN8G6NCJR-XNC
BUG=b:139085024
BRANCH=master
TEST=rework new source to DUT and re-flash bios to DUT and
verify DUT will bring up successfully
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I0d039af53938086733308a081a77a7398e7bf5d5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Add the configuration 'Juniper' for the new mainboard.
BUG=b:137517228
TEST=make menuconfig; select 'juniper' and build
Change-Id: I94e3ac7f6de3fecf177e344cb217eaecf6362d69
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35550
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
All variants of hatch are using Comet Lake and so the selection can be
done in Kconfig without requiring each variant to do the same.
Change-Id: Ief34296334ede5ba0f5f13381e92427ccc440707
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Andrew McRae <amcrae@chromium.org>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Sort the names of all variant mainboards in an ascending order.
Change-Id: I19d502298744c0e0cbc91eb836c62ca90cdb9a5c
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Enable VBOOT in Kconfig and provide a flashmap that includes all the
needed sections for VBOOT support.
Change-Id: I3d58094256d2730dbd249291a8f1ed8df9dfe62d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
The implementation of udelay() with LAPIC timers
existed first, as we did not have calculations
implemented for TSC frequency.
Change-Id: If510bcaadee67e3a5792b3fc7389353b672712f9
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34200
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The Razer Blade Stealth H2U is a KabyLake System using:
- Intel KBL 7500U
- ITE8528E SuperIO
- Intel 600P Series NVMe SSD
- Either four MT52L1G32D4PG (16GB) or MT52L512MB32D4PG (8GB)
of soldered memory in dualchannel mode
- (Optional) Touchscreen
- HDMI 2.0a via DP-1: Paradetech PS175
- AlpineRidge Thunderbolt 3 controller
- TPS65982 USB-PD power switch / multiplexer
Even though it has a 16MB chip equipped (W25Q128.V) only the first 8MB
are used and mapped via IFD. The rest is left empty (0xFF). The flash is
not secured in any way and can be read via flashrom. It should be the
source for this port's IFD and ME blobs.
Working:
- USB-A Ports left and right
- Speakers
- Touchscreen (USB)
- Onboard Keyboard in Linux
- NVMe SSD
- SeaBIOS, Tianocore and Grub Payloads
- Webcam
- Powersaving Modes
- Battery state and LID switch, sometimes slow to update.
- Touchpad (I2C-HID)
- Headphones
Not part of this commit:
- Thunderbolt / USB-C (Requires advanced EC signaling)
- Full HDMI support (Currently requires plugged connection at boot)
Change-Id: I7ede881d631e1863f07f5130f84bc3b8ca61a350
Signed-off-by: Johanna Schander <coreboot@mimoja.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Disable root port IOU0 to which built-in NIC is attached.
TEST=on OCP monolake, hide built-in NIC and make sure OS does not report
built-in NIC
Change-Id: I2384e7dd073355f0ced2902ac2d8418996b1c5aa
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
- configure DMA fw_cfg
- add support to read using fw_cfg_dma
- provide fw config version id info in logs
BUG=N/A
TEST=Build and boot using qemu-i440fx.
Change-Id: I0be5355b124af40aba62c0840790d46ed0fe80a2
Signed-off-by: Himanshu Sahdev <himanshusah@hcl.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35365
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Fill the dimm info struct to make SMBIOS type 17 appear.
TESTED=Up Squared
Change-Id: I4de63362c8fea8a886594cdcf0eec48421afb605
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34564
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drop unused CNF2_LPC_EN, as there is no device which uses IO 0x4e/4f.
Do not use the mainboard model to set COMA_LPC_EN. Make use of
NO_UART_ON_SUPERIO instead, as it is more future-proof.
Change-Id: Iac49250b0f509a42012f82db8aa85ba85559c66f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35444
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
BUG=b:140545732
TEST=build bios and spd index set to 6, verify DUT bring up normally
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I337b0bdcd37a9c4baacccbc6786968031a41b31e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35511
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
CdClock does not need to be set because the board does not use IGD.
Change-Id: I6835ccdf80530f9efc6fdeb0363dcf9267f99d21
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Implement Locator and Bank fields (as reported by dmidecode) to match
vendor BIOS.
TEST=on OCP monolake, run dmidecode tool and see that "Locator" field
matches expectation.
Change-Id: Ia271ff1e596ba469cf42e23d8390401c27670a27
Signed-off-by: Andrey Petrov <anpetrov@fb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
The specified CBFS_SIZE does not make sense.
The boards BIOS region is 0xb00000. Correct the value.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ia3014c7fd081030607790ced6bb55323086f1161
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35458
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A closer read of the EDS indicates that when GPIO Driver mode is
selected, GPIO input event updates are limited to GPI_STS only.
GPI_GPE_STS updates are therefore masked, and we don't want to enable
this behavior. It masks the GPE and does not allow us to see this GPE
as a wake source, obscuring the reason that the system woke up.
Also switch the IRQ from level-triggered to edge-triggered,
otherwise the system will auto-wake from any sleep state when the
pen is ejected from the garage.
BUG=b:132981083
BRANCH=none
TEST=Wake up system from S0ix using pen eject, verify that mosys
eventlog shows GPE#8 as the S0ix wakeup source. Wake up system from S3
via pen eject, and verify that the wakeup source shows as GPE#8.
Change-Id: If017e12e23134f5cfed7cbb6047cc9badd9bf7e8
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35459
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Implementing logic base on sensor detection to determine SKU id.
BUG=b:140472369
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5e71ae6b97378b78055735bbf4b6b55ffe38b978
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35366
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initialize the input_hertz and uart_pci_addr fields of the lb_serial
struct to prevent later undefined reads in lb_add_serial(). This was
done for exynos5420 in commit ff94e00362 (soc/samsung/exynos5420/uart.c:
Init new serial struct variables), and this patch finishes the rest.
Note that not all of the drivers can have the UART PCI address
configured at build time, so a follow-up patch will be needed to correct
those ones.
Change-Id: I733bc8185e2f2d28a9823495b53d6b09dce4deb1
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1354778
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34548
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Add DPTF based thermal control for ambient sensor for CML based
Helios system. Also, update other sensor names information.
BUG=b:139335207
BRANCH=None
TEST=Build and Boot on Helios board and check all sensor details.
Change-Id: I322d53536fbdf6db70f5a24afb322d9f206eaeac
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35447
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Update DPTF thermal temperature threshold values for CML based
Helios system. This updates CPU active cooling temperature
threshold to appropriate values which addresses the issue of
running the Fan at lower CPU temperature as per bug.
Also, added active cooling temperature thresholds for other
TSR sensors.
BUG=b:141087272
BRANCH=None
TEST=Build and boot on Helios board to check the fan functionality.
Change-Id: I5c8502f8c9e6121c18024d2a8d5a4f7680797b8d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35446
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is no board named X11SSH+-TF.
Change-Id: Ide01a8d59c09747dfe7d59fd9e17bd5194fb14e4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Add SKU#18 to config power sequence below:
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:134854577,b:137033609
BRANCH=octopus
TEST=build
Change-Id: I58e07518f6daaf608684c9fa1b1c88fc592ea117
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35442
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change adds SPD files for Drallion. Use spd_index
matrix to correspond mem_id. This can save the dummy spd index
to reduce the size of SPD.bin.
BUG=b:139397313
TEST=Compile successfully
Change-Id: I2f7e75fdbca4183bcd730e40fef4bfe280ab900b
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35346
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some T430s variants have a Thunderbolt controller wired to PCIe port
The controller hotplugs itself to the chipset when a downstream device
is hotplugged into it, so the hotplug capability should be enabled on
PCIe port #5.
TODO: find the correct gpio pin to detect the Thunderbolt controller
at runtime.
There are 3 variants of mainboard for Thinkpad T430s: Basic type
(Wistron LSN-4 11263-1), Boards with an additional discreet GPU,
Boards with an additional TB controller (Wistron LSN-4 11271-1),
each of which has a different schematic.
The gpio27 on the last type is set as set as GPIO-INPUT, compared
with GPIO-OUTPUT-HIGH on the basic type boards.
Change-Id: I61f41db100f398069e50e2da8a378b3a8d1c84bf
Signed-off-by: Bill XIE <persmule@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31631
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This Kconfig symbol is set at a default of 36 in cpu/x86 and is now
only used in the romcc bootblock to set up caching to upgrade the
microcode. It's not mainboard specific.
Change-Id: I29d3a8308025e586a823603f8d6edafd30cb9d95
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35436
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui and ATF(BL31) can get this parameter.
Change-Id: Iefa70dc0714a9283a79f97d475b07ac047f5f3b0
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This change overrides USB port settings for kohaku.
Some port settings are same with baseboard, but I'd like to describe all
settings here to be aware of current setting and usage of USB ports on
kohaku.
BUG=none
BRANCH=none
TEST=built and measured SI of USB ports internally
Change-Id: I5ac05485d1cd94416e5a0aecf7fa6769bd7c9e84
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Information based on superiotool dump.
Change-Id: I24ae9b1a7eab3095518341354544efe613912a6a
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Enables and configures GPIOs in the NCT6791D chip. The values for
registers taken from the superiotool dump.
Change-Id: I5968a6c20cc013697d64bfbe4fc2e7b2390b72b0
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This patch uprevs the Arm Trusted Firmware submodule to the new upstream
master (commit 42cdeb930).
Arm Trusted Firmware unified a bunch of stuff related to BL31 handoff
parameters across platforms which involved changing a few names around.
This patch syncs coreboot back up with that. They also made header
changes that now allow us to directly include all the headers we need
(in a safer and cleaner way than before), so we can get rid of some
structure definitions that were duplicated. Since the version of entry
point info parameters we have been using has been deprecated in Trusted
Firmware, this patch switches to the new version 2 parameter format.
NOTE: This may or may not stop Cavium from booting with the current
pinned Trusted Firmware blob. Cavium maintainers are still evaluating
whether to fix that later or drop the platform entirely.
Tested on GOOGLE_KEVIN (rk3399).
Change-Id: I0ed32bce5585ce191736f0ff2e5a94a9d2b2cc28
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
drallion_ish.bin is updated for drallion GPIO changes
and not compatible with arcada_cml.
TEST=Build and boot arcada_cml
Signed-off-by: Selma BENSAID <selma.bensaid@intel.com>
Change-Id: Idb35c33425bfd50533df74349dd645db18a65bc5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Even though GT7375P programming guide rev0.4 only requires a reset delay
of 120ms, in practice, we have to increase the reset delay to 500ms, or
Goodix FW update would fail.
This is a workaround. In the long run, we hope Goodix can fix the power
sequence in touch firmware.
BUG=b:138795891, b:138796844
TEST=boot helios board and verify Goodix FW update succeeded
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ic0049bf240de0a1c7f1b1f39bf155d48bb76fb86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35350
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This will increase ME region size and reduce the BIOS region size.
BUG=b:140665483
TEST='compile successfully'
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Change-Id: I5be2580d280569421d0870a06f9b93124b564b6f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35304
Reviewed-by: Mathew King <mathewk@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PchPwrOptEnable FSP UPD is for internal testing and not really available
in externally released FSP source hence assigning this UPD using devicetree
config dmipwroptimize doesn't do anything.
TEST=Build and boot sarien/arcada.
Change-Id: I6da2a088fb697e57d12008fa18bd1764b3da7765
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
With the current devicetree the kernel doesn't provide any serial
after serial init.
Update the devicetree to resolve this issue.
Tested on HiFive Unleashed.
Change-Id: I4427d34a12902e0eaa2186121a53152b719cadff
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Drallion uses the same touch panel as Sarien. Copy the deivce
from Sarien.
BUG=b:140415892,b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e6d2dcf4bd2ed2325137a05811af03692d40342
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35305
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
MT8183_DRAM_EMCP is enabled for devices using eMCP to run at a high DRAM
frequency (e.g., 3600Mbps).
BUG=b:80501386
BRANCH=none
TEST=Memory test passes on EMCP platform
Change-Id: Icf875427347418f796cbf193070bf047844d2267
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34433
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Setup EC_PCH_ARCORE_INT_L, tied to GPP_D17, and define as EC_SYNC_GPIO..
- change GPP_D17 definition to PAD_CFG_GPI_APIC_INVERT as
EC_PCH_ARCORE_INT_L is active low
- add EC_SYNC_GPIO to the group of chromeos_gpios for use by depthcharge
BUG=b:139384979
BRANCH=none
TEST="emerge_nocturne coreboot depthcharge chromeos-bootimage",
flash & boot nocturne in dev mode, verify that volume up and down
buttons work in the dev screen and that the device boots properly into
the kernel.
Change-Id: Ia43c622710fde8686c60b836fb8318931d79eb61
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35174
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
pull in the FPU VDDIO turn on to fix the power leakage problem
on FPU VDDIO and FPU CS during power on sequence.
BUG=b:138638571
BRANCH=none
TEST=emerge-hatch coreboot chromeos-bootimage
Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I3f6bf3676922e987c2e282b697a2333e2d90289e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34858
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tune I2C bus 1, 2 and 3 clock and make them meet spec.
BUG=b:140665478
TEST==flash coreboot to the DUT and measure I2C bus 1,2,3 clock
frequency less than 400KHz
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6b2a51a866e57d13fe528452e4efdcf17a72317f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35298
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. SKU1 for eMMC
2. SKU2 for SSD
BUG=b:140008849, b:140573677
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
From DDR4 SPD spec:
Byte 4 (0x004): SDRAM Density and Banks
Bits [7, 6]:
00 = 0 (no bank groups)
01 = 1 (2 bank groups)
10 = 2 (4 bank groups)
11 = reserved
Bit [5, 4] :
00 = 2 (4 banks)
01 = 3 (8 banks)
All others reserved
Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks.
Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Based on HW schematic to modify USB setting.
Drallion has two type C on left and two type A on right.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I925de209635d92ef61ccb9114efebb4b10f30e87
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Sets all unused sata ports to disable in the device tree
Note:
SATA4 and SATA5 are located at the bottom of the board, but there
is no connector for this. Apparently, a board with an increased
number of ports is very rare. Perhaps this is a separate variant
of the Asrock motherboard. For this reason, these ports are also
disabled
Change-Id: I5b3ad372f1d6607cc7b4a78e3c59d2a5ae1d2cf5
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Disable spi0, i2c0 and i2c1 in the “SerialIoDevMode” register for the
following reasons:
1. when the AMI BIOS is used, these pci devices are disabled in
lspci.log;
2. there are no pads in the inteltool.log that use the functions of
these buses
Change-Id: I01ab10eb3fd41e81a1726805247c2b472d72287c
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35070
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The string "register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" was mistakenly
taken from the Intel KBL-RVP8 devicetree.cb. Remove it, since the i2c4
bus is disabled in the "SerialIoDevMode" register
Change-Id: I44ecd5c22efd66b02a2851dc14a1a95421f39a71
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
1) VR domains current limit Icc max for Sky/Kaby Lake S is set based
on the processor TDP [1]. Updates information about this
2) Sets VR voltage limit to 1.52V, as described in the datasheets [2,3]
[1] Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde
[2] page 112-119, 6th Generation Intel(R) Processor Families
for S-Platforms, Volume 1 of 2, Datasheet, August 2018.
Document Number: 332687-008EN
[3] 7th Generation Intel(R) Processor Families for S Platforms and
Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1,
December 2018, Document Number: 335195-003
Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Based on HW schematic to modify PCIE setting.
BUG=b:138082886
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia744a6f3cba76c507c1c43b0a981cb6d89c1a40f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Use sku-id to load the SAR values for Bloog device.
BUG=b:138180187
BRANCH=octopus
TEST=build and verify load Bloog SAR by sku-id
Cq-Depend: chromium:1771477
Change-Id: Id0bc2609fd1c4eaeb380f8f1532ab30d34e2aeb3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
To avoid possible panel failures due to incorrect timing settings for
PTN3460, the internal graphic device should be disabled.
Change-Id: Ie0b9ed99fb78461bb48d6f2ff328643cd8c2cd15
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Rename the table from Liara specific to simply specifying
that it's using 2T command rate
BUG=139841929
TEST=build and do stress test
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I6e10b95c8aea50e68d8a3b710f30dda4f6b807d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35116
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
override 'uint32_t sku_id(void)' so that lib_sysinfo.sku_id get a
correct value in depthcharge
BUG=b:140010592
BRANCH=none
TEST=boot treeya board, in depthcharge stage, lib_sysinfo.sku_id
print correct value.
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I631f62021e8104a69a43667a811c9c23e3105596
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35214
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Magf - <magf@bitland.corp-partner.google.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Padmelon board code was written for Merlin Falcon (family 15h models 60h-6fh),
but as the needed binaries are not yet merged (commit 33615), a config
HAVE_MERLINFALCON_BINARIES was added. If the binaries are not available,
the board defaults to Prairie Falcon, which use the same binaries as Stoney
Ridge. Once the binaries are merged, the config will be eliminated. Fan
control is done through F81803A SIO, and IRQ/GPIO and other board
characteristics are the same regardless of Merlin Falcon or Prairie Falcon.
Padmelon board was created to accept Prairie Falcon, Brown Falcon and Merlin
Falcon. The requested development was for Merlin Falcon. There are some small
spec changes (such as number of memory channels) between SOCs. Brown Falcon
was not investigated, Prairie Falcon is very similar to Stoney Ridge.
Started from Gardenia code, added changes created by Marc Jones and finally
revised against schematic, which added changes to GPIO settings.
BUG=none.
TEST=Both versions tested and boot to Linux using SeaBIOS.
Change-Id: I5a366ddeb4cfebd177a8744f6edb87aecd4787dd
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Select NO_UART_ON_SUPERIO as the SoC internal UART is used.
The current code is working, so this is just a cosmetic fix to remove
some unused options from Kconfig.
Change-Id: I206557c397da74b572e669feb1e38f0c8473d0d9
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35151
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion will use soldered down memory and use
GPP_F12 to GPP_F16 indicates mem_id.
BUG=b:139397313
BRANCH=N/A
TEST=N/A
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib5ada54fd2b8f358b59de8089e5405cf3e34825a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Its entirely no-op and is getting in the way of real hardware timers for
power9/talos ii.
Change-Id: I2d21d4ac3d1a7d3f099ed6ec4faf10079b1ee1d1
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35082
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
As per GT7375P programming guide rev0.4, we want to enforce a delay
of 120ms after the reset is completed, before HID_I2C starts.
BUG=b:140276418
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Id69a9db996bcd9001ef850c50898fbd55327b4df
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Summary:
This patch calls monolake board specific function to query
settings stored in VPD binary blob to configure FSP UPD
variable HyperThreading.
Test Plan:
* Build an OCP MonoLake coreboot image, run following command
to initialize RW_VPD and insert HyperThreading key:
vpd -f build/coreboot.rom -O -i RW_VPD -s 'HyperThreading=0'
* Flash the image to MonoLake, boot and observe following
message in boot log:
Detected 16 CPU threads
If RW_VPD partition does not exist, or if HyperThreading
key/value pair does not exist, the boot log has:
Detected 32 CPU threads
Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: I799d27734fe4b67cd1f40cae710151a01562b1b2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34636
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Remove duplicated code and instead use the IPMI KCS driver, which provides
the same functionality.
Change-Id: I419713c9bef02084cca1ff4cf11c33c2e3e8d3c1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andrey Petrov <anpetrov@fb.com>
This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 [1]
registers values from the inteltool dump, is more understandable and
makes the code much cleaner. The pad configuration in this patch was
generated using the pch-pads-parser utility [2]. The inteltool dump
before and after the patch is identical (see notes)
Notes:
1. For some reason, GPIO RX State (RO) for the GPP_F4 and GPP_G10
changed the value to 0, but this doesn't affect the motherboard
operation. Perhaps this is because PAD_CFG1_GPIO_DRIVER is set to
PAD_CFG_GPI_INT(), and the pad is not actually connected. So far I
haven't circuit diagram to check this out.
2. According to the documentation [1], the value 3h for RXEVCFG is
implemented as setting 0h.
3. If the available macros from gpio_defs.h [3] can't determine the
configuration of the pad, the utility [2] generates common
_PAD_CFG_STRUCT() macros
[1] page 1429,Intel (R) 100 Series and Intel (R) C230 Series PCH
Family Platform Controller Hub (PCH), Datasheet, Vol 2 of 2,
February 2019, Document Number: 332691-003EN
[2] https://github.com/maxpoliak/pch-pads-parser/tree/stable_1.0
[3] src/soc/intel/common/block/include/intelblocks/gpio_defs.h
Change-Id: I01ad4bd29235fbe2b23abce5fbaaa7e63c87f529
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Add support for the X11SSH-TF which is based on Intel KBL.
Working:
* SeaBIOS payload
* LinuxBoot payload
* IPMI of BMC
* PCIe, SATA, USB and M.2 ports
* RS232 serial
* Native graphics init
Not working:
* TianoCore doesn't work yet as the Aspeed NGI is text mode only.
* Intel SGX, due to random crashes in soc/intel/common
For more details have a look at the documentation.
Please apply those patches as well for good user experience:
Ica0c20255f661dd61edc3a7d15646b7447c4658e
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Change-Id: I2edaa4a928de3a065e517c0f20e3302b4b702323
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Adjust CID to allow for Windows driver to attach without breaking
functionality under Linux. Same change made as to google/cyan
(which uses same Realtek RT5650 codec) in commit 607d72b.
Test: build/boot Windowns 10 on google/buddy, observe audio
drivers correctly attached to codec and Intel SST devices.
Change-Id: I839acc8427ee9b5c425885858a513e9b0b9d0f93
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/30564
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Drallion will change debug port UART from 2 to 0. Followed HW
schematic to modify it.
BUG=b:139095062
BRANCH=N/A
TEST=Build without error
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ib2bcded8de3c9fb2c0a4ccbd002b1f219bccceb5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35132
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Enable acoustic noise mitgation for hatch platform, the slow slew rates
are fast time dived by 8 and disable Fast PKG C State Ramp(IA, GT, SA).
BUG=b:131779678
TEST=waveform test and reduce the noise level.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I49e834825b3f1e5bf02f9523d7caa93b544c9d17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35005
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This removes the need to select ARCH_ARM in SOC Kconfig
Also don't define the default as this result in spurious lines in the
.config.
Change-Id: I1ed4a71599641db606510e5304b9f0acf9b7eb88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31313
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The current HWID for drallion is reported as invalid by chrome, generate
new valid HWID with the following command and taking last 4 digits.
`printf "%d\n" 0x$(crc32 <(echo -n '$1'))`
BUG=b:140013681
Change-Id: I410d37fc3f3372e9420d674b65f2c9a704b670f2
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
During boot sequence sometime touchscreen reset keeps failing. Also, kernel
dmesg shows "dmesg:i2c_hid i2c-GDIX0000:00: failed to reset device" message.
This adds around 4 more seconds to the boot sequence. Setting the appropriate
delay of 120ms between enable and reset for Goodix Touchscreen helps to
synchronize and address this failure. This value is 120 ms as per Goodix Spec.
BUG=b:138413748
BRANCH=None
TEST=Built and tested on Hatch system
Change-Id: I15005c568f285ec7bad9a0bec4498e2fdd20782b
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34626
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This is LVDS bridge, I assume this was lost while upstreaming
or converting boards to variants.
Change-Id: I816a6b4035c4e935150cc77089c4224eee719c10
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Device is present in devicetree but not included in
the build.
Change-Id: I8555d94902e94c623d8fbe6f1a4ffe7637988530
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
New emmc DLL values for Kindred
BUG=b:136784418
BRANCH=none
TEST=Boot to OS 100 times on Kindred proto 1 board.
Change-Id: I52acb445c47fcdb9b60512dd501d810b1ae4dc10
Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35041
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Drallion doesn't have on board LAN, remove GBE bin file config.
BUG=b:139906731
TEST=emerge-drallion coreboot chromeos-bootimage and check
image-drallion.bin not include GBE region
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ifbc295afd8d875b5098b0ce75252b51523a5c76e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mathew King <mathewk@chromium.org>
Drallion will use soldered down memory. Add dummy spd file.
BUG=b:139397313
BRANCH=N/A
TEST=Build and check cbfs has the dummy spd.bin
Change-Id: Ife59c2dd689d72b117f30e832a3ce7eed4fa4220
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35113
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The file chip.h has a special purpose for defining the
configuration structure used in static devicetree.
Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This provides stack guards with checking and common
entry into postcar.
Change-Id: If0729721f0165187946107eb98e8bc754f28e517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34973
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This provides stack guards with checking and common
entry into postcar.
The code in cpu/intel/car/romstage.c is candidate
for becoming architectural so function prototype
is moved to <arch/romstage.h>.
Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These are required to cover the absensce of .data and
.bss sections in some programs, most notably ARCH_X86
in execute-in-place with cache-as-ram.
Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a
variable that was previously declared with CAR_GLOBAL.
Test for !defined(__PRE_RAM__) can be transformed into
ENV_RAMSTAGE here as the warnings about invalid bmcinfo
structure do not need to be repeated in SMM console, which
is generally disabled anyways due to DEBUG_SMI=n.
Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Kukui AP doesn't remember if the last AP reset was due to AP watchdog.
We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query
the reset reason from EC.
BUG=b:109900671,b:118654976
BRANCH=none
TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog'
2. wait for watchdog reset
3. check 'mosys eventlog list | grep watchdog'
Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
EFP1 is configured as 'DisplayPort with HDMI/DVI
compatibility'. Using this setting 4K monitor is configured
into lower resolution.
Change EFP1 setting to 'HDMI/DVI'
The next addtional small changes are made in VBT:
UEFI GOP Driver
Child Device 2 = LFP
Child Device 3 = EFP1/LFP
LFP Panel configuration Y-Res of Panel #10 = 1920
BUG=N/A
TEST=LCD and HDMI on Facebook FBG1701
Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.
Test: boot google/link, observe onboard RAM correctly
detected on both channels
Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M)
that’s possible with QEMU on AArch64 virt because it tries to search
the DRAM_SIZE_MB range to find the true memory size.
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
In the next board version, we will use GPP_D9 as enable control for touch
screen.
BUG=b:137133946
TEST=build
Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
sx9310 and FPMCU are not used in Kindred.
BUG=none
TEST=build
Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
When upstreamed, GPIO and RAM config for clapper variant was taken
from an older branch, leading some boards to fail to boot.
Update based on chromium branch firmware-clapper-5216.199.B,
commit 362d845 [baytrail: implement baytrail technical advisory 556192]
Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This reverts commit 38dbd68920.
Reason for revert:
ODM helped to verify w/ BT runtime suspend disabled + revert this change
And issue is gone. so I revert this change
see the test result in
https://partnerissuetracker.corp.google.com/issues/136039607#comment32
Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
These variants are to support the sarien and arcada boards
with CML SOC, the drallion variant will be used to support the
upcoming drallion board.
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
Declare the following panel for Kodama:
- AUO B101UAN08.3
BUG=b:139699622
TEST=builds Kodama image and working properly
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The panel description may be pretty large (for example, 1.3k for BOE
TV101) due to init commands and we should only load the right config
when display is needed.
BUG=None
TEST=make -j; boots and see display on Krane.
Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
These platforms use different signature for this function, so
declare them with different name to make room in global namespace.
Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Treeya doesn't support the keyboard backlight.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data.
Reference to Aleena project.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Enable ACPI TBMC notification on tablet mode change to support
convertible treeya devices.
BUG=b:135551210
BRANCH=grunt
TEST=emerge-grunt coreboot
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Id0618c8df66267b88008dc5057892de6b530629f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
Synaptics touchscreen
BUG=b:139699619
TEST=emerge-grunt coreboot chromeos-bootimage
flash bios image to DUT and make sure the touchpad and
touchscreen can work
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I002badd49e678e1c32c802352923ca51efb45cef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35000
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
coreboot would clear CMOS by request via IPMI command, for example
BMC can issue "bios-util server --boot_order enable --clear_CMOS"
to set the request and reboot the system, then coreboot would clear CMOS
on the next boot.
Tested on Mono Lake
Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34857
Reviewed-by: Johnny Lin
Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Port_List is an array of 8 elements, and GCC 9 is warning that there
are no 'others' when all 8 elements are explicitly initialized, which is
causing the build to fail. Remove the 'others => Disabled' clause to
silence this.
Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Print an error message and die if the PCI device cannot be found.
Change-Id: I10c58502658ebf12d1a8fe826ee7d47a618fd1c8
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1403000
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 136538{8,9}, 140134{1,4}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33135
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the
FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of
the first array and overwrite both of them at once. However, FSP_M_CONFIG
is not declared with the packed attribute, so this is not guaranteed to
work and is undefined behaviour to boot. It is cleaner and less tricky
to copy them independently. The same is true for DqsMapCpu2DramCh0 and
DqsMapCpu2DramCh1, so we change those as well.
Change-Id: If394f14c4a39d6787ae31868241229646c26be7a
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1365730, 14013{38,39,40,42,43}
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33066
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
It probably doesn't make sense to continue if the CK804 isn't found, and
doing so would perform uninitialized reads of the busn and io_base
arrays anyway, so let's return early.
Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1370586
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Level trigger is recommended setting for touchscreen interrupt of
kohaku, so we would change it as the recommedation.
BUG=b:139179200
BRANCH=none
TEST=Verified touchscreen works on kohaku
Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
When entry to romstage is via cpu/intel/car/romstage.c
BIST has not been passed down the path for sometime.
Change-Id: I345975c53014902269cee21fc393331d33a84dce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This is based on the hatch variant
BUG=b:138879565
TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp
chromeos-bootimage look for image-akemi.*.bin generated under the
/build/hatch/firmware/
Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Disable SATA controller and SATA port 1 for eMMC SKUs
BUG=b:132918661
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22
Change-Id: I6d95ff94b079a564f74c19739370101899843f00
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
1. Disable eMMC controller for new SKU ID 23 and 24
2. Disable HS400 mode
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24
Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The src/lib/edid now supports reporting manufacturer name so we should
define that in MIPI panels and print out in initialization.
BUG=None
TEST=emerge-kukui coreboot; boots properly
Change-Id: If844da84ecca31307127b14c66bbe17c408699f3
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34853
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The fixed size of init command in lcm_init_table is wasting lots of
space and we should change to packed array since the command buffer
already provides length information.
With this change, BOE panel init commands have been reduced from 4848
bytes to 1309 bytes.
BUG=b:80501386,b:117254947
TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly
Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Some Kukui variants may have eDP panels connected via a PS8640 MIPI bridge
which we may retrieve EDID dynamically.
BUG=b🅱️137517228
TEST=emerge-jacuzzi coreboot chromeos-bootimage; boots and see display.
Change-Id: I85aac5255e6a3e6019299670486214ecffbf9801
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34516
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Declare the following panel for Kodama:
- BOE TV101WUM-N53
BUG=b:138156559
TEST=builds Kodama image and working properly
Change-Id: I129cb6bf084b76da3ad33b7a19e38e884442b1aa
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34505
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Support Kukui rev 2 panel (via SSD2858).
BUG=b:129299873
BRANCH=none
TEST=Build as Kukui and boots on Rev 2 unit.
Change-Id: Icc16c4297eb3c6b6a4770a36661a2e3cab418048
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Declare the following panels for Krane:
- BOE TV101WUM-NL6
- AUO KD101N80-45NA
The edid info and init command are from:
https://crrev.com/c/1565758
BUG=b:129299873
BRANCH=none
TEST=Builds krane image and boots properly.
Change-Id: Id19c6c2b4c1c728c39aa26301adf7d6fb5046403
Signed-off-by: Jitao Shi <jitao.shi@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Many devices in Kukui family will be using MIPI panels, which needs
hard-coded EDID and initialization commands. And because each device may
have its own layout and ID, there should be very few devices sharing
same panel configuration. As a result, we want to put panel data (EDID
and init commands) into board-specific modules, provided by
`get_panel_description` function.
The panel numeric ID is identified by ADC 2, and is currently available
as higher 4 bits of sku_id(). After ID is retrieved, the
get_panel_description should return a reference to the EDID and table of
init commands. The default implementation is to simply return NULL, and
the data for real devices should be provided by panel_*.c in further commits.
BUG=b:80501386,b:117254947
BRANCH=none
TEST=boot correctly on Kukui
Change-Id: I19213aee1ac0f69f42e73be9e5ab72394f412a01
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
For systems with real MIPI panels (8173/oak was using PS8640 eDP
bridge), we have to send DCS commands to initialize panel.
BUG=b:80501386,b:117254947
TEST=make -j # board = oak and boots
Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change updates the Atmel touchscreen ACPI node to use PRP0001 as
_HID to allow OF-style compatible string matching for enumeration.
Reason for this change: Atmel touchscreen driver in Linux kernel looks
for "compatible" property to decide if it is okay to attach to the
device. This check seems to be a protection against old firmware in
the field that do not have the right properties.
BUG=b:129162037
TEST=Verified that touchscreen works on Kohaku.
Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The default is DMIC0 on, but Kohaku is also using DMIC1
BUG=b:133282247
BRANCH=None
TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav
make sure 4 channels recording work
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
SiFive's ZSBL has initialized flash, but only 16MB of space is available.
1. add code for spi
2. add code to map flash to memory spaces
Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9
Signed-off-by: Xiang Wang <merle@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33055
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
It is easier to track CAR_GLOBAL_MIGRATION which is
the approach to be deprecated with the next release.
This change enforces new policy; POSTCAR_STAGE=y is
not allowed together with CAR_GLOBAL_MIGRATION=y.
Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Almost all platforms force it on. Make it enabled by
default but under user control to optionally disable it.
Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Martin Roth <martinroth@google.com>
The Kohaku V24 schematic adds two additional temperature sensors
to the EC. Add these to the DPTF tables.
Cq-Depend: chromium:1742914
BRANCH=none
BUG=b:138578073
TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel.
1. Build EC
``cd ~/trunk/src/platform/ec``
``make -j BOARD=kohaku``
2. Program EC
``./util/flash_ec --board=kohaku``
3. Reboot device
4. Rebuild BIOS
``cd ~/trunk/src/third_party/coreboot``
``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge
vboot_reference libpayload coreboot-private-files intel-cmlfsp
coreboot-private-files-hatch coreboot chromeos-bootimage``
5. Use flashrom to program the BIOS
6. Reboot device
7. Log into the root console (ctrl-alt-F2 or servo)
8. Example thermal sensor information
``grep . /sys/class/thermal/t*/type``
Look for "TSR0" through "TSR3" in the output.
Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Oops, I missed this in the last CL.
The pin needs to be configured as owned by GPIO, so that the kernel
driver can bind it with an IRQ.
BUG=b:139165490
TEST=Ensure kernel nastygram about inability to claim the IRQ is gone
Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
HDA is not configured.
Enable SOC_INTEL_COMMON_BLOCK_HDA_VERB to configure the HDA using
cim_verb_data[] table.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: I9bb542091ad200833894431f5b840f48dd388173
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34655
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
One case slipped past the review and rebase of 733c28fa42
(soc/intel/{cnl,icl}: Use new power-failure-state API).
Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
pmc_soc_restore_power_failure() is only called from SMM, so add
`pmc.c` to the `smm` class. Once all platforms moved to the new
API, it can be implemented in a central place, avoiding the weak-
function trap.
Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The 'dual DSI mode' was never used by any real boards running coreboot
and is introducing lots of complexity when it comes to refactoring.
In order to create a common display stack for MTK SOCs, we want to first
drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more
similar to each other.
BUG=b:80501386,b:117254947
TEST=emerge-oak coreboot
Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Sarien.
Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown
when S0ix is enabled.
BUG=None
BRANCH=None
TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Arcada.
Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There was the potential for misuse of the override early GPIO table,
because if the override early GPIO table did not have a corresponding
entry in the base table, it would not get overridden, and there was
no way to know except manual inspection (this has already happened
here), so now all hatch mainboards are required to explicitly list out
all of their required early GPIOs.
TEST=booted several hatch boards, verified that they can communicate
with TPM and successfully train memory
Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported
is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of
qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu
via a flag.
To execute:
$ qemu-system-aarch64 -M virt,secure=on,virtualization=on \
-cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic
Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The pinctrl driver in the linux kernel automatically turns off SCI
routing for all GPIOs exported via ACPI, so this patch sets up
dual-routing of the EMR_GARAGE_DET signal so that one can be used
for IRQs and one for the SCI wake.
Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The touchscreen controller was never added to the device tree, and the
next board rev will have this IC connected. Set it up in the device tree
with conservative power resource timings from the datasheet.
BUG=b:138869702
BRANCH=none
TEST=compiles; current board rev does not have touch IC
Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Enabling stylus pen device and pen_eject event.
- Adding enable_gpio for power sequencing
- Configuring GPP_H4 and GPP_H5 as native function
- Adding PENH device node for pen ejection event
BUG=b:137326841
BRANCH=none
TEST=Verified pen input operation and pen_eject event (pop-up and wake
from s0ix on pen ejection)
Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
FSP1.0 has low memory corruptions below CONFIG_RAMTOP
on S3 resume path, as romstage ram stack will be utilised
before there is a chance to make the necessary backup
to CBMEM.
Previously done for intel/minnowmax in commit b6fc727.
Change-Id: I2e128079b180f9978e8519b190648d516aaee0dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34673
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Vortininja needs different SAR values than meep. Use sku-id to load SAR values.
BUG=b:138261454
BRANCH=octopus
TEST=build and verified SAR values by sku id
Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Add support for the integrated TPM in Kconfig and update device tree.
Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
This patch makes SPKR_PA_EN PIN output and high for boot beep
to work in pre-os environment.
BUG=b:135104721
BRANCH=NONE
TEST=Boot Beep is working with required ALC1011 depthcharge code
changes.
Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting
point, I took mainboard/sarien as the reference code and modified WHL
to Comet Lake.
BUG=b:138098572
Test=compiles
Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com>
Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen
T4 specification and resolve re-bind hid over i2c driver failed after
touchscreen firmware auto update.
BUG=b:132211627
TEST=Stress touchscreen firmware auto update 200 times and not found
re-bind driver failed.
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
The Allwinner code was never completed and lacks a driver to load
romstage from the bootblock.
Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values.
BUG=b:138091179
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested on qemu-riscv:
Boots into Linux until initrd should be loaded.
Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
BRANCH=none
BUG=b:138152075
TEST=Build for cometlake board with the PmTimerDisabled policy in
devicetree set to 1.
With PmTimerDisabled = 0
>> iotools mmio_read8 0xfe0018fc
0x00
With PmTimerDisabled = 1
>> iotools mmio_read8 0xfe0018fc
0x02
Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines
whether the ACPI Timer is enabled to run.
- 0: ACPI Timer is enabled
- 1: ACPI Timer is disabled
Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Add rise time / fall time to I2C config in device tree to ensure I2C
CLK runs accurately at I2C_SPEED_FAST (400 kHz).
BUG=b:138258384
BRANCH=none
TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run
at 395-399 kHz.
Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Moving these to bootblock as we are seeing some instances where
devices are rebooting into the recovery broken screen with the 0x5a error (no
bootable storage device in system). This needed to be done for KBL
platforms and never got transferred to hatch.
Please reference https://review.coreboot.org/c/coreboot/+/23647
BUG=b:137681648
BRANCH=None
TEST=Run autotest faft_bios and faft_ec suites
Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and
DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown
when S0ix is enabled.
BUG=133345634
BRANCH=None
TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)]
value is 0xFE on Hatch.
Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This change adds a user selectable option to enable all WiFi SAR
configs that apply to hatch.
BUG=b:138177048
Change-Id: I4b72f90896841e7c556d4a1b8cdad8ca89d01021
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The virt machine is special as it doesn't emulate flash and it puts
the coreboot.rom at start of DRAM. The payload loader doesn't know
about CBFS in DRAM and overwrites the CBFS while decompressing
payloads, resulting in undefined behaviour.
Mark the region as SRAM to make sure the payload won't
overwrite the CBFS while decompressing.
As payload is always decompressed to DRAM, it wouldn't touch
SRAM memory regions.
Change-Id: I36a18cb727f660ac9e77df413026627ea160c1e1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33426
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Fix regression introduced in bd4bcab
"lib: Rewrite qemu-armv7 ramdetect".
The detected DRAM size is in MiB, thus needs to adjusted accordingly
before passed to ram_resource.
Wasn't seen earlier as everything works, except payload loading.
Change-Id: I4931372f530e7b4e453a01e5595d15d95a544803
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34601
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
The build directory might not exist in the src dir.
BUG=b:112267918
TEST=make what-jenkins-does
Change-Id: I2d4fa6cc455592f92070796cd065cd66646d5ba9
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
* Move armv7 RAM dection to a common place
* Enable it for all emulated platforms
* Use 32bit probe values and restore memory even on failure
* Use the new logic on the following boards:
** qemu-armv7
** qemu-riscv
Tested on qemu-system-riscv:
Fixes kernel panic due to wrong memory limits reported.
Change-Id: I37386c6a95bfc3b7b25aeae32c6e14cff9913513
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Add VBT 8.0.1038 binary.
Panel #10 is modified to support the 1200x1920 LCD panel.
This panel is configured as default.
LCD and HDMI are working fine.
BUG=N/A
TEST=booting Facebook FBG1701
Change-Id: If327e4e071df61b02fcec45213c2b700320ef269
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Also don't define the default as this result in spurious lines in the
.config.
This also cleans up an unused Kconfig file.
In the generated config.h CPU_QEMU_POWER8 is gone as expected and
ARCH_RAMSTAGE_PPC64 moves a few lines, but the value stays the same.
Change-Id: I70b64e49e1ce07b8f30d9bbc493272bdfb3bb0bf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31314
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Based on updated schematics, change polarity of USI_INT, and add
the reset and enable GPIOs to the touchscreen ACPI node. The stop
GPIO can't be used with the current implementation of _ON, as the
way it's wired will cause power sequencing to fail.
BUG=b:137133194, b:138240502
BRANCH=none
TEST=Compiles, don't have next board rev to test with
Change-Id: I1dfb8e649418e4c5e9b897fb4bc11393adc21ea2
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34528
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Remove old hda_verb.c code copied from intel/kblrvp7, as it's
been superseded by the common block HDA implementation.
Fixes a null pointer error preventing the HDA codecs from being
initialized, as found in Coverity CID 1403651.
Test: build/boot Librem 13v2, verify functional audio
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Change-Id: I2fd5363aad027f215f93964bc6a85f00fea86c88
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34531
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable I2C0 in fleex then verify EMR function successfully
BUG=b:135968368
BRANCH=octopus
TEST=EMR function working normally with I2C0 in Grob360S.
Change-Id: I784ff32418bc839bcec14fbfd7236f708828690e
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
The 'Jacuzzi' is a different base board that will share most of Kukui
design. For AP firmware, there will be only a few changes expected,
mostly in display (for MIPI bridge) and EC/keyboard so we want to create
it as variants inside Kukui folder, not forking a new directory.
BUG=b:137517228
TEST=make menuconfig; select 'krane' and build; select 'jacuzzi' and build.
Change-Id: Ic2b04e01628dc3db40f79f9bbdd5cc77d9466753
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34344
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We do not want to disguise somewhat complex function
calls as simple macros.
Change-Id: I298f7f9a1c6a64cfba454e919eeaedc7bb2d4801
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This is based on the grunt variant.
BUG=b:135551210
BRANCH=none
TEST=emerge-grunt coreboot chromeos-bootimage
Ensure that image-treeya.*.bin are created
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: I40f3c9de87350777b02dd91d8c5b9dbe2eb9f6b5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34435
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This change provides an implementation of variant_devtree_update() for
kindred that disable eMMC controller when SKU ID = 1 or 3
BUG=b:132918661
TEST=Verify eMMC is disabled when SKU ID = 1 or 3
Change-Id: I8ccb4dae54f223881e0ced9e034bf45b994cc6f2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
We would like to wake eve up in suspend from an MKBP event. This commit
simply enables MKBP events to wake the system in suspend using the
existing host event interface. There is an accompanying series of
patches in the EC firmware for eve that will allow a MKBP wake mask to
be configured.
BUG=chromium:786721
BRANCH=firmware-eve-9584.B
TEST=Build and flash eve, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I75b05c83a4204d55df11589299a7488d04bbd073
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34454
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Functional changes were already done in 5eb81bed2e (sb/intel/i82801gx:
Detect if the southbridge supports AHCI) but we forgot to update the
`chip.h` and devicetrees.
Change-Id: I0e25f54ead8f5bbc6041d31347038e800787b624
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34462
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The EC ID of the ECDT needs to be null-terminated (see ACPI specification,
section 5.2.15), which currently isn't being done due to an off-by-one
error. strncpy() is bug-prone exactly because of issues like this, so just
skip it entirely and use memcpy() instead.
Change-Id: I0b62e1f32177c9768fa978053ab26bca93d7248d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1402104
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Disable unused USB devices in the device tree so that the concerned ACPI
objects do not get exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the USB devices are disabled based
on port status and the concerned ACPI objects are not exported.
Change-Id: I0faccdfb8a9df9ec52130437433b15973e3d6f1a
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Add devicetree configuration for USB devices so that USB Port
Capabilities (_UPC) and Physical Location of Device (_PLD) ACPI objects
can be exported to the OS.
BUG=b:133513961
BRANCH=octopus
TEST=Boot to ChromeOS. Ensure that the _UPC & _PLD ACPI objects are
exported for the configured USB devices in the SSDT table.
Change-Id: I832ffe305d256296b7447035c5e5dcafb7c296d9
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
We would like to wake nocturne up in suspend from an MKBP event. On
Nocturne, MKBP events are notified to the host via a GPIO from the EC,
EC_INT_L. However, the AP cannot wake from suspend from this GPIO.
Therefore, we'll use the host event interface to wake the system
instead.
This commit simply enables MKBP events to wake the system in suspend.
BUG=chromium:786721
BRANCH=firmware-nocturne-10984.B
TEST=Build and flash nocturne, generate MKBP events on the EC and verify
that the system wakes up in suspend.
Change-Id: I6aff4d38051c939257533229fd0085e42c01d02f
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
The processor P_BLK doesn't support throttling. This behaviour could be
emulated with SMM, but instead just update the FADT to indicate no support
for legacy I/O based throttling using P_CNT.
We have _PTC defined in SSDT, which should be used in favour of P_CNT by
ACPI aware OS, so this change has no effect on modern OS.
Drop all occurences of p_cnt_throttling_supported and update autoport
to not generate it any more.
Change-Id: Iaf82518d5114d6de7cef01dca2d3087eea8ff927
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This patch configures GPIO pin GPP_G7 as NF1 with internal pull down.
As per schematics SD host controller SD_WP pin is not connected to
uSD card connector. Configured gpio pin as NF1 with internal pull down
in order to overcome gpio default state in hatch which makes SoC
SD_WP pin is enable.
BUG=b:137729527
BRANCH=None
TEST=Able to write/read data to/from sd card after mounting card device.
Change-Id: I0187267670e1dea3e1d5e83d0b29967714d6065e
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34396
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Following changes are done to enable ALC1011 codec on Helios
1. ACL1011 4 devices to I2C4
2. GPIO H13 is set to GPO as per schematics
Verified SSDT table and i2cdetect from kernel.
Signed-off-by: Naveen Manohar <naveen.m@intel.com>
Change-Id: I0d71e3bd2d4493d059a33023c1afe1b630181d4f
Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33932
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This change provides an implementation of variant_memory_sku() for
helios that overrides memory ID 3 and 4 to 0 and 1 to workaround the
incorrect memory straps in hardware for board id 0 and unknown.
BUG=b:133455595
Change-Id: I38fab1f91decac5d0a146e5a6c74e88f677af305
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34252
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
This change adds support for variant_memory_sku() that allows variant
to return memory SKU ID. Current implementation of memory_sku() is
renamed to weak implementation of variant_memory_sku(). Functionally
this change should be the same as before for all hatch variants. This
function will be overriden by helios in a follow-up CL.
BUG=b:133455595
Change-Id: I509c263ec08e0060c12ef1ea9fed673f1e3f3a41
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Autoport generates these structures as static so let's make it consistent.
See also commit 128205fd with Change-Id
I83382d38a4a3b7ed11b8e7077cc5fbe154e261a7 ("autoport/bd82x6x.go: Improve
gpio.c generation").
Change-Id: I4e07bd755ca4a65b76c69625d235a879fe7b43cb
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33524
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Correct all GPIOs with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
In additional, set an internal pull to any GPI that does not have an
external resistor so that the input is not in an undefined state.
Change-Id: Ia8fe457eddbed0f4ee6bff9ef9dd7a92545be40b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
The limitation for SD-Card was originally only made for mc_apl2
mainboard. Since other mc_apl mainboards also use the SD-Card interface,
the speed mode setting is made in the parent mainboard_final.
In additional, all UHS-I bus speed modes are disabled because of a
limitation for industry use cases. This means that only HS mode is
permitted.
Change-Id: I2f1b51f13a53c2507c52d6a169d6384b8570b3bc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch makes VGPIO_3 GPIO PIN output and low independent of
cnvi is connected or not.
BUG=b:123062346
BRANCH=None
TEST=boot up Hatch device and make sure VGPIO_3 gpio pin is driven low.
Change-Id: I629b99676f56747de1b244724709e14069250097
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34376
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This CL allows that everyone can use main() in lib/bootblock.c
even if you select CONFIG_BOOTBLOCK_CUSTOM. I also rename main
functions used in some soc/ to avoid the collision with the
main function defined at lib/bootblock.c.
Change-Id: I0575c9d1ce9dea9facfcc86760dff4deee9c1e29
Signed-off-by: Asami Doi <d0iasm.pub@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34250
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Initial support for Portwell PQ7-M107 (Q7) module.
Code based on Intel Strago mainboard.
BUG=N/A
TEST=booting SeaBIOS and Linux 4.20 kernel on PQ7-M107
Change-Id: I7d3173fdcf881f894a75cd9798ba173b425d4e62
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Currently, bluetooth FW is not loaded after a reboot. In order to do
this, we have to disable the bluetooth disable gpio (GPP_C14) in
bootblock and re-enable it in ramstage.
BUG=b:137307516
BRANCH=None
TEST=boot up Hatch device and make sure (in dmesg) that proper
bluetooth FW in loaded
Change-Id: Ic5e447d9de57790f7a100e9e03f36b047c19d8f9
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34354
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
GPIOs related to power sequnce are
GPIO_67 - EN_PP3300
GPIO_117 - FULL_CARD_POWER_ON_OFF
GPIO_161 - PLT_RST_LTE_L
1. Power on: GPIO_67 -> 0ms -> GPIO_117 -> 30ms -> GPIO_161
2. Power off: GPIO_161 -> 30ms -> GPIO_117 -> 100ms -> GPIO_67
3. Power reset:
- keep GPIO_67 and GPIO_117 high and
- pull down GPIO_161 for 30ms then release it.
BUG=b:137033609
BRANCH=octopus
TEST=build image and verify on the DUT with LTE DB.
Change-Id: I7bf6fee087c885c22363b44aa98aa61f91be90b4
Signed-off-by: Marco Chen <marcochen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
These configuration files can be used to build Kodama firmware.
BUG=b:135490566
TEST=check variant: kodama via make menuconfig; make -j
Change-Id: I72e80e800ba041df1dda2b0f84470d1ef58bc946
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33616
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Elan's touchpad requires min 0.3us data hold time.
To fine tune the data hold time of i2c1 to meet
specification of Elan's touchpad.
BUG=None
BRANCH=None
TEST=Verified data hold time of i2c1 is around 320ns
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0fa9db3b50e74f193261be96bd9e305bb19841e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Crews <ncrews@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Hatch and variants use GPP_A21 for trackpad IRQ and wake. Fix
overridetree.cb to advertise the right IRQ.
Change-Id: Ib87c858b89e8726c3bc80f83be0729ef4625268e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34248
Reviewed-by: Philip Chen <philipchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Bluebird needs to use different SAR values than Casta.
Bluebird sku id is 2.
CQ-DEPEND=CL:*1435310
BUG=b:129725065
BRANCH=octopus
TEST=build
Change-Id: I107a8519832fcf906b94f958a3dc508d19bb4727
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34080
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Remove implementation of 24 MHz clock, available only
on Haswell ULT SKUs. Use TSC_MONOTONIC_TIMER instead
for all boards.
Change-Id: Ic4aeb084d1b0913368f5eaa46e1bd68411435517
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
By setting the GPIOs 42 and 43 to native function 1 the LPSS UART 1 is
activated.
Change-Id: I74abd1b6fb5459cf11a5bdee182c99462f613b7a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Update the AC/DC loadline values for all domains. Using the same
values as in arcada.
BUG=None
BRANCH=None
TEST=Build and Boot hatch EVT
Change-Id: If8ea48794d11dc68e40e6504c0d46a2b273a8ab6
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33371
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
GPIO46 is wired to a tiny switch on the board labelled "GPU Boost".
Since coreboot could make use of it, add a comment about it on gpio.c.
Change-Id: I0efa85e6d8235711521b10e56b7c89a25c4b2b7f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This GPIO is corrected with reference to the Apollo Lake SoC EDS Vol 4
revision 2.4 chapter 10.1.2.3 List of Pins that are GPIOs but cannot be
used in Function 0 (GPIO) mode.
Change-Id: I98628ade3a1e19730ca6e6b4a63c28e6816176ce
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
We need to reduce the eMMC bus speed for these Apollo Lake mainboards
because of a limitation on Intel side for industry use cases.
Change-Id: Ide6a1a302001c0752d149bfdab175a27c8f8cc35
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Currently some of the LCM ID voltage gaps are below 100mV. For example, the
voltage difference between ID 2 and 3 is 503-440=63mV. To reduce the risk of
misrecognition from the hardware level, the voltages are adjusted so that all
the voltage gaps are larger than 100mV. The RD2 resistor values are also
updated.
BUG=b:136987483
TEST=emerge-kukui coreboot
Change-Id: Ib5c1f927fb54d8c9579f030e42eeec5a27daaceb
Signed-off-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34192
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The tolerance of ADC is +-10mV, but the resistors may also
introduce 1% variation, and causing the final measured
voltage to vary around 5%.
By the advisory from hardware team, checking the tolerance
seems not really solving or helping anything so we should
just ignore that and try to find best matched ID (this
also aligns to what Gru did).
BUG=b:136990271
TEST=Booted on Krane and no longer seeing ADC out of range
BRANCH=None
Change-Id: Ie02ca5aaafbcfa8f411d973ad0266eee385d6878
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34161
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: You-Cheng Syu <youcheng@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Before the system enters S0ix or S3, each GPIO community
will have its dynamic clock gating turned on. Upon return
to S0, the dynamic clock gating will be turned back off.
BUG=b:130764684
BRANCH=none
TEST=Used dut-power to verify that the clock gating is enabled
in S0ix and S3. Also used Store(..., Debug) statements in the
ASL code to verify it was getting called.
Change-Id: I20ff2aac035eaa5912af6c946d837567a4918bbf
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Include the lpit.asl file in Hatch's DSDT definition.
BUG=b:130764684
BRANCH=none
TEST=S3 suspend/resume and S0ix entry/exit work correctly.
Ran > 200 iterations of suspend_stress_test and no issues found.
Change-Id: If8ebff3db091257e8452869636c0e024f3123e8b
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34175
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
The dynamic clock gating is causing boards to miss interrupts
whose pulses are shorter than 4us. Disable it using FSP UPDs.
BUG=b:130764684
BRANCH=none
TEST=Compiles
Change-Id: I8f1ec8f7c31192bce2a761ec99b86638435dc27c
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Evan Green <evgreen@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Increases CPU max core count to 16 for coffeelake Refresh-S Platform.
TEST: boot to linux OS on CFL-S refresh Intel RVP and verified the output
of cat /proc/cpuinfo shows no of processor=16.
Signed-off-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Change-Id: I579ff6ae8227844741406c503d3994408ec2b617
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34156
Reviewed-by: Boon Tiong Teo <boon.tiong.teo@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
HP_INT_L(GPP_H0) is configured for GPIO IRQ instead of APIC IRQ since
it needs to trigger on both edges. With GPIO IRQ, it is necessary to
configure the trigger type in coreboot to match the ACPI
configuration. This is because:
1. ACPI configuration is used by intel-pinctrl driver in Linux kernel
to re-configure the trigger type for the pad in GPIO DW0 config
register. This is done when kernel driver probes and requests irq for
its device.
2. On resume from S3, the pad configuration gets reset and coreboot
sets the trigger type to LEVEL. However, kernel driver does not probe
again. This results in the trigger type being configured incorrectly.
This change updates the GPIO configuration for GPP_H0 to set the same
trigger type as advertised in ACPI for the kernel.
BUG=b:132672011
TEST=Verified that S3 works fine. Verified that interrupt on GPP_H0
works fine on boot as well as after suspend/resume.
Change-Id: Ieb44c7403a2f4911b4a8f422053dee8bcfb91d85
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34181
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This also removes the relevant RCBA replays the mainboard dir.
Change-Id: I75dd9d1bcd09d835f205a51c087d52ebb4e166f6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33038
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Thomas Heijligen <src@posteo.de>
The QEMU machine "PC" doesn't support MCFG.
Die after console init if the user selected the wrong qemu machine
and print a message to use the correct machine type.
Without this patch ramstage dies with non-helpful message:
"get_pbus: dev is NULL!"
Change-Id: I9d1b24176de971c5f827091bc5bc1bac8426f3f6
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31425
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
increase reset off delay time
Goodix touchscreen cannot work in normal mode because PP3300_TOUCHSCREEN_DX
dropped. Configure GPP_D9 as enable pin in the devicetree.cb to fix the power
sequence. Increase reset_off_delay time from 1ms to 3ms to met the HW requirement.
BUG=b:135287161
BRANCH=None
TEST=local build and measure sequence with Goodix touch screen
Change-Id: I33140869990aa4715c780b0fa322921e450530ef
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33808
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This patch updates the following GPIO settings.
1. Set Native termination for GPP_G0 - G4 SD card pins.
2. Set GPP_B19 to NF1.
BUG=b:123907904
TEST=Verified SD card functionality on hatch. Checked for SD detection,
transferred files to and from SD card.
Change-Id: I4549ac7377d7f58f51cda0eb96a62604fd31d2f2
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32176
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
G505S doesn't have any SAS or NVMe controllers and couldn't have a TPM,
so it makes sense to disable the related SeaBIOS options for this board.
This reduces the size of compiled SeaBIOS by 129344-110048=19296 bytes.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: Ib0183b7786ecd77bb0df923bc84908275f2fe14c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33870
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
We have 3 similar Lenovo mainboards - x60 (oldest), t60, and z61t (most
recent addition). The only one with two consequent 2s as the C-types
is t60:
static acpi_cstate_t cst_entries[] = {
{ 1, 1, 1000, { 0x7f, 1, 2, { 0 }, 1, 0 } },
{ 2, 1, 500, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV2, 0 } },
{ 2, 17, 250, { 0x01, 8, 0, { 0 }, DEFAULT_PMBASE + LV3, 0 } },
};
It seems that 3 could be a better choice for the last line here.
UNTESTED on a real hardware.
Change-Id: I090e82d5f4ae25c768ff45a01a8dd76ff8a96a90
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Find the NIC device based on the PCIe root port function.
Change-Id: Ia8c6e115c9b836ee60862427dfc9d46ca3dd1b69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34003
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
With VBOOT=y && VBOOT_MEASURED_BOOT=y message
digest will be allocated from the stack and
1 KiB reserve used with the recent platforms
was no longer sufficient.
The comment of LZMA scratchpad consuming stack
was obsolete for postcar, so these can be reduced
to same 4 KiB.
Change-Id: Iba1fb5bfad6946f316feac2d8c998a782142a56a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
It's forbidden to use dereference CAR_GLOBAL variables
directly. The notation fails after CAR teardown for
romstage.
Change-Id: I6e6285ca0f520608c2a344517fbac943aeb36d87
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33995
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It was never tested or injected.
Change-Id: I3fd82aaa11afc5adab212ec6709580b4bcc67ca3
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34001
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Google project name is Bloog.
Bloog is 12-inch LCD.
Blooguard is 14-inch LCD so would prefer to use a different SAR values instead.
Use sku-id to load the SAR values.
BUG=b:135078377
BRANCH=octopus
TEST=build and verify SAR load by sku-id
Change-Id: Id80df28a961eb1f62714558df2b219aa552ecb97
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Previously, We had to use GPP_A21 for trackpad wake and GPP_D21 for
trackpad interrupts due to ITSS not honoring the INVERT config. Now
that's fixed, we can configure trackpad wake and interrupts on GPP_A21
only.
BUG=b:130436471
BRANCH=None
TEST=1. boot a hatch device and make sure we can move the cursor with the trackpad
2. Run powerd_dbus_suspend and wake by clicking on the trackpad and ensure
through "mosys eventlog list" that the wake source is the trackpad.\
3. Run "echo mem > /sys/power/state", wait until device goes into S3,
click trackpad to ensure device wakes.
Change-Id: I26a99206c42ba442f91ae577b98366fc2fd6c0ca
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33820
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Now that ITSS config is fixed, we can set the IOAPIC pad configs
correctly.
BUG=b:123967687
BRANCH=None
TEST=Make sure Hatch is booting and tested out trackpad to make
sure can move cursor and wake by clicking on the trackpad
after running powerd_dbus_suspend.
Change-Id: I0b125996338b6f16e03b7ca184f6337c696a5f64
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33819
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Since ttyS0 isn't used for UART0, configure ttyS4 as default
Change-Id: Ia0469226253b08328807d5401c05633296e43d22
Signed-off-by: Felix Singer <felix.singer@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33785
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It has been observed by me and Elisenda Cuadros / Gergely Kiss [1] that
the boot process of this board is super slow when UART 0 is being used -
even if nothing is connected to it. Enable UART according to
CONFIG_UART_FOR_CONSOLE - and, if UART 0 is selected, it will be initialized
at romstage and this problem will not happen.
[1] https://mail.coreboot.org/pipermail/coreboot/2018-February/086132.html
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I6579aa8fd092da84f8afdcc33496db45c582919f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33796
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Correct i2c address of trackpad. It should be 0x20.
BUG=None
BRANCH=None
TEST=Verified trackpad works on pre-evt system
Change-Id: I7ded21ce8ff9e907e436777a27edb4273512011d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Shelley Chen <shchen@google.com>
Drop hacked uart code and use the generic 8250 uart driver for ns16550a.
Tested on qemu-system-riscv64:
* The UART is still working.
Change-Id: I6efda913fa39e0cfa466b52c570572aca90dacdf
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33735
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
By default, the LPC SIRQ mode is set to Quiet mode. Therefore, COM-port
from the SurerIO chip don't work correctly after the LPC controller (PCI
0:1f.0) initialization. Console output is broken. The patch fixes this
bug by overriding the serirq_mode option in the devicetree.cb to set
Continuous SIRQ mode
Change-Id: I37e26b271fb61f6c0343d6bf65c029924df82caf
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33801
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
A FPMCU power-control pin (GPP_C11) is added to the latest
hatch reference schematic.
Even though this is not implemented in hatch rev1 board, the future
hatch family boards with FPMCU should all have this control pin.
On the old boards without this control pin, GPP_C11 is a floating TP,
and thus this patch should be backward-compatible.
BUG=b:130307667, b:135216932
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: I6a84eeb6aab562258e749a8a5d09dadfa0e43587
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33655
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
There is no need to add internal termination (PU/PD) on the
not-connected pads. This change gets rid of the terminations on the NC
pads.
Change-Id: I3df538d7127e5ef75e6e6ff9db3524e26f0450ed
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
CBFS_SIZE equals size of whole SPI device.
The descriptor and ME need to be placed in bottom part.
Reduce the CBFS_SIZE to maximum avalaible size.
BUG=N/A
TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Iecfae4573100c6787b6e8b1c4f2583a7fb3d95a3
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33484
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
tc348860_table contains the eDP to MIPI Bridge controller type.
b101uan08_table used the LCD Panel type.
Use LCD Panel type for name of tables.
Remove the incomplete resolution comments and specify the resolution at
the start of the table to 1200x1920.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: Ic152ea1f95f155ab76638b57a259d37ce6f43037
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33736
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
It seems that the EC on t60/x60/z61t doesn't support it. This wasn't
even introduced in z61t so let's remove the remaining bits.
This commit follows up on commit a5fcc2e4 with Change-Id
Id2964002406a5fcf992f0ffc3627e3f66a2bb13f ("mb/lenovo/x60/t60: Remove
`fn_ctrl_swap` option").
Tested on a real hardware.
Change-Id: Ifd5e7823af305cc4a0194ee2097a749e43680c55
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Andrey Korolyov <andrey@xdel.ru>
Tested with SeaBIOS as a payload, booting Arch Linux with
a Linux kernel. The new code is based on autoport and the
existing GA-H61M-S2PV code.
The GA-H61M-S2PV has been boot-tested too, it still boots.
Working:
- S3 suspend/resume
- USB ports and headers (Intel USB2 and EtronTech USB3)
- Gigabit Ethernet
- Integrated DVI/VGA graphics (libgfxinit)
- PCIe x16 graphics
- PCIe x1 ports
- PS/2 port with a keyboard
- SATA controllers (Intel SATA2 and Marvell SATA3)
- User-space fan control (fancontrol on Linux)
- Native raminit (4+4GB DDR3-1333)
- flashrom, using the internal programmer. Tested with coreboot,
as well as with the vendor firmware. Backup chip is untested.
Untested:
- VGA BIOS for integrated graphics init
- Audio: Only front/read outputs has been tested.
- Non-Linux OSes
- ACPI thermal zone and OS-independent fan control
Not working:
- Default IFD defines the BIOS region as the entire flash chip.
Using 'flashrom --ifd -i bios' is asking for a failed flash!
Change-Id: I37928de158bb8fbb47fbda5d1ccd4efba7edab26
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31832
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
FBG1701 contains a TC358860 eDP to MIPI Bridge controller which needs
to be configured.
Add mainboard_configure_edp_bridge() to program the controller.
CPLD version is used to determine which table must be programmed.
The eDP is an i2c slave which expects the next i2c bus data for block
write:
<Slave Addr> <Reg Addr[15:8]> <Reg Addr[7:0]> followed by data with LSB
first.
BUG=N/A
TEST=Config eDP and verify LCD panels are working on Facebook FBG-1701
Change-Id: I262cb4376b86db94e3bb9522c556b5cc3ff38335
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The asrock/h110m has a NCT6791D, but is selecting the NCT6776-specific
SUPERIO_NUVOTON_NCT6776_COM_A symbol. Use the NCT6791D symbol instead.
Change-Id: I9f3fde161844f919b070f2b6ce7e106411439a9a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maxim Polyakov <m.poliakov@yahoo.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
* Enable decoding the IPMI KCS to LPC
* Select the IPMI driver
* Add the PNP device that holds the IPMI KCS base address
Tested on Wedge100s.
Change-Id: I35634bbcbe6893bd72ec7e41f6ca7bba09d819a2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Support SAMSUNG KMDP6001DA-B425 and MICRON MT29VZZZAD8DQKSL EMCP LPDDR4X DDR
From the calibration log of MICRON MT29VZZZAD8DQKSL, we found
the begin pass range of RX window earlier than with other DDR type.
So need change the DQS starting offset to increase the scan range of RX window.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on EMCP DRAM
Change-Id: I5fcc8673a2fbd7ec3a8776ab61c57f8903ddda20
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com>
Garg proto build has 3 SKUs:
garg 2A2C DB: SKU ID - 1
garg HDMI DB: SKU ID - 9
garg LTE DB: SKU ID - 17
For SKU#9, VBT will need to be overridden to enable DDI_C output to HDMI
BUG=b:134912735
BRANCH=octopus
TEST=emerge-octopus coreboot chromeos-bootimage
Cq-Depend: chrome-internal:1380847
Change-Id: I6c0ec086496eaf217ea8e326f5084d886d0e698f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Make the linker script dynamic to support non default ROM sizes.
Prevents weird runtime issues due to stages overwriting parts of the
CBFS while decompressing stages.
Change-Id: I37b9187c719b907959f02a272ec0459aabbcda3c
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33412
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Files onboard.h and mainboard.h are not used for building.
Remove these files as include.
BUG=N/A
TEST=Build and boot embedded Linux 4.20 on Facebook FBG-1701
Change-Id: Ifeb0047357e641cbe1affbbaf5402213802c774c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Fix value of 1 is used for asl_compiler_revision.
Use asl_revision for this.
BUG=N/A
TEST=booting Linux 4.20 kernel on Facebook FBG1701
Change-Id: Iffd8fe637d4669b7099fb6eafc9873560502bf80
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33423
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Lance Zhao <lance.zhao@gmail.com>
This does the following:
- select MAINBOARD_USES_FSP2_0 on Kabylake (does not support FSP1.1)
- Remove stale Kconfig option on intel/saddlebrook
- select SOC_INTEL_KABYLAKE on intel/kblrvp
Change-Id: I64f48eeb00150aea039d533b0ac471fdd8483b90
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33561
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Increase the size of bootblock from 96K to 128K.
Change-Id: Ifc6e7239ed2978a8490fa229945ebd5ed9182298
Signed-off-by: Nitheesh Sekar <nsekar@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33159
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
There is already an external pull-up/down resistor tied to
this pin to identify if the board is single-channel or
dual-channel memory SKU.
BUG=b:135496271
BRANCH=none
TEST=build
Signed-off-by: Philip Chen <philipchen@google.com>
Change-Id: Ie218657fd9dde113ab26cf5551d1dff1b6e392b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33583
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This code to handle the brightness from SMM is copied from the Lenovo
Thinkpad X60 code, but does not work on later generation. The PCI
device it tries to address does not even exist on those devices.
Change-Id: I0c25c3e5bec651b27158a84cc91289639a04ceb6
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33508
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Those are copied from Lenovo X60 code, but are unused.
NOTE: No ACPI C-state are generated on this platform but Linux has a
separate driver for that.
Change-Id: Ie9b49f5451d8cde9c36672cac1f0f14cb3f0095e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33140
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
TODO: There is no reason to do this in SMM.
Change-Id: I8bbb2f65bbe674bd1bc4ae8a4086bd1f5e9a79fa
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33139
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Switch the default clock output for single LVDS mode to odd bus only.
Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This patch enables TPM on SPI and adds the needed devicetree entry for
mc_apl5.
TEST=Build coreboot for mc_apl5 board and check the TPM console output.
In addition the TPM was correctly verified by our Linux driver.
Change-Id: Iafc967c7a2bfee9bdb9b6591d12328620e2887cc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33173
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Increase SPI flash speed from 26MHz to 56MHz and set correct tick_dly
to get faster boot process.
BUG=b:80501386
BRANCH=none
TEST=emerge-kukui coreboot; emerge-elm coreboot
Change-Id: I8f44883b4f4a198146330caf5420dc39d5592a0a
Signed-off-by: Mengqi Zhang <Mengqi.Zhang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32462
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Enable RTC so that we can see correct timestamp in CrOS eventlogs.
BUG=b:134461866
TEST='mosys eventlog list' shows correct timestamp on Kukui
Change-Id: Ie9ef7c9343c781e348429cd5376a4a5519641e16
Signed-off-by: You-Cheng Syu <youcheng@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Adjust FMAP sections that
- ELOG only needs 4K (by driver limitation)
- SHARED_DATA only needs 4K or less (for netboot params)
- SMMSTORE is probably not needed since UEFI@ARM is not available yet
- VPD can be smaller (most x86 devices have only 16/8K for RO/RW)
- Increase RW_LEGACY to 1M (recommended value)
- Move all new saved space to CBFS
BUG=b:134624821
TEST=Built Kukui image and boots on Rev2 units.
Change-Id: Id2910df73ea47bfa32e056d631d1c3e5f1eed0d1
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
The default voltage of vsim2 is set to 2.76V for sim card usage.
In general, 2.76V of vsim2 is composed of 2.7V main voltage and 0.06V calibration voltage.
However, vsim2 is used for the tx_ovdd power of display port IT6505 on the kukui board design which needs 2.7V.
So we set it to 2.7V with modifying calibration value.
BUG=b:126139364
BRANCH=none
TEST=measure vsim2 voltage with multimeter
Change-Id: I4dffdde89cbde91286d92e6c2b445f0b3d0ad2fe
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32057
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Hatch newer board revision do not use USB port5 for discrete BT.
Hence remove the port configuration and UBS2 P5 asl entry. The older
board version would continue to use USB2 P5 hence moved the entry to
overridetree.cb
Change-Id: I98297d6b81e3184b7b0a14710f3790f5df30d68b
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This patch configures FSP UPD values for HPD and DDC of DDI ports for
WHLRVP.
BUG=none
TEST=Tested that eDP & DP works on WHLRVP
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: sridhar <sridhar.siricilla@intel.com>
Change-Id: I576469f5564e3e56159762752dbe4557e9dc1912
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33435
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
The clock was previously set to 52MHz to workaround the fact that
depthcharge didn't support tuning.
Tuning has now been enabled in depthcharge:
https://chromium-review.googlesource.com/c/chromiumos/platform/depthcharge/+/1655553
BUG=b:122244718
TEST=Verified on grunt that it speeds up boot by 130ms
Change-Id: If847cea2a7848bcd175958db86e652d4f710201a
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit follows up on commit commit 89989cf6 with Change-Id:
I1f44ffeb54955ed660162a791c6281f292b1116a ("src: Drop unused include
<arch/acpi.h>").
Change-Id: I3dc12373b32b95d25ba7b302cbca5f927678315d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33365
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit follows up on commit 8b7a1614 with Change-Id:
I73c557d6ef009fb2cac35fdea500dee76f525330 ("src/mainboard: Remove
unneeded include <arch/io.h>").
Change-Id: I7f307bf5b6cdcfebe1a290ce344b962fcecc8781
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
The temperature delta between on-board thermistor and
surface temp change, so update DPTF parameter accordingly.
BUG=b:113101335
TEST=Tested in thermal chamber by thermal team.
See comment 148 / 153 in the bug.
Change-Id: Ie18be94fc1e7476755fb0e6947cce559854a82dd
Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Bob Moragues <moragues@google.com>
Move the memory strap gpios to variant/gpio.h, as the memory straps
are different for helios.
Change-Id: I1833c9539687011ee27fd3e88c0581e30ca59354
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
All usage of pci_read_config8 was removed in commit d44d4f0f with
Change-Id Ia959eb5b747846048396e66d4c926c96c27f3878 ("mb/lenovo/*:
Remove useless smihandler code"). So we don't need this include anymore.
Change-Id: Ic4f038c80e17799016ae7e92a5675cfe7c71e400
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33510
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Helios has a number of GPIO changes w/r/t to its baseboard.
Override early, sleep and normal GPIOs as appropriate.
BUG=b:135257452
BRANCH=none
TEST=Compile only (no boards to test with)
Change-Id: I45793ad6515df5af5b925d92106bd943374353d4
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33485
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Change tcc offset from 0 to 10 degree celsius for bloog.
BUG=b:135225497
BRANCH=octopus
TEST=Build and verify test result by thermal team.
Change-Id: I4cbff846914a776c67692005f8b40cd73cfaf231
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Memory id's are 1-indexed for DDR4, so we need to check that the SPD
index is non-zero before converting it to the 0-indexed value in the
bitmap.
Change-Id: Icc542239d91c39b89c23f31856c28e7c20b2fc4d
Signed-off-by: Jacob Garber <jgarber1@ualberta.ca>
Found-by: Coverity CID 1387028
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
The gpio_key wakeup_event_action in the ACPI tables was backwards, causing
devices to wake up on pen insertion instead of removal. Changed to
EV_ACT_DEASSERTED.
BUG=b:134547896
BRANCH=none
TEST=Verified in OS, device only wakes up on pen removal
Change-Id: I0816ed9fb23cf00fd8e40bcdd25ff7a9f48badbd
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33427
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Change the SPD makefile to use the LPDDR3 SPDs. Set up the arrays
for mapping SoC DQS pins to LPDDR3 pins.
BRANCH=none
BUG=b:133455595
TEST=`FEATURES="noclean" FW_NAME="helios" emerge-hatch chromeos-ec
depthcharge vboot_reference libpayload coreboot-private-files
intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`
Ensure the firmware builds without error.
Change-Id: Iebaba2ec65dfcf36674b4733b421ada107b22b09
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33456
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
These 4 GPIOs are being disconnected in the next board so use the
board ID to configure these pins as not connected to ensure
they do not cause leakage.
Also remove the ACPI _PTS S5 code that was configuring the GPIOs.
This does mean they will cause small leakage in S5 on existing boards,
but it will not affect the new boards.
BUG=b:132393441
TEST=boot on sarien with fake board ID and ensure that coreboot
configures these pads as expected.
Change-Id: I6ac04b9a635829811a09aeab7cba3bb58cfcff47
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>
This patch is not actually disabling HECI1 as it requires a dedicated FSP UPD
for WHL/CML SoC code to set this HECI1 chip config.
Change-Id: Ia88f3315a9dc3365d0acc13ed887e7c596c97c91
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
No C_ENVIRONMENT_BOOTBLOCK support for Braswell is available.
Enable support and add required files for the Braswell Bootblock in C.
The next changes are made support C_ENVIRONMENT_BOOTBLOCK:
- Add car_stage_entry() function bootblock-c_entry() functions.
- Specify config DCACHE_BSP_STACK_SIZE and C_ENV_BOOTBLOCK_SIZE.
- Add bootblock_c_entry().
- Move init from car_soc_XXX_console_init() to bootblock_soc_XXX_Init()
Removed the unused cache_as_ram_main() and weak car_XXX_XXX_console_init()
BUG=NA
TEST=Booting Embedded Linux on Facebook FBG-1701
Building Google Banos
Change-Id: Iab48ad72f1514c93f20d70db5ef4fd8fa2383e8c
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/29662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Disable dynamic clock gating for the community cr50's IRQ lives on.
That IRQ is pulsed very quickly, and with clock gating enabled pulses
tend to be missed. This is expecially true on the default 0.0.22
firmware that cr50 comes with out of the factory.
BUG=b:130764684 b:130338605
BRANCH=None
TEST=Boot hatch with cr50 "intap" firmware that can vary the pulse width,
observe that even with sub-microsecond pulses no IRQs are missed.
Change-Id: I34d14fb7cc97e33eecfda2c99cc53a541c87662d
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Evan Green <evgreen@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33326
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
It was determined through testing that 16MB of reserved VRAM is
sufficient. Additional RAM for the graphics driver is allocated out
of system memory.
BUG=b:123579702
TEST=Boot Grunt, watch VRAM usage with graphics driver logging.
Change-Id: I44b640f015b45c0dc3d701929549f3a1082a9268
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33368
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
